drivers/edac/i82860_edac.c

   1 /*
   2  * Intel 82860 Memory Controller kernel module
   3  * (C) 2005 Red Hat (http://www.redhat.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Ben Woodard <woodard@redhat.com>
   8  * shamelessly copied from and based upon the edac_i82875 driver
   9  * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/pci_ids.h>
  16 #include <linux/edac.h>
  17 #include "edac_core.h"
  18
  19 #define  I82860_REVISION " Ver: 2.0.2"
  20 #define EDAC_MOD_STR    "i82860_edac"
  21
  22 #define i82860_printk(level, fmt, arg...) \
  23         edac_printk(level, "i82860", fmt, ##arg)
  24
  25 #define i82860_mc_printk(mci, level, fmt, arg...) \
  26         edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
  27
  28 #ifndef PCI_DEVICE_ID_INTEL_82860_0
  29 #define PCI_DEVICE_ID_INTEL_82860_0     0x2531
  30 #endif                          /* PCI_DEVICE_ID_INTEL_82860_0 */
  31
  32 #define I82860_MCHCFG 0x50
  33 #define I82860_GBA 0x60
  34 #define I82860_GBA_MASK 0x7FF
  35 #define I82860_GBA_SHIFT 24
  36 #define I82860_ERRSTS 0xC8
  37 #define I82860_EAP 0xE4
  38 #define I82860_DERRCTL_STS 0xE2
  39
  40 enum i82860_chips {
  41         I82860 = 0,
  42 };
  43
  44 struct i82860_dev_info {
  45         const char *ctl_name;
  46 };
  47
  48 struct i82860_error_info {
  49         u16 errsts;
  50         u32 eap;
  51         u16 derrsyn;
  52         u16 errsts2;
  53 };
  54
  55 static const struct i82860_dev_info i82860_devs[] = {
  56         [I82860] = {
  57                 .ctl_name = "i82860"},
  58 };
  59
  60 static struct pci_dev *mci_pdev;        /* init dev: in case that AGP code
  61                                          * has already registered driver
  62                                          */
  63 static struct edac_pci_ctl_info *i82860_pci;
  64
  65 static void i82860_get_error_info(struct mem_ctl_info *mci,
  66                                 struct i82860_error_info *info)
  67 {
  68         struct pci_dev *pdev;
  69
  70         pdev = to_pci_dev(mci->dev);
  71
  72         /*
  73          * This is a mess because there is no atomic way to read all the
  74          * registers at once and the registers can transition from CE being
  75          * overwritten by UE.
  76          */
  77         pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
  78         pci_read_config_dword(pdev, I82860_EAP, &info->eap);
  79         pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
  80         pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
  81
  82         pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
  83
  84         /*
  85          * If the error is the same for both reads then the first set of reads
  86          * is valid.  If there is a change then there is a CE no info and the
  87          * second set of reads is valid and should be UE info.
  88          */
  89         if (!(info->errsts2 & 0x0003))
  90                 return;
  91
  92         if ((info->errsts ^ info->errsts2) & 0x0003) {
  93                 pci_read_config_dword(pdev, I82860_EAP, &info->eap);
  94                 pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
  95         }
  96 }
  97
  98 static int i82860_process_error_info(struct mem_ctl_info *mci,
  99                                 struct i82860_error_info *info,
 100                                 int handle_errors)
 101 {
 102         int row;
 103
 104         if (!(info->errsts2 & 0x0003))
 105                 return 0;
 106
 107         if (!handle_errors)
 108                 return 1;
 109
 110         if ((info->errsts ^ info->errsts2) & 0x0003) {
 111                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
 112                 info->errsts = info->errsts2;
 113         }
 114
 115         info->eap >>= PAGE_SHIFT;
 116         row = edac_mc_find_csrow_by_page(mci, info->eap);
 117
 118         if (info->errsts & 0x0002)
 119                 edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
 120         else
 121                 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
 122                                 "i82860 UE");
 123
 124         return 1;
 125 }
 126
 127 static void i82860_check(struct mem_ctl_info *mci)
 128 {
 129         struct i82860_error_info info;
 130
 131         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 132         i82860_get_error_info(mci, &info);
 133         i82860_process_error_info(mci, &info, 1);
 134 }
 135
 136 static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
 137 {
 138         unsigned long last_cumul_size;
 139         u16 mchcfg_ddim;        /* DRAM Data Integrity Mode 0=none, 2=edac */
 140         u16 value;
 141         u32 cumul_size;
 142         struct csrow_info *csrow;
 143         struct dimm_info *dimm;
 144         int index;
 145
 146         pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
 147         mchcfg_ddim = mchcfg_ddim & 0x180;
 148         last_cumul_size = 0;
 149
 150         /* The group row boundary (GRA) reg values are boundary address
 151          * for each DRAM row with a granularity of 16MB.  GRA regs are
 152          * cumulative; therefore GRA15 will contain the total memory contained
 153          * in all eight rows.
 154          */
 155         for (index = 0; index < mci->nr_csrows; index++) {
 156                 csrow = &mci->csrows[index];
 157                 dimm = csrow->channels[0].dimm;
 158
 159                 pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
 160                 cumul_size = (value & I82860_GBA_MASK) <<
 161                         (I82860_GBA_SHIFT - PAGE_SHIFT);
 162                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 163                         cumul_size);
 164
 165                 if (cumul_size == last_cumul_size)
 166                         continue;       /* not populated */
 167
 168                 csrow->first_page = last_cumul_size;
 169                 csrow->last_page = cumul_size - 1;
 170                 dimm->nr_pages = cumul_size - last_cumul_size;
 171                 last_cumul_size = cumul_size;
 172                 dimm->grain = 1 << 12;  /* I82860_EAP has 4KiB reolution */
 173                 dimm->mtype = MEM_RMBS;
 174                 dimm->dtype = DEV_UNKNOWN;
 175                 dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
 176         }
 177 }
 178
 179 static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
 180 {
 181         struct mem_ctl_info *mci;
 182         struct i82860_error_info discard;
 183
 184         /* RDRAM has channels but these don't map onto the abstractions that
 185            edac uses.
 186            The device groups from the GRA registers seem to map reasonably
 187            well onto the notion of a chip select row.
 188            There are 16 GRA registers and since the name is associated with
 189            the channel and the GRA registers map to physical devices so we are
 190            going to make 1 channel for group.
 191          */
 192         mci = edac_mc_alloc(0, 16, 1, 0);
 193
 194         if (!mci)
 195                 return -ENOMEM;
 196
 197         debugf3("%s(): init mci\n", __func__);
 198         mci->dev = &pdev->dev;
 199         mci->mtype_cap = MEM_FLAG_DDR;
 200         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 201         /* I"m not sure about this but I think that all RDRAM is SECDED */
 202         mci->edac_cap = EDAC_FLAG_SECDED;
 203         mci->mod_name = EDAC_MOD_STR;
 204         mci->mod_ver = I82860_REVISION;
 205         mci->ctl_name = i82860_devs[dev_idx].ctl_name;
 206         mci->dev_name = pci_name(pdev);
 207         mci->edac_check = i82860_check;
 208         mci->ctl_page_to_phys = NULL;
 209         i82860_init_csrows(mci, pdev);
 210         i82860_get_error_info(mci, &discard);   /* clear counters */
 211
 212         /* Here we assume that we will never see multiple instances of this
 213          * type of memory controller.  The ID is therefore hardcoded to 0.
 214          */
 215         if (edac_mc_add_mc(mci)) {
 216                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 217                 goto fail;
 218         }
 219
 220         /* allocating generic PCI control info */
 221         i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
 222         if (!i82860_pci) {
 223                 printk(KERN_WARNING
 224                         "%s(): Unable to create PCI control\n",
 225                         __func__);
 226                 printk(KERN_WARNING
 227                         "%s(): PCI error report via EDAC not setup\n",
 228                         __func__);
 229         }
 230
 231         /* get this far and it's successful */
 232         debugf3("%s(): success\n", __func__);
 233
 234         return 0;
 235
 236 fail:
 237         edac_mc_free(mci);
 238         return -ENODEV;
 239 }
 240
 241 /* returns count (>= 0), or negative on error */
 242 static int __devinit i82860_init_one(struct pci_dev *pdev,
 243                                 const struct pci_device_id *ent)
 244 {
 245         int rc;
 246
 247         debugf0("%s()\n", __func__);
 248         i82860_printk(KERN_INFO, "i82860 init one\n");
 249
 250         if (pci_enable_device(pdev) < 0)
 251                 return -EIO;
 252
 253         rc = i82860_probe1(pdev, ent->driver_data);
 254
 255         if (rc == 0)
 256                 mci_pdev = pci_dev_get(pdev);
 257
 258         return rc;
 259 }
 260
 261 static void __devexit i82860_remove_one(struct pci_dev *pdev)
 262 {
 263         struct mem_ctl_info *mci;
 264
 265         debugf0("%s()\n", __func__);
 266
 267         if (i82860_pci)
 268                 edac_pci_release_generic_ctl(i82860_pci);
 269
 270         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 271                 return;
 272
 273         edac_mc_free(mci);
 274 }
 275
 276 static DEFINE_PCI_DEVICE_TABLE(i82860_pci_tbl) = {
 277         {
 278          PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 279          I82860},
 280         {
 281          0,
 282          }                      /* 0 terminated list. */
 283 };
 284
 285 MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
 286
 287 static struct pci_driver i82860_driver = {
 288         .name = EDAC_MOD_STR,
 289         .probe = i82860_init_one,
 290         .remove = __devexit_p(i82860_remove_one),
 291         .id_table = i82860_pci_tbl,
 292 };
 293
 294 static int __init i82860_init(void)
 295 {
 296         int pci_rc;
 297
 298         debugf3("%s()\n", __func__);
 299
 300        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
 301        opstate_init();
 302
 303         if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
 304                 goto fail0;
 305
 306         if (!mci_pdev) {
 307                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 308                                         PCI_DEVICE_ID_INTEL_82860_0, NULL);
 309
 310                 if (mci_pdev == NULL) {
 311                         debugf0("860 pci_get_device fail\n");
 312                         pci_rc = -ENODEV;
 313                         goto fail1;
 314                 }
 315
 316                 pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
 317
 318                 if (pci_rc < 0) {
 319                         debugf0("860 init fail\n");
 320                         pci_rc = -ENODEV;
 321                         goto fail1;
 322                 }
 323         }
 324
 325         return 0;
 326
 327 fail1:
 328         pci_unregister_driver(&i82860_driver);
 329
 330 fail0:
 331         if (mci_pdev != NULL)
 332                 pci_dev_put(mci_pdev);
 333
 334         return pci_rc;
 335 }
 336
 337 static void __exit i82860_exit(void)
 338 {
 339         debugf3("%s()\n", __func__);
 340
 341         pci_unregister_driver(&i82860_driver);
 342
 343         if (mci_pdev != NULL)
 344                 pci_dev_put(mci_pdev);
 345 }
 346
 347 module_init(i82860_init);
 348 module_exit(i82860_exit);
 349
 350 MODULE_LICENSE("GPL");
 351 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
 352                 "Ben Woodard <woodard@redhat.com>");
 353 MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
 354
 355 module_param(edac_op_state, int, 0444);
 356 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");