drivers/edac/i82860_edac.c

   1 /*
   2  * Intel 82860 Memory Controller kernel module
   3  * (C) 2005 Red Hat (http://www.redhat.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Ben Woodard <woodard@redhat.com>
   8  * shamelessly copied from and based upon the edac_i82875 driver
   9  * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/pci_ids.h>
  16 #include <linux/slab.h>
  17 #include "edac_mc.h"
  18
  19 #define  I82860_REVISION " Ver: 2.0.0 " __DATE__
  20
  21 #define i82860_printk(level, fmt, arg...) \
  22         edac_printk(level, "i82860", fmt, ##arg)
  23
  24 #define i82860_mc_printk(mci, level, fmt, arg...) \
  25         edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
  26
  27 #ifndef PCI_DEVICE_ID_INTEL_82860_0
  28 #define PCI_DEVICE_ID_INTEL_82860_0     0x2531
  29 #endif                          /* PCI_DEVICE_ID_INTEL_82860_0 */
  30
  31 #define I82860_MCHCFG 0x50
  32 #define I82860_GBA 0x60
  33 #define I82860_GBA_MASK 0x7FF
  34 #define I82860_GBA_SHIFT 24
  35 #define I82860_ERRSTS 0xC8
  36 #define I82860_EAP 0xE4
  37 #define I82860_DERRCTL_STS 0xE2
  38
  39 enum i82860_chips {
  40         I82860 = 0,
  41 };
  42
  43 struct i82860_dev_info {
  44         const char *ctl_name;
  45 };
  46
  47 struct i82860_error_info {
  48         u16 errsts;
  49         u32 eap;
  50         u16 derrsyn;
  51         u16 errsts2;
  52 };
  53
  54 static const struct i82860_dev_info i82860_devs[] = {
  55         [I82860] = {
  56                 .ctl_name = "i82860"
  57         },
  58 };
  59
  60 static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code
  61                                          * has already registered driver
  62                                          */
  63
  64 static void i82860_get_error_info(struct mem_ctl_info *mci,
  65                 struct i82860_error_info *info)
  66 {
  67         struct pci_dev *pdev;
  68
  69         pdev = to_pci_dev(mci->dev);
  70
  71         /*
  72          * This is a mess because there is no atomic way to read all the
  73          * registers at once and the registers can transition from CE being
  74          * overwritten by UE.
  75          */
  76         pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
  77         pci_read_config_dword(pdev, I82860_EAP, &info->eap);
  78         pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
  79         pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
  80
  81         pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
  82
  83         /*
  84          * If the error is the same for both reads then the first set of reads
  85          * is valid.  If there is a change then there is a CE no info and the
  86          * second set of reads is valid and should be UE info.
  87          */
  88         if (!(info->errsts2 & 0x0003))
  89                 return;
  90
  91         if ((info->errsts ^ info->errsts2) & 0x0003) {
  92                 pci_read_config_dword(pdev, I82860_EAP, &info->eap);
  93                 pci_read_config_word(pdev, I82860_DERRCTL_STS,
  94                                 &info->derrsyn);
  95         }
  96 }
  97
  98 static int i82860_process_error_info(struct mem_ctl_info *mci,
  99                 struct i82860_error_info *info, int handle_errors)
 100 {
 101         int row;
 102
 103         if (!(info->errsts2 & 0x0003))
 104                 return 0;
 105
 106         if (!handle_errors)
 107                 return 1;
 108
 109         if ((info->errsts ^ info->errsts2) & 0x0003) {
 110                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
 111                 info->errsts = info->errsts2;
 112         }
 113
 114         info->eap >>= PAGE_SHIFT;
 115         row = edac_mc_find_csrow_by_page(mci, info->eap);
 116
 117         if (info->errsts & 0x0002)
 118                 edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
 119         else
 120                 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
 121                                 "i82860 UE");
 122
 123         return 1;
 124 }
 125
 126 static void i82860_check(struct mem_ctl_info *mci)
 127 {
 128         struct i82860_error_info info;
 129
 130         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 131         i82860_get_error_info(mci, &info);
 132         i82860_process_error_info(mci, &info, 1);
 133 }
 134
 135 static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
 136 {
 137         unsigned long last_cumul_size;
 138         u16 mchcfg_ddim;  /* DRAM Data Integrity Mode 0=none, 2=edac */
 139         u16 value;
 140         u32 cumul_size;
 141         struct csrow_info *csrow;
 142         int index;
 143
 144         pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
 145         mchcfg_ddim = mchcfg_ddim & 0x180;
 146         last_cumul_size = 0;
 147
 148         /* The group row boundary (GRA) reg values are boundary address
 149          * for each DRAM row with a granularity of 16MB.  GRA regs are
 150          * cumulative; therefore GRA15 will contain the total memory contained
 151          * in all eight rows.
 152          */
 153         for (index = 0; index < mci->nr_csrows; index++) {
 154                 csrow = &mci->csrows[index];
 155                 pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
 156                 cumul_size = (value & I82860_GBA_MASK) <<
 157                     (I82860_GBA_SHIFT - PAGE_SHIFT);
 158                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 159                         cumul_size);
 160
 161                 if (cumul_size == last_cumul_size)
 162                         continue;       /* not populated */
 163
 164                 csrow->first_page = last_cumul_size;
 165                 csrow->last_page = cumul_size - 1;
 166                 csrow->nr_pages = cumul_size - last_cumul_size;
 167                 last_cumul_size = cumul_size;
 168                 csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
 169                 csrow->mtype = MEM_RMBS;
 170                 csrow->dtype = DEV_UNKNOWN;
 171                 csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
 172         }
 173 }
 174
 175 static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
 176 {
 177         struct mem_ctl_info *mci;
 178         struct i82860_error_info discard;
 179
 180         /* RDRAM has channels but these don't map onto the abstractions that
 181            edac uses.
 182            The device groups from the GRA registers seem to map reasonably
 183            well onto the notion of a chip select row.
 184            There are 16 GRA registers and since the name is associated with
 185            the channel and the GRA registers map to physical devices so we are
 186            going to make 1 channel for group.
 187          */
 188         mci = edac_mc_alloc(0, 16, 1);
 189
 190         if (!mci)
 191                 return -ENOMEM;
 192
 193         debugf3("%s(): init mci\n", __func__);
 194         mci->dev = &pdev->dev;
 195         mci->mtype_cap = MEM_FLAG_DDR;
 196         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 197         /* I"m not sure about this but I think that all RDRAM is SECDED */
 198         mci->edac_cap = EDAC_FLAG_SECDED;
 199         mci->mod_name = EDAC_MOD_STR;
 200         mci->mod_ver = I82860_REVISION;
 201         mci->ctl_name = i82860_devs[dev_idx].ctl_name;
 202         mci->edac_check = i82860_check;
 203         mci->ctl_page_to_phys = NULL;
 204         i82860_init_csrows(mci, pdev);
 205         i82860_get_error_info(mci, &discard);  /* clear counters */
 206
 207         /* Here we assume that we will never see multiple instances of this
 208          * type of memory controller.  The ID is therefore hardcoded to 0.
 209          */
 210         if (edac_mc_add_mc(mci,0)) {
 211                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 212                 goto fail;
 213         }
 214
 215         /* get this far and it's successful */
 216         debugf3("%s(): success\n", __func__);
 217
 218         return 0;
 219
 220 fail:
 221         edac_mc_free(mci);
 222         return -ENODEV;
 223 }
 224
 225 /* returns count (>= 0), or negative on error */
 226 static int __devinit i82860_init_one(struct pci_dev *pdev,
 227                 const struct pci_device_id *ent)
 228 {
 229         int rc;
 230
 231         debugf0("%s()\n", __func__);
 232         i82860_printk(KERN_INFO, "i82860 init one\n");
 233
 234         if (pci_enable_device(pdev) < 0)
 235                 return -EIO;
 236
 237         rc = i82860_probe1(pdev, ent->driver_data);
 238
 239         if (rc == 0)
 240                 mci_pdev = pci_dev_get(pdev);
 241
 242         return rc;
 243 }
 244
 245 static void __devexit i82860_remove_one(struct pci_dev *pdev)
 246 {
 247         struct mem_ctl_info *mci;
 248
 249         debugf0("%s()\n", __func__);
 250
 251         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 252                 return;
 253
 254         edac_mc_free(mci);
 255 }
 256
 257 static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
 258         {
 259                 PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 260                 I82860
 261         },
 262         {
 263                 0,
 264         }       /* 0 terminated list. */
 265 };
 266
 267 MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
 268
 269 static struct pci_driver i82860_driver = {
 270         .name = EDAC_MOD_STR,
 271         .probe = i82860_init_one,
 272         .remove = __devexit_p(i82860_remove_one),
 273         .id_table = i82860_pci_tbl,
 274 };
 275
 276 static int __init i82860_init(void)
 277 {
 278         int pci_rc;
 279
 280         debugf3("%s()\n", __func__);
 281
 282         if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
 283                 goto fail0;
 284
 285         if (!mci_pdev) {
 286                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 287                                         PCI_DEVICE_ID_INTEL_82860_0, NULL);
 288
 289                 if (mci_pdev == NULL) {
 290                         debugf0("860 pci_get_device fail\n");
 291                         pci_rc = -ENODEV;
 292                         goto fail1;
 293                 }
 294
 295                 pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
 296
 297                 if (pci_rc < 0) {
 298                         debugf0("860 init fail\n");
 299                         pci_rc = -ENODEV;
 300                         goto fail1;
 301                 }
 302         }
 303
 304         return 0;
 305
 306 fail1:
 307         pci_unregister_driver(&i82860_driver);
 308
 309 fail0:
 310         if (mci_pdev != NULL)
 311                 pci_dev_put(mci_pdev);
 312
 313         return pci_rc;
 314 }
 315
 316 static void __exit i82860_exit(void)
 317 {
 318         debugf3("%s()\n", __func__);
 319
 320         pci_unregister_driver(&i82860_driver);
 321
 322         if (mci_pdev != NULL)
 323                 pci_dev_put(mci_pdev);
 324 }
 325
 326 module_init(i82860_init);
 327 module_exit(i82860_exit);
 328
 329 MODULE_LICENSE("GPL");
 330 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
 331         "Ben Woodard <woodard@redhat.com>");
 332 MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");