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x86/mce: Kill drain_mcelog_buffer()
[deliverable/linux.git] / drivers / edac / sb_edac.c
1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab
11 */
12
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
25 #include <asm/mce.h>
26
27 #include "edac_core.h"
28
29 /* Static vars */
30 static LIST_HEAD(sbridge_edac_list);
31 static DEFINE_MUTEX(sbridge_edac_lock);
32 static int probed;
33
34 /*
35 * Alter this version for the module when modifications are made
36 */
37 #define SBRIDGE_REVISION " Ver: 1.1.1 "
38 #define EDAC_MOD_STR "sbridge_edac"
39
40 /*
41 * Debug macros
42 */
43 #define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46 #define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49 /*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52 #define GET_BITFIELD(v, lo, hi) \
53 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
54
55 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
56 static const u32 sbridge_dram_rule[] = {
57 0x80, 0x88, 0x90, 0x98, 0xa0,
58 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
59 };
60
61 static const u32 ibridge_dram_rule[] = {
62 0x60, 0x68, 0x70, 0x78, 0x80,
63 0x88, 0x90, 0x98, 0xa0, 0xa8,
64 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
65 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
66 };
67
68 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
69 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
70 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
71 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
72 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
73
74 static char *get_dram_attr(u32 reg)
75 {
76 switch(DRAM_ATTR(reg)) {
77 case 0:
78 return "DRAM";
79 case 1:
80 return "MMCFG";
81 case 2:
82 return "NXM";
83 default:
84 return "unknown";
85 }
86 }
87
88 static const u32 sbridge_interleave_list[] = {
89 0x84, 0x8c, 0x94, 0x9c, 0xa4,
90 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
91 };
92
93 static const u32 ibridge_interleave_list[] = {
94 0x64, 0x6c, 0x74, 0x7c, 0x84,
95 0x8c, 0x94, 0x9c, 0xa4, 0xac,
96 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
97 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
98 };
99
100 struct interleave_pkg {
101 unsigned char start;
102 unsigned char end;
103 };
104
105 static const struct interleave_pkg sbridge_interleave_pkg[] = {
106 { 0, 2 },
107 { 3, 5 },
108 { 8, 10 },
109 { 11, 13 },
110 { 16, 18 },
111 { 19, 21 },
112 { 24, 26 },
113 { 27, 29 },
114 };
115
116 static const struct interleave_pkg ibridge_interleave_pkg[] = {
117 { 0, 3 },
118 { 4, 7 },
119 { 8, 11 },
120 { 12, 15 },
121 { 16, 19 },
122 { 20, 23 },
123 { 24, 27 },
124 { 28, 31 },
125 };
126
127 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
128 int interleave)
129 {
130 return GET_BITFIELD(reg, table[interleave].start,
131 table[interleave].end);
132 }
133
134 /* Devices 12 Function 7 */
135
136 #define TOLM 0x80
137 #define TOHM 0x84
138 #define HASWELL_TOLM 0xd0
139 #define HASWELL_TOHM_0 0xd4
140 #define HASWELL_TOHM_1 0xd8
141
142 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
143 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
144
145 /* Device 13 Function 6 */
146
147 #define SAD_TARGET 0xf0
148
149 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
150
151 #define SAD_CONTROL 0xf4
152
153 /* Device 14 function 0 */
154
155 static const u32 tad_dram_rule[] = {
156 0x40, 0x44, 0x48, 0x4c,
157 0x50, 0x54, 0x58, 0x5c,
158 0x60, 0x64, 0x68, 0x6c,
159 };
160 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
161
162 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
163 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
164 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
165 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
166 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
167 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
168 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
169
170 /* Device 15, function 0 */
171
172 #define MCMTR 0x7c
173
174 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
175 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
176 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
177
178 /* Device 15, function 1 */
179
180 #define RASENABLES 0xac
181 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
182
183 /* Device 15, functions 2-5 */
184
185 static const int mtr_regs[] = {
186 0x80, 0x84, 0x88,
187 };
188
189 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
190 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
191 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
192 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
193 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
194
195 static const u32 tad_ch_nilv_offset[] = {
196 0x90, 0x94, 0x98, 0x9c,
197 0xa0, 0xa4, 0xa8, 0xac,
198 0xb0, 0xb4, 0xb8, 0xbc,
199 };
200 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
201 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
202
203 static const u32 rir_way_limit[] = {
204 0x108, 0x10c, 0x110, 0x114, 0x118,
205 };
206 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
207
208 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
209 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
210
211 #define MAX_RIR_WAY 8
212
213 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
214 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
215 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
216 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
217 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
218 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
219 };
220
221 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
222 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
223
224 /* Device 16, functions 2-7 */
225
226 /*
227 * FIXME: Implement the error count reads directly
228 */
229
230 static const u32 correrrcnt[] = {
231 0x104, 0x108, 0x10c, 0x110,
232 };
233
234 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
235 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
236 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
237 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
238
239 static const u32 correrrthrsld[] = {
240 0x11c, 0x120, 0x124, 0x128,
241 };
242
243 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
244 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
245
246
247 /* Device 17, function 0 */
248
249 #define SB_RANK_CFG_A 0x0328
250
251 #define IB_RANK_CFG_A 0x0320
252
253 /*
254 * sbridge structs
255 */
256
257 #define NUM_CHANNELS 8 /* 2MC per socket, four chan per MC */
258 #define MAX_DIMMS 3 /* Max DIMMS per channel */
259 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
260
261 enum type {
262 SANDY_BRIDGE,
263 IVY_BRIDGE,
264 HASWELL,
265 BROADWELL,
266 };
267
268 struct sbridge_pvt;
269 struct sbridge_info {
270 enum type type;
271 u32 mcmtr;
272 u32 rankcfgr;
273 u64 (*get_tolm)(struct sbridge_pvt *pvt);
274 u64 (*get_tohm)(struct sbridge_pvt *pvt);
275 u64 (*rir_limit)(u32 reg);
276 const u32 *dram_rule;
277 const u32 *interleave_list;
278 const struct interleave_pkg *interleave_pkg;
279 u8 max_sad;
280 u8 max_interleave;
281 u8 (*get_node_id)(struct sbridge_pvt *pvt);
282 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
283 struct pci_dev *pci_vtd;
284 };
285
286 struct sbridge_channel {
287 u32 ranks;
288 u32 dimms;
289 };
290
291 struct pci_id_descr {
292 int dev_id;
293 int optional;
294 };
295
296 struct pci_id_table {
297 const struct pci_id_descr *descr;
298 int n_devs;
299 };
300
301 struct sbridge_dev {
302 struct list_head list;
303 u8 bus, mc;
304 u8 node_id, source_id;
305 struct pci_dev **pdev;
306 int n_devs;
307 struct mem_ctl_info *mci;
308 };
309
310 struct sbridge_pvt {
311 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
312 struct pci_dev *pci_sad0, *pci_sad1;
313 struct pci_dev *pci_ha0, *pci_ha1;
314 struct pci_dev *pci_br0, *pci_br1;
315 struct pci_dev *pci_ha1_ta;
316 struct pci_dev *pci_tad[NUM_CHANNELS];
317
318 struct sbridge_dev *sbridge_dev;
319
320 struct sbridge_info info;
321 struct sbridge_channel channel[NUM_CHANNELS];
322
323 /* Memory type detection */
324 bool is_mirrored, is_lockstep, is_close_pg;
325
326 /* Fifo double buffers */
327 struct mce mce_entry[MCE_LOG_LEN];
328 struct mce mce_outentry[MCE_LOG_LEN];
329
330 /* Fifo in/out counters */
331 unsigned mce_in, mce_out;
332
333 /* Count indicator to show errors not got */
334 unsigned mce_overrun;
335
336 /* Memory description */
337 u64 tolm, tohm;
338 };
339
340 #define PCI_DESCR(device_id, opt) \
341 .dev_id = (device_id), \
342 .optional = opt
343
344 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
345 /* Processor Home Agent */
346 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
347
348 /* Memory controller */
349 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
350 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
351 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
352 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
353 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
354 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
355 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
356
357 /* System Address Decoder */
358 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
359 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
360
361 /* Broadcast Registers */
362 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
363 };
364
365 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
366 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
367 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
368 {0,} /* 0 terminated list. */
369 };
370
371 /* This changes depending if 1HA or 2HA:
372 * 1HA:
373 * 0x0eb8 (17.0) is DDRIO0
374 * 2HA:
375 * 0x0ebc (17.4) is DDRIO0
376 */
377 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
378 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
379
380 /* pci ids */
381 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
382 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
383 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
384 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
385 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
386 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
387 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
388 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
389 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
390 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
391 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
392 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
393 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
394 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
395 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
396 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c
397 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d
398
399 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
400 /* Processor Home Agent */
401 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) },
402
403 /* Memory controller */
404 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) },
405 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) },
406 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) },
407 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) },
408 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) },
409 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) },
410
411 /* System Address Decoder */
412 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) },
413
414 /* Broadcast Registers */
415 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) },
416 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) },
417
418 /* Optional, mode 2HA */
419 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
420 #if 0
421 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
422 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
423 #endif
424 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
425 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
426 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1) },
427 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1) },
428
429 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
430 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
431 };
432
433 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
434 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
435 {0,} /* 0 terminated list. */
436 };
437
438 /* Haswell support */
439 /* EN processor:
440 * - 1 IMC
441 * - 3 DDR3 channels, 2 DPC per channel
442 * EP processor:
443 * - 1 or 2 IMC
444 * - 4 DDR4 channels, 3 DPC per channel
445 * EP 4S processor:
446 * - 2 IMC
447 * - 4 DDR4 channels, 3 DPC per channel
448 * EX processor:
449 * - 2 IMC
450 * - each IMC interfaces with a SMI 2 channel
451 * - each SMI channel interfaces with a scalable memory buffer
452 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
453 */
454 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
455 #define HASWELL_HASYSDEFEATURE2 0x84
456 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
457 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
458 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
459 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
460 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
461 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
462 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
463 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
464 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
465 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
466 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
467 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
468 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
469 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
470 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
471 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
472 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
473 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
474 static const struct pci_id_descr pci_dev_descr_haswell[] = {
475 /* first item must be the HA */
476 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
477
478 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) },
479 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) },
480
481 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) },
482
483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) },
484 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) },
485 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) },
486 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) },
487 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) },
488 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
489
490 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
491
492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
493 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
494 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) },
495 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) },
496 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) },
497 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) },
498 };
499
500 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
501 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
502 {0,} /* 0 terminated list. */
503 };
504
505 /*
506 * Broadwell support
507 *
508 * DE processor:
509 * - 1 IMC
510 * - 2 DDR3 channels, 2 DPC per channel
511 * EP processor:
512 * - 1 or 2 IMC
513 * - 4 DDR4 channels, 3 DPC per channel
514 * EP 4S processor:
515 * - 2 IMC
516 * - 4 DDR4 channels, 3 DPC per channel
517 * EX processor:
518 * - 2 IMC
519 * - each IMC interfaces with a SMI 2 channel
520 * - each SMI channel interfaces with a scalable memory buffer
521 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
522 */
523 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
524 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
525 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60
526 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
527 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
528 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68
529 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
530 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
531 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
532 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
533 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
534 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
535 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
536 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
537 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
538 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
539 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
540 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
541
542 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
543 /* first item must be the HA */
544 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) },
545
546 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) },
547 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) },
548
549 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1) },
550
551 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) },
552 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) },
553 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) },
554 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) },
555 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1) },
556 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1) },
557
558 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) },
559
560 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1) },
561 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1) },
562 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1) },
563 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1) },
564 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1) },
565 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1) },
566 };
567
568 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
569 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
570 {0,} /* 0 terminated list. */
571 };
572
573 /*
574 * pci_device_id table for which devices we are looking for
575 */
576 static const struct pci_device_id sbridge_pci_tbl[] = {
577 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
578 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
579 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
580 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
581 {0,} /* 0 terminated list. */
582 };
583
584
585 /****************************************************************************
586 Ancillary status routines
587 ****************************************************************************/
588
589 static inline int numrank(enum type type, u32 mtr)
590 {
591 int ranks = (1 << RANK_CNT_BITS(mtr));
592 int max = 4;
593
594 if (type == HASWELL || type == BROADWELL)
595 max = 8;
596
597 if (ranks > max) {
598 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
599 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
600 return -EINVAL;
601 }
602
603 return ranks;
604 }
605
606 static inline int numrow(u32 mtr)
607 {
608 int rows = (RANK_WIDTH_BITS(mtr) + 12);
609
610 if (rows < 13 || rows > 18) {
611 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
612 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
613 return -EINVAL;
614 }
615
616 return 1 << rows;
617 }
618
619 static inline int numcol(u32 mtr)
620 {
621 int cols = (COL_WIDTH_BITS(mtr) + 10);
622
623 if (cols > 12) {
624 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
625 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
626 return -EINVAL;
627 }
628
629 return 1 << cols;
630 }
631
632 static struct sbridge_dev *get_sbridge_dev(u8 bus)
633 {
634 struct sbridge_dev *sbridge_dev;
635
636 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
637 if (sbridge_dev->bus == bus)
638 return sbridge_dev;
639 }
640
641 return NULL;
642 }
643
644 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
645 const struct pci_id_table *table)
646 {
647 struct sbridge_dev *sbridge_dev;
648
649 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
650 if (!sbridge_dev)
651 return NULL;
652
653 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
654 GFP_KERNEL);
655 if (!sbridge_dev->pdev) {
656 kfree(sbridge_dev);
657 return NULL;
658 }
659
660 sbridge_dev->bus = bus;
661 sbridge_dev->n_devs = table->n_devs;
662 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
663
664 return sbridge_dev;
665 }
666
667 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
668 {
669 list_del(&sbridge_dev->list);
670 kfree(sbridge_dev->pdev);
671 kfree(sbridge_dev);
672 }
673
674 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
675 {
676 u32 reg;
677
678 /* Address range is 32:28 */
679 pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
680 return GET_TOLM(reg);
681 }
682
683 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
684 {
685 u32 reg;
686
687 pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
688 return GET_TOHM(reg);
689 }
690
691 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
692 {
693 u32 reg;
694
695 pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
696
697 return GET_TOLM(reg);
698 }
699
700 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
701 {
702 u32 reg;
703
704 pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
705
706 return GET_TOHM(reg);
707 }
708
709 static u64 rir_limit(u32 reg)
710 {
711 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
712 }
713
714 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
715 {
716 u32 reg;
717 enum mem_type mtype;
718
719 if (pvt->pci_ddrio) {
720 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
721 &reg);
722 if (GET_BITFIELD(reg, 11, 11))
723 /* FIXME: Can also be LRDIMM */
724 mtype = MEM_RDDR3;
725 else
726 mtype = MEM_DDR3;
727 } else
728 mtype = MEM_UNKNOWN;
729
730 return mtype;
731 }
732
733 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
734 {
735 u32 reg;
736 bool registered = false;
737 enum mem_type mtype = MEM_UNKNOWN;
738
739 if (!pvt->pci_ddrio)
740 goto out;
741
742 pci_read_config_dword(pvt->pci_ddrio,
743 HASWELL_DDRCRCLKCONTROLS, &reg);
744 /* Is_Rdimm */
745 if (GET_BITFIELD(reg, 16, 16))
746 registered = true;
747
748 pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
749 if (GET_BITFIELD(reg, 14, 14)) {
750 if (registered)
751 mtype = MEM_RDDR4;
752 else
753 mtype = MEM_DDR4;
754 } else {
755 if (registered)
756 mtype = MEM_RDDR3;
757 else
758 mtype = MEM_DDR3;
759 }
760
761 out:
762 return mtype;
763 }
764
765 static u8 get_node_id(struct sbridge_pvt *pvt)
766 {
767 u32 reg;
768 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
769 return GET_BITFIELD(reg, 0, 2);
770 }
771
772 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
773 {
774 u32 reg;
775
776 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
777 return GET_BITFIELD(reg, 0, 3);
778 }
779
780 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
781 {
782 u32 reg;
783
784 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
785 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
786 }
787
788 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
789 {
790 u64 rc;
791 u32 reg;
792
793 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
794 rc = GET_BITFIELD(reg, 26, 31);
795 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
796 rc = ((reg << 6) | rc) << 26;
797
798 return rc | 0x1ffffff;
799 }
800
801 static u64 haswell_rir_limit(u32 reg)
802 {
803 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
804 }
805
806 static inline u8 sad_pkg_socket(u8 pkg)
807 {
808 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
809 return ((pkg >> 3) << 2) | (pkg & 0x3);
810 }
811
812 static inline u8 sad_pkg_ha(u8 pkg)
813 {
814 return (pkg >> 2) & 0x1;
815 }
816
817 /****************************************************************************
818 Memory check routines
819 ****************************************************************************/
820 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
821 {
822 struct pci_dev *pdev = NULL;
823
824 do {
825 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
826 if (pdev && pdev->bus->number == bus)
827 break;
828 } while (pdev);
829
830 return pdev;
831 }
832
833 /**
834 * check_if_ecc_is_active() - Checks if ECC is active
835 * @bus: Device bus
836 * @type: Memory controller type
837 * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
838 * disabled
839 */
840 static int check_if_ecc_is_active(const u8 bus, enum type type)
841 {
842 struct pci_dev *pdev = NULL;
843 u32 mcmtr, id;
844
845 switch (type) {
846 case IVY_BRIDGE:
847 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
848 break;
849 case HASWELL:
850 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
851 break;
852 case SANDY_BRIDGE:
853 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
854 break;
855 case BROADWELL:
856 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
857 break;
858 default:
859 return -ENODEV;
860 }
861
862 pdev = get_pdev_same_bus(bus, id);
863 if (!pdev) {
864 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
865 "%04x:%04x! on bus %02d\n",
866 PCI_VENDOR_ID_INTEL, id, bus);
867 return -ENODEV;
868 }
869
870 pci_read_config_dword(pdev, MCMTR, &mcmtr);
871 if (!IS_ECC_ENABLED(mcmtr)) {
872 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
873 return -ENODEV;
874 }
875 return 0;
876 }
877
878 static int get_dimm_config(struct mem_ctl_info *mci)
879 {
880 struct sbridge_pvt *pvt = mci->pvt_info;
881 struct dimm_info *dimm;
882 unsigned i, j, banks, ranks, rows, cols, npages;
883 u64 size;
884 u32 reg;
885 enum edac_type mode;
886 enum mem_type mtype;
887
888 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL)
889 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
890 else
891 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
892
893 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
894
895 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
896 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
897 pvt->sbridge_dev->mc,
898 pvt->sbridge_dev->node_id,
899 pvt->sbridge_dev->source_id);
900
901 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
902 if (IS_MIRROR_ENABLED(reg)) {
903 edac_dbg(0, "Memory mirror is enabled\n");
904 pvt->is_mirrored = true;
905 } else {
906 edac_dbg(0, "Memory mirror is disabled\n");
907 pvt->is_mirrored = false;
908 }
909
910 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
911 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
912 edac_dbg(0, "Lockstep is enabled\n");
913 mode = EDAC_S8ECD8ED;
914 pvt->is_lockstep = true;
915 } else {
916 edac_dbg(0, "Lockstep is disabled\n");
917 mode = EDAC_S4ECD4ED;
918 pvt->is_lockstep = false;
919 }
920 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
921 edac_dbg(0, "address map is on closed page mode\n");
922 pvt->is_close_pg = true;
923 } else {
924 edac_dbg(0, "address map is on open page mode\n");
925 pvt->is_close_pg = false;
926 }
927
928 mtype = pvt->info.get_memory_type(pvt);
929 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
930 edac_dbg(0, "Memory is registered\n");
931 else if (mtype == MEM_UNKNOWN)
932 edac_dbg(0, "Cannot determine memory type\n");
933 else
934 edac_dbg(0, "Memory is unregistered\n");
935
936 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
937 banks = 16;
938 else
939 banks = 8;
940
941 for (i = 0; i < NUM_CHANNELS; i++) {
942 u32 mtr;
943
944 if (!pvt->pci_tad[i])
945 continue;
946 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
947 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
948 i, j, 0);
949 pci_read_config_dword(pvt->pci_tad[i],
950 mtr_regs[j], &mtr);
951 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
952 if (IS_DIMM_PRESENT(mtr)) {
953 pvt->channel[i].dimms++;
954
955 ranks = numrank(pvt->info.type, mtr);
956 rows = numrow(mtr);
957 cols = numcol(mtr);
958
959 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
960 npages = MiB_TO_PAGES(size);
961
962 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
963 pvt->sbridge_dev->mc, i/4, i%4, j,
964 size, npages,
965 banks, ranks, rows, cols);
966
967 dimm->nr_pages = npages;
968 dimm->grain = 32;
969 switch (banks) {
970 case 16:
971 dimm->dtype = DEV_X16;
972 break;
973 case 8:
974 dimm->dtype = DEV_X8;
975 break;
976 case 4:
977 dimm->dtype = DEV_X4;
978 break;
979 }
980 dimm->mtype = mtype;
981 dimm->edac_mode = mode;
982 snprintf(dimm->label, sizeof(dimm->label),
983 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
984 pvt->sbridge_dev->source_id, i/4, i%4, j);
985 }
986 }
987 }
988
989 return 0;
990 }
991
992 static void get_memory_layout(const struct mem_ctl_info *mci)
993 {
994 struct sbridge_pvt *pvt = mci->pvt_info;
995 int i, j, k, n_sads, n_tads, sad_interl;
996 u32 reg;
997 u64 limit, prv = 0;
998 u64 tmp_mb;
999 u32 gb, mb;
1000 u32 rir_way;
1001
1002 /*
1003 * Step 1) Get TOLM/TOHM ranges
1004 */
1005
1006 pvt->tolm = pvt->info.get_tolm(pvt);
1007 tmp_mb = (1 + pvt->tolm) >> 20;
1008
1009 gb = div_u64_rem(tmp_mb, 1024, &mb);
1010 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1011 gb, (mb*1000)/1024, (u64)pvt->tolm);
1012
1013 /* Address range is already 45:25 */
1014 pvt->tohm = pvt->info.get_tohm(pvt);
1015 tmp_mb = (1 + pvt->tohm) >> 20;
1016
1017 gb = div_u64_rem(tmp_mb, 1024, &mb);
1018 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1019 gb, (mb*1000)/1024, (u64)pvt->tohm);
1020
1021 /*
1022 * Step 2) Get SAD range and SAD Interleave list
1023 * TAD registers contain the interleave wayness. However, it
1024 * seems simpler to just discover it indirectly, with the
1025 * algorithm bellow.
1026 */
1027 prv = 0;
1028 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1029 /* SAD_LIMIT Address range is 45:26 */
1030 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1031 &reg);
1032 limit = SAD_LIMIT(reg);
1033
1034 if (!DRAM_RULE_ENABLE(reg))
1035 continue;
1036
1037 if (limit <= prv)
1038 break;
1039
1040 tmp_mb = (limit + 1) >> 20;
1041 gb = div_u64_rem(tmp_mb, 1024, &mb);
1042 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1043 n_sads,
1044 get_dram_attr(reg),
1045 gb, (mb*1000)/1024,
1046 ((u64)tmp_mb) << 20L,
1047 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
1048 reg);
1049 prv = limit;
1050
1051 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1052 &reg);
1053 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1054 for (j = 0; j < 8; j++) {
1055 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1056 if (j > 0 && sad_interl == pkg)
1057 break;
1058
1059 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1060 n_sads, j, pkg);
1061 }
1062 }
1063
1064 /*
1065 * Step 3) Get TAD range
1066 */
1067 prv = 0;
1068 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1069 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1070 &reg);
1071 limit = TAD_LIMIT(reg);
1072 if (limit <= prv)
1073 break;
1074 tmp_mb = (limit + 1) >> 20;
1075
1076 gb = div_u64_rem(tmp_mb, 1024, &mb);
1077 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1078 n_tads, gb, (mb*1000)/1024,
1079 ((u64)tmp_mb) << 20L,
1080 (u32)TAD_SOCK(reg),
1081 (u32)TAD_CH(reg),
1082 (u32)TAD_TGT0(reg),
1083 (u32)TAD_TGT1(reg),
1084 (u32)TAD_TGT2(reg),
1085 (u32)TAD_TGT3(reg),
1086 reg);
1087 prv = limit;
1088 }
1089
1090 /*
1091 * Step 4) Get TAD offsets, per each channel
1092 */
1093 for (i = 0; i < NUM_CHANNELS; i++) {
1094 if (!pvt->channel[i].dimms)
1095 continue;
1096 for (j = 0; j < n_tads; j++) {
1097 pci_read_config_dword(pvt->pci_tad[i],
1098 tad_ch_nilv_offset[j],
1099 &reg);
1100 tmp_mb = TAD_OFFSET(reg) >> 20;
1101 gb = div_u64_rem(tmp_mb, 1024, &mb);
1102 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1103 i, j,
1104 gb, (mb*1000)/1024,
1105 ((u64)tmp_mb) << 20L,
1106 reg);
1107 }
1108 }
1109
1110 /*
1111 * Step 6) Get RIR Wayness/Limit, per each channel
1112 */
1113 for (i = 0; i < NUM_CHANNELS; i++) {
1114 if (!pvt->channel[i].dimms)
1115 continue;
1116 for (j = 0; j < MAX_RIR_RANGES; j++) {
1117 pci_read_config_dword(pvt->pci_tad[i],
1118 rir_way_limit[j],
1119 &reg);
1120
1121 if (!IS_RIR_VALID(reg))
1122 continue;
1123
1124 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1125 rir_way = 1 << RIR_WAY(reg);
1126 gb = div_u64_rem(tmp_mb, 1024, &mb);
1127 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1128 i, j,
1129 gb, (mb*1000)/1024,
1130 ((u64)tmp_mb) << 20L,
1131 rir_way,
1132 reg);
1133
1134 for (k = 0; k < rir_way; k++) {
1135 pci_read_config_dword(pvt->pci_tad[i],
1136 rir_offset[j][k],
1137 &reg);
1138 tmp_mb = RIR_OFFSET(reg) << 6;
1139
1140 gb = div_u64_rem(tmp_mb, 1024, &mb);
1141 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1142 i, j, k,
1143 gb, (mb*1000)/1024,
1144 ((u64)tmp_mb) << 20L,
1145 (u32)RIR_RNK_TGT(reg),
1146 reg);
1147 }
1148 }
1149 }
1150 }
1151
1152 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1153 {
1154 struct sbridge_dev *sbridge_dev;
1155
1156 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1157 if (sbridge_dev->node_id == node_id)
1158 return sbridge_dev->mci;
1159 }
1160 return NULL;
1161 }
1162
1163 static int get_memory_error_data(struct mem_ctl_info *mci,
1164 u64 addr,
1165 u8 *socket, u8 *ha,
1166 long *channel_mask,
1167 u8 *rank,
1168 char **area_type, char *msg)
1169 {
1170 struct mem_ctl_info *new_mci;
1171 struct sbridge_pvt *pvt = mci->pvt_info;
1172 struct pci_dev *pci_ha;
1173 int n_rir, n_sads, n_tads, sad_way, sck_xch;
1174 int sad_interl, idx, base_ch;
1175 int interleave_mode, shiftup = 0;
1176 unsigned sad_interleave[pvt->info.max_interleave];
1177 u32 reg, dram_rule;
1178 u8 ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
1179 u32 tad_offset;
1180 u32 rir_way;
1181 u32 mb, gb;
1182 u64 ch_addr, offset, limit = 0, prv = 0;
1183
1184
1185 /*
1186 * Step 0) Check if the address is at special memory ranges
1187 * The check bellow is probably enough to fill all cases where
1188 * the error is not inside a memory, except for the legacy
1189 * range (e. g. VGA addresses). It is unlikely, however, that the
1190 * memory controller would generate an error on that range.
1191 */
1192 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1193 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1194 return -EINVAL;
1195 }
1196 if (addr >= (u64)pvt->tohm) {
1197 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1198 return -EINVAL;
1199 }
1200
1201 /*
1202 * Step 1) Get socket
1203 */
1204 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1205 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1206 &reg);
1207
1208 if (!DRAM_RULE_ENABLE(reg))
1209 continue;
1210
1211 limit = SAD_LIMIT(reg);
1212 if (limit <= prv) {
1213 sprintf(msg, "Can't discover the memory socket");
1214 return -EINVAL;
1215 }
1216 if (addr <= limit)
1217 break;
1218 prv = limit;
1219 }
1220 if (n_sads == pvt->info.max_sad) {
1221 sprintf(msg, "Can't discover the memory socket");
1222 return -EINVAL;
1223 }
1224 dram_rule = reg;
1225 *area_type = get_dram_attr(dram_rule);
1226 interleave_mode = INTERLEAVE_MODE(dram_rule);
1227
1228 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1229 &reg);
1230
1231 if (pvt->info.type == SANDY_BRIDGE) {
1232 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1233 for (sad_way = 0; sad_way < 8; sad_way++) {
1234 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1235 if (sad_way > 0 && sad_interl == pkg)
1236 break;
1237 sad_interleave[sad_way] = pkg;
1238 edac_dbg(0, "SAD interleave #%d: %d\n",
1239 sad_way, sad_interleave[sad_way]);
1240 }
1241 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1242 pvt->sbridge_dev->mc,
1243 n_sads,
1244 addr,
1245 limit,
1246 sad_way + 7,
1247 !interleave_mode ? "" : "XOR[18:16]");
1248 if (interleave_mode)
1249 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1250 else
1251 idx = (addr >> 6) & 7;
1252 switch (sad_way) {
1253 case 1:
1254 idx = 0;
1255 break;
1256 case 2:
1257 idx = idx & 1;
1258 break;
1259 case 4:
1260 idx = idx & 3;
1261 break;
1262 case 8:
1263 break;
1264 default:
1265 sprintf(msg, "Can't discover socket interleave");
1266 return -EINVAL;
1267 }
1268 *socket = sad_interleave[idx];
1269 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1270 idx, sad_way, *socket);
1271 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1272 int bits, a7mode = A7MODE(dram_rule);
1273
1274 if (a7mode) {
1275 /* A7 mode swaps P9 with P6 */
1276 bits = GET_BITFIELD(addr, 7, 8) << 1;
1277 bits |= GET_BITFIELD(addr, 9, 9);
1278 } else
1279 bits = GET_BITFIELD(addr, 6, 8);
1280
1281 if (interleave_mode == 0) {
1282 /* interleave mode will XOR {8,7,6} with {18,17,16} */
1283 idx = GET_BITFIELD(addr, 16, 18);
1284 idx ^= bits;
1285 } else
1286 idx = bits;
1287
1288 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1289 *socket = sad_pkg_socket(pkg);
1290 sad_ha = sad_pkg_ha(pkg);
1291 if (sad_ha)
1292 ch_add = 4;
1293
1294 if (a7mode) {
1295 /* MCChanShiftUpEnable */
1296 pci_read_config_dword(pvt->pci_ha0,
1297 HASWELL_HASYSDEFEATURE2, &reg);
1298 shiftup = GET_BITFIELD(reg, 22, 22);
1299 }
1300
1301 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
1302 idx, *socket, sad_ha, shiftup);
1303 } else {
1304 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
1305 idx = (addr >> 6) & 7;
1306 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1307 *socket = sad_pkg_socket(pkg);
1308 sad_ha = sad_pkg_ha(pkg);
1309 if (sad_ha)
1310 ch_add = 4;
1311 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
1312 idx, *socket, sad_ha);
1313 }
1314
1315 *ha = sad_ha;
1316
1317 /*
1318 * Move to the proper node structure, in order to access the
1319 * right PCI registers
1320 */
1321 new_mci = get_mci_for_node_id(*socket);
1322 if (!new_mci) {
1323 sprintf(msg, "Struct for socket #%u wasn't initialized",
1324 *socket);
1325 return -EINVAL;
1326 }
1327 mci = new_mci;
1328 pvt = mci->pvt_info;
1329
1330 /*
1331 * Step 2) Get memory channel
1332 */
1333 prv = 0;
1334 if (pvt->info.type == SANDY_BRIDGE)
1335 pci_ha = pvt->pci_ha0;
1336 else {
1337 if (sad_ha)
1338 pci_ha = pvt->pci_ha1;
1339 else
1340 pci_ha = pvt->pci_ha0;
1341 }
1342 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1343 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
1344 limit = TAD_LIMIT(reg);
1345 if (limit <= prv) {
1346 sprintf(msg, "Can't discover the memory channel");
1347 return -EINVAL;
1348 }
1349 if (addr <= limit)
1350 break;
1351 prv = limit;
1352 }
1353 if (n_tads == MAX_TAD) {
1354 sprintf(msg, "Can't discover the memory channel");
1355 return -EINVAL;
1356 }
1357
1358 ch_way = TAD_CH(reg) + 1;
1359 sck_way = TAD_SOCK(reg) + 1;
1360
1361 if (ch_way == 3)
1362 idx = addr >> 6;
1363 else
1364 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
1365 idx = idx % ch_way;
1366
1367 /*
1368 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1369 */
1370 switch (idx) {
1371 case 0:
1372 base_ch = TAD_TGT0(reg);
1373 break;
1374 case 1:
1375 base_ch = TAD_TGT1(reg);
1376 break;
1377 case 2:
1378 base_ch = TAD_TGT2(reg);
1379 break;
1380 case 3:
1381 base_ch = TAD_TGT3(reg);
1382 break;
1383 default:
1384 sprintf(msg, "Can't discover the TAD target");
1385 return -EINVAL;
1386 }
1387 *channel_mask = 1 << base_ch;
1388
1389 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1390 tad_ch_nilv_offset[n_tads],
1391 &tad_offset);
1392
1393 if (pvt->is_mirrored) {
1394 *channel_mask |= 1 << ((base_ch + 2) % 4);
1395 switch(ch_way) {
1396 case 2:
1397 case 4:
1398 sck_xch = 1 << sck_way * (ch_way >> 1);
1399 break;
1400 default:
1401 sprintf(msg, "Invalid mirror set. Can't decode addr");
1402 return -EINVAL;
1403 }
1404 } else
1405 sck_xch = (1 << sck_way) * ch_way;
1406
1407 if (pvt->is_lockstep)
1408 *channel_mask |= 1 << ((base_ch + 1) % 4);
1409
1410 offset = TAD_OFFSET(tad_offset);
1411
1412 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1413 n_tads,
1414 addr,
1415 limit,
1416 (u32)TAD_SOCK(reg),
1417 ch_way,
1418 offset,
1419 idx,
1420 base_ch,
1421 *channel_mask);
1422
1423 /* Calculate channel address */
1424 /* Remove the TAD offset */
1425
1426 if (offset > addr) {
1427 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1428 offset, addr);
1429 return -EINVAL;
1430 }
1431 addr -= offset;
1432 /* Store the low bits [0:6] of the addr */
1433 ch_addr = addr & 0x7f;
1434 /* Remove socket wayness and remove 6 bits */
1435 addr >>= 6;
1436 addr = div_u64(addr, sck_xch);
1437 #if 0
1438 /* Divide by channel way */
1439 addr = addr / ch_way;
1440 #endif
1441 /* Recover the last 6 bits */
1442 ch_addr |= addr << 6;
1443
1444 /*
1445 * Step 3) Decode rank
1446 */
1447 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1448 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1449 rir_way_limit[n_rir],
1450 &reg);
1451
1452 if (!IS_RIR_VALID(reg))
1453 continue;
1454
1455 limit = pvt->info.rir_limit(reg);
1456 gb = div_u64_rem(limit >> 20, 1024, &mb);
1457 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1458 n_rir,
1459 gb, (mb*1000)/1024,
1460 limit,
1461 1 << RIR_WAY(reg));
1462 if (ch_addr <= limit)
1463 break;
1464 }
1465 if (n_rir == MAX_RIR_RANGES) {
1466 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1467 ch_addr);
1468 return -EINVAL;
1469 }
1470 rir_way = RIR_WAY(reg);
1471
1472 if (pvt->is_close_pg)
1473 idx = (ch_addr >> 6);
1474 else
1475 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1476 idx %= 1 << rir_way;
1477
1478 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1479 rir_offset[n_rir][idx],
1480 &reg);
1481 *rank = RIR_RNK_TGT(reg);
1482
1483 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1484 n_rir,
1485 ch_addr,
1486 limit,
1487 rir_way,
1488 idx);
1489
1490 return 0;
1491 }
1492
1493 /****************************************************************************
1494 Device initialization routines: put/get, init/exit
1495 ****************************************************************************/
1496
1497 /*
1498 * sbridge_put_all_devices 'put' all the devices that we have
1499 * reserved via 'get'
1500 */
1501 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1502 {
1503 int i;
1504
1505 edac_dbg(0, "\n");
1506 for (i = 0; i < sbridge_dev->n_devs; i++) {
1507 struct pci_dev *pdev = sbridge_dev->pdev[i];
1508 if (!pdev)
1509 continue;
1510 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1511 pdev->bus->number,
1512 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1513 pci_dev_put(pdev);
1514 }
1515 }
1516
1517 static void sbridge_put_all_devices(void)
1518 {
1519 struct sbridge_dev *sbridge_dev, *tmp;
1520
1521 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1522 sbridge_put_devices(sbridge_dev);
1523 free_sbridge_dev(sbridge_dev);
1524 }
1525 }
1526
1527 static int sbridge_get_onedevice(struct pci_dev **prev,
1528 u8 *num_mc,
1529 const struct pci_id_table *table,
1530 const unsigned devno)
1531 {
1532 struct sbridge_dev *sbridge_dev;
1533 const struct pci_id_descr *dev_descr = &table->descr[devno];
1534 struct pci_dev *pdev = NULL;
1535 u8 bus = 0;
1536
1537 sbridge_printk(KERN_DEBUG,
1538 "Seeking for: PCI ID %04x:%04x\n",
1539 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1540
1541 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1542 dev_descr->dev_id, *prev);
1543
1544 if (!pdev) {
1545 if (*prev) {
1546 *prev = pdev;
1547 return 0;
1548 }
1549
1550 if (dev_descr->optional)
1551 return 0;
1552
1553 /* if the HA wasn't found */
1554 if (devno == 0)
1555 return -ENODEV;
1556
1557 sbridge_printk(KERN_INFO,
1558 "Device not found: %04x:%04x\n",
1559 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1560
1561 /* End of list, leave */
1562 return -ENODEV;
1563 }
1564 bus = pdev->bus->number;
1565
1566 sbridge_dev = get_sbridge_dev(bus);
1567 if (!sbridge_dev) {
1568 sbridge_dev = alloc_sbridge_dev(bus, table);
1569 if (!sbridge_dev) {
1570 pci_dev_put(pdev);
1571 return -ENOMEM;
1572 }
1573 (*num_mc)++;
1574 }
1575
1576 if (sbridge_dev->pdev[devno]) {
1577 sbridge_printk(KERN_ERR,
1578 "Duplicated device for %04x:%04x\n",
1579 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1580 pci_dev_put(pdev);
1581 return -ENODEV;
1582 }
1583
1584 sbridge_dev->pdev[devno] = pdev;
1585
1586 /* Be sure that the device is enabled */
1587 if (unlikely(pci_enable_device(pdev) < 0)) {
1588 sbridge_printk(KERN_ERR,
1589 "Couldn't enable %04x:%04x\n",
1590 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1591 return -ENODEV;
1592 }
1593
1594 edac_dbg(0, "Detected %04x:%04x\n",
1595 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1596
1597 /*
1598 * As stated on drivers/pci/search.c, the reference count for
1599 * @from is always decremented if it is not %NULL. So, as we need
1600 * to get all devices up to null, we need to do a get for the device
1601 */
1602 pci_dev_get(pdev);
1603
1604 *prev = pdev;
1605
1606 return 0;
1607 }
1608
1609 /*
1610 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
1611 * devices we want to reference for this driver.
1612 * @num_mc: pointer to the memory controllers count, to be incremented in case
1613 * of success.
1614 * @table: model specific table
1615 *
1616 * returns 0 in case of success or error code
1617 */
1618 static int sbridge_get_all_devices(u8 *num_mc,
1619 const struct pci_id_table *table)
1620 {
1621 int i, rc;
1622 struct pci_dev *pdev = NULL;
1623
1624 while (table && table->descr) {
1625 for (i = 0; i < table->n_devs; i++) {
1626 pdev = NULL;
1627 do {
1628 rc = sbridge_get_onedevice(&pdev, num_mc,
1629 table, i);
1630 if (rc < 0) {
1631 if (i == 0) {
1632 i = table->n_devs;
1633 break;
1634 }
1635 sbridge_put_all_devices();
1636 return -ENODEV;
1637 }
1638 } while (pdev);
1639 }
1640 table++;
1641 }
1642
1643 return 0;
1644 }
1645
1646 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
1647 struct sbridge_dev *sbridge_dev)
1648 {
1649 struct sbridge_pvt *pvt = mci->pvt_info;
1650 struct pci_dev *pdev;
1651 int i;
1652
1653 for (i = 0; i < sbridge_dev->n_devs; i++) {
1654 pdev = sbridge_dev->pdev[i];
1655 if (!pdev)
1656 continue;
1657
1658 switch (pdev->device) {
1659 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
1660 pvt->pci_sad0 = pdev;
1661 break;
1662 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
1663 pvt->pci_sad1 = pdev;
1664 break;
1665 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
1666 pvt->pci_br0 = pdev;
1667 break;
1668 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
1669 pvt->pci_ha0 = pdev;
1670 break;
1671 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
1672 pvt->pci_ta = pdev;
1673 break;
1674 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
1675 pvt->pci_ras = pdev;
1676 break;
1677 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
1678 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
1679 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
1680 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
1681 {
1682 int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
1683 pvt->pci_tad[id] = pdev;
1684 }
1685 break;
1686 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
1687 pvt->pci_ddrio = pdev;
1688 break;
1689 default:
1690 goto error;
1691 }
1692
1693 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
1694 pdev->vendor, pdev->device,
1695 sbridge_dev->bus,
1696 pdev);
1697 }
1698
1699 /* Check if everything were registered */
1700 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1701 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
1702 goto enodev;
1703
1704 for (i = 0; i < NUM_CHANNELS; i++) {
1705 if (!pvt->pci_tad[i])
1706 goto enodev;
1707 }
1708 return 0;
1709
1710 enodev:
1711 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1712 return -ENODEV;
1713
1714 error:
1715 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
1716 PCI_VENDOR_ID_INTEL, pdev->device);
1717 return -EINVAL;
1718 }
1719
1720 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
1721 struct sbridge_dev *sbridge_dev)
1722 {
1723 struct sbridge_pvt *pvt = mci->pvt_info;
1724 struct pci_dev *pdev;
1725 u8 saw_chan_mask = 0;
1726 int i;
1727
1728 for (i = 0; i < sbridge_dev->n_devs; i++) {
1729 pdev = sbridge_dev->pdev[i];
1730 if (!pdev)
1731 continue;
1732
1733 switch (pdev->device) {
1734 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
1735 pvt->pci_ha0 = pdev;
1736 break;
1737 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
1738 pvt->pci_ta = pdev;
1739 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
1740 pvt->pci_ras = pdev;
1741 break;
1742 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
1743 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
1744 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
1745 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
1746 {
1747 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
1748 pvt->pci_tad[id] = pdev;
1749 saw_chan_mask |= 1 << id;
1750 }
1751 break;
1752 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
1753 pvt->pci_ddrio = pdev;
1754 break;
1755 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
1756 pvt->pci_ddrio = pdev;
1757 break;
1758 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
1759 pvt->pci_sad0 = pdev;
1760 break;
1761 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
1762 pvt->pci_br0 = pdev;
1763 break;
1764 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
1765 pvt->pci_br1 = pdev;
1766 break;
1767 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
1768 pvt->pci_ha1 = pdev;
1769 break;
1770 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
1771 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
1772 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
1773 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
1774 {
1775 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
1776 pvt->pci_tad[id] = pdev;
1777 saw_chan_mask |= 1 << id;
1778 }
1779 break;
1780 default:
1781 goto error;
1782 }
1783
1784 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1785 sbridge_dev->bus,
1786 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1787 pdev);
1788 }
1789
1790 /* Check if everything were registered */
1791 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
1792 !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
1793 !pvt->pci_ta)
1794 goto enodev;
1795
1796 if (saw_chan_mask != 0x0f && /* -EN */
1797 saw_chan_mask != 0x33 && /* -EP */
1798 saw_chan_mask != 0xff) /* -EX */
1799 goto enodev;
1800 return 0;
1801
1802 enodev:
1803 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1804 return -ENODEV;
1805
1806 error:
1807 sbridge_printk(KERN_ERR,
1808 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
1809 pdev->device);
1810 return -EINVAL;
1811 }
1812
1813 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
1814 struct sbridge_dev *sbridge_dev)
1815 {
1816 struct sbridge_pvt *pvt = mci->pvt_info;
1817 struct pci_dev *pdev;
1818 u8 saw_chan_mask = 0;
1819 int i;
1820
1821 /* there's only one device per system; not tied to any bus */
1822 if (pvt->info.pci_vtd == NULL)
1823 /* result will be checked later */
1824 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1825 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
1826 NULL);
1827
1828 for (i = 0; i < sbridge_dev->n_devs; i++) {
1829 pdev = sbridge_dev->pdev[i];
1830 if (!pdev)
1831 continue;
1832
1833 switch (pdev->device) {
1834 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
1835 pvt->pci_sad0 = pdev;
1836 break;
1837 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
1838 pvt->pci_sad1 = pdev;
1839 break;
1840 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
1841 pvt->pci_ha0 = pdev;
1842 break;
1843 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
1844 pvt->pci_ta = pdev;
1845 break;
1846 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
1847 pvt->pci_ras = pdev;
1848 break;
1849 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
1850 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
1851 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
1852 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
1853 {
1854 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
1855
1856 pvt->pci_tad[id] = pdev;
1857 saw_chan_mask |= 1 << id;
1858 }
1859 break;
1860 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
1861 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
1862 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
1863 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
1864 {
1865 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
1866
1867 pvt->pci_tad[id] = pdev;
1868 saw_chan_mask |= 1 << id;
1869 }
1870 break;
1871 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
1872 pvt->pci_ddrio = pdev;
1873 break;
1874 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
1875 pvt->pci_ha1 = pdev;
1876 break;
1877 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
1878 pvt->pci_ha1_ta = pdev;
1879 break;
1880 default:
1881 break;
1882 }
1883
1884 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1885 sbridge_dev->bus,
1886 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1887 pdev);
1888 }
1889
1890 /* Check if everything were registered */
1891 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1892 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
1893 goto enodev;
1894
1895 if (saw_chan_mask != 0x0f && /* -EN */
1896 saw_chan_mask != 0x33 && /* -EP */
1897 saw_chan_mask != 0xff) /* -EX */
1898 goto enodev;
1899 return 0;
1900
1901 enodev:
1902 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1903 return -ENODEV;
1904 }
1905
1906 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
1907 struct sbridge_dev *sbridge_dev)
1908 {
1909 struct sbridge_pvt *pvt = mci->pvt_info;
1910 struct pci_dev *pdev;
1911 u8 saw_chan_mask = 0;
1912 int i;
1913
1914 /* there's only one device per system; not tied to any bus */
1915 if (pvt->info.pci_vtd == NULL)
1916 /* result will be checked later */
1917 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1918 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
1919 NULL);
1920
1921 for (i = 0; i < sbridge_dev->n_devs; i++) {
1922 pdev = sbridge_dev->pdev[i];
1923 if (!pdev)
1924 continue;
1925
1926 switch (pdev->device) {
1927 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
1928 pvt->pci_sad0 = pdev;
1929 break;
1930 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
1931 pvt->pci_sad1 = pdev;
1932 break;
1933 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
1934 pvt->pci_ha0 = pdev;
1935 break;
1936 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
1937 pvt->pci_ta = pdev;
1938 break;
1939 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
1940 pvt->pci_ras = pdev;
1941 break;
1942 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
1943 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
1944 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
1945 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
1946 {
1947 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
1948 pvt->pci_tad[id] = pdev;
1949 saw_chan_mask |= 1 << id;
1950 }
1951 break;
1952 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
1953 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
1954 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
1955 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
1956 {
1957 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
1958 pvt->pci_tad[id] = pdev;
1959 saw_chan_mask |= 1 << id;
1960 }
1961 break;
1962 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
1963 pvt->pci_ddrio = pdev;
1964 break;
1965 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
1966 pvt->pci_ha1 = pdev;
1967 break;
1968 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
1969 pvt->pci_ha1_ta = pdev;
1970 break;
1971 default:
1972 break;
1973 }
1974
1975 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1976 sbridge_dev->bus,
1977 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1978 pdev);
1979 }
1980
1981 /* Check if everything were registered */
1982 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1983 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
1984 goto enodev;
1985
1986 if (saw_chan_mask != 0x0f && /* -EN */
1987 saw_chan_mask != 0x33 && /* -EP */
1988 saw_chan_mask != 0xff) /* -EX */
1989 goto enodev;
1990 return 0;
1991
1992 enodev:
1993 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1994 return -ENODEV;
1995 }
1996
1997 /****************************************************************************
1998 Error check routines
1999 ****************************************************************************/
2000
2001 /*
2002 * While Sandy Bridge has error count registers, SMI BIOS read values from
2003 * and resets the counters. So, they are not reliable for the OS to read
2004 * from them. So, we have no option but to just trust on whatever MCE is
2005 * telling us about the errors.
2006 */
2007 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2008 const struct mce *m)
2009 {
2010 struct mem_ctl_info *new_mci;
2011 struct sbridge_pvt *pvt = mci->pvt_info;
2012 enum hw_event_mc_err_type tp_event;
2013 char *type, *optype, msg[256];
2014 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2015 bool overflow = GET_BITFIELD(m->status, 62, 62);
2016 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2017 bool recoverable;
2018 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2019 u32 mscod = GET_BITFIELD(m->status, 16, 31);
2020 u32 errcode = GET_BITFIELD(m->status, 0, 15);
2021 u32 channel = GET_BITFIELD(m->status, 0, 3);
2022 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2023 long channel_mask, first_channel;
2024 u8 rank, socket, ha;
2025 int rc, dimm;
2026 char *area_type = NULL;
2027
2028 if (pvt->info.type != SANDY_BRIDGE)
2029 recoverable = true;
2030 else
2031 recoverable = GET_BITFIELD(m->status, 56, 56);
2032
2033 if (uncorrected_error) {
2034 if (ripv) {
2035 type = "FATAL";
2036 tp_event = HW_EVENT_ERR_FATAL;
2037 } else {
2038 type = "NON_FATAL";
2039 tp_event = HW_EVENT_ERR_UNCORRECTED;
2040 }
2041 } else {
2042 type = "CORRECTED";
2043 tp_event = HW_EVENT_ERR_CORRECTED;
2044 }
2045
2046 /*
2047 * According with Table 15-9 of the Intel Architecture spec vol 3A,
2048 * memory errors should fit in this mask:
2049 * 000f 0000 1mmm cccc (binary)
2050 * where:
2051 * f = Correction Report Filtering Bit. If 1, subsequent errors
2052 * won't be shown
2053 * mmm = error type
2054 * cccc = channel
2055 * If the mask doesn't match, report an error to the parsing logic
2056 */
2057 if (! ((errcode & 0xef80) == 0x80)) {
2058 optype = "Can't parse: it is not a mem";
2059 } else {
2060 switch (optypenum) {
2061 case 0:
2062 optype = "generic undef request error";
2063 break;
2064 case 1:
2065 optype = "memory read error";
2066 break;
2067 case 2:
2068 optype = "memory write error";
2069 break;
2070 case 3:
2071 optype = "addr/cmd error";
2072 break;
2073 case 4:
2074 optype = "memory scrubbing error";
2075 break;
2076 default:
2077 optype = "reserved";
2078 break;
2079 }
2080 }
2081
2082 /* Only decode errors with an valid address (ADDRV) */
2083 if (!GET_BITFIELD(m->status, 58, 58))
2084 return;
2085
2086 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
2087 &channel_mask, &rank, &area_type, msg);
2088 if (rc < 0)
2089 goto err_parsing;
2090 new_mci = get_mci_for_node_id(socket);
2091 if (!new_mci) {
2092 strcpy(msg, "Error: socket got corrupted!");
2093 goto err_parsing;
2094 }
2095 mci = new_mci;
2096 pvt = mci->pvt_info;
2097
2098 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
2099
2100 if (rank < 4)
2101 dimm = 0;
2102 else if (rank < 8)
2103 dimm = 1;
2104 else
2105 dimm = 2;
2106
2107
2108 /*
2109 * FIXME: On some memory configurations (mirror, lockstep), the
2110 * Memory Controller can't point the error to a single DIMM. The
2111 * EDAC core should be handling the channel mask, in order to point
2112 * to the group of dimm's where the error may be happening.
2113 */
2114 if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
2115 channel = first_channel;
2116
2117 snprintf(msg, sizeof(msg),
2118 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
2119 overflow ? " OVERFLOW" : "",
2120 (uncorrected_error && recoverable) ? " recoverable" : "",
2121 area_type,
2122 mscod, errcode,
2123 socket, ha,
2124 channel_mask,
2125 rank);
2126
2127 edac_dbg(0, "%s\n", msg);
2128
2129 /* FIXME: need support for channel mask */
2130
2131 if (channel == CHANNEL_UNSPECIFIED)
2132 channel = -1;
2133
2134 /* Call the helper to output message */
2135 edac_mc_handle_error(tp_event, mci, core_err_cnt,
2136 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
2137 4*ha+channel, dimm, -1,
2138 optype, msg);
2139 return;
2140 err_parsing:
2141 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
2142 -1, -1, -1,
2143 msg, "");
2144
2145 }
2146
2147 /*
2148 * sbridge_check_error Retrieve and process errors reported by the
2149 * hardware. Called by the Core module.
2150 */
2151 static void sbridge_check_error(struct mem_ctl_info *mci)
2152 {
2153 struct sbridge_pvt *pvt = mci->pvt_info;
2154 int i;
2155 unsigned count = 0;
2156 struct mce *m;
2157
2158 /*
2159 * MCE first step: Copy all mce errors into a temporary buffer
2160 * We use a double buffering here, to reduce the risk of
2161 * loosing an error.
2162 */
2163 smp_rmb();
2164 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
2165 % MCE_LOG_LEN;
2166 if (!count)
2167 return;
2168
2169 m = pvt->mce_outentry;
2170 if (pvt->mce_in + count > MCE_LOG_LEN) {
2171 unsigned l = MCE_LOG_LEN - pvt->mce_in;
2172
2173 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
2174 smp_wmb();
2175 pvt->mce_in = 0;
2176 count -= l;
2177 m += l;
2178 }
2179 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
2180 smp_wmb();
2181 pvt->mce_in += count;
2182
2183 smp_rmb();
2184 if (pvt->mce_overrun) {
2185 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
2186 pvt->mce_overrun);
2187 smp_wmb();
2188 pvt->mce_overrun = 0;
2189 }
2190
2191 /*
2192 * MCE second step: parse errors and display
2193 */
2194 for (i = 0; i < count; i++)
2195 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
2196 }
2197
2198 /*
2199 * sbridge_mce_check_error Replicates mcelog routine to get errors
2200 * This routine simply queues mcelog errors, and
2201 * return. The error itself should be handled later
2202 * by sbridge_check_error.
2203 * WARNING: As this routine should be called at NMI time, extra care should
2204 * be taken to avoid deadlocks, and to be as fast as possible.
2205 */
2206 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
2207 void *data)
2208 {
2209 struct mce *mce = (struct mce *)data;
2210 struct mem_ctl_info *mci;
2211 struct sbridge_pvt *pvt;
2212 char *type;
2213
2214 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2215 return NOTIFY_DONE;
2216
2217 mci = get_mci_for_node_id(mce->socketid);
2218 if (!mci)
2219 return NOTIFY_BAD;
2220 pvt = mci->pvt_info;
2221
2222 /*
2223 * Just let mcelog handle it if the error is
2224 * outside the memory controller. A memory error
2225 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
2226 * bit 12 has an special meaning.
2227 */
2228 if ((mce->status & 0xefff) >> 7 != 1)
2229 return NOTIFY_DONE;
2230
2231 if (mce->mcgstatus & MCG_STATUS_MCIP)
2232 type = "Exception";
2233 else
2234 type = "Event";
2235
2236 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
2237
2238 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
2239 "Bank %d: %016Lx\n", mce->extcpu, type,
2240 mce->mcgstatus, mce->bank, mce->status);
2241 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
2242 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
2243 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
2244
2245 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
2246 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
2247 mce->time, mce->socketid, mce->apicid);
2248
2249 smp_rmb();
2250 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
2251 smp_wmb();
2252 pvt->mce_overrun++;
2253 return NOTIFY_DONE;
2254 }
2255
2256 /* Copy memory error at the ringbuffer */
2257 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
2258 smp_wmb();
2259 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
2260
2261 /* Handle fatal errors immediately */
2262 if (mce->mcgstatus & 1)
2263 sbridge_check_error(mci);
2264
2265 /* Advice mcelog that the error were handled */
2266 return NOTIFY_STOP;
2267 }
2268
2269 static struct notifier_block sbridge_mce_dec = {
2270 .notifier_call = sbridge_mce_check_error,
2271 };
2272
2273 /****************************************************************************
2274 EDAC register/unregister logic
2275 ****************************************************************************/
2276
2277 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
2278 {
2279 struct mem_ctl_info *mci = sbridge_dev->mci;
2280 struct sbridge_pvt *pvt;
2281
2282 if (unlikely(!mci || !mci->pvt_info)) {
2283 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
2284
2285 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
2286 return;
2287 }
2288
2289 pvt = mci->pvt_info;
2290
2291 edac_dbg(0, "MC: mci = %p, dev = %p\n",
2292 mci, &sbridge_dev->pdev[0]->dev);
2293
2294 /* Remove MC sysfs nodes */
2295 edac_mc_del_mc(mci->pdev);
2296
2297 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
2298 kfree(mci->ctl_name);
2299 edac_mc_free(mci);
2300 sbridge_dev->mci = NULL;
2301 }
2302
2303 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
2304 {
2305 struct mem_ctl_info *mci;
2306 struct edac_mc_layer layers[2];
2307 struct sbridge_pvt *pvt;
2308 struct pci_dev *pdev = sbridge_dev->pdev[0];
2309 int rc;
2310
2311 /* Check the number of active and not disabled channels */
2312 rc = check_if_ecc_is_active(sbridge_dev->bus, type);
2313 if (unlikely(rc < 0))
2314 return rc;
2315
2316 /* allocate a new MC control structure */
2317 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2318 layers[0].size = NUM_CHANNELS;
2319 layers[0].is_virt_csrow = false;
2320 layers[1].type = EDAC_MC_LAYER_SLOT;
2321 layers[1].size = MAX_DIMMS;
2322 layers[1].is_virt_csrow = true;
2323 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
2324 sizeof(*pvt));
2325
2326 if (unlikely(!mci))
2327 return -ENOMEM;
2328
2329 edac_dbg(0, "MC: mci = %p, dev = %p\n",
2330 mci, &pdev->dev);
2331
2332 pvt = mci->pvt_info;
2333 memset(pvt, 0, sizeof(*pvt));
2334
2335 /* Associate sbridge_dev and mci for future usage */
2336 pvt->sbridge_dev = sbridge_dev;
2337 sbridge_dev->mci = mci;
2338
2339 mci->mtype_cap = MEM_FLAG_DDR3;
2340 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2341 mci->edac_cap = EDAC_FLAG_NONE;
2342 mci->mod_name = "sbridge_edac.c";
2343 mci->mod_ver = SBRIDGE_REVISION;
2344 mci->dev_name = pci_name(pdev);
2345 mci->ctl_page_to_phys = NULL;
2346
2347 /* Set the function pointer to an actual operation function */
2348 mci->edac_check = sbridge_check_error;
2349
2350 pvt->info.type = type;
2351 switch (type) {
2352 case IVY_BRIDGE:
2353 pvt->info.rankcfgr = IB_RANK_CFG_A;
2354 pvt->info.get_tolm = ibridge_get_tolm;
2355 pvt->info.get_tohm = ibridge_get_tohm;
2356 pvt->info.dram_rule = ibridge_dram_rule;
2357 pvt->info.get_memory_type = get_memory_type;
2358 pvt->info.get_node_id = get_node_id;
2359 pvt->info.rir_limit = rir_limit;
2360 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2361 pvt->info.interleave_list = ibridge_interleave_list;
2362 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2363 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2364 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
2365
2366 /* Store pci devices at mci for faster access */
2367 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
2368 if (unlikely(rc < 0))
2369 goto fail0;
2370 break;
2371 case SANDY_BRIDGE:
2372 pvt->info.rankcfgr = SB_RANK_CFG_A;
2373 pvt->info.get_tolm = sbridge_get_tolm;
2374 pvt->info.get_tohm = sbridge_get_tohm;
2375 pvt->info.dram_rule = sbridge_dram_rule;
2376 pvt->info.get_memory_type = get_memory_type;
2377 pvt->info.get_node_id = get_node_id;
2378 pvt->info.rir_limit = rir_limit;
2379 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
2380 pvt->info.interleave_list = sbridge_interleave_list;
2381 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
2382 pvt->info.interleave_pkg = sbridge_interleave_pkg;
2383 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
2384
2385 /* Store pci devices at mci for faster access */
2386 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
2387 if (unlikely(rc < 0))
2388 goto fail0;
2389 break;
2390 case HASWELL:
2391 /* rankcfgr isn't used */
2392 pvt->info.get_tolm = haswell_get_tolm;
2393 pvt->info.get_tohm = haswell_get_tohm;
2394 pvt->info.dram_rule = ibridge_dram_rule;
2395 pvt->info.get_memory_type = haswell_get_memory_type;
2396 pvt->info.get_node_id = haswell_get_node_id;
2397 pvt->info.rir_limit = haswell_rir_limit;
2398 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2399 pvt->info.interleave_list = ibridge_interleave_list;
2400 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2401 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2402 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
2403
2404 /* Store pci devices at mci for faster access */
2405 rc = haswell_mci_bind_devs(mci, sbridge_dev);
2406 if (unlikely(rc < 0))
2407 goto fail0;
2408 break;
2409 case BROADWELL:
2410 /* rankcfgr isn't used */
2411 pvt->info.get_tolm = haswell_get_tolm;
2412 pvt->info.get_tohm = haswell_get_tohm;
2413 pvt->info.dram_rule = ibridge_dram_rule;
2414 pvt->info.get_memory_type = haswell_get_memory_type;
2415 pvt->info.get_node_id = haswell_get_node_id;
2416 pvt->info.rir_limit = haswell_rir_limit;
2417 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2418 pvt->info.interleave_list = ibridge_interleave_list;
2419 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2420 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2421 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
2422
2423 /* Store pci devices at mci for faster access */
2424 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
2425 if (unlikely(rc < 0))
2426 goto fail0;
2427 break;
2428 }
2429
2430 /* Get dimm basic config and the memory layout */
2431 get_dimm_config(mci);
2432 get_memory_layout(mci);
2433
2434 /* record ptr to the generic device */
2435 mci->pdev = &pdev->dev;
2436
2437 /* add this new MC control structure to EDAC's list of MCs */
2438 if (unlikely(edac_mc_add_mc(mci))) {
2439 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
2440 rc = -EINVAL;
2441 goto fail0;
2442 }
2443
2444 return 0;
2445
2446 fail0:
2447 kfree(mci->ctl_name);
2448 edac_mc_free(mci);
2449 sbridge_dev->mci = NULL;
2450 return rc;
2451 }
2452
2453 /*
2454 * sbridge_probe Probe for ONE instance of device to see if it is
2455 * present.
2456 * return:
2457 * 0 for FOUND a device
2458 * < 0 for error code
2459 */
2460
2461 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2462 {
2463 int rc = -ENODEV;
2464 u8 mc, num_mc = 0;
2465 struct sbridge_dev *sbridge_dev;
2466 enum type type = SANDY_BRIDGE;
2467
2468 /* get the pci devices we want to reserve for our use */
2469 mutex_lock(&sbridge_edac_lock);
2470
2471 /*
2472 * All memory controllers are allocated at the first pass.
2473 */
2474 if (unlikely(probed >= 1)) {
2475 mutex_unlock(&sbridge_edac_lock);
2476 return -ENODEV;
2477 }
2478 probed++;
2479
2480 switch (pdev->device) {
2481 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2482 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
2483 type = IVY_BRIDGE;
2484 break;
2485 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2486 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
2487 type = SANDY_BRIDGE;
2488 break;
2489 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2490 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
2491 type = HASWELL;
2492 break;
2493 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2494 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table);
2495 type = BROADWELL;
2496 break;
2497 }
2498 if (unlikely(rc < 0)) {
2499 edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device);
2500 goto fail0;
2501 }
2502
2503 mc = 0;
2504
2505 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
2506 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
2507 mc, mc + 1, num_mc);
2508
2509 sbridge_dev->mc = mc++;
2510 rc = sbridge_register_mci(sbridge_dev, type);
2511 if (unlikely(rc < 0))
2512 goto fail1;
2513 }
2514
2515 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
2516
2517 mutex_unlock(&sbridge_edac_lock);
2518 return 0;
2519
2520 fail1:
2521 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2522 sbridge_unregister_mci(sbridge_dev);
2523
2524 sbridge_put_all_devices();
2525 fail0:
2526 mutex_unlock(&sbridge_edac_lock);
2527 return rc;
2528 }
2529
2530 /*
2531 * sbridge_remove destructor for one instance of device
2532 *
2533 */
2534 static void sbridge_remove(struct pci_dev *pdev)
2535 {
2536 struct sbridge_dev *sbridge_dev;
2537
2538 edac_dbg(0, "\n");
2539
2540 /*
2541 * we have a trouble here: pdev value for removal will be wrong, since
2542 * it will point to the X58 register used to detect that the machine
2543 * is a Nehalem or upper design. However, due to the way several PCI
2544 * devices are grouped together to provide MC functionality, we need
2545 * to use a different method for releasing the devices
2546 */
2547
2548 mutex_lock(&sbridge_edac_lock);
2549
2550 if (unlikely(!probed)) {
2551 mutex_unlock(&sbridge_edac_lock);
2552 return;
2553 }
2554
2555 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2556 sbridge_unregister_mci(sbridge_dev);
2557
2558 /* Release PCI resources */
2559 sbridge_put_all_devices();
2560
2561 probed--;
2562
2563 mutex_unlock(&sbridge_edac_lock);
2564 }
2565
2566 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
2567
2568 /*
2569 * sbridge_driver pci_driver structure for this module
2570 *
2571 */
2572 static struct pci_driver sbridge_driver = {
2573 .name = "sbridge_edac",
2574 .probe = sbridge_probe,
2575 .remove = sbridge_remove,
2576 .id_table = sbridge_pci_tbl,
2577 };
2578
2579 /*
2580 * sbridge_init Module entry function
2581 * Try to initialize this module for its devices
2582 */
2583 static int __init sbridge_init(void)
2584 {
2585 int pci_rc;
2586
2587 edac_dbg(2, "\n");
2588
2589 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2590 opstate_init();
2591
2592 pci_rc = pci_register_driver(&sbridge_driver);
2593 if (pci_rc >= 0) {
2594 mce_register_decode_chain(&sbridge_mce_dec);
2595 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2596 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
2597 return 0;
2598 }
2599
2600 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2601 pci_rc);
2602
2603 return pci_rc;
2604 }
2605
2606 /*
2607 * sbridge_exit() Module exit function
2608 * Unregister the driver
2609 */
2610 static void __exit sbridge_exit(void)
2611 {
2612 edac_dbg(2, "\n");
2613 pci_unregister_driver(&sbridge_driver);
2614 mce_unregister_decode_chain(&sbridge_mce_dec);
2615 }
2616
2617 module_init(sbridge_init);
2618 module_exit(sbridge_exit);
2619
2620 module_param(edac_op_state, int, 0444);
2621 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
2622
2623 MODULE_LICENSE("GPL");
2624 MODULE_AUTHOR("Mauro Carvalho Chehab");
2625 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2626 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
2627 SBRIDGE_REVISION);
Linux kernel - Deliverables
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