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firewire: remove line breaks before function names
[deliverable/linux.git] / drivers / firewire / fw-ohci.c
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/mm.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
33
34 #include <asm/page.h>
35 #include <asm/system.h>
36
37 #ifdef CONFIG_PPC_PMAC
38 #include <asm/pmac_feature.h>
39 #endif
40
41 #include "fw-ohci.h"
42 #include "fw-transaction.h"
43
44 #define DESCRIPTOR_OUTPUT_MORE 0
45 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
46 #define DESCRIPTOR_INPUT_MORE (2 << 12)
47 #define DESCRIPTOR_INPUT_LAST (3 << 12)
48 #define DESCRIPTOR_STATUS (1 << 11)
49 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
50 #define DESCRIPTOR_PING (1 << 7)
51 #define DESCRIPTOR_YY (1 << 6)
52 #define DESCRIPTOR_NO_IRQ (0 << 4)
53 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
54 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
55 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
56 #define DESCRIPTOR_WAIT (3 << 0)
57
58 struct descriptor {
59 __le16 req_count;
60 __le16 control;
61 __le32 data_address;
62 __le32 branch_address;
63 __le16 res_count;
64 __le16 transfer_status;
65 } __attribute__((aligned(16)));
66
67 struct db_descriptor {
68 __le16 first_size;
69 __le16 control;
70 __le16 second_req_count;
71 __le16 first_req_count;
72 __le32 branch_address;
73 __le16 second_res_count;
74 __le16 first_res_count;
75 __le32 reserved0;
76 __le32 first_buffer;
77 __le32 second_buffer;
78 __le32 reserved1;
79 } __attribute__((aligned(16)));
80
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
85
86 struct ar_buffer {
87 struct descriptor descriptor;
88 struct ar_buffer *next;
89 __le32 data[0];
90 };
91
92 struct ar_context {
93 struct fw_ohci *ohci;
94 struct ar_buffer *current_buffer;
95 struct ar_buffer *last_buffer;
96 void *pointer;
97 u32 regs;
98 struct tasklet_struct tasklet;
99 };
100
101 struct context;
102
103 typedef int (*descriptor_callback_t)(struct context *ctx,
104 struct descriptor *d,
105 struct descriptor *last);
106
107 /*
108 * A buffer that contains a block of DMA-able coherent memory used for
109 * storing a portion of a DMA descriptor program.
110 */
111 struct descriptor_buffer {
112 struct list_head list;
113 dma_addr_t buffer_bus;
114 size_t buffer_size;
115 size_t used;
116 struct descriptor buffer[0];
117 };
118
119 struct context {
120 struct fw_ohci *ohci;
121 u32 regs;
122 int total_allocation;
123
124 /*
125 * List of page-sized buffers for storing DMA descriptors.
126 * Head of list contains buffers in use and tail of list contains
127 * free buffers.
128 */
129 struct list_head buffer_list;
130
131 /*
132 * Pointer to a buffer inside buffer_list that contains the tail
133 * end of the current DMA program.
134 */
135 struct descriptor_buffer *buffer_tail;
136
137 /*
138 * The descriptor containing the branch address of the first
139 * descriptor that has not yet been filled by the device.
140 */
141 struct descriptor *last;
142
143 /*
144 * The last descriptor in the DMA program. It contains the branch
145 * address that must be updated upon appending a new descriptor.
146 */
147 struct descriptor *prev;
148
149 descriptor_callback_t callback;
150
151 struct tasklet_struct tasklet;
152 };
153
154 #define IT_HEADER_SY(v) ((v) << 0)
155 #define IT_HEADER_TCODE(v) ((v) << 4)
156 #define IT_HEADER_CHANNEL(v) ((v) << 8)
157 #define IT_HEADER_TAG(v) ((v) << 14)
158 #define IT_HEADER_SPEED(v) ((v) << 16)
159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
160
161 struct iso_context {
162 struct fw_iso_context base;
163 struct context context;
164 int excess_bytes;
165 void *header;
166 size_t header_length;
167 };
168
169 #define CONFIG_ROM_SIZE 1024
170
171 struct fw_ohci {
172 struct fw_card card;
173
174 __iomem char *registers;
175 dma_addr_t self_id_bus;
176 __le32 *self_id_cpu;
177 struct tasklet_struct bus_reset_tasklet;
178 int node_id;
179 int generation;
180 int request_generation; /* for timestamping incoming requests */
181 u32 bus_seconds;
182
183 bool use_dualbuffer;
184 bool old_uninorth;
185 bool bus_reset_packet_quirk;
186
187 /*
188 * Spinlock for accessing fw_ohci data. Never call out of
189 * this driver with this lock held.
190 */
191 spinlock_t lock;
192 u32 self_id_buffer[512];
193
194 /* Config rom buffers */
195 __be32 *config_rom;
196 dma_addr_t config_rom_bus;
197 __be32 *next_config_rom;
198 dma_addr_t next_config_rom_bus;
199 u32 next_header;
200
201 struct ar_context ar_request_ctx;
202 struct ar_context ar_response_ctx;
203 struct context at_request_ctx;
204 struct context at_response_ctx;
205
206 u32 it_context_mask;
207 struct iso_context *it_context_list;
208 u32 ir_context_mask;
209 struct iso_context *ir_context_list;
210 };
211
212 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
213 {
214 return container_of(card, struct fw_ohci, card);
215 }
216
217 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
218 #define IR_CONTEXT_BUFFER_FILL 0x80000000
219 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
220 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
221 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
222 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
223
224 #define CONTEXT_RUN 0x8000
225 #define CONTEXT_WAKE 0x1000
226 #define CONTEXT_DEAD 0x0800
227 #define CONTEXT_ACTIVE 0x0400
228
229 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
230 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
231 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
232
233 #define FW_OHCI_MAJOR 240
234 #define OHCI1394_REGISTER_SIZE 0x800
235 #define OHCI_LOOP_COUNT 500
236 #define OHCI1394_PCI_HCI_Control 0x40
237 #define SELF_ID_BUF_SIZE 0x800
238 #define OHCI_TCODE_PHY_PACKET 0x0e
239 #define OHCI_VERSION_1_1 0x010010
240
241 static char ohci_driver_name[] = KBUILD_MODNAME;
242
243 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
244
245 #define OHCI_PARAM_DEBUG_AT_AR 1
246 #define OHCI_PARAM_DEBUG_SELFIDS 2
247 #define OHCI_PARAM_DEBUG_IRQS 4
248 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
249
250 static int param_debug;
251 module_param_named(debug, param_debug, int, 0644);
252 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
253 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
254 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
255 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
256 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
257 ", or a combination, or all = -1)");
258
259 static void log_irqs(u32 evt)
260 {
261 if (likely(!(param_debug &
262 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
263 return;
264
265 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
266 !(evt & OHCI1394_busReset))
267 return;
268
269 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
270 evt & OHCI1394_selfIDComplete ? " selfID" : "",
271 evt & OHCI1394_RQPkt ? " AR_req" : "",
272 evt & OHCI1394_RSPkt ? " AR_resp" : "",
273 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
274 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
275 evt & OHCI1394_isochRx ? " IR" : "",
276 evt & OHCI1394_isochTx ? " IT" : "",
277 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
278 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
279 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
280 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
281 evt & OHCI1394_busReset ? " busReset" : "",
282 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
283 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
284 OHCI1394_respTxComplete | OHCI1394_isochRx |
285 OHCI1394_isochTx | OHCI1394_postedWriteErr |
286 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
287 OHCI1394_regAccessFail | OHCI1394_busReset)
288 ? " ?" : "");
289 }
290
291 static const char *speed[] = {
292 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
293 };
294 static const char *power[] = {
295 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
296 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
297 };
298 static const char port[] = { '.', '-', 'p', 'c', };
299
300 static char _p(u32 *s, int shift)
301 {
302 return port[*s >> shift & 3];
303 }
304
305 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
306 {
307 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
308 return;
309
310 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
311 self_id_count, generation, node_id);
312
313 for (; self_id_count--; ++s)
314 if ((*s & 1 << 23) == 0)
315 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
316 "%s gc=%d %s %s%s%s\n",
317 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
318 speed[*s >> 14 & 3], *s >> 16 & 63,
319 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
320 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
321 else
322 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
323 *s, *s >> 24 & 63,
324 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
325 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
326 }
327
328 static const char *evts[] = {
329 [0x00] = "evt_no_status", [0x01] = "-reserved-",
330 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
331 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
332 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
333 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
334 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
335 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
336 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
337 [0x10] = "-reserved-", [0x11] = "ack_complete",
338 [0x12] = "ack_pending ", [0x13] = "-reserved-",
339 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
340 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
341 [0x18] = "-reserved-", [0x19] = "-reserved-",
342 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
343 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
344 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
345 [0x20] = "pending/cancelled",
346 };
347 static const char *tcodes[] = {
348 [0x0] = "QW req", [0x1] = "BW req",
349 [0x2] = "W resp", [0x3] = "-reserved-",
350 [0x4] = "QR req", [0x5] = "BR req",
351 [0x6] = "QR resp", [0x7] = "BR resp",
352 [0x8] = "cycle start", [0x9] = "Lk req",
353 [0xa] = "async stream packet", [0xb] = "Lk resp",
354 [0xc] = "-reserved-", [0xd] = "-reserved-",
355 [0xe] = "link internal", [0xf] = "-reserved-",
356 };
357 static const char *phys[] = {
358 [0x0] = "phy config packet", [0x1] = "link-on packet",
359 [0x2] = "self-id packet", [0x3] = "-reserved-",
360 };
361
362 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
363 {
364 int tcode = header[0] >> 4 & 0xf;
365 char specific[12];
366
367 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
368 return;
369
370 if (unlikely(evt >= ARRAY_SIZE(evts)))
371 evt = 0x1f;
372
373 if (evt == OHCI1394_evt_bus_reset) {
374 fw_notify("A%c evt_bus_reset, generation %d\n",
375 dir, (header[2] >> 16) & 0xff);
376 return;
377 }
378
379 if (header[0] == ~header[1]) {
380 fw_notify("A%c %s, %s, %08x\n",
381 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
382 return;
383 }
384
385 switch (tcode) {
386 case 0x0: case 0x6: case 0x8:
387 snprintf(specific, sizeof(specific), " = %08x",
388 be32_to_cpu((__force __be32)header[3]));
389 break;
390 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
391 snprintf(specific, sizeof(specific), " %x,%x",
392 header[3] >> 16, header[3] & 0xffff);
393 break;
394 default:
395 specific[0] = '\0';
396 }
397
398 switch (tcode) {
399 case 0xe: case 0xa:
400 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
401 break;
402 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
403 fw_notify("A%c spd %x tl %02x, "
404 "%04x -> %04x, %s, "
405 "%s, %04x%08x%s\n",
406 dir, speed, header[0] >> 10 & 0x3f,
407 header[1] >> 16, header[0] >> 16, evts[evt],
408 tcodes[tcode], header[1] & 0xffff, header[2], specific);
409 break;
410 default:
411 fw_notify("A%c spd %x tl %02x, "
412 "%04x -> %04x, %s, "
413 "%s%s\n",
414 dir, speed, header[0] >> 10 & 0x3f,
415 header[1] >> 16, header[0] >> 16, evts[evt],
416 tcodes[tcode], specific);
417 }
418 }
419
420 #else
421
422 #define log_irqs(evt)
423 #define log_selfids(node_id, generation, self_id_count, sid)
424 #define log_ar_at_event(dir, speed, header, evt)
425
426 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
427
428 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
429 {
430 writel(data, ohci->registers + offset);
431 }
432
433 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
434 {
435 return readl(ohci->registers + offset);
436 }
437
438 static inline void flush_writes(const struct fw_ohci *ohci)
439 {
440 /* Do a dummy read to flush writes. */
441 reg_read(ohci, OHCI1394_Version);
442 }
443
444 static int ohci_update_phy_reg(struct fw_card *card, int addr,
445 int clear_bits, int set_bits)
446 {
447 struct fw_ohci *ohci = fw_ohci(card);
448 u32 val, old;
449
450 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
451 flush_writes(ohci);
452 msleep(2);
453 val = reg_read(ohci, OHCI1394_PhyControl);
454 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
455 fw_error("failed to set phy reg bits.\n");
456 return -EBUSY;
457 }
458
459 old = OHCI1394_PhyControl_ReadData(val);
460 old = (old & ~clear_bits) | set_bits;
461 reg_write(ohci, OHCI1394_PhyControl,
462 OHCI1394_PhyControl_Write(addr, old));
463
464 return 0;
465 }
466
467 static int ar_context_add_page(struct ar_context *ctx)
468 {
469 struct device *dev = ctx->ohci->card.device;
470 struct ar_buffer *ab;
471 dma_addr_t uninitialized_var(ab_bus);
472 size_t offset;
473
474 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
475 if (ab == NULL)
476 return -ENOMEM;
477
478 ab->next = NULL;
479 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
480 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
481 DESCRIPTOR_STATUS |
482 DESCRIPTOR_BRANCH_ALWAYS);
483 offset = offsetof(struct ar_buffer, data);
484 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
485 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
486 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
487 ab->descriptor.branch_address = 0;
488
489 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
490 ctx->last_buffer->next = ab;
491 ctx->last_buffer = ab;
492
493 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
494 flush_writes(ctx->ohci);
495
496 return 0;
497 }
498
499 static void ar_context_release(struct ar_context *ctx)
500 {
501 struct ar_buffer *ab, *ab_next;
502 size_t offset;
503 dma_addr_t ab_bus;
504
505 for (ab = ctx->current_buffer; ab; ab = ab_next) {
506 ab_next = ab->next;
507 offset = offsetof(struct ar_buffer, data);
508 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
509 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
510 ab, ab_bus);
511 }
512 }
513
514 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
515 #define cond_le32_to_cpu(v) \
516 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
517 #else
518 #define cond_le32_to_cpu(v) le32_to_cpu(v)
519 #endif
520
521 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
522 {
523 struct fw_ohci *ohci = ctx->ohci;
524 struct fw_packet p;
525 u32 status, length, tcode;
526 int evt;
527
528 p.header[0] = cond_le32_to_cpu(buffer[0]);
529 p.header[1] = cond_le32_to_cpu(buffer[1]);
530 p.header[2] = cond_le32_to_cpu(buffer[2]);
531
532 tcode = (p.header[0] >> 4) & 0x0f;
533 switch (tcode) {
534 case TCODE_WRITE_QUADLET_REQUEST:
535 case TCODE_READ_QUADLET_RESPONSE:
536 p.header[3] = (__force __u32) buffer[3];
537 p.header_length = 16;
538 p.payload_length = 0;
539 break;
540
541 case TCODE_READ_BLOCK_REQUEST :
542 p.header[3] = cond_le32_to_cpu(buffer[3]);
543 p.header_length = 16;
544 p.payload_length = 0;
545 break;
546
547 case TCODE_WRITE_BLOCK_REQUEST:
548 case TCODE_READ_BLOCK_RESPONSE:
549 case TCODE_LOCK_REQUEST:
550 case TCODE_LOCK_RESPONSE:
551 p.header[3] = cond_le32_to_cpu(buffer[3]);
552 p.header_length = 16;
553 p.payload_length = p.header[3] >> 16;
554 break;
555
556 case TCODE_WRITE_RESPONSE:
557 case TCODE_READ_QUADLET_REQUEST:
558 case OHCI_TCODE_PHY_PACKET:
559 p.header_length = 12;
560 p.payload_length = 0;
561 break;
562
563 default:
564 /* FIXME: Stop context, discard everything, and restart? */
565 p.header_length = 0;
566 p.payload_length = 0;
567 }
568
569 p.payload = (void *) buffer + p.header_length;
570
571 /* FIXME: What to do about evt_* errors? */
572 length = (p.header_length + p.payload_length + 3) / 4;
573 status = cond_le32_to_cpu(buffer[length]);
574 evt = (status >> 16) & 0x1f;
575
576 p.ack = evt - 16;
577 p.speed = (status >> 21) & 0x7;
578 p.timestamp = status & 0xffff;
579 p.generation = ohci->request_generation;
580
581 log_ar_at_event('R', p.speed, p.header, evt);
582
583 /*
584 * The OHCI bus reset handler synthesizes a phy packet with
585 * the new generation number when a bus reset happens (see
586 * section 8.4.2.3). This helps us determine when a request
587 * was received and make sure we send the response in the same
588 * generation. We only need this for requests; for responses
589 * we use the unique tlabel for finding the matching
590 * request.
591 *
592 * Alas some chips sometimes emit bus reset packets with a
593 * wrong generation. We set the correct generation for these
594 * at a slightly incorrect time (in bus_reset_tasklet).
595 */
596 if (evt == OHCI1394_evt_bus_reset) {
597 if (!ohci->bus_reset_packet_quirk)
598 ohci->request_generation = (p.header[2] >> 16) & 0xff;
599 } else if (ctx == &ohci->ar_request_ctx) {
600 fw_core_handle_request(&ohci->card, &p);
601 } else {
602 fw_core_handle_response(&ohci->card, &p);
603 }
604
605 return buffer + length + 1;
606 }
607
608 static void ar_context_tasklet(unsigned long data)
609 {
610 struct ar_context *ctx = (struct ar_context *)data;
611 struct fw_ohci *ohci = ctx->ohci;
612 struct ar_buffer *ab;
613 struct descriptor *d;
614 void *buffer, *end;
615
616 ab = ctx->current_buffer;
617 d = &ab->descriptor;
618
619 if (d->res_count == 0) {
620 size_t size, rest, offset;
621 dma_addr_t start_bus;
622 void *start;
623
624 /*
625 * This descriptor is finished and we may have a
626 * packet split across this and the next buffer. We
627 * reuse the page for reassembling the split packet.
628 */
629
630 offset = offsetof(struct ar_buffer, data);
631 start = buffer = ab;
632 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
633
634 ab = ab->next;
635 d = &ab->descriptor;
636 size = buffer + PAGE_SIZE - ctx->pointer;
637 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
638 memmove(buffer, ctx->pointer, size);
639 memcpy(buffer + size, ab->data, rest);
640 ctx->current_buffer = ab;
641 ctx->pointer = (void *) ab->data + rest;
642 end = buffer + size + rest;
643
644 while (buffer < end)
645 buffer = handle_ar_packet(ctx, buffer);
646
647 dma_free_coherent(ohci->card.device, PAGE_SIZE,
648 start, start_bus);
649 ar_context_add_page(ctx);
650 } else {
651 buffer = ctx->pointer;
652 ctx->pointer = end =
653 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
654
655 while (buffer < end)
656 buffer = handle_ar_packet(ctx, buffer);
657 }
658 }
659
660 static int ar_context_init(struct ar_context *ctx,
661 struct fw_ohci *ohci, u32 regs)
662 {
663 struct ar_buffer ab;
664
665 ctx->regs = regs;
666 ctx->ohci = ohci;
667 ctx->last_buffer = &ab;
668 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
669
670 ar_context_add_page(ctx);
671 ar_context_add_page(ctx);
672 ctx->current_buffer = ab.next;
673 ctx->pointer = ctx->current_buffer->data;
674
675 return 0;
676 }
677
678 static void ar_context_run(struct ar_context *ctx)
679 {
680 struct ar_buffer *ab = ctx->current_buffer;
681 dma_addr_t ab_bus;
682 size_t offset;
683
684 offset = offsetof(struct ar_buffer, data);
685 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
686
687 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
688 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
689 flush_writes(ctx->ohci);
690 }
691
692 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
693 {
694 int b, key;
695
696 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
697 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
698
699 /* figure out which descriptor the branch address goes in */
700 if (z == 2 && (b == 3 || key == 2))
701 return d;
702 else
703 return d + z - 1;
704 }
705
706 static void context_tasklet(unsigned long data)
707 {
708 struct context *ctx = (struct context *) data;
709 struct descriptor *d, *last;
710 u32 address;
711 int z;
712 struct descriptor_buffer *desc;
713
714 desc = list_entry(ctx->buffer_list.next,
715 struct descriptor_buffer, list);
716 last = ctx->last;
717 while (last->branch_address != 0) {
718 struct descriptor_buffer *old_desc = desc;
719 address = le32_to_cpu(last->branch_address);
720 z = address & 0xf;
721 address &= ~0xf;
722
723 /* If the branch address points to a buffer outside of the
724 * current buffer, advance to the next buffer. */
725 if (address < desc->buffer_bus ||
726 address >= desc->buffer_bus + desc->used)
727 desc = list_entry(desc->list.next,
728 struct descriptor_buffer, list);
729 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
730 last = find_branch_descriptor(d, z);
731
732 if (!ctx->callback(ctx, d, last))
733 break;
734
735 if (old_desc != desc) {
736 /* If we've advanced to the next buffer, move the
737 * previous buffer to the free list. */
738 unsigned long flags;
739 old_desc->used = 0;
740 spin_lock_irqsave(&ctx->ohci->lock, flags);
741 list_move_tail(&old_desc->list, &ctx->buffer_list);
742 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
743 }
744 ctx->last = last;
745 }
746 }
747
748 /*
749 * Allocate a new buffer and add it to the list of free buffers for this
750 * context. Must be called with ohci->lock held.
751 */
752 static int context_add_buffer(struct context *ctx)
753 {
754 struct descriptor_buffer *desc;
755 dma_addr_t uninitialized_var(bus_addr);
756 int offset;
757
758 /*
759 * 16MB of descriptors should be far more than enough for any DMA
760 * program. This will catch run-away userspace or DoS attacks.
761 */
762 if (ctx->total_allocation >= 16*1024*1024)
763 return -ENOMEM;
764
765 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
766 &bus_addr, GFP_ATOMIC);
767 if (!desc)
768 return -ENOMEM;
769
770 offset = (void *)&desc->buffer - (void *)desc;
771 desc->buffer_size = PAGE_SIZE - offset;
772 desc->buffer_bus = bus_addr + offset;
773 desc->used = 0;
774
775 list_add_tail(&desc->list, &ctx->buffer_list);
776 ctx->total_allocation += PAGE_SIZE;
777
778 return 0;
779 }
780
781 static int context_init(struct context *ctx, struct fw_ohci *ohci,
782 u32 regs, descriptor_callback_t callback)
783 {
784 ctx->ohci = ohci;
785 ctx->regs = regs;
786 ctx->total_allocation = 0;
787
788 INIT_LIST_HEAD(&ctx->buffer_list);
789 if (context_add_buffer(ctx) < 0)
790 return -ENOMEM;
791
792 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
793 struct descriptor_buffer, list);
794
795 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
796 ctx->callback = callback;
797
798 /*
799 * We put a dummy descriptor in the buffer that has a NULL
800 * branch address and looks like it's been sent. That way we
801 * have a descriptor to append DMA programs to.
802 */
803 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
804 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
805 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
806 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
807 ctx->last = ctx->buffer_tail->buffer;
808 ctx->prev = ctx->buffer_tail->buffer;
809
810 return 0;
811 }
812
813 static void context_release(struct context *ctx)
814 {
815 struct fw_card *card = &ctx->ohci->card;
816 struct descriptor_buffer *desc, *tmp;
817
818 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
819 dma_free_coherent(card->device, PAGE_SIZE, desc,
820 desc->buffer_bus -
821 ((void *)&desc->buffer - (void *)desc));
822 }
823
824 /* Must be called with ohci->lock held */
825 static struct descriptor *context_get_descriptors(struct context *ctx,
826 int z, dma_addr_t *d_bus)
827 {
828 struct descriptor *d = NULL;
829 struct descriptor_buffer *desc = ctx->buffer_tail;
830
831 if (z * sizeof(*d) > desc->buffer_size)
832 return NULL;
833
834 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
835 /* No room for the descriptor in this buffer, so advance to the
836 * next one. */
837
838 if (desc->list.next == &ctx->buffer_list) {
839 /* If there is no free buffer next in the list,
840 * allocate one. */
841 if (context_add_buffer(ctx) < 0)
842 return NULL;
843 }
844 desc = list_entry(desc->list.next,
845 struct descriptor_buffer, list);
846 ctx->buffer_tail = desc;
847 }
848
849 d = desc->buffer + desc->used / sizeof(*d);
850 memset(d, 0, z * sizeof(*d));
851 *d_bus = desc->buffer_bus + desc->used;
852
853 return d;
854 }
855
856 static void context_run(struct context *ctx, u32 extra)
857 {
858 struct fw_ohci *ohci = ctx->ohci;
859
860 reg_write(ohci, COMMAND_PTR(ctx->regs),
861 le32_to_cpu(ctx->last->branch_address));
862 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
863 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
864 flush_writes(ohci);
865 }
866
867 static void context_append(struct context *ctx,
868 struct descriptor *d, int z, int extra)
869 {
870 dma_addr_t d_bus;
871 struct descriptor_buffer *desc = ctx->buffer_tail;
872
873 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
874
875 desc->used += (z + extra) * sizeof(*d);
876 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
877 ctx->prev = find_branch_descriptor(d, z);
878
879 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
880 flush_writes(ctx->ohci);
881 }
882
883 static void context_stop(struct context *ctx)
884 {
885 u32 reg;
886 int i;
887
888 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
889 flush_writes(ctx->ohci);
890
891 for (i = 0; i < 10; i++) {
892 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
893 if ((reg & CONTEXT_ACTIVE) == 0)
894 return;
895
896 mdelay(1);
897 }
898 fw_error("Error: DMA context still active (0x%08x)\n", reg);
899 }
900
901 struct driver_data {
902 struct fw_packet *packet;
903 };
904
905 /*
906 * This function apppends a packet to the DMA queue for transmission.
907 * Must always be called with the ochi->lock held to ensure proper
908 * generation handling and locking around packet queue manipulation.
909 */
910 static int at_context_queue_packet(struct context *ctx,
911 struct fw_packet *packet)
912 {
913 struct fw_ohci *ohci = ctx->ohci;
914 dma_addr_t d_bus, uninitialized_var(payload_bus);
915 struct driver_data *driver_data;
916 struct descriptor *d, *last;
917 __le32 *header;
918 int z, tcode;
919 u32 reg;
920
921 d = context_get_descriptors(ctx, 4, &d_bus);
922 if (d == NULL) {
923 packet->ack = RCODE_SEND_ERROR;
924 return -1;
925 }
926
927 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
928 d[0].res_count = cpu_to_le16(packet->timestamp);
929
930 /*
931 * The DMA format for asyncronous link packets is different
932 * from the IEEE1394 layout, so shift the fields around
933 * accordingly. If header_length is 8, it's a PHY packet, to
934 * which we need to prepend an extra quadlet.
935 */
936
937 header = (__le32 *) &d[1];
938 if (packet->header_length > 8) {
939 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
940 (packet->speed << 16));
941 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
942 (packet->header[0] & 0xffff0000));
943 header[2] = cpu_to_le32(packet->header[2]);
944
945 tcode = (packet->header[0] >> 4) & 0x0f;
946 if (TCODE_IS_BLOCK_PACKET(tcode))
947 header[3] = cpu_to_le32(packet->header[3]);
948 else
949 header[3] = (__force __le32) packet->header[3];
950
951 d[0].req_count = cpu_to_le16(packet->header_length);
952 } else {
953 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
954 (packet->speed << 16));
955 header[1] = cpu_to_le32(packet->header[0]);
956 header[2] = cpu_to_le32(packet->header[1]);
957 d[0].req_count = cpu_to_le16(12);
958 }
959
960 driver_data = (struct driver_data *) &d[3];
961 driver_data->packet = packet;
962 packet->driver_data = driver_data;
963
964 if (packet->payload_length > 0) {
965 payload_bus =
966 dma_map_single(ohci->card.device, packet->payload,
967 packet->payload_length, DMA_TO_DEVICE);
968 if (dma_mapping_error(ohci->card.device, payload_bus)) {
969 packet->ack = RCODE_SEND_ERROR;
970 return -1;
971 }
972 packet->payload_bus = payload_bus;
973
974 d[2].req_count = cpu_to_le16(packet->payload_length);
975 d[2].data_address = cpu_to_le32(payload_bus);
976 last = &d[2];
977 z = 3;
978 } else {
979 last = &d[0];
980 z = 2;
981 }
982
983 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
984 DESCRIPTOR_IRQ_ALWAYS |
985 DESCRIPTOR_BRANCH_ALWAYS);
986
987 /*
988 * If the controller and packet generations don't match, we need to
989 * bail out and try again. If IntEvent.busReset is set, the AT context
990 * is halted, so appending to the context and trying to run it is
991 * futile. Most controllers do the right thing and just flush the AT
992 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
993 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
994 * up stalling out. So we just bail out in software and try again
995 * later, and everyone is happy.
996 * FIXME: Document how the locking works.
997 */
998 if (ohci->generation != packet->generation ||
999 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1000 if (packet->payload_length > 0)
1001 dma_unmap_single(ohci->card.device, payload_bus,
1002 packet->payload_length, DMA_TO_DEVICE);
1003 packet->ack = RCODE_GENERATION;
1004 return -1;
1005 }
1006
1007 context_append(ctx, d, z, 4 - z);
1008
1009 /* If the context isn't already running, start it up. */
1010 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1011 if ((reg & CONTEXT_RUN) == 0)
1012 context_run(ctx, 0);
1013
1014 return 0;
1015 }
1016
1017 static int handle_at_packet(struct context *context,
1018 struct descriptor *d,
1019 struct descriptor *last)
1020 {
1021 struct driver_data *driver_data;
1022 struct fw_packet *packet;
1023 struct fw_ohci *ohci = context->ohci;
1024 int evt;
1025
1026 if (last->transfer_status == 0)
1027 /* This descriptor isn't done yet, stop iteration. */
1028 return 0;
1029
1030 driver_data = (struct driver_data *) &d[3];
1031 packet = driver_data->packet;
1032 if (packet == NULL)
1033 /* This packet was cancelled, just continue. */
1034 return 1;
1035
1036 if (packet->payload_bus)
1037 dma_unmap_single(ohci->card.device, packet->payload_bus,
1038 packet->payload_length, DMA_TO_DEVICE);
1039
1040 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1041 packet->timestamp = le16_to_cpu(last->res_count);
1042
1043 log_ar_at_event('T', packet->speed, packet->header, evt);
1044
1045 switch (evt) {
1046 case OHCI1394_evt_timeout:
1047 /* Async response transmit timed out. */
1048 packet->ack = RCODE_CANCELLED;
1049 break;
1050
1051 case OHCI1394_evt_flushed:
1052 /*
1053 * The packet was flushed should give same error as
1054 * when we try to use a stale generation count.
1055 */
1056 packet->ack = RCODE_GENERATION;
1057 break;
1058
1059 case OHCI1394_evt_missing_ack:
1060 /*
1061 * Using a valid (current) generation count, but the
1062 * node is not on the bus or not sending acks.
1063 */
1064 packet->ack = RCODE_NO_ACK;
1065 break;
1066
1067 case ACK_COMPLETE + 0x10:
1068 case ACK_PENDING + 0x10:
1069 case ACK_BUSY_X + 0x10:
1070 case ACK_BUSY_A + 0x10:
1071 case ACK_BUSY_B + 0x10:
1072 case ACK_DATA_ERROR + 0x10:
1073 case ACK_TYPE_ERROR + 0x10:
1074 packet->ack = evt - 0x10;
1075 break;
1076
1077 default:
1078 packet->ack = RCODE_SEND_ERROR;
1079 break;
1080 }
1081
1082 packet->callback(packet, &ohci->card, packet->ack);
1083
1084 return 1;
1085 }
1086
1087 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1088 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1089 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1090 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1091 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1092
1093 static void handle_local_rom(struct fw_ohci *ohci,
1094 struct fw_packet *packet, u32 csr)
1095 {
1096 struct fw_packet response;
1097 int tcode, length, i;
1098
1099 tcode = HEADER_GET_TCODE(packet->header[0]);
1100 if (TCODE_IS_BLOCK_PACKET(tcode))
1101 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1102 else
1103 length = 4;
1104
1105 i = csr - CSR_CONFIG_ROM;
1106 if (i + length > CONFIG_ROM_SIZE) {
1107 fw_fill_response(&response, packet->header,
1108 RCODE_ADDRESS_ERROR, NULL, 0);
1109 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1110 fw_fill_response(&response, packet->header,
1111 RCODE_TYPE_ERROR, NULL, 0);
1112 } else {
1113 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1114 (void *) ohci->config_rom + i, length);
1115 }
1116
1117 fw_core_handle_response(&ohci->card, &response);
1118 }
1119
1120 static void handle_local_lock(struct fw_ohci *ohci,
1121 struct fw_packet *packet, u32 csr)
1122 {
1123 struct fw_packet response;
1124 int tcode, length, ext_tcode, sel;
1125 __be32 *payload, lock_old;
1126 u32 lock_arg, lock_data;
1127
1128 tcode = HEADER_GET_TCODE(packet->header[0]);
1129 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1130 payload = packet->payload;
1131 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1132
1133 if (tcode == TCODE_LOCK_REQUEST &&
1134 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1135 lock_arg = be32_to_cpu(payload[0]);
1136 lock_data = be32_to_cpu(payload[1]);
1137 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1138 lock_arg = 0;
1139 lock_data = 0;
1140 } else {
1141 fw_fill_response(&response, packet->header,
1142 RCODE_TYPE_ERROR, NULL, 0);
1143 goto out;
1144 }
1145
1146 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1147 reg_write(ohci, OHCI1394_CSRData, lock_data);
1148 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1149 reg_write(ohci, OHCI1394_CSRControl, sel);
1150
1151 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1152 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1153 else
1154 fw_notify("swap not done yet\n");
1155
1156 fw_fill_response(&response, packet->header,
1157 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1158 out:
1159 fw_core_handle_response(&ohci->card, &response);
1160 }
1161
1162 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1163 {
1164 u64 offset;
1165 u32 csr;
1166
1167 if (ctx == &ctx->ohci->at_request_ctx) {
1168 packet->ack = ACK_PENDING;
1169 packet->callback(packet, &ctx->ohci->card, packet->ack);
1170 }
1171
1172 offset =
1173 ((unsigned long long)
1174 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1175 packet->header[2];
1176 csr = offset - CSR_REGISTER_BASE;
1177
1178 /* Handle config rom reads. */
1179 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1180 handle_local_rom(ctx->ohci, packet, csr);
1181 else switch (csr) {
1182 case CSR_BUS_MANAGER_ID:
1183 case CSR_BANDWIDTH_AVAILABLE:
1184 case CSR_CHANNELS_AVAILABLE_HI:
1185 case CSR_CHANNELS_AVAILABLE_LO:
1186 handle_local_lock(ctx->ohci, packet, csr);
1187 break;
1188 default:
1189 if (ctx == &ctx->ohci->at_request_ctx)
1190 fw_core_handle_request(&ctx->ohci->card, packet);
1191 else
1192 fw_core_handle_response(&ctx->ohci->card, packet);
1193 break;
1194 }
1195
1196 if (ctx == &ctx->ohci->at_response_ctx) {
1197 packet->ack = ACK_COMPLETE;
1198 packet->callback(packet, &ctx->ohci->card, packet->ack);
1199 }
1200 }
1201
1202 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1203 {
1204 unsigned long flags;
1205 int ret;
1206
1207 spin_lock_irqsave(&ctx->ohci->lock, flags);
1208
1209 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1210 ctx->ohci->generation == packet->generation) {
1211 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1212 handle_local_request(ctx, packet);
1213 return;
1214 }
1215
1216 ret = at_context_queue_packet(ctx, packet);
1217 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1218
1219 if (ret < 0)
1220 packet->callback(packet, &ctx->ohci->card, packet->ack);
1221
1222 }
1223
1224 static void bus_reset_tasklet(unsigned long data)
1225 {
1226 struct fw_ohci *ohci = (struct fw_ohci *)data;
1227 int self_id_count, i, j, reg;
1228 int generation, new_generation;
1229 unsigned long flags;
1230 void *free_rom = NULL;
1231 dma_addr_t free_rom_bus = 0;
1232
1233 reg = reg_read(ohci, OHCI1394_NodeID);
1234 if (!(reg & OHCI1394_NodeID_idValid)) {
1235 fw_notify("node ID not valid, new bus reset in progress\n");
1236 return;
1237 }
1238 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1239 fw_notify("malconfigured bus\n");
1240 return;
1241 }
1242 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1243 OHCI1394_NodeID_nodeNumber);
1244
1245 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1246 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1247 fw_notify("inconsistent self IDs\n");
1248 return;
1249 }
1250 /*
1251 * The count in the SelfIDCount register is the number of
1252 * bytes in the self ID receive buffer. Since we also receive
1253 * the inverted quadlets and a header quadlet, we shift one
1254 * bit extra to get the actual number of self IDs.
1255 */
1256 self_id_count = (reg >> 3) & 0x3ff;
1257 if (self_id_count == 0) {
1258 fw_notify("inconsistent self IDs\n");
1259 return;
1260 }
1261 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1262 rmb();
1263
1264 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1265 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1266 fw_notify("inconsistent self IDs\n");
1267 return;
1268 }
1269 ohci->self_id_buffer[j] =
1270 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1271 }
1272 rmb();
1273
1274 /*
1275 * Check the consistency of the self IDs we just read. The
1276 * problem we face is that a new bus reset can start while we
1277 * read out the self IDs from the DMA buffer. If this happens,
1278 * the DMA buffer will be overwritten with new self IDs and we
1279 * will read out inconsistent data. The OHCI specification
1280 * (section 11.2) recommends a technique similar to
1281 * linux/seqlock.h, where we remember the generation of the
1282 * self IDs in the buffer before reading them out and compare
1283 * it to the current generation after reading them out. If
1284 * the two generations match we know we have a consistent set
1285 * of self IDs.
1286 */
1287
1288 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1289 if (new_generation != generation) {
1290 fw_notify("recursive bus reset detected, "
1291 "discarding self ids\n");
1292 return;
1293 }
1294
1295 /* FIXME: Document how the locking works. */
1296 spin_lock_irqsave(&ohci->lock, flags);
1297
1298 ohci->generation = generation;
1299 context_stop(&ohci->at_request_ctx);
1300 context_stop(&ohci->at_response_ctx);
1301 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1302
1303 if (ohci->bus_reset_packet_quirk)
1304 ohci->request_generation = generation;
1305
1306 /*
1307 * This next bit is unrelated to the AT context stuff but we
1308 * have to do it under the spinlock also. If a new config rom
1309 * was set up before this reset, the old one is now no longer
1310 * in use and we can free it. Update the config rom pointers
1311 * to point to the current config rom and clear the
1312 * next_config_rom pointer so a new udpate can take place.
1313 */
1314
1315 if (ohci->next_config_rom != NULL) {
1316 if (ohci->next_config_rom != ohci->config_rom) {
1317 free_rom = ohci->config_rom;
1318 free_rom_bus = ohci->config_rom_bus;
1319 }
1320 ohci->config_rom = ohci->next_config_rom;
1321 ohci->config_rom_bus = ohci->next_config_rom_bus;
1322 ohci->next_config_rom = NULL;
1323
1324 /*
1325 * Restore config_rom image and manually update
1326 * config_rom registers. Writing the header quadlet
1327 * will indicate that the config rom is ready, so we
1328 * do that last.
1329 */
1330 reg_write(ohci, OHCI1394_BusOptions,
1331 be32_to_cpu(ohci->config_rom[2]));
1332 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1333 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1334 }
1335
1336 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1337 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1338 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1339 #endif
1340
1341 spin_unlock_irqrestore(&ohci->lock, flags);
1342
1343 if (free_rom)
1344 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1345 free_rom, free_rom_bus);
1346
1347 log_selfids(ohci->node_id, generation,
1348 self_id_count, ohci->self_id_buffer);
1349
1350 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1351 self_id_count, ohci->self_id_buffer);
1352 }
1353
1354 static irqreturn_t irq_handler(int irq, void *data)
1355 {
1356 struct fw_ohci *ohci = data;
1357 u32 event, iso_event, cycle_time;
1358 int i;
1359
1360 event = reg_read(ohci, OHCI1394_IntEventClear);
1361
1362 if (!event || !~event)
1363 return IRQ_NONE;
1364
1365 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1366 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1367 log_irqs(event);
1368
1369 if (event & OHCI1394_selfIDComplete)
1370 tasklet_schedule(&ohci->bus_reset_tasklet);
1371
1372 if (event & OHCI1394_RQPkt)
1373 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1374
1375 if (event & OHCI1394_RSPkt)
1376 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1377
1378 if (event & OHCI1394_reqTxComplete)
1379 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1380
1381 if (event & OHCI1394_respTxComplete)
1382 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1383
1384 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1385 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1386
1387 while (iso_event) {
1388 i = ffs(iso_event) - 1;
1389 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1390 iso_event &= ~(1 << i);
1391 }
1392
1393 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1394 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1395
1396 while (iso_event) {
1397 i = ffs(iso_event) - 1;
1398 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1399 iso_event &= ~(1 << i);
1400 }
1401
1402 if (unlikely(event & OHCI1394_regAccessFail))
1403 fw_error("Register access failure - "
1404 "please notify linux1394-devel@lists.sf.net\n");
1405
1406 if (unlikely(event & OHCI1394_postedWriteErr))
1407 fw_error("PCI posted write error\n");
1408
1409 if (unlikely(event & OHCI1394_cycleTooLong)) {
1410 if (printk_ratelimit())
1411 fw_notify("isochronous cycle too long\n");
1412 reg_write(ohci, OHCI1394_LinkControlSet,
1413 OHCI1394_LinkControl_cycleMaster);
1414 }
1415
1416 if (event & OHCI1394_cycle64Seconds) {
1417 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1418 if ((cycle_time & 0x80000000) == 0)
1419 ohci->bus_seconds++;
1420 }
1421
1422 return IRQ_HANDLED;
1423 }
1424
1425 static int software_reset(struct fw_ohci *ohci)
1426 {
1427 int i;
1428
1429 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1430
1431 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1432 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1433 OHCI1394_HCControl_softReset) == 0)
1434 return 0;
1435 msleep(1);
1436 }
1437
1438 return -EBUSY;
1439 }
1440
1441 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1442 {
1443 struct fw_ohci *ohci = fw_ohci(card);
1444 struct pci_dev *dev = to_pci_dev(card->device);
1445 u32 lps;
1446 int i;
1447
1448 if (software_reset(ohci)) {
1449 fw_error("Failed to reset ohci card.\n");
1450 return -EBUSY;
1451 }
1452
1453 /*
1454 * Now enable LPS, which we need in order to start accessing
1455 * most of the registers. In fact, on some cards (ALI M5251),
1456 * accessing registers in the SClk domain without LPS enabled
1457 * will lock up the machine. Wait 50msec to make sure we have
1458 * full link enabled. However, with some cards (well, at least
1459 * a JMicron PCIe card), we have to try again sometimes.
1460 */
1461 reg_write(ohci, OHCI1394_HCControlSet,
1462 OHCI1394_HCControl_LPS |
1463 OHCI1394_HCControl_postedWriteEnable);
1464 flush_writes(ohci);
1465
1466 for (lps = 0, i = 0; !lps && i < 3; i++) {
1467 msleep(50);
1468 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1469 OHCI1394_HCControl_LPS;
1470 }
1471
1472 if (!lps) {
1473 fw_error("Failed to set Link Power Status\n");
1474 return -EIO;
1475 }
1476
1477 reg_write(ohci, OHCI1394_HCControlClear,
1478 OHCI1394_HCControl_noByteSwapData);
1479
1480 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1481 reg_write(ohci, OHCI1394_LinkControlClear,
1482 OHCI1394_LinkControl_rcvPhyPkt);
1483 reg_write(ohci, OHCI1394_LinkControlSet,
1484 OHCI1394_LinkControl_rcvSelfID |
1485 OHCI1394_LinkControl_cycleTimerEnable |
1486 OHCI1394_LinkControl_cycleMaster);
1487
1488 reg_write(ohci, OHCI1394_ATRetries,
1489 OHCI1394_MAX_AT_REQ_RETRIES |
1490 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1491 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1492
1493 ar_context_run(&ohci->ar_request_ctx);
1494 ar_context_run(&ohci->ar_response_ctx);
1495
1496 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1497 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1498 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1499 reg_write(ohci, OHCI1394_IntMaskSet,
1500 OHCI1394_selfIDComplete |
1501 OHCI1394_RQPkt | OHCI1394_RSPkt |
1502 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1503 OHCI1394_isochRx | OHCI1394_isochTx |
1504 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1505 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1506 OHCI1394_masterIntEnable);
1507 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1508 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1509
1510 /* Activate link_on bit and contender bit in our self ID packets.*/
1511 if (ohci_update_phy_reg(card, 4, 0,
1512 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1513 return -EIO;
1514
1515 /*
1516 * When the link is not yet enabled, the atomic config rom
1517 * update mechanism described below in ohci_set_config_rom()
1518 * is not active. We have to update ConfigRomHeader and
1519 * BusOptions manually, and the write to ConfigROMmap takes
1520 * effect immediately. We tie this to the enabling of the
1521 * link, so we have a valid config rom before enabling - the
1522 * OHCI requires that ConfigROMhdr and BusOptions have valid
1523 * values before enabling.
1524 *
1525 * However, when the ConfigROMmap is written, some controllers
1526 * always read back quadlets 0 and 2 from the config rom to
1527 * the ConfigRomHeader and BusOptions registers on bus reset.
1528 * They shouldn't do that in this initial case where the link
1529 * isn't enabled. This means we have to use the same
1530 * workaround here, setting the bus header to 0 and then write
1531 * the right values in the bus reset tasklet.
1532 */
1533
1534 if (config_rom) {
1535 ohci->next_config_rom =
1536 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1537 &ohci->next_config_rom_bus,
1538 GFP_KERNEL);
1539 if (ohci->next_config_rom == NULL)
1540 return -ENOMEM;
1541
1542 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1543 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1544 } else {
1545 /*
1546 * In the suspend case, config_rom is NULL, which
1547 * means that we just reuse the old config rom.
1548 */
1549 ohci->next_config_rom = ohci->config_rom;
1550 ohci->next_config_rom_bus = ohci->config_rom_bus;
1551 }
1552
1553 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1554 ohci->next_config_rom[0] = 0;
1555 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1556 reg_write(ohci, OHCI1394_BusOptions,
1557 be32_to_cpu(ohci->next_config_rom[2]));
1558 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1559
1560 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1561
1562 if (request_irq(dev->irq, irq_handler,
1563 IRQF_SHARED, ohci_driver_name, ohci)) {
1564 fw_error("Failed to allocate shared interrupt %d.\n",
1565 dev->irq);
1566 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1567 ohci->config_rom, ohci->config_rom_bus);
1568 return -EIO;
1569 }
1570
1571 reg_write(ohci, OHCI1394_HCControlSet,
1572 OHCI1394_HCControl_linkEnable |
1573 OHCI1394_HCControl_BIBimageValid);
1574 flush_writes(ohci);
1575
1576 /*
1577 * We are ready to go, initiate bus reset to finish the
1578 * initialization.
1579 */
1580
1581 fw_core_initiate_bus_reset(&ohci->card, 1);
1582
1583 return 0;
1584 }
1585
1586 static int ohci_set_config_rom(struct fw_card *card,
1587 u32 *config_rom, size_t length)
1588 {
1589 struct fw_ohci *ohci;
1590 unsigned long flags;
1591 int ret = -EBUSY;
1592 __be32 *next_config_rom;
1593 dma_addr_t uninitialized_var(next_config_rom_bus);
1594
1595 ohci = fw_ohci(card);
1596
1597 /*
1598 * When the OHCI controller is enabled, the config rom update
1599 * mechanism is a bit tricky, but easy enough to use. See
1600 * section 5.5.6 in the OHCI specification.
1601 *
1602 * The OHCI controller caches the new config rom address in a
1603 * shadow register (ConfigROMmapNext) and needs a bus reset
1604 * for the changes to take place. When the bus reset is
1605 * detected, the controller loads the new values for the
1606 * ConfigRomHeader and BusOptions registers from the specified
1607 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1608 * shadow register. All automatically and atomically.
1609 *
1610 * Now, there's a twist to this story. The automatic load of
1611 * ConfigRomHeader and BusOptions doesn't honor the
1612 * noByteSwapData bit, so with a be32 config rom, the
1613 * controller will load be32 values in to these registers
1614 * during the atomic update, even on litte endian
1615 * architectures. The workaround we use is to put a 0 in the
1616 * header quadlet; 0 is endian agnostic and means that the
1617 * config rom isn't ready yet. In the bus reset tasklet we
1618 * then set up the real values for the two registers.
1619 *
1620 * We use ohci->lock to avoid racing with the code that sets
1621 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1622 */
1623
1624 next_config_rom =
1625 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1626 &next_config_rom_bus, GFP_KERNEL);
1627 if (next_config_rom == NULL)
1628 return -ENOMEM;
1629
1630 spin_lock_irqsave(&ohci->lock, flags);
1631
1632 if (ohci->next_config_rom == NULL) {
1633 ohci->next_config_rom = next_config_rom;
1634 ohci->next_config_rom_bus = next_config_rom_bus;
1635
1636 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1637 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1638 length * 4);
1639
1640 ohci->next_header = config_rom[0];
1641 ohci->next_config_rom[0] = 0;
1642
1643 reg_write(ohci, OHCI1394_ConfigROMmap,
1644 ohci->next_config_rom_bus);
1645 ret = 0;
1646 }
1647
1648 spin_unlock_irqrestore(&ohci->lock, flags);
1649
1650 /*
1651 * Now initiate a bus reset to have the changes take
1652 * effect. We clean up the old config rom memory and DMA
1653 * mappings in the bus reset tasklet, since the OHCI
1654 * controller could need to access it before the bus reset
1655 * takes effect.
1656 */
1657 if (ret == 0)
1658 fw_core_initiate_bus_reset(&ohci->card, 1);
1659 else
1660 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1661 next_config_rom, next_config_rom_bus);
1662
1663 return ret;
1664 }
1665
1666 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1667 {
1668 struct fw_ohci *ohci = fw_ohci(card);
1669
1670 at_context_transmit(&ohci->at_request_ctx, packet);
1671 }
1672
1673 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1674 {
1675 struct fw_ohci *ohci = fw_ohci(card);
1676
1677 at_context_transmit(&ohci->at_response_ctx, packet);
1678 }
1679
1680 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1681 {
1682 struct fw_ohci *ohci = fw_ohci(card);
1683 struct context *ctx = &ohci->at_request_ctx;
1684 struct driver_data *driver_data = packet->driver_data;
1685 int ret = -ENOENT;
1686
1687 tasklet_disable(&ctx->tasklet);
1688
1689 if (packet->ack != 0)
1690 goto out;
1691
1692 if (packet->payload_bus)
1693 dma_unmap_single(ohci->card.device, packet->payload_bus,
1694 packet->payload_length, DMA_TO_DEVICE);
1695
1696 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1697 driver_data->packet = NULL;
1698 packet->ack = RCODE_CANCELLED;
1699 packet->callback(packet, &ohci->card, packet->ack);
1700 ret = 0;
1701 out:
1702 tasklet_enable(&ctx->tasklet);
1703
1704 return ret;
1705 }
1706
1707 static int ohci_enable_phys_dma(struct fw_card *card,
1708 int node_id, int generation)
1709 {
1710 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1711 return 0;
1712 #else
1713 struct fw_ohci *ohci = fw_ohci(card);
1714 unsigned long flags;
1715 int n, ret = 0;
1716
1717 /*
1718 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1719 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1720 */
1721
1722 spin_lock_irqsave(&ohci->lock, flags);
1723
1724 if (ohci->generation != generation) {
1725 ret = -ESTALE;
1726 goto out;
1727 }
1728
1729 /*
1730 * Note, if the node ID contains a non-local bus ID, physical DMA is
1731 * enabled for _all_ nodes on remote buses.
1732 */
1733
1734 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1735 if (n < 32)
1736 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1737 else
1738 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1739
1740 flush_writes(ohci);
1741 out:
1742 spin_unlock_irqrestore(&ohci->lock, flags);
1743
1744 return ret;
1745 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1746 }
1747
1748 static u64 ohci_get_bus_time(struct fw_card *card)
1749 {
1750 struct fw_ohci *ohci = fw_ohci(card);
1751 u32 cycle_time;
1752 u64 bus_time;
1753
1754 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1755 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1756
1757 return bus_time;
1758 }
1759
1760 static void copy_iso_headers(struct iso_context *ctx, void *p)
1761 {
1762 int i = ctx->header_length;
1763
1764 if (i + ctx->base.header_size > PAGE_SIZE)
1765 return;
1766
1767 /*
1768 * The iso header is byteswapped to little endian by
1769 * the controller, but the remaining header quadlets
1770 * are big endian. We want to present all the headers
1771 * as big endian, so we have to swap the first quadlet.
1772 */
1773 if (ctx->base.header_size > 0)
1774 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1775 if (ctx->base.header_size > 4)
1776 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1777 if (ctx->base.header_size > 8)
1778 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1779 ctx->header_length += ctx->base.header_size;
1780 }
1781
1782 static int handle_ir_dualbuffer_packet(struct context *context,
1783 struct descriptor *d,
1784 struct descriptor *last)
1785 {
1786 struct iso_context *ctx =
1787 container_of(context, struct iso_context, context);
1788 struct db_descriptor *db = (struct db_descriptor *) d;
1789 __le32 *ir_header;
1790 size_t header_length;
1791 void *p, *end;
1792
1793 if (db->first_res_count != 0 && db->second_res_count != 0) {
1794 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1795 /* This descriptor isn't done yet, stop iteration. */
1796 return 0;
1797 }
1798 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1799 }
1800
1801 header_length = le16_to_cpu(db->first_req_count) -
1802 le16_to_cpu(db->first_res_count);
1803
1804 p = db + 1;
1805 end = p + header_length;
1806 while (p < end) {
1807 copy_iso_headers(ctx, p);
1808 ctx->excess_bytes +=
1809 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1810 p += max(ctx->base.header_size, (size_t)8);
1811 }
1812
1813 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1814 le16_to_cpu(db->second_res_count);
1815
1816 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1817 ir_header = (__le32 *) (db + 1);
1818 ctx->base.callback(&ctx->base,
1819 le32_to_cpu(ir_header[0]) & 0xffff,
1820 ctx->header_length, ctx->header,
1821 ctx->base.callback_data);
1822 ctx->header_length = 0;
1823 }
1824
1825 return 1;
1826 }
1827
1828 static int handle_ir_packet_per_buffer(struct context *context,
1829 struct descriptor *d,
1830 struct descriptor *last)
1831 {
1832 struct iso_context *ctx =
1833 container_of(context, struct iso_context, context);
1834 struct descriptor *pd;
1835 __le32 *ir_header;
1836 void *p;
1837
1838 for (pd = d; pd <= last; pd++) {
1839 if (pd->transfer_status)
1840 break;
1841 }
1842 if (pd > last)
1843 /* Descriptor(s) not done yet, stop iteration */
1844 return 0;
1845
1846 p = last + 1;
1847 copy_iso_headers(ctx, p);
1848
1849 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1850 ir_header = (__le32 *) p;
1851 ctx->base.callback(&ctx->base,
1852 le32_to_cpu(ir_header[0]) & 0xffff,
1853 ctx->header_length, ctx->header,
1854 ctx->base.callback_data);
1855 ctx->header_length = 0;
1856 }
1857
1858 return 1;
1859 }
1860
1861 static int handle_it_packet(struct context *context,
1862 struct descriptor *d,
1863 struct descriptor *last)
1864 {
1865 struct iso_context *ctx =
1866 container_of(context, struct iso_context, context);
1867
1868 if (last->transfer_status == 0)
1869 /* This descriptor isn't done yet, stop iteration. */
1870 return 0;
1871
1872 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1873 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1874 0, NULL, ctx->base.callback_data);
1875
1876 return 1;
1877 }
1878
1879 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1880 int type, size_t header_size)
1881 {
1882 struct fw_ohci *ohci = fw_ohci(card);
1883 struct iso_context *ctx, *list;
1884 descriptor_callback_t callback;
1885 u32 *mask, regs;
1886 unsigned long flags;
1887 int index, ret = -ENOMEM;
1888
1889 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1890 mask = &ohci->it_context_mask;
1891 list = ohci->it_context_list;
1892 callback = handle_it_packet;
1893 } else {
1894 mask = &ohci->ir_context_mask;
1895 list = ohci->ir_context_list;
1896 if (ohci->use_dualbuffer)
1897 callback = handle_ir_dualbuffer_packet;
1898 else
1899 callback = handle_ir_packet_per_buffer;
1900 }
1901
1902 spin_lock_irqsave(&ohci->lock, flags);
1903 index = ffs(*mask) - 1;
1904 if (index >= 0)
1905 *mask &= ~(1 << index);
1906 spin_unlock_irqrestore(&ohci->lock, flags);
1907
1908 if (index < 0)
1909 return ERR_PTR(-EBUSY);
1910
1911 if (type == FW_ISO_CONTEXT_TRANSMIT)
1912 regs = OHCI1394_IsoXmitContextBase(index);
1913 else
1914 regs = OHCI1394_IsoRcvContextBase(index);
1915
1916 ctx = &list[index];
1917 memset(ctx, 0, sizeof(*ctx));
1918 ctx->header_length = 0;
1919 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1920 if (ctx->header == NULL)
1921 goto out;
1922
1923 ret = context_init(&ctx->context, ohci, regs, callback);
1924 if (ret < 0)
1925 goto out_with_header;
1926
1927 return &ctx->base;
1928
1929 out_with_header:
1930 free_page((unsigned long)ctx->header);
1931 out:
1932 spin_lock_irqsave(&ohci->lock, flags);
1933 *mask |= 1 << index;
1934 spin_unlock_irqrestore(&ohci->lock, flags);
1935
1936 return ERR_PTR(ret);
1937 }
1938
1939 static int ohci_start_iso(struct fw_iso_context *base,
1940 s32 cycle, u32 sync, u32 tags)
1941 {
1942 struct iso_context *ctx = container_of(base, struct iso_context, base);
1943 struct fw_ohci *ohci = ctx->context.ohci;
1944 u32 control, match;
1945 int index;
1946
1947 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1948 index = ctx - ohci->it_context_list;
1949 match = 0;
1950 if (cycle >= 0)
1951 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1952 (cycle & 0x7fff) << 16;
1953
1954 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1955 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1956 context_run(&ctx->context, match);
1957 } else {
1958 index = ctx - ohci->ir_context_list;
1959 control = IR_CONTEXT_ISOCH_HEADER;
1960 if (ohci->use_dualbuffer)
1961 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1962 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1963 if (cycle >= 0) {
1964 match |= (cycle & 0x07fff) << 12;
1965 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1966 }
1967
1968 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1969 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1970 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1971 context_run(&ctx->context, control);
1972 }
1973
1974 return 0;
1975 }
1976
1977 static int ohci_stop_iso(struct fw_iso_context *base)
1978 {
1979 struct fw_ohci *ohci = fw_ohci(base->card);
1980 struct iso_context *ctx = container_of(base, struct iso_context, base);
1981 int index;
1982
1983 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1984 index = ctx - ohci->it_context_list;
1985 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1986 } else {
1987 index = ctx - ohci->ir_context_list;
1988 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1989 }
1990 flush_writes(ohci);
1991 context_stop(&ctx->context);
1992
1993 return 0;
1994 }
1995
1996 static void ohci_free_iso_context(struct fw_iso_context *base)
1997 {
1998 struct fw_ohci *ohci = fw_ohci(base->card);
1999 struct iso_context *ctx = container_of(base, struct iso_context, base);
2000 unsigned long flags;
2001 int index;
2002
2003 ohci_stop_iso(base);
2004 context_release(&ctx->context);
2005 free_page((unsigned long)ctx->header);
2006
2007 spin_lock_irqsave(&ohci->lock, flags);
2008
2009 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2010 index = ctx - ohci->it_context_list;
2011 ohci->it_context_mask |= 1 << index;
2012 } else {
2013 index = ctx - ohci->ir_context_list;
2014 ohci->ir_context_mask |= 1 << index;
2015 }
2016
2017 spin_unlock_irqrestore(&ohci->lock, flags);
2018 }
2019
2020 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2021 struct fw_iso_packet *packet,
2022 struct fw_iso_buffer *buffer,
2023 unsigned long payload)
2024 {
2025 struct iso_context *ctx = container_of(base, struct iso_context, base);
2026 struct descriptor *d, *last, *pd;
2027 struct fw_iso_packet *p;
2028 __le32 *header;
2029 dma_addr_t d_bus, page_bus;
2030 u32 z, header_z, payload_z, irq;
2031 u32 payload_index, payload_end_index, next_page_index;
2032 int page, end_page, i, length, offset;
2033
2034 /*
2035 * FIXME: Cycle lost behavior should be configurable: lose
2036 * packet, retransmit or terminate..
2037 */
2038
2039 p = packet;
2040 payload_index = payload;
2041
2042 if (p->skip)
2043 z = 1;
2044 else
2045 z = 2;
2046 if (p->header_length > 0)
2047 z++;
2048
2049 /* Determine the first page the payload isn't contained in. */
2050 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2051 if (p->payload_length > 0)
2052 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2053 else
2054 payload_z = 0;
2055
2056 z += payload_z;
2057
2058 /* Get header size in number of descriptors. */
2059 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2060
2061 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2062 if (d == NULL)
2063 return -ENOMEM;
2064
2065 if (!p->skip) {
2066 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2067 d[0].req_count = cpu_to_le16(8);
2068
2069 header = (__le32 *) &d[1];
2070 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2071 IT_HEADER_TAG(p->tag) |
2072 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2073 IT_HEADER_CHANNEL(ctx->base.channel) |
2074 IT_HEADER_SPEED(ctx->base.speed));
2075 header[1] =
2076 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2077 p->payload_length));
2078 }
2079
2080 if (p->header_length > 0) {
2081 d[2].req_count = cpu_to_le16(p->header_length);
2082 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2083 memcpy(&d[z], p->header, p->header_length);
2084 }
2085
2086 pd = d + z - payload_z;
2087 payload_end_index = payload_index + p->payload_length;
2088 for (i = 0; i < payload_z; i++) {
2089 page = payload_index >> PAGE_SHIFT;
2090 offset = payload_index & ~PAGE_MASK;
2091 next_page_index = (page + 1) << PAGE_SHIFT;
2092 length =
2093 min(next_page_index, payload_end_index) - payload_index;
2094 pd[i].req_count = cpu_to_le16(length);
2095
2096 page_bus = page_private(buffer->pages[page]);
2097 pd[i].data_address = cpu_to_le32(page_bus + offset);
2098
2099 payload_index += length;
2100 }
2101
2102 if (p->interrupt)
2103 irq = DESCRIPTOR_IRQ_ALWAYS;
2104 else
2105 irq = DESCRIPTOR_NO_IRQ;
2106
2107 last = z == 2 ? d : d + z - 1;
2108 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2109 DESCRIPTOR_STATUS |
2110 DESCRIPTOR_BRANCH_ALWAYS |
2111 irq);
2112
2113 context_append(&ctx->context, d, z, header_z);
2114
2115 return 0;
2116 }
2117
2118 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2119 struct fw_iso_packet *packet,
2120 struct fw_iso_buffer *buffer,
2121 unsigned long payload)
2122 {
2123 struct iso_context *ctx = container_of(base, struct iso_context, base);
2124 struct db_descriptor *db = NULL;
2125 struct descriptor *d;
2126 struct fw_iso_packet *p;
2127 dma_addr_t d_bus, page_bus;
2128 u32 z, header_z, length, rest;
2129 int page, offset, packet_count, header_size;
2130
2131 /*
2132 * FIXME: Cycle lost behavior should be configurable: lose
2133 * packet, retransmit or terminate..
2134 */
2135
2136 p = packet;
2137 z = 2;
2138
2139 /*
2140 * The OHCI controller puts the isochronous header and trailer in the
2141 * buffer, so we need at least 8 bytes.
2142 */
2143 packet_count = p->header_length / ctx->base.header_size;
2144 header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2145
2146 /* Get header size in number of descriptors. */
2147 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2148 page = payload >> PAGE_SHIFT;
2149 offset = payload & ~PAGE_MASK;
2150 rest = p->payload_length;
2151
2152 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2153 while (rest > 0) {
2154 d = context_get_descriptors(&ctx->context,
2155 z + header_z, &d_bus);
2156 if (d == NULL)
2157 return -ENOMEM;
2158
2159 db = (struct db_descriptor *) d;
2160 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2161 DESCRIPTOR_BRANCH_ALWAYS);
2162 db->first_size =
2163 cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2164 if (p->skip && rest == p->payload_length) {
2165 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2166 db->first_req_count = db->first_size;
2167 } else {
2168 db->first_req_count = cpu_to_le16(header_size);
2169 }
2170 db->first_res_count = db->first_req_count;
2171 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2172
2173 if (p->skip && rest == p->payload_length)
2174 length = 4;
2175 else if (offset + rest < PAGE_SIZE)
2176 length = rest;
2177 else
2178 length = PAGE_SIZE - offset;
2179
2180 db->second_req_count = cpu_to_le16(length);
2181 db->second_res_count = db->second_req_count;
2182 page_bus = page_private(buffer->pages[page]);
2183 db->second_buffer = cpu_to_le32(page_bus + offset);
2184
2185 if (p->interrupt && length == rest)
2186 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2187
2188 context_append(&ctx->context, d, z, header_z);
2189 offset = (offset + length) & ~PAGE_MASK;
2190 rest -= length;
2191 if (offset == 0)
2192 page++;
2193 }
2194
2195 return 0;
2196 }
2197
2198 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2199 struct fw_iso_packet *packet,
2200 struct fw_iso_buffer *buffer,
2201 unsigned long payload)
2202 {
2203 struct iso_context *ctx = container_of(base, struct iso_context, base);
2204 struct descriptor *d = NULL, *pd = NULL;
2205 struct fw_iso_packet *p = packet;
2206 dma_addr_t d_bus, page_bus;
2207 u32 z, header_z, rest;
2208 int i, j, length;
2209 int page, offset, packet_count, header_size, payload_per_buffer;
2210
2211 /*
2212 * The OHCI controller puts the isochronous header and trailer in the
2213 * buffer, so we need at least 8 bytes.
2214 */
2215 packet_count = p->header_length / ctx->base.header_size;
2216 header_size = max(ctx->base.header_size, (size_t)8);
2217
2218 /* Get header size in number of descriptors. */
2219 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2220 page = payload >> PAGE_SHIFT;
2221 offset = payload & ~PAGE_MASK;
2222 payload_per_buffer = p->payload_length / packet_count;
2223
2224 for (i = 0; i < packet_count; i++) {
2225 /* d points to the header descriptor */
2226 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2227 d = context_get_descriptors(&ctx->context,
2228 z + header_z, &d_bus);
2229 if (d == NULL)
2230 return -ENOMEM;
2231
2232 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2233 DESCRIPTOR_INPUT_MORE);
2234 if (p->skip && i == 0)
2235 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2236 d->req_count = cpu_to_le16(header_size);
2237 d->res_count = d->req_count;
2238 d->transfer_status = 0;
2239 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2240
2241 rest = payload_per_buffer;
2242 for (j = 1; j < z; j++) {
2243 pd = d + j;
2244 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2245 DESCRIPTOR_INPUT_MORE);
2246
2247 if (offset + rest < PAGE_SIZE)
2248 length = rest;
2249 else
2250 length = PAGE_SIZE - offset;
2251 pd->req_count = cpu_to_le16(length);
2252 pd->res_count = pd->req_count;
2253 pd->transfer_status = 0;
2254
2255 page_bus = page_private(buffer->pages[page]);
2256 pd->data_address = cpu_to_le32(page_bus + offset);
2257
2258 offset = (offset + length) & ~PAGE_MASK;
2259 rest -= length;
2260 if (offset == 0)
2261 page++;
2262 }
2263 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2264 DESCRIPTOR_INPUT_LAST |
2265 DESCRIPTOR_BRANCH_ALWAYS);
2266 if (p->interrupt && i == packet_count - 1)
2267 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2268
2269 context_append(&ctx->context, d, z, header_z);
2270 }
2271
2272 return 0;
2273 }
2274
2275 static int ohci_queue_iso(struct fw_iso_context *base,
2276 struct fw_iso_packet *packet,
2277 struct fw_iso_buffer *buffer,
2278 unsigned long payload)
2279 {
2280 struct iso_context *ctx = container_of(base, struct iso_context, base);
2281 unsigned long flags;
2282 int ret;
2283
2284 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2285 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2286 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2287 else if (ctx->context.ohci->use_dualbuffer)
2288 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2289 buffer, payload);
2290 else
2291 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2292 buffer, payload);
2293 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2294
2295 return ret;
2296 }
2297
2298 static const struct fw_card_driver ohci_driver = {
2299 .enable = ohci_enable,
2300 .update_phy_reg = ohci_update_phy_reg,
2301 .set_config_rom = ohci_set_config_rom,
2302 .send_request = ohci_send_request,
2303 .send_response = ohci_send_response,
2304 .cancel_packet = ohci_cancel_packet,
2305 .enable_phys_dma = ohci_enable_phys_dma,
2306 .get_bus_time = ohci_get_bus_time,
2307
2308 .allocate_iso_context = ohci_allocate_iso_context,
2309 .free_iso_context = ohci_free_iso_context,
2310 .queue_iso = ohci_queue_iso,
2311 .start_iso = ohci_start_iso,
2312 .stop_iso = ohci_stop_iso,
2313 };
2314
2315 #ifdef CONFIG_PPC_PMAC
2316 static void ohci_pmac_on(struct pci_dev *dev)
2317 {
2318 if (machine_is(powermac)) {
2319 struct device_node *ofn = pci_device_to_OF_node(dev);
2320
2321 if (ofn) {
2322 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2323 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2324 }
2325 }
2326 }
2327
2328 static void ohci_pmac_off(struct pci_dev *dev)
2329 {
2330 if (machine_is(powermac)) {
2331 struct device_node *ofn = pci_device_to_OF_node(dev);
2332
2333 if (ofn) {
2334 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2335 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2336 }
2337 }
2338 }
2339 #else
2340 #define ohci_pmac_on(dev)
2341 #define ohci_pmac_off(dev)
2342 #endif /* CONFIG_PPC_PMAC */
2343
2344 static int __devinit pci_probe(struct pci_dev *dev,
2345 const struct pci_device_id *ent)
2346 {
2347 struct fw_ohci *ohci;
2348 u32 bus_options, max_receive, link_speed, version;
2349 u64 guid;
2350 int err;
2351 size_t size;
2352
2353 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2354 if (ohci == NULL) {
2355 err = -ENOMEM;
2356 goto fail;
2357 }
2358
2359 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2360
2361 ohci_pmac_on(dev);
2362
2363 err = pci_enable_device(dev);
2364 if (err) {
2365 fw_error("Failed to enable OHCI hardware\n");
2366 goto fail_free;
2367 }
2368
2369 pci_set_master(dev);
2370 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2371 pci_set_drvdata(dev, ohci);
2372
2373 spin_lock_init(&ohci->lock);
2374
2375 tasklet_init(&ohci->bus_reset_tasklet,
2376 bus_reset_tasklet, (unsigned long)ohci);
2377
2378 err = pci_request_region(dev, 0, ohci_driver_name);
2379 if (err) {
2380 fw_error("MMIO resource unavailable\n");
2381 goto fail_disable;
2382 }
2383
2384 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2385 if (ohci->registers == NULL) {
2386 fw_error("Failed to remap registers\n");
2387 err = -ENXIO;
2388 goto fail_iomem;
2389 }
2390
2391 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2392 ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2393
2394 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2395 #if !defined(CONFIG_X86_32)
2396 /* dual-buffer mode is broken with descriptor addresses above 2G */
2397 if (dev->vendor == PCI_VENDOR_ID_TI &&
2398 dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2399 ohci->use_dualbuffer = false;
2400 #endif
2401
2402 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2403 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2404 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2405 #endif
2406 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2407
2408 ar_context_init(&ohci->ar_request_ctx, ohci,
2409 OHCI1394_AsReqRcvContextControlSet);
2410
2411 ar_context_init(&ohci->ar_response_ctx, ohci,
2412 OHCI1394_AsRspRcvContextControlSet);
2413
2414 context_init(&ohci->at_request_ctx, ohci,
2415 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2416
2417 context_init(&ohci->at_response_ctx, ohci,
2418 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2419
2420 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2421 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2422 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2423 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2424 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2425
2426 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2427 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2428 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2429 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2430 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2431
2432 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2433 err = -ENOMEM;
2434 goto fail_contexts;
2435 }
2436
2437 /* self-id dma buffer allocation */
2438 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2439 SELF_ID_BUF_SIZE,
2440 &ohci->self_id_bus,
2441 GFP_KERNEL);
2442 if (ohci->self_id_cpu == NULL) {
2443 err = -ENOMEM;
2444 goto fail_contexts;
2445 }
2446
2447 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2448 max_receive = (bus_options >> 12) & 0xf;
2449 link_speed = bus_options & 0x7;
2450 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2451 reg_read(ohci, OHCI1394_GUIDLo);
2452
2453 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2454 if (err < 0)
2455 goto fail_self_id;
2456
2457 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2458 dev_name(&dev->dev), version >> 16, version & 0xff);
2459 return 0;
2460
2461 fail_self_id:
2462 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2463 ohci->self_id_cpu, ohci->self_id_bus);
2464 fail_contexts:
2465 kfree(ohci->ir_context_list);
2466 kfree(ohci->it_context_list);
2467 context_release(&ohci->at_response_ctx);
2468 context_release(&ohci->at_request_ctx);
2469 ar_context_release(&ohci->ar_response_ctx);
2470 ar_context_release(&ohci->ar_request_ctx);
2471 pci_iounmap(dev, ohci->registers);
2472 fail_iomem:
2473 pci_release_region(dev, 0);
2474 fail_disable:
2475 pci_disable_device(dev);
2476 fail_free:
2477 kfree(&ohci->card);
2478 ohci_pmac_off(dev);
2479 fail:
2480 if (err == -ENOMEM)
2481 fw_error("Out of memory\n");
2482
2483 return err;
2484 }
2485
2486 static void pci_remove(struct pci_dev *dev)
2487 {
2488 struct fw_ohci *ohci;
2489
2490 ohci = pci_get_drvdata(dev);
2491 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2492 flush_writes(ohci);
2493 fw_core_remove_card(&ohci->card);
2494
2495 /*
2496 * FIXME: Fail all pending packets here, now that the upper
2497 * layers can't queue any more.
2498 */
2499
2500 software_reset(ohci);
2501 free_irq(dev->irq, ohci);
2502
2503 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2504 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2505 ohci->next_config_rom, ohci->next_config_rom_bus);
2506 if (ohci->config_rom)
2507 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2508 ohci->config_rom, ohci->config_rom_bus);
2509 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2510 ohci->self_id_cpu, ohci->self_id_bus);
2511 ar_context_release(&ohci->ar_request_ctx);
2512 ar_context_release(&ohci->ar_response_ctx);
2513 context_release(&ohci->at_request_ctx);
2514 context_release(&ohci->at_response_ctx);
2515 kfree(ohci->it_context_list);
2516 kfree(ohci->ir_context_list);
2517 pci_iounmap(dev, ohci->registers);
2518 pci_release_region(dev, 0);
2519 pci_disable_device(dev);
2520 kfree(&ohci->card);
2521 ohci_pmac_off(dev);
2522
2523 fw_notify("Removed fw-ohci device.\n");
2524 }
2525
2526 #ifdef CONFIG_PM
2527 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2528 {
2529 struct fw_ohci *ohci = pci_get_drvdata(dev);
2530 int err;
2531
2532 software_reset(ohci);
2533 free_irq(dev->irq, ohci);
2534 err = pci_save_state(dev);
2535 if (err) {
2536 fw_error("pci_save_state failed\n");
2537 return err;
2538 }
2539 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2540 if (err)
2541 fw_error("pci_set_power_state failed with %d\n", err);
2542 ohci_pmac_off(dev);
2543
2544 return 0;
2545 }
2546
2547 static int pci_resume(struct pci_dev *dev)
2548 {
2549 struct fw_ohci *ohci = pci_get_drvdata(dev);
2550 int err;
2551
2552 ohci_pmac_on(dev);
2553 pci_set_power_state(dev, PCI_D0);
2554 pci_restore_state(dev);
2555 err = pci_enable_device(dev);
2556 if (err) {
2557 fw_error("pci_enable_device failed\n");
2558 return err;
2559 }
2560
2561 return ohci_enable(&ohci->card, NULL, 0);
2562 }
2563 #endif
2564
2565 static struct pci_device_id pci_table[] = {
2566 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2567 { }
2568 };
2569
2570 MODULE_DEVICE_TABLE(pci, pci_table);
2571
2572 static struct pci_driver fw_ohci_pci_driver = {
2573 .name = ohci_driver_name,
2574 .id_table = pci_table,
2575 .probe = pci_probe,
2576 .remove = pci_remove,
2577 #ifdef CONFIG_PM
2578 .resume = pci_resume,
2579 .suspend = pci_suspend,
2580 #endif
2581 };
2582
2583 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2584 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2585 MODULE_LICENSE("GPL");
2586
2587 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2588 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2589 MODULE_ALIAS("ohci1394");
2590 #endif
2591
2592 static int __init fw_ohci_init(void)
2593 {
2594 return pci_register_driver(&fw_ohci_pci_driver);
2595 }
2596
2597 static void __exit fw_ohci_cleanup(void)
2598 {
2599 pci_unregister_driver(&fw_ohci_pci_driver);
2600 }
2601
2602 module_init(fw_ohci_init);
2603 module_exit(fw_ohci_cleanup);
Linux kernel - Deliverables
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