1 /* -*- c-basic-offset: 8 -*-
3 * fw-ohci.c - Driver for OHCI 1394 boards
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/poll.h>
28 #include <linux/dma-mapping.h>
30 #include <asm/uaccess.h>
31 #include <asm/semaphore.h>
33 #include "fw-transaction.h"
36 #define descriptor_output_more 0
37 #define descriptor_output_last (1 << 12)
38 #define descriptor_input_more (2 << 12)
39 #define descriptor_input_last (3 << 12)
40 #define descriptor_status (1 << 11)
41 #define descriptor_key_immediate (2 << 8)
42 #define descriptor_ping (1 << 7)
43 #define descriptor_yy (1 << 6)
44 #define descriptor_no_irq (0 << 4)
45 #define descriptor_irq_error (1 << 4)
46 #define descriptor_irq_always (3 << 4)
47 #define descriptor_branch_always (3 << 2)
48 #define descriptor_wait (3 << 0)
54 __le32 branch_address
;
56 __le16 transfer_status
;
57 } __attribute__((aligned(16)));
59 struct db_descriptor
{
62 __le16 second_req_count
;
63 __le16 first_req_count
;
64 __le32 branch_address
;
65 __le16 second_res_count
;
66 __le16 first_res_count
;
71 } __attribute__((aligned(16)));
73 #define control_set(regs) (regs)
74 #define control_clear(regs) ((regs) + 4)
75 #define command_ptr(regs) ((regs) + 12)
76 #define context_match(regs) ((regs) + 16)
79 struct descriptor descriptor
;
80 struct ar_buffer
*next
;
86 struct ar_buffer
*current_buffer
;
87 struct ar_buffer
*last_buffer
;
90 struct tasklet_struct tasklet
;
95 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
97 struct descriptor
*last
);
102 struct descriptor
*buffer
;
103 dma_addr_t buffer_bus
;
105 struct descriptor
*head_descriptor
;
106 struct descriptor
*tail_descriptor
;
107 struct descriptor
*tail_descriptor_last
;
108 struct descriptor
*prev_descriptor
;
110 descriptor_callback_t callback
;
112 struct tasklet_struct tasklet
;
115 #define it_header_sy(v) ((v) << 0)
116 #define it_header_tcode(v) ((v) << 4)
117 #define it_header_channel(v) ((v) << 8)
118 #define it_header_tag(v) ((v) << 14)
119 #define it_header_speed(v) ((v) << 16)
120 #define it_header_data_length(v) ((v) << 16)
123 struct fw_iso_context base
;
124 struct context context
;
126 size_t header_length
;
129 #define CONFIG_ROM_SIZE 1024
135 __iomem
char *registers
;
136 dma_addr_t self_id_bus
;
138 struct tasklet_struct bus_reset_tasklet
;
141 int request_generation
;
143 /* Spinlock for accessing fw_ohci data. Never call out of
144 * this driver with this lock held. */
146 u32 self_id_buffer
[512];
148 /* Config rom buffers */
150 dma_addr_t config_rom_bus
;
151 __be32
*next_config_rom
;
152 dma_addr_t next_config_rom_bus
;
155 struct ar_context ar_request_ctx
;
156 struct ar_context ar_response_ctx
;
157 struct context at_request_ctx
;
158 struct context at_response_ctx
;
161 struct iso_context
*it_context_list
;
163 struct iso_context
*ir_context_list
;
166 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
168 return container_of(card
, struct fw_ohci
, card
);
171 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
172 #define IR_CONTEXT_BUFFER_FILL 0x80000000
173 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
174 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
175 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
176 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
178 #define CONTEXT_RUN 0x8000
179 #define CONTEXT_WAKE 0x1000
180 #define CONTEXT_DEAD 0x0800
181 #define CONTEXT_ACTIVE 0x0400
183 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
184 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
185 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
187 #define FW_OHCI_MAJOR 240
188 #define OHCI1394_REGISTER_SIZE 0x800
189 #define OHCI_LOOP_COUNT 500
190 #define OHCI1394_PCI_HCI_Control 0x40
191 #define SELF_ID_BUF_SIZE 0x800
192 #define OHCI_TCODE_PHY_PACKET 0x0e
193 #define OHCI_VERSION_1_1 0x010010
194 #define ISO_BUFFER_SIZE (64 * 1024)
195 #define AT_BUFFER_SIZE 4096
197 static char ohci_driver_name
[] = KBUILD_MODNAME
;
199 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
201 writel(data
, ohci
->registers
+ offset
);
204 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
206 return readl(ohci
->registers
+ offset
);
209 static inline void flush_writes(const struct fw_ohci
*ohci
)
211 /* Do a dummy read to flush writes. */
212 reg_read(ohci
, OHCI1394_Version
);
216 ohci_update_phy_reg(struct fw_card
*card
, int addr
,
217 int clear_bits
, int set_bits
)
219 struct fw_ohci
*ohci
= fw_ohci(card
);
222 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
224 val
= reg_read(ohci
, OHCI1394_PhyControl
);
225 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
226 fw_error("failed to set phy reg bits.\n");
230 old
= OHCI1394_PhyControl_ReadData(val
);
231 old
= (old
& ~clear_bits
) | set_bits
;
232 reg_write(ohci
, OHCI1394_PhyControl
,
233 OHCI1394_PhyControl_Write(addr
, old
));
238 static int ar_context_add_page(struct ar_context
*ctx
)
240 struct device
*dev
= ctx
->ohci
->card
.device
;
241 struct ar_buffer
*ab
;
245 ab
= (struct ar_buffer
*) __get_free_page(GFP_ATOMIC
);
249 ab_bus
= dma_map_single(dev
, ab
, PAGE_SIZE
, DMA_BIDIRECTIONAL
);
250 if (dma_mapping_error(ab_bus
)) {
251 free_page((unsigned long) ab
);
255 memset(&ab
->descriptor
, 0, sizeof ab
->descriptor
);
256 ab
->descriptor
.control
= cpu_to_le16(descriptor_input_more
|
258 descriptor_branch_always
);
259 offset
= offsetof(struct ar_buffer
, data
);
260 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
261 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
262 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
263 ab
->descriptor
.branch_address
= 0;
265 dma_sync_single_for_device(dev
, ab_bus
, PAGE_SIZE
, DMA_BIDIRECTIONAL
);
267 ctx
->last_buffer
->descriptor
.branch_address
= ab_bus
| 1;
268 ctx
->last_buffer
->next
= ab
;
269 ctx
->last_buffer
= ab
;
271 reg_write(ctx
->ohci
, control_set(ctx
->regs
), CONTEXT_WAKE
);
272 flush_writes(ctx
->ohci
);
277 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
279 struct fw_ohci
*ohci
= ctx
->ohci
;
281 u32 status
, length
, tcode
;
283 p
.header
[0] = le32_to_cpu(buffer
[0]);
284 p
.header
[1] = le32_to_cpu(buffer
[1]);
285 p
.header
[2] = le32_to_cpu(buffer
[2]);
287 tcode
= (p
.header
[0] >> 4) & 0x0f;
289 case TCODE_WRITE_QUADLET_REQUEST
:
290 case TCODE_READ_QUADLET_RESPONSE
:
291 p
.header
[3] = (__force __u32
) buffer
[3];
292 p
.header_length
= 16;
293 p
.payload_length
= 0;
296 case TCODE_READ_BLOCK_REQUEST
:
297 p
.header
[3] = le32_to_cpu(buffer
[3]);
298 p
.header_length
= 16;
299 p
.payload_length
= 0;
302 case TCODE_WRITE_BLOCK_REQUEST
:
303 case TCODE_READ_BLOCK_RESPONSE
:
304 case TCODE_LOCK_REQUEST
:
305 case TCODE_LOCK_RESPONSE
:
306 p
.header
[3] = le32_to_cpu(buffer
[3]);
307 p
.header_length
= 16;
308 p
.payload_length
= p
.header
[3] >> 16;
311 case TCODE_WRITE_RESPONSE
:
312 case TCODE_READ_QUADLET_REQUEST
:
313 case OHCI_TCODE_PHY_PACKET
:
314 p
.header_length
= 12;
315 p
.payload_length
= 0;
319 p
.payload
= (void *) buffer
+ p
.header_length
;
321 /* FIXME: What to do about evt_* errors? */
322 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
323 status
= le32_to_cpu(buffer
[length
]);
325 p
.ack
= ((status
>> 16) & 0x1f) - 16;
326 p
.speed
= (status
>> 21) & 0x7;
327 p
.timestamp
= status
& 0xffff;
328 p
.generation
= ohci
->request_generation
;
330 /* The OHCI bus reset handler synthesizes a phy packet with
331 * the new generation number when a bus reset happens (see
332 * section 8.4.2.3). This helps us determine when a request
333 * was received and make sure we send the response in the same
334 * generation. We only need this for requests; for responses
335 * we use the unique tlabel for finding the matching
338 if (p
.ack
+ 16 == 0x09)
339 ohci
->request_generation
= (buffer
[2] >> 16) & 0xff;
340 else if (ctx
== &ohci
->ar_request_ctx
)
341 fw_core_handle_request(&ohci
->card
, &p
);
343 fw_core_handle_response(&ohci
->card
, &p
);
345 return buffer
+ length
+ 1;
348 static void ar_context_tasklet(unsigned long data
)
350 struct ar_context
*ctx
= (struct ar_context
*)data
;
351 struct fw_ohci
*ohci
= ctx
->ohci
;
352 struct ar_buffer
*ab
;
353 struct descriptor
*d
;
356 ab
= ctx
->current_buffer
;
359 if (d
->res_count
== 0) {
360 size_t size
, rest
, offset
;
362 /* This descriptor is finished and we may have a
363 * packet split across this and the next buffer. We
364 * reuse the page for reassembling the split packet. */
366 offset
= offsetof(struct ar_buffer
, data
);
367 dma_unmap_single(ohci
->card
.device
,
368 ab
->descriptor
.data_address
- offset
,
369 PAGE_SIZE
, DMA_BIDIRECTIONAL
);
374 size
= buffer
+ PAGE_SIZE
- ctx
->pointer
;
375 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
376 memmove(buffer
, ctx
->pointer
, size
);
377 memcpy(buffer
+ size
, ab
->data
, rest
);
378 ctx
->current_buffer
= ab
;
379 ctx
->pointer
= (void *) ab
->data
+ rest
;
380 end
= buffer
+ size
+ rest
;
383 buffer
= handle_ar_packet(ctx
, buffer
);
385 free_page((unsigned long)buffer
);
386 ar_context_add_page(ctx
);
388 buffer
= ctx
->pointer
;
390 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
393 buffer
= handle_ar_packet(ctx
, buffer
);
398 ar_context_init(struct ar_context
*ctx
, struct fw_ohci
*ohci
, u32 regs
)
404 ctx
->last_buffer
= &ab
;
405 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
407 ar_context_add_page(ctx
);
408 ar_context_add_page(ctx
);
409 ctx
->current_buffer
= ab
.next
;
410 ctx
->pointer
= ctx
->current_buffer
->data
;
412 reg_write(ctx
->ohci
, command_ptr(ctx
->regs
), ab
.descriptor
.branch_address
);
413 reg_write(ctx
->ohci
, control_set(ctx
->regs
), CONTEXT_RUN
);
414 flush_writes(ctx
->ohci
);
419 static void context_tasklet(unsigned long data
)
421 struct context
*ctx
= (struct context
*) data
;
422 struct fw_ohci
*ohci
= ctx
->ohci
;
423 struct descriptor
*d
, *last
;
427 dma_sync_single_for_cpu(ohci
->card
.device
, ctx
->buffer_bus
,
428 ctx
->buffer_size
, DMA_TO_DEVICE
);
430 d
= ctx
->tail_descriptor
;
431 last
= ctx
->tail_descriptor_last
;
433 while (last
->branch_address
!= 0) {
434 address
= le32_to_cpu(last
->branch_address
);
436 d
= ctx
->buffer
+ (address
- ctx
->buffer_bus
) / sizeof *d
;
437 last
= (z
== 2) ? d
: d
+ z
- 1;
439 if (!ctx
->callback(ctx
, d
, last
))
442 ctx
->tail_descriptor
= d
;
443 ctx
->tail_descriptor_last
= last
;
448 context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
449 size_t buffer_size
, u32 regs
,
450 descriptor_callback_t callback
)
454 ctx
->buffer_size
= buffer_size
;
455 ctx
->buffer
= kmalloc(buffer_size
, GFP_KERNEL
);
456 if (ctx
->buffer
== NULL
)
459 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
460 ctx
->callback
= callback
;
463 dma_map_single(ohci
->card
.device
, ctx
->buffer
,
464 buffer_size
, DMA_TO_DEVICE
);
465 if (dma_mapping_error(ctx
->buffer_bus
)) {
470 ctx
->head_descriptor
= ctx
->buffer
;
471 ctx
->prev_descriptor
= ctx
->buffer
;
472 ctx
->tail_descriptor
= ctx
->buffer
;
473 ctx
->tail_descriptor_last
= ctx
->buffer
;
475 /* We put a dummy descriptor in the buffer that has a NULL
476 * branch address and looks like it's been sent. That way we
477 * have a descriptor to append DMA programs to. Also, the
478 * ring buffer invariant is that it always has at least one
479 * element so that head == tail means buffer full. */
481 memset(ctx
->head_descriptor
, 0, sizeof *ctx
->head_descriptor
);
482 ctx
->head_descriptor
->control
= cpu_to_le16(descriptor_output_last
);
483 ctx
->head_descriptor
->transfer_status
= cpu_to_le16(0x8011);
484 ctx
->head_descriptor
++;
490 context_release(struct context
*ctx
)
492 struct fw_card
*card
= &ctx
->ohci
->card
;
494 dma_unmap_single(card
->device
, ctx
->buffer_bus
,
495 ctx
->buffer_size
, DMA_TO_DEVICE
);
499 static struct descriptor
*
500 context_get_descriptors(struct context
*ctx
, int z
, dma_addr_t
*d_bus
)
502 struct descriptor
*d
, *tail
, *end
;
504 d
= ctx
->head_descriptor
;
505 tail
= ctx
->tail_descriptor
;
506 end
= ctx
->buffer
+ ctx
->buffer_size
/ sizeof(struct descriptor
);
510 } else if (d
> tail
&& d
+ z
<= end
) {
512 } else if (d
> tail
&& ctx
->buffer
+ z
<= tail
) {
520 memset(d
, 0, z
* sizeof *d
);
521 *d_bus
= ctx
->buffer_bus
+ (d
- ctx
->buffer
) * sizeof *d
;
526 static void context_run(struct context
*ctx
, u32 extra
)
528 struct fw_ohci
*ohci
= ctx
->ohci
;
530 reg_write(ohci
, command_ptr(ctx
->regs
),
531 le32_to_cpu(ctx
->tail_descriptor_last
->branch_address
));
532 reg_write(ohci
, control_clear(ctx
->regs
), ~0);
533 reg_write(ohci
, control_set(ctx
->regs
), CONTEXT_RUN
| extra
);
537 static void context_append(struct context
*ctx
,
538 struct descriptor
*d
, int z
, int extra
)
542 d_bus
= ctx
->buffer_bus
+ (d
- ctx
->buffer
) * sizeof *d
;
544 ctx
->head_descriptor
= d
+ z
+ extra
;
545 ctx
->prev_descriptor
->branch_address
= cpu_to_le32(d_bus
| z
);
546 ctx
->prev_descriptor
= z
== 2 ? d
: d
+ z
- 1;
548 dma_sync_single_for_device(ctx
->ohci
->card
.device
, ctx
->buffer_bus
,
549 ctx
->buffer_size
, DMA_TO_DEVICE
);
551 reg_write(ctx
->ohci
, control_set(ctx
->regs
), CONTEXT_WAKE
);
552 flush_writes(ctx
->ohci
);
555 static void context_stop(struct context
*ctx
)
560 reg_write(ctx
->ohci
, control_clear(ctx
->regs
), CONTEXT_RUN
);
561 flush_writes(ctx
->ohci
);
563 for (i
= 0; i
< 10; i
++) {
564 reg
= reg_read(ctx
->ohci
, control_set(ctx
->regs
));
565 if ((reg
& CONTEXT_ACTIVE
) == 0)
568 fw_notify("context_stop: still active (0x%08x)\n", reg
);
574 struct fw_packet
*packet
;
577 /* This function apppends a packet to the DMA queue for transmission.
578 * Must always be called with the ochi->lock held to ensure proper
579 * generation handling and locking around packet queue manipulation. */
581 at_context_queue_packet(struct context
*ctx
, struct fw_packet
*packet
)
583 struct fw_ohci
*ohci
= ctx
->ohci
;
584 dma_addr_t d_bus
, payload_bus
;
585 struct driver_data
*driver_data
;
586 struct descriptor
*d
, *last
;
591 d
= context_get_descriptors(ctx
, 4, &d_bus
);
593 packet
->ack
= RCODE_SEND_ERROR
;
597 d
[0].control
= cpu_to_le16(descriptor_key_immediate
);
598 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
600 /* The DMA format for asyncronous link packets is different
601 * from the IEEE1394 layout, so shift the fields around
602 * accordingly. If header_length is 8, it's a PHY packet, to
603 * which we need to prepend an extra quadlet. */
605 header
= (__le32
*) &d
[1];
606 if (packet
->header_length
> 8) {
607 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
608 (packet
->speed
<< 16));
609 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
610 (packet
->header
[0] & 0xffff0000));
611 header
[2] = cpu_to_le32(packet
->header
[2]);
613 tcode
= (packet
->header
[0] >> 4) & 0x0f;
614 if (TCODE_IS_BLOCK_PACKET(tcode
))
615 header
[3] = cpu_to_le32(packet
->header
[3]);
617 header
[3] = (__force __le32
) packet
->header
[3];
619 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
621 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
622 (packet
->speed
<< 16));
623 header
[1] = cpu_to_le32(packet
->header
[0]);
624 header
[2] = cpu_to_le32(packet
->header
[1]);
625 d
[0].req_count
= cpu_to_le16(12);
628 driver_data
= (struct driver_data
*) &d
[3];
629 driver_data
->packet
= packet
;
631 if (packet
->payload_length
> 0) {
633 dma_map_single(ohci
->card
.device
, packet
->payload
,
634 packet
->payload_length
, DMA_TO_DEVICE
);
635 if (dma_mapping_error(payload_bus
)) {
636 packet
->ack
= RCODE_SEND_ERROR
;
640 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
641 d
[2].data_address
= cpu_to_le32(payload_bus
);
649 last
->control
|= cpu_to_le16(descriptor_output_last
|
650 descriptor_irq_always
|
651 descriptor_branch_always
);
653 /* FIXME: Document how the locking works. */
654 if (ohci
->generation
!= packet
->generation
) {
655 packet
->ack
= RCODE_GENERATION
;
659 context_append(ctx
, d
, z
, 4 - z
);
661 /* If the context isn't already running, start it up. */
662 reg
= reg_read(ctx
->ohci
, control_set(ctx
->regs
));
663 if ((reg
& CONTEXT_ACTIVE
) == 0)
669 static int handle_at_packet(struct context
*context
,
670 struct descriptor
*d
,
671 struct descriptor
*last
)
673 struct driver_data
*driver_data
;
674 struct fw_packet
*packet
;
675 struct fw_ohci
*ohci
= context
->ohci
;
676 dma_addr_t payload_bus
;
679 if (last
->transfer_status
== 0)
680 /* This descriptor isn't done yet, stop iteration. */
683 driver_data
= (struct driver_data
*) &d
[3];
684 packet
= driver_data
->packet
;
686 /* This packet was cancelled, just continue. */
689 payload_bus
= le32_to_cpu(last
->data_address
);
690 if (payload_bus
!= 0)
691 dma_unmap_single(ohci
->card
.device
, payload_bus
,
692 packet
->payload_length
, DMA_TO_DEVICE
);
694 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
695 packet
->timestamp
= le16_to_cpu(last
->res_count
);
698 case OHCI1394_evt_timeout
:
699 /* Async response transmit timed out. */
700 packet
->ack
= RCODE_CANCELLED
;
703 case OHCI1394_evt_flushed
:
704 /* The packet was flushed should give same error as
705 * when we try to use a stale generation count. */
706 packet
->ack
= RCODE_GENERATION
;
709 case OHCI1394_evt_missing_ack
:
710 /* Using a valid (current) generation count, but the
711 * node is not on the bus or not sending acks. */
712 packet
->ack
= RCODE_NO_ACK
;
715 case ACK_COMPLETE
+ 0x10:
716 case ACK_PENDING
+ 0x10:
717 case ACK_BUSY_X
+ 0x10:
718 case ACK_BUSY_A
+ 0x10:
719 case ACK_BUSY_B
+ 0x10:
720 case ACK_DATA_ERROR
+ 0x10:
721 case ACK_TYPE_ERROR
+ 0x10:
722 packet
->ack
= evt
- 0x10;
726 packet
->ack
= RCODE_SEND_ERROR
;
730 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
735 #define header_get_destination(q) (((q) >> 16) & 0xffff)
736 #define header_get_tcode(q) (((q) >> 4) & 0x0f)
737 #define header_get_offset_high(q) (((q) >> 0) & 0xffff)
738 #define header_get_data_length(q) (((q) >> 16) & 0xffff)
739 #define header_get_extended_tcode(q) (((q) >> 0) & 0xffff)
742 handle_local_rom(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
744 struct fw_packet response
;
745 int tcode
, length
, i
;
747 tcode
= header_get_tcode(packet
->header
[0]);
748 if (TCODE_IS_BLOCK_PACKET(tcode
))
749 length
= header_get_data_length(packet
->header
[3]);
753 i
= csr
- CSR_CONFIG_ROM
;
754 if (i
+ length
> CONFIG_ROM_SIZE
) {
755 fw_fill_response(&response
, packet
->header
,
756 RCODE_ADDRESS_ERROR
, NULL
, 0);
757 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
758 fw_fill_response(&response
, packet
->header
,
759 RCODE_TYPE_ERROR
, NULL
, 0);
761 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
762 (void *) ohci
->config_rom
+ i
, length
);
765 fw_core_handle_response(&ohci
->card
, &response
);
769 handle_local_lock(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
771 struct fw_packet response
;
772 int tcode
, length
, ext_tcode
, sel
;
773 __be32
*payload
, lock_old
;
774 u32 lock_arg
, lock_data
;
776 tcode
= header_get_tcode(packet
->header
[0]);
777 length
= header_get_data_length(packet
->header
[3]);
778 payload
= packet
->payload
;
779 ext_tcode
= header_get_extended_tcode(packet
->header
[3]);
781 if (tcode
== TCODE_LOCK_REQUEST
&&
782 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
783 lock_arg
= be32_to_cpu(payload
[0]);
784 lock_data
= be32_to_cpu(payload
[1]);
785 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
789 fw_fill_response(&response
, packet
->header
,
790 RCODE_TYPE_ERROR
, NULL
, 0);
794 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
795 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
796 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
797 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
799 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
800 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
802 fw_notify("swap not done yet\n");
804 fw_fill_response(&response
, packet
->header
,
805 RCODE_COMPLETE
, &lock_old
, sizeof lock_old
);
807 fw_core_handle_response(&ohci
->card
, &response
);
811 handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
816 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
817 packet
->ack
= ACK_PENDING
;
818 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
822 ((unsigned long long)
823 header_get_offset_high(packet
->header
[1]) << 32) |
825 csr
= offset
- CSR_REGISTER_BASE
;
827 /* Handle config rom reads. */
828 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
829 handle_local_rom(ctx
->ohci
, packet
, csr
);
831 case CSR_BUS_MANAGER_ID
:
832 case CSR_BANDWIDTH_AVAILABLE
:
833 case CSR_CHANNELS_AVAILABLE_HI
:
834 case CSR_CHANNELS_AVAILABLE_LO
:
835 handle_local_lock(ctx
->ohci
, packet
, csr
);
838 if (ctx
== &ctx
->ohci
->at_request_ctx
)
839 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
841 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
845 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
846 packet
->ack
= ACK_COMPLETE
;
847 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
852 at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
857 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
859 if (header_get_destination(packet
->header
[0]) == ctx
->ohci
->node_id
&&
860 ctx
->ohci
->generation
== packet
->generation
) {
861 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
862 handle_local_request(ctx
, packet
);
866 retval
= at_context_queue_packet(ctx
, packet
);
867 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
870 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
874 static void bus_reset_tasklet(unsigned long data
)
876 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
877 int self_id_count
, i
, j
, reg
;
878 int generation
, new_generation
;
881 reg
= reg_read(ohci
, OHCI1394_NodeID
);
882 if (!(reg
& OHCI1394_NodeID_idValid
)) {
883 fw_error("node ID not valid, new bus reset in progress\n");
886 ohci
->node_id
= reg
& 0xffff;
888 /* The count in the SelfIDCount register is the number of
889 * bytes in the self ID receive buffer. Since we also receive
890 * the inverted quadlets and a header quadlet, we shift one
891 * bit extra to get the actual number of self IDs. */
893 self_id_count
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 3) & 0x3ff;
894 generation
= (le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
896 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
897 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1])
898 fw_error("inconsistent self IDs\n");
899 ohci
->self_id_buffer
[j
] = le32_to_cpu(ohci
->self_id_cpu
[i
]);
902 /* Check the consistency of the self IDs we just read. The
903 * problem we face is that a new bus reset can start while we
904 * read out the self IDs from the DMA buffer. If this happens,
905 * the DMA buffer will be overwritten with new self IDs and we
906 * will read out inconsistent data. The OHCI specification
907 * (section 11.2) recommends a technique similar to
908 * linux/seqlock.h, where we remember the generation of the
909 * self IDs in the buffer before reading them out and compare
910 * it to the current generation after reading them out. If
911 * the two generations match we know we have a consistent set
914 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
915 if (new_generation
!= generation
) {
916 fw_notify("recursive bus reset detected, "
917 "discarding self ids\n");
921 /* FIXME: Document how the locking works. */
922 spin_lock_irqsave(&ohci
->lock
, flags
);
924 ohci
->generation
= generation
;
925 context_stop(&ohci
->at_request_ctx
);
926 context_stop(&ohci
->at_response_ctx
);
927 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
929 /* This next bit is unrelated to the AT context stuff but we
930 * have to do it under the spinlock also. If a new config rom
931 * was set up before this reset, the old one is now no longer
932 * in use and we can free it. Update the config rom pointers
933 * to point to the current config rom and clear the
934 * next_config_rom pointer so a new udpate can take place. */
936 if (ohci
->next_config_rom
!= NULL
) {
937 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
938 ohci
->config_rom
, ohci
->config_rom_bus
);
939 ohci
->config_rom
= ohci
->next_config_rom
;
940 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
941 ohci
->next_config_rom
= NULL
;
943 /* Restore config_rom image and manually update
944 * config_rom registers. Writing the header quadlet
945 * will indicate that the config rom is ready, so we
947 reg_write(ohci
, OHCI1394_BusOptions
,
948 be32_to_cpu(ohci
->config_rom
[2]));
949 ohci
->config_rom
[0] = cpu_to_be32(ohci
->next_header
);
950 reg_write(ohci
, OHCI1394_ConfigROMhdr
, ohci
->next_header
);
953 spin_unlock_irqrestore(&ohci
->lock
, flags
);
955 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
956 self_id_count
, ohci
->self_id_buffer
);
959 static irqreturn_t
irq_handler(int irq
, void *data
)
961 struct fw_ohci
*ohci
= data
;
962 u32 event
, iso_event
;
965 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
970 reg_write(ohci
, OHCI1394_IntEventClear
, event
);
972 if (event
& OHCI1394_selfIDComplete
)
973 tasklet_schedule(&ohci
->bus_reset_tasklet
);
975 if (event
& OHCI1394_RQPkt
)
976 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
978 if (event
& OHCI1394_RSPkt
)
979 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
981 if (event
& OHCI1394_reqTxComplete
)
982 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
984 if (event
& OHCI1394_respTxComplete
)
985 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
987 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
988 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
991 i
= ffs(iso_event
) - 1;
992 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
993 iso_event
&= ~(1 << i
);
996 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
997 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1000 i
= ffs(iso_event
) - 1;
1001 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1002 iso_event
&= ~(1 << i
);
1008 static int ohci_enable(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1010 struct fw_ohci
*ohci
= fw_ohci(card
);
1011 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1013 /* When the link is not yet enabled, the atomic config rom
1014 * update mechanism described below in ohci_set_config_rom()
1015 * is not active. We have to update ConfigRomHeader and
1016 * BusOptions manually, and the write to ConfigROMmap takes
1017 * effect immediately. We tie this to the enabling of the
1018 * link, so we have a valid config rom before enabling - the
1019 * OHCI requires that ConfigROMhdr and BusOptions have valid
1020 * values before enabling.
1022 * However, when the ConfigROMmap is written, some controllers
1023 * always read back quadlets 0 and 2 from the config rom to
1024 * the ConfigRomHeader and BusOptions registers on bus reset.
1025 * They shouldn't do that in this initial case where the link
1026 * isn't enabled. This means we have to use the same
1027 * workaround here, setting the bus header to 0 and then write
1028 * the right values in the bus reset tasklet.
1031 ohci
->next_config_rom
=
1032 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1033 &ohci
->next_config_rom_bus
, GFP_KERNEL
);
1034 if (ohci
->next_config_rom
== NULL
)
1037 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1038 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
, length
* 4);
1040 ohci
->next_header
= config_rom
[0];
1041 ohci
->next_config_rom
[0] = 0;
1042 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1043 reg_write(ohci
, OHCI1394_BusOptions
, config_rom
[2]);
1044 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1046 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1048 if (request_irq(dev
->irq
, irq_handler
,
1049 IRQF_SHARED
, ohci_driver_name
, ohci
)) {
1050 fw_error("Failed to allocate shared interrupt %d.\n",
1052 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1053 ohci
->config_rom
, ohci
->config_rom_bus
);
1057 reg_write(ohci
, OHCI1394_HCControlSet
,
1058 OHCI1394_HCControl_linkEnable
|
1059 OHCI1394_HCControl_BIBimageValid
);
1062 /* We are ready to go, initiate bus reset to finish the
1063 * initialization. */
1065 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1071 ohci_set_config_rom(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1073 struct fw_ohci
*ohci
;
1074 unsigned long flags
;
1076 __be32
*next_config_rom
;
1077 dma_addr_t next_config_rom_bus
;
1079 ohci
= fw_ohci(card
);
1081 /* When the OHCI controller is enabled, the config rom update
1082 * mechanism is a bit tricky, but easy enough to use. See
1083 * section 5.5.6 in the OHCI specification.
1085 * The OHCI controller caches the new config rom address in a
1086 * shadow register (ConfigROMmapNext) and needs a bus reset
1087 * for the changes to take place. When the bus reset is
1088 * detected, the controller loads the new values for the
1089 * ConfigRomHeader and BusOptions registers from the specified
1090 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1091 * shadow register. All automatically and atomically.
1093 * Now, there's a twist to this story. The automatic load of
1094 * ConfigRomHeader and BusOptions doesn't honor the
1095 * noByteSwapData bit, so with a be32 config rom, the
1096 * controller will load be32 values in to these registers
1097 * during the atomic update, even on litte endian
1098 * architectures. The workaround we use is to put a 0 in the
1099 * header quadlet; 0 is endian agnostic and means that the
1100 * config rom isn't ready yet. In the bus reset tasklet we
1101 * then set up the real values for the two registers.
1103 * We use ohci->lock to avoid racing with the code that sets
1104 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1108 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1109 &next_config_rom_bus
, GFP_KERNEL
);
1110 if (next_config_rom
== NULL
)
1113 spin_lock_irqsave(&ohci
->lock
, flags
);
1115 if (ohci
->next_config_rom
== NULL
) {
1116 ohci
->next_config_rom
= next_config_rom
;
1117 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1119 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1120 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
,
1123 ohci
->next_header
= config_rom
[0];
1124 ohci
->next_config_rom
[0] = 0;
1126 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1127 ohci
->next_config_rom_bus
);
1129 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1130 next_config_rom
, next_config_rom_bus
);
1134 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1136 /* Now initiate a bus reset to have the changes take
1137 * effect. We clean up the old config rom memory and DMA
1138 * mappings in the bus reset tasklet, since the OHCI
1139 * controller could need to access it before the bus reset
1142 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1147 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1149 struct fw_ohci
*ohci
= fw_ohci(card
);
1151 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1154 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1156 struct fw_ohci
*ohci
= fw_ohci(card
);
1158 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1161 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1163 struct fw_ohci
*ohci
= fw_ohci(card
);
1164 struct context
*ctx
= &ohci
->at_request_ctx
;
1165 struct driver_data
*driver_data
= packet
->driver_data
;
1166 int retval
= -ENOENT
;
1168 tasklet_disable(&ctx
->tasklet
);
1170 if (packet
->ack
!= 0)
1173 driver_data
->packet
= NULL
;
1174 packet
->ack
= RCODE_CANCELLED
;
1175 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1179 tasklet_enable(&ctx
->tasklet
);
1185 ohci_enable_phys_dma(struct fw_card
*card
, int node_id
, int generation
)
1187 struct fw_ohci
*ohci
= fw_ohci(card
);
1188 unsigned long flags
;
1191 /* FIXME: Make sure this bitmask is cleared when we clear the busReset
1192 * interrupt bit. Clear physReqResourceAllBuses on bus reset. */
1194 spin_lock_irqsave(&ohci
->lock
, flags
);
1196 if (ohci
->generation
!= generation
) {
1201 /* NOTE, if the node ID contains a non-local bus ID, physical DMA is
1202 * enabled for _all_ nodes on remote buses. */
1204 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
1206 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
1208 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
1212 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1216 static int handle_ir_bufferfill_packet(struct context
*context
,
1217 struct descriptor
*d
,
1218 struct descriptor
*last
)
1220 struct iso_context
*ctx
=
1221 container_of(context
, struct iso_context
, context
);
1223 if (d
->res_count
> 0)
1226 if (le16_to_cpu(last
->control
) & descriptor_irq_always
)
1227 ctx
->base
.callback(&ctx
->base
,
1228 le16_to_cpu(last
->res_count
),
1229 0, NULL
, ctx
->base
.callback_data
);
1234 static int handle_ir_dualbuffer_packet(struct context
*context
,
1235 struct descriptor
*d
,
1236 struct descriptor
*last
)
1238 struct iso_context
*ctx
=
1239 container_of(context
, struct iso_context
, context
);
1240 struct db_descriptor
*db
= (struct db_descriptor
*) d
;
1241 size_t header_length
;
1243 if (db
->first_res_count
> 0 && db
->second_res_count
> 0)
1244 /* This descriptor isn't done yet, stop iteration. */
1247 header_length
= db
->first_req_count
- db
->first_res_count
;
1248 if (ctx
->header_length
+ header_length
<= PAGE_SIZE
)
1249 memcpy(ctx
->header
+ ctx
->header_length
, db
+ 1, header_length
);
1250 ctx
->header_length
+= header_length
;
1252 if (le16_to_cpu(db
->control
) & descriptor_irq_always
) {
1253 ctx
->base
.callback(&ctx
->base
, 0,
1254 ctx
->header_length
, ctx
->header
,
1255 ctx
->base
.callback_data
);
1256 ctx
->header_length
= 0;
1262 static int handle_it_packet(struct context
*context
,
1263 struct descriptor
*d
,
1264 struct descriptor
*last
)
1266 struct iso_context
*ctx
=
1267 container_of(context
, struct iso_context
, context
);
1269 if (last
->transfer_status
== 0)
1270 /* This descriptor isn't done yet, stop iteration. */
1273 if (le16_to_cpu(last
->control
) & descriptor_irq_always
)
1274 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
1275 0, NULL
, ctx
->base
.callback_data
);
1280 static struct fw_iso_context
*
1281 ohci_allocate_iso_context(struct fw_card
*card
, int type
,
1282 int sync
, int tags
, size_t header_size
)
1284 struct fw_ohci
*ohci
= fw_ohci(card
);
1285 struct iso_context
*ctx
, *list
;
1286 descriptor_callback_t callback
;
1288 unsigned long flags
;
1289 int index
, retval
= -ENOMEM
;
1291 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
1292 mask
= &ohci
->it_context_mask
;
1293 list
= ohci
->it_context_list
;
1294 callback
= handle_it_packet
;
1296 mask
= &ohci
->ir_context_mask
;
1297 list
= ohci
->ir_context_list
;
1298 if (header_size
> 0)
1299 callback
= handle_ir_dualbuffer_packet
;
1301 callback
= handle_ir_bufferfill_packet
;
1304 if (callback
== handle_ir_dualbuffer_packet
&&
1305 ohci
->version
< OHCI_VERSION_1_1
)
1306 return ERR_PTR(-EINVAL
);
1308 spin_lock_irqsave(&ohci
->lock
, flags
);
1309 index
= ffs(*mask
) - 1;
1311 *mask
&= ~(1 << index
);
1312 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1315 return ERR_PTR(-EBUSY
);
1317 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
1318 regs
= OHCI1394_IsoXmitContextBase(index
);
1320 regs
= OHCI1394_IsoRcvContextBase(index
);
1323 memset(ctx
, 0, sizeof *ctx
);
1324 ctx
->header_length
= 0;
1325 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
1326 if (ctx
->header
== NULL
)
1329 retval
= context_init(&ctx
->context
, ohci
, ISO_BUFFER_SIZE
,
1332 goto out_with_header
;
1337 free_page((unsigned long)ctx
->header
);
1339 spin_lock_irqsave(&ohci
->lock
, flags
);
1340 *mask
|= 1 << index
;
1341 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1343 return ERR_PTR(retval
);
1346 static int ohci_start_iso(struct fw_iso_context
*base
, s32 cycle
)
1348 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1349 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
1350 u32 cycle_match
= 0, mode
;
1353 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1354 index
= ctx
- ohci
->it_context_list
;
1356 cycle_match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
1357 (cycle
& 0x7fff) << 16;
1359 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
1360 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
1361 context_run(&ctx
->context
, cycle_match
);
1363 index
= ctx
- ohci
->ir_context_list
;
1365 if (ctx
->base
.header_size
> 0)
1366 mode
= IR_CONTEXT_DUAL_BUFFER_MODE
;
1368 mode
= IR_CONTEXT_BUFFER_FILL
;
1369 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
1370 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
1371 reg_write(ohci
, context_match(ctx
->context
.regs
),
1372 (ctx
->base
.tags
<< 28) |
1373 (ctx
->base
.sync
<< 8) | ctx
->base
.channel
);
1374 context_run(&ctx
->context
, mode
);
1380 static int ohci_stop_iso(struct fw_iso_context
*base
)
1382 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1383 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1386 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1387 index
= ctx
- ohci
->it_context_list
;
1388 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
1390 index
= ctx
- ohci
->ir_context_list
;
1391 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
1394 context_stop(&ctx
->context
);
1399 static void ohci_free_iso_context(struct fw_iso_context
*base
)
1401 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1402 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1403 unsigned long flags
;
1406 ohci_stop_iso(base
);
1407 context_release(&ctx
->context
);
1408 free_page((unsigned long)ctx
->header
);
1410 spin_lock_irqsave(&ohci
->lock
, flags
);
1412 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1413 index
= ctx
- ohci
->it_context_list
;
1414 ohci
->it_context_mask
|= 1 << index
;
1416 index
= ctx
- ohci
->ir_context_list
;
1417 ohci
->ir_context_mask
|= 1 << index
;
1420 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1424 ohci_queue_iso_transmit(struct fw_iso_context
*base
,
1425 struct fw_iso_packet
*packet
,
1426 struct fw_iso_buffer
*buffer
,
1427 unsigned long payload
)
1429 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1430 struct descriptor
*d
, *last
, *pd
;
1431 struct fw_iso_packet
*p
;
1433 dma_addr_t d_bus
, page_bus
;
1434 u32 z
, header_z
, payload_z
, irq
;
1435 u32 payload_index
, payload_end_index
, next_page_index
;
1436 int page
, end_page
, i
, length
, offset
;
1438 /* FIXME: Cycle lost behavior should be configurable: lose
1439 * packet, retransmit or terminate.. */
1442 payload_index
= payload
;
1448 if (p
->header_length
> 0)
1451 /* Determine the first page the payload isn't contained in. */
1452 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
1453 if (p
->payload_length
> 0)
1454 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
1460 /* Get header size in number of descriptors. */
1461 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof *d
);
1463 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
1468 d
[0].control
= cpu_to_le16(descriptor_key_immediate
);
1469 d
[0].req_count
= cpu_to_le16(8);
1471 header
= (__le32
*) &d
[1];
1472 header
[0] = cpu_to_le32(it_header_sy(p
->sy
) |
1473 it_header_tag(p
->tag
) |
1474 it_header_tcode(TCODE_STREAM_DATA
) |
1475 it_header_channel(ctx
->base
.channel
) |
1476 it_header_speed(ctx
->base
.speed
));
1478 cpu_to_le32(it_header_data_length(p
->header_length
+
1479 p
->payload_length
));
1482 if (p
->header_length
> 0) {
1483 d
[2].req_count
= cpu_to_le16(p
->header_length
);
1484 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof *d
);
1485 memcpy(&d
[z
], p
->header
, p
->header_length
);
1488 pd
= d
+ z
- payload_z
;
1489 payload_end_index
= payload_index
+ p
->payload_length
;
1490 for (i
= 0; i
< payload_z
; i
++) {
1491 page
= payload_index
>> PAGE_SHIFT
;
1492 offset
= payload_index
& ~PAGE_MASK
;
1493 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
1495 min(next_page_index
, payload_end_index
) - payload_index
;
1496 pd
[i
].req_count
= cpu_to_le16(length
);
1498 page_bus
= page_private(buffer
->pages
[page
]);
1499 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
1501 payload_index
+= length
;
1505 irq
= descriptor_irq_always
;
1507 irq
= descriptor_no_irq
;
1509 last
= z
== 2 ? d
: d
+ z
- 1;
1510 last
->control
|= cpu_to_le16(descriptor_output_last
|
1512 descriptor_branch_always
|
1515 context_append(&ctx
->context
, d
, z
, header_z
);
1521 setup_wait_descriptor(struct context
*ctx
)
1523 struct descriptor
*d
;
1526 d
= context_get_descriptors(ctx
, 1, &d_bus
);
1530 d
->control
= cpu_to_le16(descriptor_input_more
|
1532 descriptor_branch_always
|
1535 context_append(ctx
, d
, 1, 0);
1541 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context
*base
,
1542 struct fw_iso_packet
*packet
,
1543 struct fw_iso_buffer
*buffer
,
1544 unsigned long payload
)
1546 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1547 struct db_descriptor
*db
= NULL
;
1548 struct descriptor
*d
;
1549 struct fw_iso_packet
*p
;
1550 dma_addr_t d_bus
, page_bus
;
1551 u32 z
, header_z
, length
, rest
;
1554 /* FIXME: Cycle lost behavior should be configurable: lose
1555 * packet, retransmit or terminate.. */
1557 if (packet
->skip
&& setup_wait_descriptor(&ctx
->context
) < 0)
1563 /* Get header size in number of descriptors. */
1564 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof *d
);
1565 page
= payload
>> PAGE_SHIFT
;
1566 offset
= payload
& ~PAGE_MASK
;
1567 rest
= p
->payload_length
;
1569 /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1570 /* FIXME: handle descriptor_wait */
1571 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1573 d
= context_get_descriptors(&ctx
->context
,
1574 z
+ header_z
, &d_bus
);
1578 db
= (struct db_descriptor
*) d
;
1579 db
->control
= cpu_to_le16(descriptor_status
|
1580 descriptor_branch_always
);
1581 db
->first_size
= cpu_to_le16(ctx
->base
.header_size
);
1582 db
->first_req_count
= cpu_to_le16(p
->header_length
);
1583 db
->first_res_count
= db
->first_req_count
;
1584 db
->first_buffer
= cpu_to_le32(d_bus
+ sizeof *db
);
1586 if (offset
+ rest
< PAGE_SIZE
)
1589 length
= PAGE_SIZE
- offset
;
1591 db
->second_req_count
= cpu_to_le16(length
);
1592 db
->second_res_count
= db
->second_req_count
;
1593 page_bus
= page_private(buffer
->pages
[page
]);
1594 db
->second_buffer
= cpu_to_le32(page_bus
+ offset
);
1596 if (p
->interrupt
&& length
== rest
)
1597 db
->control
|= cpu_to_le16(descriptor_irq_always
);
1599 context_append(&ctx
->context
, d
, z
, header_z
);
1600 offset
= (offset
+ length
) & ~PAGE_MASK
;
1609 ohci_queue_iso_receive_bufferfill(struct fw_iso_context
*base
,
1610 struct fw_iso_packet
*packet
,
1611 struct fw_iso_buffer
*buffer
,
1612 unsigned long payload
)
1614 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1615 struct descriptor
*d
= NULL
;
1616 dma_addr_t d_bus
, page_bus
;
1620 page
= payload
>> PAGE_SHIFT
;
1621 offset
= payload
& ~PAGE_MASK
;
1622 rest
= packet
->payload_length
;
1624 if (packet
->skip
&& setup_wait_descriptor(&ctx
->context
) < 0)
1628 d
= context_get_descriptors(&ctx
->context
, 1, &d_bus
);
1632 d
->control
= cpu_to_le16(descriptor_input_more
|
1634 descriptor_branch_always
);
1636 if (offset
+ rest
< PAGE_SIZE
)
1639 length
= PAGE_SIZE
- offset
;
1641 page_bus
= page_private(buffer
->pages
[page
]);
1642 d
->data_address
= cpu_to_le32(page_bus
+ offset
);
1643 d
->req_count
= cpu_to_le16(length
);
1644 d
->res_count
= cpu_to_le16(length
);
1646 if (packet
->interrupt
&& length
== rest
)
1647 d
->control
|= cpu_to_le16(descriptor_irq_always
);
1649 context_append(&ctx
->context
, d
, 1, 0);
1651 offset
= (offset
+ length
) & ~PAGE_MASK
;
1660 ohci_queue_iso(struct fw_iso_context
*base
,
1661 struct fw_iso_packet
*packet
,
1662 struct fw_iso_buffer
*buffer
,
1663 unsigned long payload
)
1665 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1667 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
1668 return ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
1669 else if (base
->header_size
== 0)
1670 return ohci_queue_iso_receive_bufferfill(base
, packet
,
1672 else if (ctx
->context
.ohci
->version
>= OHCI_VERSION_1_1
)
1673 return ohci_queue_iso_receive_dualbuffer(base
, packet
,
1676 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1680 static const struct fw_card_driver ohci_driver
= {
1681 .name
= ohci_driver_name
,
1682 .enable
= ohci_enable
,
1683 .update_phy_reg
= ohci_update_phy_reg
,
1684 .set_config_rom
= ohci_set_config_rom
,
1685 .send_request
= ohci_send_request
,
1686 .send_response
= ohci_send_response
,
1687 .cancel_packet
= ohci_cancel_packet
,
1688 .enable_phys_dma
= ohci_enable_phys_dma
,
1690 .allocate_iso_context
= ohci_allocate_iso_context
,
1691 .free_iso_context
= ohci_free_iso_context
,
1692 .queue_iso
= ohci_queue_iso
,
1693 .start_iso
= ohci_start_iso
,
1694 .stop_iso
= ohci_stop_iso
,
1697 static int software_reset(struct fw_ohci
*ohci
)
1701 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1703 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1704 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1705 OHCI1394_HCControl_softReset
) == 0)
1713 /* ---------- pci subsystem interface ---------- */
1723 static int cleanup(struct fw_ohci
*ohci
, int stage
, int code
)
1725 struct pci_dev
*dev
= to_pci_dev(ohci
->card
.device
);
1728 case CLEANUP_SELF_ID
:
1729 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
1730 ohci
->self_id_cpu
, ohci
->self_id_bus
);
1731 case CLEANUP_REGISTERS
:
1732 kfree(ohci
->it_context_list
);
1733 kfree(ohci
->ir_context_list
);
1734 pci_iounmap(dev
, ohci
->registers
);
1736 pci_release_region(dev
, 0);
1737 case CLEANUP_DISABLE
:
1738 pci_disable_device(dev
);
1739 case CLEANUP_PUT_CARD
:
1740 fw_card_put(&ohci
->card
);
1746 static int __devinit
1747 pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
1749 struct fw_ohci
*ohci
;
1750 u32 bus_options
, max_receive
, link_speed
;
1755 ohci
= kzalloc(sizeof *ohci
, GFP_KERNEL
);
1757 fw_error("Could not malloc fw_ohci data.\n");
1761 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
1763 if (pci_enable_device(dev
)) {
1764 fw_error("Failed to enable OHCI hardware.\n");
1765 return cleanup(ohci
, CLEANUP_PUT_CARD
, -ENODEV
);
1768 pci_set_master(dev
);
1769 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
1770 pci_set_drvdata(dev
, ohci
);
1772 spin_lock_init(&ohci
->lock
);
1774 tasklet_init(&ohci
->bus_reset_tasklet
,
1775 bus_reset_tasklet
, (unsigned long)ohci
);
1777 if (pci_request_region(dev
, 0, ohci_driver_name
)) {
1778 fw_error("MMIO resource unavailable\n");
1779 return cleanup(ohci
, CLEANUP_DISABLE
, -EBUSY
);
1782 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
1783 if (ohci
->registers
== NULL
) {
1784 fw_error("Failed to remap registers\n");
1785 return cleanup(ohci
, CLEANUP_IOMEM
, -ENXIO
);
1788 if (software_reset(ohci
)) {
1789 fw_error("Failed to reset ohci card.\n");
1790 return cleanup(ohci
, CLEANUP_REGISTERS
, -EBUSY
);
1793 /* Now enable LPS, which we need in order to start accessing
1794 * most of the registers. In fact, on some cards (ALI M5251),
1795 * accessing registers in the SClk domain without LPS enabled
1796 * will lock up the machine. Wait 50msec to make sure we have
1797 * full link enabled. */
1798 reg_write(ohci
, OHCI1394_HCControlSet
,
1799 OHCI1394_HCControl_LPS
|
1800 OHCI1394_HCControl_postedWriteEnable
);
1804 reg_write(ohci
, OHCI1394_HCControlClear
,
1805 OHCI1394_HCControl_noByteSwapData
);
1807 reg_write(ohci
, OHCI1394_LinkControlSet
,
1808 OHCI1394_LinkControl_rcvSelfID
|
1809 OHCI1394_LinkControl_cycleTimerEnable
|
1810 OHCI1394_LinkControl_cycleMaster
);
1812 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
1813 OHCI1394_AsReqRcvContextControlSet
);
1815 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
1816 OHCI1394_AsRspRcvContextControlSet
);
1818 context_init(&ohci
->at_request_ctx
, ohci
, AT_BUFFER_SIZE
,
1819 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
1821 context_init(&ohci
->at_response_ctx
, ohci
, AT_BUFFER_SIZE
,
1822 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
1824 reg_write(ohci
, OHCI1394_ATRetries
,
1825 OHCI1394_MAX_AT_REQ_RETRIES
|
1826 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1827 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1829 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
1830 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
1831 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
1832 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
1833 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
1835 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
1836 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
1837 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
1838 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
1839 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
1841 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
1842 fw_error("Out of memory for it/ir contexts.\n");
1843 return cleanup(ohci
, CLEANUP_REGISTERS
, -ENOMEM
);
1846 /* self-id dma buffer allocation */
1847 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
1851 if (ohci
->self_id_cpu
== NULL
) {
1852 fw_error("Out of memory for self ID buffer.\n");
1853 return cleanup(ohci
, CLEANUP_REGISTERS
, -ENOMEM
);
1856 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1857 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1858 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1859 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1860 reg_write(ohci
, OHCI1394_IntMaskSet
,
1861 OHCI1394_selfIDComplete
|
1862 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1863 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1864 OHCI1394_isochRx
| OHCI1394_isochTx
|
1865 OHCI1394_masterIntEnable
);
1867 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
1868 max_receive
= (bus_options
>> 12) & 0xf;
1869 link_speed
= bus_options
& 0x7;
1870 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
1871 reg_read(ohci
, OHCI1394_GUIDLo
);
1873 error_code
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
1875 return cleanup(ohci
, CLEANUP_SELF_ID
, error_code
);
1877 ohci
->version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
1878 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1879 dev
->dev
.bus_id
, ohci
->version
>> 16, ohci
->version
& 0xff);
1884 static void pci_remove(struct pci_dev
*dev
)
1886 struct fw_ohci
*ohci
;
1888 ohci
= pci_get_drvdata(dev
);
1889 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1891 fw_core_remove_card(&ohci
->card
);
1893 /* FIXME: Fail all pending packets here, now that the upper
1894 * layers can't queue any more. */
1896 software_reset(ohci
);
1897 free_irq(dev
->irq
, ohci
);
1898 cleanup(ohci
, CLEANUP_SELF_ID
, 0);
1900 fw_notify("Removed fw-ohci device.\n");
1903 static struct pci_device_id pci_table
[] = {
1904 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
1908 MODULE_DEVICE_TABLE(pci
, pci_table
);
1910 static struct pci_driver fw_ohci_pci_driver
= {
1911 .name
= ohci_driver_name
,
1912 .id_table
= pci_table
,
1914 .remove
= pci_remove
,
1917 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1918 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1919 MODULE_LICENSE("GPL");
1921 static int __init
fw_ohci_init(void)
1923 return pci_register_driver(&fw_ohci_pci_driver
);
1926 static void __exit
fw_ohci_cleanup(void)
1928 pci_unregister_driver(&fw_ohci_pci_driver
);
1931 module_init(fw_ohci_init
);
1932 module_exit(fw_ohci_cleanup
);