2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/poll.h>
28 #include <linux/dma-mapping.h>
30 #include <asm/uaccess.h>
31 #include <asm/semaphore.h>
33 #include "fw-transaction.h"
36 #define DESCRIPTOR_OUTPUT_MORE 0
37 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
38 #define DESCRIPTOR_INPUT_MORE (2 << 12)
39 #define DESCRIPTOR_INPUT_LAST (3 << 12)
40 #define DESCRIPTOR_STATUS (1 << 11)
41 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
42 #define DESCRIPTOR_PING (1 << 7)
43 #define DESCRIPTOR_YY (1 << 6)
44 #define DESCRIPTOR_NO_IRQ (0 << 4)
45 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
46 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
47 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
48 #define DESCRIPTOR_WAIT (3 << 0)
54 __le32 branch_address
;
56 __le16 transfer_status
;
57 } __attribute__((aligned(16)));
59 struct db_descriptor
{
62 __le16 second_req_count
;
63 __le16 first_req_count
;
64 __le32 branch_address
;
65 __le16 second_res_count
;
66 __le16 first_res_count
;
71 } __attribute__((aligned(16)));
73 #define CONTROL_SET(regs) (regs)
74 #define CONTROL_CLEAR(regs) ((regs) + 4)
75 #define COMMAND_PTR(regs) ((regs) + 12)
76 #define CONTEXT_MATCH(regs) ((regs) + 16)
79 struct descriptor descriptor
;
80 struct ar_buffer
*next
;
86 struct ar_buffer
*current_buffer
;
87 struct ar_buffer
*last_buffer
;
90 struct tasklet_struct tasklet
;
95 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
97 struct descriptor
*last
);
102 struct descriptor
*buffer
;
103 dma_addr_t buffer_bus
;
105 struct descriptor
*head_descriptor
;
106 struct descriptor
*tail_descriptor
;
107 struct descriptor
*tail_descriptor_last
;
108 struct descriptor
*prev_descriptor
;
110 descriptor_callback_t callback
;
112 struct tasklet_struct tasklet
;
115 #define IT_HEADER_SY(v) ((v) << 0)
116 #define IT_HEADER_TCODE(v) ((v) << 4)
117 #define IT_HEADER_CHANNEL(v) ((v) << 8)
118 #define IT_HEADER_TAG(v) ((v) << 14)
119 #define IT_HEADER_SPEED(v) ((v) << 16)
120 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
123 struct fw_iso_context base
;
124 struct context context
;
126 size_t header_length
;
129 #define CONFIG_ROM_SIZE 1024
135 __iomem
char *registers
;
136 dma_addr_t self_id_bus
;
138 struct tasklet_struct bus_reset_tasklet
;
141 int request_generation
;
145 * Spinlock for accessing fw_ohci data. Never call out of
146 * this driver with this lock held.
149 u32 self_id_buffer
[512];
151 /* Config rom buffers */
153 dma_addr_t config_rom_bus
;
154 __be32
*next_config_rom
;
155 dma_addr_t next_config_rom_bus
;
158 struct ar_context ar_request_ctx
;
159 struct ar_context ar_response_ctx
;
160 struct context at_request_ctx
;
161 struct context at_response_ctx
;
164 struct iso_context
*it_context_list
;
166 struct iso_context
*ir_context_list
;
169 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
171 return container_of(card
, struct fw_ohci
, card
);
174 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
175 #define IR_CONTEXT_BUFFER_FILL 0x80000000
176 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
177 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
178 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
179 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
181 #define CONTEXT_RUN 0x8000
182 #define CONTEXT_WAKE 0x1000
183 #define CONTEXT_DEAD 0x0800
184 #define CONTEXT_ACTIVE 0x0400
186 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
187 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
188 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
190 #define FW_OHCI_MAJOR 240
191 #define OHCI1394_REGISTER_SIZE 0x800
192 #define OHCI_LOOP_COUNT 500
193 #define OHCI1394_PCI_HCI_Control 0x40
194 #define SELF_ID_BUF_SIZE 0x800
195 #define OHCI_TCODE_PHY_PACKET 0x0e
196 #define OHCI_VERSION_1_1 0x010010
197 #define ISO_BUFFER_SIZE (64 * 1024)
198 #define AT_BUFFER_SIZE 4096
200 static char ohci_driver_name
[] = KBUILD_MODNAME
;
202 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
204 writel(data
, ohci
->registers
+ offset
);
207 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
209 return readl(ohci
->registers
+ offset
);
212 static inline void flush_writes(const struct fw_ohci
*ohci
)
214 /* Do a dummy read to flush writes. */
215 reg_read(ohci
, OHCI1394_Version
);
219 ohci_update_phy_reg(struct fw_card
*card
, int addr
,
220 int clear_bits
, int set_bits
)
222 struct fw_ohci
*ohci
= fw_ohci(card
);
225 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
227 val
= reg_read(ohci
, OHCI1394_PhyControl
);
228 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
229 fw_error("failed to set phy reg bits.\n");
233 old
= OHCI1394_PhyControl_ReadData(val
);
234 old
= (old
& ~clear_bits
) | set_bits
;
235 reg_write(ohci
, OHCI1394_PhyControl
,
236 OHCI1394_PhyControl_Write(addr
, old
));
241 static int ar_context_add_page(struct ar_context
*ctx
)
243 struct device
*dev
= ctx
->ohci
->card
.device
;
244 struct ar_buffer
*ab
;
248 ab
= (struct ar_buffer
*) __get_free_page(GFP_ATOMIC
);
252 ab_bus
= dma_map_single(dev
, ab
, PAGE_SIZE
, DMA_BIDIRECTIONAL
);
253 if (dma_mapping_error(ab_bus
)) {
254 free_page((unsigned long) ab
);
258 memset(&ab
->descriptor
, 0, sizeof ab
->descriptor
);
259 ab
->descriptor
.control
= cpu_to_le16(DESCRIPTOR_INPUT_MORE
|
261 DESCRIPTOR_BRANCH_ALWAYS
);
262 offset
= offsetof(struct ar_buffer
, data
);
263 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
264 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
265 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
266 ab
->descriptor
.branch_address
= 0;
268 dma_sync_single_for_device(dev
, ab_bus
, PAGE_SIZE
, DMA_BIDIRECTIONAL
);
270 ctx
->last_buffer
->descriptor
.branch_address
= ab_bus
| 1;
271 ctx
->last_buffer
->next
= ab
;
272 ctx
->last_buffer
= ab
;
274 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
275 flush_writes(ctx
->ohci
);
280 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
282 struct fw_ohci
*ohci
= ctx
->ohci
;
284 u32 status
, length
, tcode
;
286 p
.header
[0] = le32_to_cpu(buffer
[0]);
287 p
.header
[1] = le32_to_cpu(buffer
[1]);
288 p
.header
[2] = le32_to_cpu(buffer
[2]);
290 tcode
= (p
.header
[0] >> 4) & 0x0f;
292 case TCODE_WRITE_QUADLET_REQUEST
:
293 case TCODE_READ_QUADLET_RESPONSE
:
294 p
.header
[3] = (__force __u32
) buffer
[3];
295 p
.header_length
= 16;
296 p
.payload_length
= 0;
299 case TCODE_READ_BLOCK_REQUEST
:
300 p
.header
[3] = le32_to_cpu(buffer
[3]);
301 p
.header_length
= 16;
302 p
.payload_length
= 0;
305 case TCODE_WRITE_BLOCK_REQUEST
:
306 case TCODE_READ_BLOCK_RESPONSE
:
307 case TCODE_LOCK_REQUEST
:
308 case TCODE_LOCK_RESPONSE
:
309 p
.header
[3] = le32_to_cpu(buffer
[3]);
310 p
.header_length
= 16;
311 p
.payload_length
= p
.header
[3] >> 16;
314 case TCODE_WRITE_RESPONSE
:
315 case TCODE_READ_QUADLET_REQUEST
:
316 case OHCI_TCODE_PHY_PACKET
:
317 p
.header_length
= 12;
318 p
.payload_length
= 0;
322 p
.payload
= (void *) buffer
+ p
.header_length
;
324 /* FIXME: What to do about evt_* errors? */
325 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
326 status
= le32_to_cpu(buffer
[length
]);
328 p
.ack
= ((status
>> 16) & 0x1f) - 16;
329 p
.speed
= (status
>> 21) & 0x7;
330 p
.timestamp
= status
& 0xffff;
331 p
.generation
= ohci
->request_generation
;
334 * The OHCI bus reset handler synthesizes a phy packet with
335 * the new generation number when a bus reset happens (see
336 * section 8.4.2.3). This helps us determine when a request
337 * was received and make sure we send the response in the same
338 * generation. We only need this for requests; for responses
339 * we use the unique tlabel for finding the matching
343 if (p
.ack
+ 16 == 0x09)
344 ohci
->request_generation
= (buffer
[2] >> 16) & 0xff;
345 else if (ctx
== &ohci
->ar_request_ctx
)
346 fw_core_handle_request(&ohci
->card
, &p
);
348 fw_core_handle_response(&ohci
->card
, &p
);
350 return buffer
+ length
+ 1;
353 static void ar_context_tasklet(unsigned long data
)
355 struct ar_context
*ctx
= (struct ar_context
*)data
;
356 struct fw_ohci
*ohci
= ctx
->ohci
;
357 struct ar_buffer
*ab
;
358 struct descriptor
*d
;
361 ab
= ctx
->current_buffer
;
364 if (d
->res_count
== 0) {
365 size_t size
, rest
, offset
;
368 * This descriptor is finished and we may have a
369 * packet split across this and the next buffer. We
370 * reuse the page for reassembling the split packet.
373 offset
= offsetof(struct ar_buffer
, data
);
374 dma_unmap_single(ohci
->card
.device
,
375 ab
->descriptor
.data_address
- offset
,
376 PAGE_SIZE
, DMA_BIDIRECTIONAL
);
381 size
= buffer
+ PAGE_SIZE
- ctx
->pointer
;
382 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
383 memmove(buffer
, ctx
->pointer
, size
);
384 memcpy(buffer
+ size
, ab
->data
, rest
);
385 ctx
->current_buffer
= ab
;
386 ctx
->pointer
= (void *) ab
->data
+ rest
;
387 end
= buffer
+ size
+ rest
;
390 buffer
= handle_ar_packet(ctx
, buffer
);
392 free_page((unsigned long)buffer
);
393 ar_context_add_page(ctx
);
395 buffer
= ctx
->pointer
;
397 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
400 buffer
= handle_ar_packet(ctx
, buffer
);
405 ar_context_init(struct ar_context
*ctx
, struct fw_ohci
*ohci
, u32 regs
)
411 ctx
->last_buffer
= &ab
;
412 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
414 ar_context_add_page(ctx
);
415 ar_context_add_page(ctx
);
416 ctx
->current_buffer
= ab
.next
;
417 ctx
->pointer
= ctx
->current_buffer
->data
;
419 reg_write(ctx
->ohci
, COMMAND_PTR(ctx
->regs
), ab
.descriptor
.branch_address
);
420 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
);
421 flush_writes(ctx
->ohci
);
426 static void context_tasklet(unsigned long data
)
428 struct context
*ctx
= (struct context
*) data
;
429 struct fw_ohci
*ohci
= ctx
->ohci
;
430 struct descriptor
*d
, *last
;
434 dma_sync_single_for_cpu(ohci
->card
.device
, ctx
->buffer_bus
,
435 ctx
->buffer_size
, DMA_TO_DEVICE
);
437 d
= ctx
->tail_descriptor
;
438 last
= ctx
->tail_descriptor_last
;
440 while (last
->branch_address
!= 0) {
441 address
= le32_to_cpu(last
->branch_address
);
443 d
= ctx
->buffer
+ (address
- ctx
->buffer_bus
) / sizeof *d
;
444 last
= (z
== 2) ? d
: d
+ z
- 1;
446 if (!ctx
->callback(ctx
, d
, last
))
449 ctx
->tail_descriptor
= d
;
450 ctx
->tail_descriptor_last
= last
;
455 context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
456 size_t buffer_size
, u32 regs
,
457 descriptor_callback_t callback
)
461 ctx
->buffer_size
= buffer_size
;
462 ctx
->buffer
= kmalloc(buffer_size
, GFP_KERNEL
);
463 if (ctx
->buffer
== NULL
)
466 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
467 ctx
->callback
= callback
;
470 dma_map_single(ohci
->card
.device
, ctx
->buffer
,
471 buffer_size
, DMA_TO_DEVICE
);
472 if (dma_mapping_error(ctx
->buffer_bus
)) {
477 ctx
->head_descriptor
= ctx
->buffer
;
478 ctx
->prev_descriptor
= ctx
->buffer
;
479 ctx
->tail_descriptor
= ctx
->buffer
;
480 ctx
->tail_descriptor_last
= ctx
->buffer
;
483 * We put a dummy descriptor in the buffer that has a NULL
484 * branch address and looks like it's been sent. That way we
485 * have a descriptor to append DMA programs to. Also, the
486 * ring buffer invariant is that it always has at least one
487 * element so that head == tail means buffer full.
490 memset(ctx
->head_descriptor
, 0, sizeof *ctx
->head_descriptor
);
491 ctx
->head_descriptor
->control
= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
);
492 ctx
->head_descriptor
->transfer_status
= cpu_to_le16(0x8011);
493 ctx
->head_descriptor
++;
499 context_release(struct context
*ctx
)
501 struct fw_card
*card
= &ctx
->ohci
->card
;
503 dma_unmap_single(card
->device
, ctx
->buffer_bus
,
504 ctx
->buffer_size
, DMA_TO_DEVICE
);
508 static struct descriptor
*
509 context_get_descriptors(struct context
*ctx
, int z
, dma_addr_t
*d_bus
)
511 struct descriptor
*d
, *tail
, *end
;
513 d
= ctx
->head_descriptor
;
514 tail
= ctx
->tail_descriptor
;
515 end
= ctx
->buffer
+ ctx
->buffer_size
/ sizeof(struct descriptor
);
519 } else if (d
> tail
&& d
+ z
<= end
) {
521 } else if (d
> tail
&& ctx
->buffer
+ z
<= tail
) {
529 memset(d
, 0, z
* sizeof *d
);
530 *d_bus
= ctx
->buffer_bus
+ (d
- ctx
->buffer
) * sizeof *d
;
535 static void context_run(struct context
*ctx
, u32 extra
)
537 struct fw_ohci
*ohci
= ctx
->ohci
;
539 reg_write(ohci
, COMMAND_PTR(ctx
->regs
),
540 le32_to_cpu(ctx
->tail_descriptor_last
->branch_address
));
541 reg_write(ohci
, CONTROL_CLEAR(ctx
->regs
), ~0);
542 reg_write(ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
| extra
);
546 static void context_append(struct context
*ctx
,
547 struct descriptor
*d
, int z
, int extra
)
551 d_bus
= ctx
->buffer_bus
+ (d
- ctx
->buffer
) * sizeof *d
;
553 ctx
->head_descriptor
= d
+ z
+ extra
;
554 ctx
->prev_descriptor
->branch_address
= cpu_to_le32(d_bus
| z
);
555 ctx
->prev_descriptor
= z
== 2 ? d
: d
+ z
- 1;
557 dma_sync_single_for_device(ctx
->ohci
->card
.device
, ctx
->buffer_bus
,
558 ctx
->buffer_size
, DMA_TO_DEVICE
);
560 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
561 flush_writes(ctx
->ohci
);
564 static void context_stop(struct context
*ctx
)
569 reg_write(ctx
->ohci
, CONTROL_CLEAR(ctx
->regs
), CONTEXT_RUN
);
570 flush_writes(ctx
->ohci
);
572 for (i
= 0; i
< 10; i
++) {
573 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
574 if ((reg
& CONTEXT_ACTIVE
) == 0)
577 fw_notify("context_stop: still active (0x%08x)\n", reg
);
583 struct fw_packet
*packet
;
587 * This function apppends a packet to the DMA queue for transmission.
588 * Must always be called with the ochi->lock held to ensure proper
589 * generation handling and locking around packet queue manipulation.
592 at_context_queue_packet(struct context
*ctx
, struct fw_packet
*packet
)
594 struct fw_ohci
*ohci
= ctx
->ohci
;
595 dma_addr_t d_bus
, payload_bus
;
596 struct driver_data
*driver_data
;
597 struct descriptor
*d
, *last
;
602 d
= context_get_descriptors(ctx
, 4, &d_bus
);
604 packet
->ack
= RCODE_SEND_ERROR
;
608 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
609 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
612 * The DMA format for asyncronous link packets is different
613 * from the IEEE1394 layout, so shift the fields around
614 * accordingly. If header_length is 8, it's a PHY packet, to
615 * which we need to prepend an extra quadlet.
618 header
= (__le32
*) &d
[1];
619 if (packet
->header_length
> 8) {
620 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
621 (packet
->speed
<< 16));
622 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
623 (packet
->header
[0] & 0xffff0000));
624 header
[2] = cpu_to_le32(packet
->header
[2]);
626 tcode
= (packet
->header
[0] >> 4) & 0x0f;
627 if (TCODE_IS_BLOCK_PACKET(tcode
))
628 header
[3] = cpu_to_le32(packet
->header
[3]);
630 header
[3] = (__force __le32
) packet
->header
[3];
632 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
634 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
635 (packet
->speed
<< 16));
636 header
[1] = cpu_to_le32(packet
->header
[0]);
637 header
[2] = cpu_to_le32(packet
->header
[1]);
638 d
[0].req_count
= cpu_to_le16(12);
641 driver_data
= (struct driver_data
*) &d
[3];
642 driver_data
->packet
= packet
;
643 packet
->driver_data
= driver_data
;
645 if (packet
->payload_length
> 0) {
647 dma_map_single(ohci
->card
.device
, packet
->payload
,
648 packet
->payload_length
, DMA_TO_DEVICE
);
649 if (dma_mapping_error(payload_bus
)) {
650 packet
->ack
= RCODE_SEND_ERROR
;
654 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
655 d
[2].data_address
= cpu_to_le32(payload_bus
);
663 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
664 DESCRIPTOR_IRQ_ALWAYS
|
665 DESCRIPTOR_BRANCH_ALWAYS
);
667 /* FIXME: Document how the locking works. */
668 if (ohci
->generation
!= packet
->generation
) {
669 packet
->ack
= RCODE_GENERATION
;
673 context_append(ctx
, d
, z
, 4 - z
);
675 /* If the context isn't already running, start it up. */
676 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
677 if ((reg
& CONTEXT_RUN
) == 0)
683 static int handle_at_packet(struct context
*context
,
684 struct descriptor
*d
,
685 struct descriptor
*last
)
687 struct driver_data
*driver_data
;
688 struct fw_packet
*packet
;
689 struct fw_ohci
*ohci
= context
->ohci
;
690 dma_addr_t payload_bus
;
693 if (last
->transfer_status
== 0)
694 /* This descriptor isn't done yet, stop iteration. */
697 driver_data
= (struct driver_data
*) &d
[3];
698 packet
= driver_data
->packet
;
700 /* This packet was cancelled, just continue. */
703 payload_bus
= le32_to_cpu(last
->data_address
);
704 if (payload_bus
!= 0)
705 dma_unmap_single(ohci
->card
.device
, payload_bus
,
706 packet
->payload_length
, DMA_TO_DEVICE
);
708 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
709 packet
->timestamp
= le16_to_cpu(last
->res_count
);
712 case OHCI1394_evt_timeout
:
713 /* Async response transmit timed out. */
714 packet
->ack
= RCODE_CANCELLED
;
717 case OHCI1394_evt_flushed
:
719 * The packet was flushed should give same error as
720 * when we try to use a stale generation count.
722 packet
->ack
= RCODE_GENERATION
;
725 case OHCI1394_evt_missing_ack
:
727 * Using a valid (current) generation count, but the
728 * node is not on the bus or not sending acks.
730 packet
->ack
= RCODE_NO_ACK
;
733 case ACK_COMPLETE
+ 0x10:
734 case ACK_PENDING
+ 0x10:
735 case ACK_BUSY_X
+ 0x10:
736 case ACK_BUSY_A
+ 0x10:
737 case ACK_BUSY_B
+ 0x10:
738 case ACK_DATA_ERROR
+ 0x10:
739 case ACK_TYPE_ERROR
+ 0x10:
740 packet
->ack
= evt
- 0x10;
744 packet
->ack
= RCODE_SEND_ERROR
;
748 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
753 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
754 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
755 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
756 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
757 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
760 handle_local_rom(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
762 struct fw_packet response
;
763 int tcode
, length
, i
;
765 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
766 if (TCODE_IS_BLOCK_PACKET(tcode
))
767 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
771 i
= csr
- CSR_CONFIG_ROM
;
772 if (i
+ length
> CONFIG_ROM_SIZE
) {
773 fw_fill_response(&response
, packet
->header
,
774 RCODE_ADDRESS_ERROR
, NULL
, 0);
775 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
776 fw_fill_response(&response
, packet
->header
,
777 RCODE_TYPE_ERROR
, NULL
, 0);
779 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
780 (void *) ohci
->config_rom
+ i
, length
);
783 fw_core_handle_response(&ohci
->card
, &response
);
787 handle_local_lock(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
789 struct fw_packet response
;
790 int tcode
, length
, ext_tcode
, sel
;
791 __be32
*payload
, lock_old
;
792 u32 lock_arg
, lock_data
;
794 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
795 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
796 payload
= packet
->payload
;
797 ext_tcode
= HEADER_GET_EXTENDED_TCODE(packet
->header
[3]);
799 if (tcode
== TCODE_LOCK_REQUEST
&&
800 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
801 lock_arg
= be32_to_cpu(payload
[0]);
802 lock_data
= be32_to_cpu(payload
[1]);
803 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
807 fw_fill_response(&response
, packet
->header
,
808 RCODE_TYPE_ERROR
, NULL
, 0);
812 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
813 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
814 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
815 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
817 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
818 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
820 fw_notify("swap not done yet\n");
822 fw_fill_response(&response
, packet
->header
,
823 RCODE_COMPLETE
, &lock_old
, sizeof lock_old
);
825 fw_core_handle_response(&ohci
->card
, &response
);
829 handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
834 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
835 packet
->ack
= ACK_PENDING
;
836 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
840 ((unsigned long long)
841 HEADER_GET_OFFSET_HIGH(packet
->header
[1]) << 32) |
843 csr
= offset
- CSR_REGISTER_BASE
;
845 /* Handle config rom reads. */
846 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
847 handle_local_rom(ctx
->ohci
, packet
, csr
);
849 case CSR_BUS_MANAGER_ID
:
850 case CSR_BANDWIDTH_AVAILABLE
:
851 case CSR_CHANNELS_AVAILABLE_HI
:
852 case CSR_CHANNELS_AVAILABLE_LO
:
853 handle_local_lock(ctx
->ohci
, packet
, csr
);
856 if (ctx
== &ctx
->ohci
->at_request_ctx
)
857 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
859 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
863 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
864 packet
->ack
= ACK_COMPLETE
;
865 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
870 at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
875 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
877 if (HEADER_GET_DESTINATION(packet
->header
[0]) == ctx
->ohci
->node_id
&&
878 ctx
->ohci
->generation
== packet
->generation
) {
879 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
880 handle_local_request(ctx
, packet
);
884 retval
= at_context_queue_packet(ctx
, packet
);
885 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
888 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
892 static void bus_reset_tasklet(unsigned long data
)
894 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
895 int self_id_count
, i
, j
, reg
;
896 int generation
, new_generation
;
899 reg
= reg_read(ohci
, OHCI1394_NodeID
);
900 if (!(reg
& OHCI1394_NodeID_idValid
)) {
901 fw_error("node ID not valid, new bus reset in progress\n");
904 ohci
->node_id
= reg
& 0xffff;
907 * The count in the SelfIDCount register is the number of
908 * bytes in the self ID receive buffer. Since we also receive
909 * the inverted quadlets and a header quadlet, we shift one
910 * bit extra to get the actual number of self IDs.
913 self_id_count
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 3) & 0x3ff;
914 generation
= (le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
916 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
917 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1])
918 fw_error("inconsistent self IDs\n");
919 ohci
->self_id_buffer
[j
] = le32_to_cpu(ohci
->self_id_cpu
[i
]);
923 * Check the consistency of the self IDs we just read. The
924 * problem we face is that a new bus reset can start while we
925 * read out the self IDs from the DMA buffer. If this happens,
926 * the DMA buffer will be overwritten with new self IDs and we
927 * will read out inconsistent data. The OHCI specification
928 * (section 11.2) recommends a technique similar to
929 * linux/seqlock.h, where we remember the generation of the
930 * self IDs in the buffer before reading them out and compare
931 * it to the current generation after reading them out. If
932 * the two generations match we know we have a consistent set
936 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
937 if (new_generation
!= generation
) {
938 fw_notify("recursive bus reset detected, "
939 "discarding self ids\n");
943 /* FIXME: Document how the locking works. */
944 spin_lock_irqsave(&ohci
->lock
, flags
);
946 ohci
->generation
= generation
;
947 context_stop(&ohci
->at_request_ctx
);
948 context_stop(&ohci
->at_response_ctx
);
949 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
952 * This next bit is unrelated to the AT context stuff but we
953 * have to do it under the spinlock also. If a new config rom
954 * was set up before this reset, the old one is now no longer
955 * in use and we can free it. Update the config rom pointers
956 * to point to the current config rom and clear the
957 * next_config_rom pointer so a new udpate can take place.
960 if (ohci
->next_config_rom
!= NULL
) {
961 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
962 ohci
->config_rom
, ohci
->config_rom_bus
);
963 ohci
->config_rom
= ohci
->next_config_rom
;
964 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
965 ohci
->next_config_rom
= NULL
;
968 * Restore config_rom image and manually update
969 * config_rom registers. Writing the header quadlet
970 * will indicate that the config rom is ready, so we
973 reg_write(ohci
, OHCI1394_BusOptions
,
974 be32_to_cpu(ohci
->config_rom
[2]));
975 ohci
->config_rom
[0] = cpu_to_be32(ohci
->next_header
);
976 reg_write(ohci
, OHCI1394_ConfigROMhdr
, ohci
->next_header
);
979 spin_unlock_irqrestore(&ohci
->lock
, flags
);
981 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
982 self_id_count
, ohci
->self_id_buffer
);
985 static irqreturn_t
irq_handler(int irq
, void *data
)
987 struct fw_ohci
*ohci
= data
;
988 u32 event
, iso_event
, cycle_time
;
991 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
996 reg_write(ohci
, OHCI1394_IntEventClear
, event
);
998 if (event
& OHCI1394_selfIDComplete
)
999 tasklet_schedule(&ohci
->bus_reset_tasklet
);
1001 if (event
& OHCI1394_RQPkt
)
1002 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
1004 if (event
& OHCI1394_RSPkt
)
1005 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
1007 if (event
& OHCI1394_reqTxComplete
)
1008 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
1010 if (event
& OHCI1394_respTxComplete
)
1011 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
1013 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
1014 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
1017 i
= ffs(iso_event
) - 1;
1018 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
1019 iso_event
&= ~(1 << i
);
1022 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
1023 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1026 i
= ffs(iso_event
) - 1;
1027 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1028 iso_event
&= ~(1 << i
);
1031 if (event
& OHCI1394_cycle64Seconds
) {
1032 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1033 if ((cycle_time
& 0x80000000) == 0)
1034 ohci
->bus_seconds
++;
1040 static int ohci_enable(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1042 struct fw_ohci
*ohci
= fw_ohci(card
);
1043 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1046 * When the link is not yet enabled, the atomic config rom
1047 * update mechanism described below in ohci_set_config_rom()
1048 * is not active. We have to update ConfigRomHeader and
1049 * BusOptions manually, and the write to ConfigROMmap takes
1050 * effect immediately. We tie this to the enabling of the
1051 * link, so we have a valid config rom before enabling - the
1052 * OHCI requires that ConfigROMhdr and BusOptions have valid
1053 * values before enabling.
1055 * However, when the ConfigROMmap is written, some controllers
1056 * always read back quadlets 0 and 2 from the config rom to
1057 * the ConfigRomHeader and BusOptions registers on bus reset.
1058 * They shouldn't do that in this initial case where the link
1059 * isn't enabled. This means we have to use the same
1060 * workaround here, setting the bus header to 0 and then write
1061 * the right values in the bus reset tasklet.
1064 ohci
->next_config_rom
=
1065 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1066 &ohci
->next_config_rom_bus
, GFP_KERNEL
);
1067 if (ohci
->next_config_rom
== NULL
)
1070 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1071 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
, length
* 4);
1073 ohci
->next_header
= config_rom
[0];
1074 ohci
->next_config_rom
[0] = 0;
1075 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1076 reg_write(ohci
, OHCI1394_BusOptions
, config_rom
[2]);
1077 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1079 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1081 if (request_irq(dev
->irq
, irq_handler
,
1082 IRQF_SHARED
, ohci_driver_name
, ohci
)) {
1083 fw_error("Failed to allocate shared interrupt %d.\n",
1085 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1086 ohci
->config_rom
, ohci
->config_rom_bus
);
1090 reg_write(ohci
, OHCI1394_HCControlSet
,
1091 OHCI1394_HCControl_linkEnable
|
1092 OHCI1394_HCControl_BIBimageValid
);
1096 * We are ready to go, initiate bus reset to finish the
1100 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1106 ohci_set_config_rom(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1108 struct fw_ohci
*ohci
;
1109 unsigned long flags
;
1111 __be32
*next_config_rom
;
1112 dma_addr_t next_config_rom_bus
;
1114 ohci
= fw_ohci(card
);
1117 * When the OHCI controller is enabled, the config rom update
1118 * mechanism is a bit tricky, but easy enough to use. See
1119 * section 5.5.6 in the OHCI specification.
1121 * The OHCI controller caches the new config rom address in a
1122 * shadow register (ConfigROMmapNext) and needs a bus reset
1123 * for the changes to take place. When the bus reset is
1124 * detected, the controller loads the new values for the
1125 * ConfigRomHeader and BusOptions registers from the specified
1126 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1127 * shadow register. All automatically and atomically.
1129 * Now, there's a twist to this story. The automatic load of
1130 * ConfigRomHeader and BusOptions doesn't honor the
1131 * noByteSwapData bit, so with a be32 config rom, the
1132 * controller will load be32 values in to these registers
1133 * during the atomic update, even on litte endian
1134 * architectures. The workaround we use is to put a 0 in the
1135 * header quadlet; 0 is endian agnostic and means that the
1136 * config rom isn't ready yet. In the bus reset tasklet we
1137 * then set up the real values for the two registers.
1139 * We use ohci->lock to avoid racing with the code that sets
1140 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1144 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1145 &next_config_rom_bus
, GFP_KERNEL
);
1146 if (next_config_rom
== NULL
)
1149 spin_lock_irqsave(&ohci
->lock
, flags
);
1151 if (ohci
->next_config_rom
== NULL
) {
1152 ohci
->next_config_rom
= next_config_rom
;
1153 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1155 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1156 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
,
1159 ohci
->next_header
= config_rom
[0];
1160 ohci
->next_config_rom
[0] = 0;
1162 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1163 ohci
->next_config_rom_bus
);
1165 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1166 next_config_rom
, next_config_rom_bus
);
1170 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1173 * Now initiate a bus reset to have the changes take
1174 * effect. We clean up the old config rom memory and DMA
1175 * mappings in the bus reset tasklet, since the OHCI
1176 * controller could need to access it before the bus reset
1180 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1185 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1187 struct fw_ohci
*ohci
= fw_ohci(card
);
1189 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1192 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1194 struct fw_ohci
*ohci
= fw_ohci(card
);
1196 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1199 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1201 struct fw_ohci
*ohci
= fw_ohci(card
);
1202 struct context
*ctx
= &ohci
->at_request_ctx
;
1203 struct driver_data
*driver_data
= packet
->driver_data
;
1204 int retval
= -ENOENT
;
1206 tasklet_disable(&ctx
->tasklet
);
1208 if (packet
->ack
!= 0)
1211 driver_data
->packet
= NULL
;
1212 packet
->ack
= RCODE_CANCELLED
;
1213 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1217 tasklet_enable(&ctx
->tasklet
);
1223 ohci_enable_phys_dma(struct fw_card
*card
, int node_id
, int generation
)
1225 struct fw_ohci
*ohci
= fw_ohci(card
);
1226 unsigned long flags
;
1230 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1231 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1234 spin_lock_irqsave(&ohci
->lock
, flags
);
1236 if (ohci
->generation
!= generation
) {
1242 * Note, if the node ID contains a non-local bus ID, physical DMA is
1243 * enabled for _all_ nodes on remote buses.
1246 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
1248 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
1250 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
1254 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1259 ohci_get_bus_time(struct fw_card
*card
)
1261 struct fw_ohci
*ohci
= fw_ohci(card
);
1265 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1266 bus_time
= ((u64
) ohci
->bus_seconds
<< 32) | cycle_time
;
1271 static int handle_ir_dualbuffer_packet(struct context
*context
,
1272 struct descriptor
*d
,
1273 struct descriptor
*last
)
1275 struct iso_context
*ctx
=
1276 container_of(context
, struct iso_context
, context
);
1277 struct db_descriptor
*db
= (struct db_descriptor
*) d
;
1279 size_t header_length
;
1283 if (db
->first_res_count
> 0 && db
->second_res_count
> 0)
1284 /* This descriptor isn't done yet, stop iteration. */
1287 header_length
= le16_to_cpu(db
->first_req_count
) -
1288 le16_to_cpu(db
->first_res_count
);
1290 i
= ctx
->header_length
;
1292 end
= p
+ header_length
;
1293 while (p
< end
&& i
+ ctx
->base
.header_size
<= PAGE_SIZE
) {
1295 * The iso header is byteswapped to little endian by
1296 * the controller, but the remaining header quadlets
1297 * are big endian. We want to present all the headers
1298 * as big endian, so we have to swap the first
1301 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1302 memcpy(ctx
->header
+ i
+ 4, p
+ 8, ctx
->base
.header_size
- 4);
1303 i
+= ctx
->base
.header_size
;
1304 p
+= ctx
->base
.header_size
+ 4;
1307 ctx
->header_length
= i
;
1309 if (le16_to_cpu(db
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1310 ir_header
= (__le32
*) (db
+ 1);
1311 ctx
->base
.callback(&ctx
->base
,
1312 le32_to_cpu(ir_header
[0]) & 0xffff,
1313 ctx
->header_length
, ctx
->header
,
1314 ctx
->base
.callback_data
);
1315 ctx
->header_length
= 0;
1321 static int handle_it_packet(struct context
*context
,
1322 struct descriptor
*d
,
1323 struct descriptor
*last
)
1325 struct iso_context
*ctx
=
1326 container_of(context
, struct iso_context
, context
);
1328 if (last
->transfer_status
== 0)
1329 /* This descriptor isn't done yet, stop iteration. */
1332 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
)
1333 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
1334 0, NULL
, ctx
->base
.callback_data
);
1339 static struct fw_iso_context
*
1340 ohci_allocate_iso_context(struct fw_card
*card
, int type
, size_t header_size
)
1342 struct fw_ohci
*ohci
= fw_ohci(card
);
1343 struct iso_context
*ctx
, *list
;
1344 descriptor_callback_t callback
;
1346 unsigned long flags
;
1347 int index
, retval
= -ENOMEM
;
1349 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
1350 mask
= &ohci
->it_context_mask
;
1351 list
= ohci
->it_context_list
;
1352 callback
= handle_it_packet
;
1354 mask
= &ohci
->ir_context_mask
;
1355 list
= ohci
->ir_context_list
;
1356 callback
= handle_ir_dualbuffer_packet
;
1359 /* FIXME: We need a fallback for pre 1.1 OHCI. */
1360 if (callback
== handle_ir_dualbuffer_packet
&&
1361 ohci
->version
< OHCI_VERSION_1_1
)
1362 return ERR_PTR(-EINVAL
);
1364 spin_lock_irqsave(&ohci
->lock
, flags
);
1365 index
= ffs(*mask
) - 1;
1367 *mask
&= ~(1 << index
);
1368 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1371 return ERR_PTR(-EBUSY
);
1373 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
1374 regs
= OHCI1394_IsoXmitContextBase(index
);
1376 regs
= OHCI1394_IsoRcvContextBase(index
);
1379 memset(ctx
, 0, sizeof *ctx
);
1380 ctx
->header_length
= 0;
1381 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
1382 if (ctx
->header
== NULL
)
1385 retval
= context_init(&ctx
->context
, ohci
, ISO_BUFFER_SIZE
,
1388 goto out_with_header
;
1393 free_page((unsigned long)ctx
->header
);
1395 spin_lock_irqsave(&ohci
->lock
, flags
);
1396 *mask
|= 1 << index
;
1397 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1399 return ERR_PTR(retval
);
1402 static int ohci_start_iso(struct fw_iso_context
*base
,
1403 s32 cycle
, u32 sync
, u32 tags
)
1405 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1406 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
1410 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1411 index
= ctx
- ohci
->it_context_list
;
1414 match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
1415 (cycle
& 0x7fff) << 16;
1417 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
1418 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
1419 context_run(&ctx
->context
, match
);
1421 index
= ctx
- ohci
->ir_context_list
;
1422 control
= IR_CONTEXT_DUAL_BUFFER_MODE
| IR_CONTEXT_ISOCH_HEADER
;
1423 match
= (tags
<< 28) | (sync
<< 8) | ctx
->base
.channel
;
1425 match
|= (cycle
& 0x07fff) << 12;
1426 control
|= IR_CONTEXT_CYCLE_MATCH_ENABLE
;
1429 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
1430 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
1431 reg_write(ohci
, CONTEXT_MATCH(ctx
->context
.regs
), match
);
1432 context_run(&ctx
->context
, control
);
1438 static int ohci_stop_iso(struct fw_iso_context
*base
)
1440 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1441 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1444 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1445 index
= ctx
- ohci
->it_context_list
;
1446 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
1448 index
= ctx
- ohci
->ir_context_list
;
1449 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
1452 context_stop(&ctx
->context
);
1457 static void ohci_free_iso_context(struct fw_iso_context
*base
)
1459 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1460 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1461 unsigned long flags
;
1464 ohci_stop_iso(base
);
1465 context_release(&ctx
->context
);
1466 free_page((unsigned long)ctx
->header
);
1468 spin_lock_irqsave(&ohci
->lock
, flags
);
1470 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1471 index
= ctx
- ohci
->it_context_list
;
1472 ohci
->it_context_mask
|= 1 << index
;
1474 index
= ctx
- ohci
->ir_context_list
;
1475 ohci
->ir_context_mask
|= 1 << index
;
1478 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1482 ohci_queue_iso_transmit(struct fw_iso_context
*base
,
1483 struct fw_iso_packet
*packet
,
1484 struct fw_iso_buffer
*buffer
,
1485 unsigned long payload
)
1487 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1488 struct descriptor
*d
, *last
, *pd
;
1489 struct fw_iso_packet
*p
;
1491 dma_addr_t d_bus
, page_bus
;
1492 u32 z
, header_z
, payload_z
, irq
;
1493 u32 payload_index
, payload_end_index
, next_page_index
;
1494 int page
, end_page
, i
, length
, offset
;
1497 * FIXME: Cycle lost behavior should be configurable: lose
1498 * packet, retransmit or terminate..
1502 payload_index
= payload
;
1508 if (p
->header_length
> 0)
1511 /* Determine the first page the payload isn't contained in. */
1512 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
1513 if (p
->payload_length
> 0)
1514 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
1520 /* Get header size in number of descriptors. */
1521 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof *d
);
1523 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
1528 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
1529 d
[0].req_count
= cpu_to_le16(8);
1531 header
= (__le32
*) &d
[1];
1532 header
[0] = cpu_to_le32(IT_HEADER_SY(p
->sy
) |
1533 IT_HEADER_TAG(p
->tag
) |
1534 IT_HEADER_TCODE(TCODE_STREAM_DATA
) |
1535 IT_HEADER_CHANNEL(ctx
->base
.channel
) |
1536 IT_HEADER_SPEED(ctx
->base
.speed
));
1538 cpu_to_le32(IT_HEADER_DATA_LENGTH(p
->header_length
+
1539 p
->payload_length
));
1542 if (p
->header_length
> 0) {
1543 d
[2].req_count
= cpu_to_le16(p
->header_length
);
1544 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof *d
);
1545 memcpy(&d
[z
], p
->header
, p
->header_length
);
1548 pd
= d
+ z
- payload_z
;
1549 payload_end_index
= payload_index
+ p
->payload_length
;
1550 for (i
= 0; i
< payload_z
; i
++) {
1551 page
= payload_index
>> PAGE_SHIFT
;
1552 offset
= payload_index
& ~PAGE_MASK
;
1553 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
1555 min(next_page_index
, payload_end_index
) - payload_index
;
1556 pd
[i
].req_count
= cpu_to_le16(length
);
1558 page_bus
= page_private(buffer
->pages
[page
]);
1559 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
1561 payload_index
+= length
;
1565 irq
= DESCRIPTOR_IRQ_ALWAYS
;
1567 irq
= DESCRIPTOR_NO_IRQ
;
1569 last
= z
== 2 ? d
: d
+ z
- 1;
1570 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
1572 DESCRIPTOR_BRANCH_ALWAYS
|
1575 context_append(&ctx
->context
, d
, z
, header_z
);
1581 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context
*base
,
1582 struct fw_iso_packet
*packet
,
1583 struct fw_iso_buffer
*buffer
,
1584 unsigned long payload
)
1586 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1587 struct db_descriptor
*db
= NULL
;
1588 struct descriptor
*d
;
1589 struct fw_iso_packet
*p
;
1590 dma_addr_t d_bus
, page_bus
;
1591 u32 z
, header_z
, length
, rest
;
1592 int page
, offset
, packet_count
, header_size
;
1595 * FIXME: Cycle lost behavior should be configurable: lose
1596 * packet, retransmit or terminate..
1600 d
= context_get_descriptors(&ctx
->context
, 2, &d_bus
);
1604 db
= (struct db_descriptor
*) d
;
1605 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1606 DESCRIPTOR_BRANCH_ALWAYS
|
1608 db
->first_size
= cpu_to_le16(ctx
->base
.header_size
+ 4);
1609 context_append(&ctx
->context
, d
, 2, 0);
1616 * The OHCI controller puts the status word in the header
1617 * buffer too, so we need 4 extra bytes per packet.
1619 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
1620 header_size
= packet_count
* (ctx
->base
.header_size
+ 4);
1622 /* Get header size in number of descriptors. */
1623 header_z
= DIV_ROUND_UP(header_size
, sizeof *d
);
1624 page
= payload
>> PAGE_SHIFT
;
1625 offset
= payload
& ~PAGE_MASK
;
1626 rest
= p
->payload_length
;
1628 /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1629 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1631 d
= context_get_descriptors(&ctx
->context
,
1632 z
+ header_z
, &d_bus
);
1636 db
= (struct db_descriptor
*) d
;
1637 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1638 DESCRIPTOR_BRANCH_ALWAYS
);
1639 db
->first_size
= cpu_to_le16(ctx
->base
.header_size
+ 4);
1640 db
->first_req_count
= cpu_to_le16(header_size
);
1641 db
->first_res_count
= db
->first_req_count
;
1642 db
->first_buffer
= cpu_to_le32(d_bus
+ sizeof *db
);
1644 if (offset
+ rest
< PAGE_SIZE
)
1647 length
= PAGE_SIZE
- offset
;
1649 db
->second_req_count
= cpu_to_le16(length
);
1650 db
->second_res_count
= db
->second_req_count
;
1651 page_bus
= page_private(buffer
->pages
[page
]);
1652 db
->second_buffer
= cpu_to_le32(page_bus
+ offset
);
1654 if (p
->interrupt
&& length
== rest
)
1655 db
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
1657 context_append(&ctx
->context
, d
, z
, header_z
);
1658 offset
= (offset
+ length
) & ~PAGE_MASK
;
1667 ohci_queue_iso(struct fw_iso_context
*base
,
1668 struct fw_iso_packet
*packet
,
1669 struct fw_iso_buffer
*buffer
,
1670 unsigned long payload
)
1672 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1674 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
1675 return ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
1676 else if (ctx
->context
.ohci
->version
>= OHCI_VERSION_1_1
)
1677 return ohci_queue_iso_receive_dualbuffer(base
, packet
,
1680 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1684 static const struct fw_card_driver ohci_driver
= {
1685 .name
= ohci_driver_name
,
1686 .enable
= ohci_enable
,
1687 .update_phy_reg
= ohci_update_phy_reg
,
1688 .set_config_rom
= ohci_set_config_rom
,
1689 .send_request
= ohci_send_request
,
1690 .send_response
= ohci_send_response
,
1691 .cancel_packet
= ohci_cancel_packet
,
1692 .enable_phys_dma
= ohci_enable_phys_dma
,
1693 .get_bus_time
= ohci_get_bus_time
,
1695 .allocate_iso_context
= ohci_allocate_iso_context
,
1696 .free_iso_context
= ohci_free_iso_context
,
1697 .queue_iso
= ohci_queue_iso
,
1698 .start_iso
= ohci_start_iso
,
1699 .stop_iso
= ohci_stop_iso
,
1702 static int software_reset(struct fw_ohci
*ohci
)
1706 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1708 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1709 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1710 OHCI1394_HCControl_softReset
) == 0)
1726 static int cleanup(struct fw_ohci
*ohci
, int stage
, int code
)
1728 struct pci_dev
*dev
= to_pci_dev(ohci
->card
.device
);
1731 case CLEANUP_SELF_ID
:
1732 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
1733 ohci
->self_id_cpu
, ohci
->self_id_bus
);
1734 case CLEANUP_REGISTERS
:
1735 kfree(ohci
->it_context_list
);
1736 kfree(ohci
->ir_context_list
);
1737 pci_iounmap(dev
, ohci
->registers
);
1739 pci_release_region(dev
, 0);
1740 case CLEANUP_DISABLE
:
1741 pci_disable_device(dev
);
1742 case CLEANUP_PUT_CARD
:
1743 fw_card_put(&ohci
->card
);
1749 static int __devinit
1750 pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
1752 struct fw_ohci
*ohci
;
1753 u32 bus_options
, max_receive
, link_speed
;
1758 ohci
= kzalloc(sizeof *ohci
, GFP_KERNEL
);
1760 fw_error("Could not malloc fw_ohci data.\n");
1764 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
1766 if (pci_enable_device(dev
)) {
1767 fw_error("Failed to enable OHCI hardware.\n");
1768 return cleanup(ohci
, CLEANUP_PUT_CARD
, -ENODEV
);
1771 pci_set_master(dev
);
1772 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
1773 pci_set_drvdata(dev
, ohci
);
1775 spin_lock_init(&ohci
->lock
);
1777 tasklet_init(&ohci
->bus_reset_tasklet
,
1778 bus_reset_tasklet
, (unsigned long)ohci
);
1780 if (pci_request_region(dev
, 0, ohci_driver_name
)) {
1781 fw_error("MMIO resource unavailable\n");
1782 return cleanup(ohci
, CLEANUP_DISABLE
, -EBUSY
);
1785 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
1786 if (ohci
->registers
== NULL
) {
1787 fw_error("Failed to remap registers\n");
1788 return cleanup(ohci
, CLEANUP_IOMEM
, -ENXIO
);
1791 if (software_reset(ohci
)) {
1792 fw_error("Failed to reset ohci card.\n");
1793 return cleanup(ohci
, CLEANUP_REGISTERS
, -EBUSY
);
1797 * Now enable LPS, which we need in order to start accessing
1798 * most of the registers. In fact, on some cards (ALI M5251),
1799 * accessing registers in the SClk domain without LPS enabled
1800 * will lock up the machine. Wait 50msec to make sure we have
1801 * full link enabled.
1803 reg_write(ohci
, OHCI1394_HCControlSet
,
1804 OHCI1394_HCControl_LPS
|
1805 OHCI1394_HCControl_postedWriteEnable
);
1809 reg_write(ohci
, OHCI1394_HCControlClear
,
1810 OHCI1394_HCControl_noByteSwapData
);
1812 reg_write(ohci
, OHCI1394_LinkControlSet
,
1813 OHCI1394_LinkControl_rcvSelfID
|
1814 OHCI1394_LinkControl_cycleTimerEnable
|
1815 OHCI1394_LinkControl_cycleMaster
);
1817 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
1818 OHCI1394_AsReqRcvContextControlSet
);
1820 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
1821 OHCI1394_AsRspRcvContextControlSet
);
1823 context_init(&ohci
->at_request_ctx
, ohci
, AT_BUFFER_SIZE
,
1824 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
1826 context_init(&ohci
->at_response_ctx
, ohci
, AT_BUFFER_SIZE
,
1827 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
1829 reg_write(ohci
, OHCI1394_ATRetries
,
1830 OHCI1394_MAX_AT_REQ_RETRIES
|
1831 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1832 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1834 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
1835 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
1836 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
1837 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
1838 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
1840 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
1841 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
1842 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
1843 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
1844 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
1846 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
1847 fw_error("Out of memory for it/ir contexts.\n");
1848 return cleanup(ohci
, CLEANUP_REGISTERS
, -ENOMEM
);
1851 /* self-id dma buffer allocation */
1852 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
1856 if (ohci
->self_id_cpu
== NULL
) {
1857 fw_error("Out of memory for self ID buffer.\n");
1858 return cleanup(ohci
, CLEANUP_REGISTERS
, -ENOMEM
);
1861 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1862 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1863 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1864 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1865 reg_write(ohci
, OHCI1394_IntMaskSet
,
1866 OHCI1394_selfIDComplete
|
1867 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1868 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1869 OHCI1394_isochRx
| OHCI1394_isochTx
|
1870 OHCI1394_masterIntEnable
|
1871 OHCI1394_cycle64Seconds
);
1873 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
1874 max_receive
= (bus_options
>> 12) & 0xf;
1875 link_speed
= bus_options
& 0x7;
1876 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
1877 reg_read(ohci
, OHCI1394_GUIDLo
);
1879 error_code
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
1881 return cleanup(ohci
, CLEANUP_SELF_ID
, error_code
);
1883 ohci
->version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
1884 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1885 dev
->dev
.bus_id
, ohci
->version
>> 16, ohci
->version
& 0xff);
1890 static void pci_remove(struct pci_dev
*dev
)
1892 struct fw_ohci
*ohci
;
1894 ohci
= pci_get_drvdata(dev
);
1895 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1897 fw_core_remove_card(&ohci
->card
);
1900 * FIXME: Fail all pending packets here, now that the upper
1901 * layers can't queue any more.
1904 software_reset(ohci
);
1905 free_irq(dev
->irq
, ohci
);
1906 cleanup(ohci
, CLEANUP_SELF_ID
, 0);
1908 fw_notify("Removed fw-ohci device.\n");
1911 static struct pci_device_id pci_table
[] = {
1912 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
1916 MODULE_DEVICE_TABLE(pci
, pci_table
);
1918 static struct pci_driver fw_ohci_pci_driver
= {
1919 .name
= ohci_driver_name
,
1920 .id_table
= pci_table
,
1922 .remove
= pci_remove
,
1925 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1926 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1927 MODULE_LICENSE("GPL");
1929 /* Provide a module alias so root-on-sbp2 initrds don't break. */
1930 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
1931 MODULE_ALIAS("ohci1394");
1934 static int __init
fw_ohci_init(void)
1936 return pci_register_driver(&fw_ohci_pci_driver
);
1939 static void __exit
fw_ohci_cleanup(void)
1941 pci_unregister_driver(&fw_ohci_pci_driver
);
1944 module_init(fw_ohci_init
);
1945 module_exit(fw_ohci_cleanup
);