2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
34 #include <asm/atomic.h>
36 #include <asm/system.h>
38 #ifdef CONFIG_PPC_PMAC
39 #include <asm/pmac_feature.h>
43 #include "fw-transaction.h"
45 #define DESCRIPTOR_OUTPUT_MORE 0
46 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
47 #define DESCRIPTOR_INPUT_MORE (2 << 12)
48 #define DESCRIPTOR_INPUT_LAST (3 << 12)
49 #define DESCRIPTOR_STATUS (1 << 11)
50 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
51 #define DESCRIPTOR_PING (1 << 7)
52 #define DESCRIPTOR_YY (1 << 6)
53 #define DESCRIPTOR_NO_IRQ (0 << 4)
54 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
55 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
56 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
57 #define DESCRIPTOR_WAIT (3 << 0)
63 __le32 branch_address
;
65 __le16 transfer_status
;
66 } __attribute__((aligned(16)));
68 struct db_descriptor
{
71 __le16 second_req_count
;
72 __le16 first_req_count
;
73 __le32 branch_address
;
74 __le16 second_res_count
;
75 __le16 first_res_count
;
80 } __attribute__((aligned(16)));
82 #define CONTROL_SET(regs) (regs)
83 #define CONTROL_CLEAR(regs) ((regs) + 4)
84 #define COMMAND_PTR(regs) ((regs) + 12)
85 #define CONTEXT_MATCH(regs) ((regs) + 16)
88 struct descriptor descriptor
;
89 struct ar_buffer
*next
;
95 struct ar_buffer
*current_buffer
;
96 struct ar_buffer
*last_buffer
;
99 struct tasklet_struct tasklet
;
104 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
105 struct descriptor
*d
,
106 struct descriptor
*last
);
109 * A buffer that contains a block of DMA-able coherent memory used for
110 * storing a portion of a DMA descriptor program.
112 struct descriptor_buffer
{
113 struct list_head list
;
114 dma_addr_t buffer_bus
;
117 struct descriptor buffer
[0];
121 struct fw_ohci
*ohci
;
123 int total_allocation
;
126 * List of page-sized buffers for storing DMA descriptors.
127 * Head of list contains buffers in use and tail of list contains
130 struct list_head buffer_list
;
133 * Pointer to a buffer inside buffer_list that contains the tail
134 * end of the current DMA program.
136 struct descriptor_buffer
*buffer_tail
;
139 * The descriptor containing the branch address of the first
140 * descriptor that has not yet been filled by the device.
142 struct descriptor
*last
;
145 * The last descriptor in the DMA program. It contains the branch
146 * address that must be updated upon appending a new descriptor.
148 struct descriptor
*prev
;
150 descriptor_callback_t callback
;
152 struct tasklet_struct tasklet
;
155 #define IT_HEADER_SY(v) ((v) << 0)
156 #define IT_HEADER_TCODE(v) ((v) << 4)
157 #define IT_HEADER_CHANNEL(v) ((v) << 8)
158 #define IT_HEADER_TAG(v) ((v) << 14)
159 #define IT_HEADER_SPEED(v) ((v) << 16)
160 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
163 struct fw_iso_context base
;
164 struct context context
;
167 size_t header_length
;
170 #define CONFIG_ROM_SIZE 1024
175 __iomem
char *registers
;
176 dma_addr_t self_id_bus
;
178 struct tasklet_struct bus_reset_tasklet
;
181 int request_generation
; /* for timestamping incoming requests */
182 atomic_t bus_seconds
;
186 bool bus_reset_packet_quirk
;
189 * Spinlock for accessing fw_ohci data. Never call out of
190 * this driver with this lock held.
193 u32 self_id_buffer
[512];
195 /* Config rom buffers */
197 dma_addr_t config_rom_bus
;
198 __be32
*next_config_rom
;
199 dma_addr_t next_config_rom_bus
;
202 struct ar_context ar_request_ctx
;
203 struct ar_context ar_response_ctx
;
204 struct context at_request_ctx
;
205 struct context at_response_ctx
;
208 struct iso_context
*it_context_list
;
209 u64 ir_context_channels
;
211 struct iso_context
*ir_context_list
;
214 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
216 return container_of(card
, struct fw_ohci
, card
);
219 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
220 #define IR_CONTEXT_BUFFER_FILL 0x80000000
221 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
222 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
223 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
224 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
226 #define CONTEXT_RUN 0x8000
227 #define CONTEXT_WAKE 0x1000
228 #define CONTEXT_DEAD 0x0800
229 #define CONTEXT_ACTIVE 0x0400
231 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
232 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
233 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
235 #define FW_OHCI_MAJOR 240
236 #define OHCI1394_REGISTER_SIZE 0x800
237 #define OHCI_LOOP_COUNT 500
238 #define OHCI1394_PCI_HCI_Control 0x40
239 #define SELF_ID_BUF_SIZE 0x800
240 #define OHCI_TCODE_PHY_PACKET 0x0e
241 #define OHCI_VERSION_1_1 0x010010
243 static char ohci_driver_name
[] = KBUILD_MODNAME
;
245 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
247 #define OHCI_PARAM_DEBUG_AT_AR 1
248 #define OHCI_PARAM_DEBUG_SELFIDS 2
249 #define OHCI_PARAM_DEBUG_IRQS 4
250 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
252 static int param_debug
;
253 module_param_named(debug
, param_debug
, int, 0644);
254 MODULE_PARM_DESC(debug
, "Verbose logging (default = 0"
255 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR
)
256 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS
)
257 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS
)
258 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS
)
259 ", or a combination, or all = -1)");
261 static void log_irqs(u32 evt
)
263 if (likely(!(param_debug
&
264 (OHCI_PARAM_DEBUG_IRQS
| OHCI_PARAM_DEBUG_BUSRESETS
))))
267 if (!(param_debug
& OHCI_PARAM_DEBUG_IRQS
) &&
268 !(evt
& OHCI1394_busReset
))
271 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt
,
272 evt
& OHCI1394_selfIDComplete
? " selfID" : "",
273 evt
& OHCI1394_RQPkt
? " AR_req" : "",
274 evt
& OHCI1394_RSPkt
? " AR_resp" : "",
275 evt
& OHCI1394_reqTxComplete
? " AT_req" : "",
276 evt
& OHCI1394_respTxComplete
? " AT_resp" : "",
277 evt
& OHCI1394_isochRx
? " IR" : "",
278 evt
& OHCI1394_isochTx
? " IT" : "",
279 evt
& OHCI1394_postedWriteErr
? " postedWriteErr" : "",
280 evt
& OHCI1394_cycleTooLong
? " cycleTooLong" : "",
281 evt
& OHCI1394_cycle64Seconds
? " cycle64Seconds" : "",
282 evt
& OHCI1394_regAccessFail
? " regAccessFail" : "",
283 evt
& OHCI1394_busReset
? " busReset" : "",
284 evt
& ~(OHCI1394_selfIDComplete
| OHCI1394_RQPkt
|
285 OHCI1394_RSPkt
| OHCI1394_reqTxComplete
|
286 OHCI1394_respTxComplete
| OHCI1394_isochRx
|
287 OHCI1394_isochTx
| OHCI1394_postedWriteErr
|
288 OHCI1394_cycleTooLong
| OHCI1394_cycle64Seconds
|
289 OHCI1394_regAccessFail
| OHCI1394_busReset
)
293 static const char *speed
[] = {
294 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
296 static const char *power
[] = {
297 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
298 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
300 static const char port
[] = { '.', '-', 'p', 'c', };
302 static char _p(u32
*s
, int shift
)
304 return port
[*s
>> shift
& 3];
307 static void log_selfids(int node_id
, int generation
, int self_id_count
, u32
*s
)
309 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_SELFIDS
)))
312 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
313 self_id_count
, generation
, node_id
);
315 for (; self_id_count
--; ++s
)
316 if ((*s
& 1 << 23) == 0)
317 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
318 "%s gc=%d %s %s%s%s\n",
319 *s
, *s
>> 24 & 63, _p(s
, 6), _p(s
, 4), _p(s
, 2),
320 speed
[*s
>> 14 & 3], *s
>> 16 & 63,
321 power
[*s
>> 8 & 7], *s
>> 22 & 1 ? "L" : "",
322 *s
>> 11 & 1 ? "c" : "", *s
& 2 ? "i" : "");
324 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
326 _p(s
, 16), _p(s
, 14), _p(s
, 12), _p(s
, 10),
327 _p(s
, 8), _p(s
, 6), _p(s
, 4), _p(s
, 2));
330 static const char *evts
[] = {
331 [0x00] = "evt_no_status", [0x01] = "-reserved-",
332 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
333 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
334 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
335 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
336 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
337 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
338 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
339 [0x10] = "-reserved-", [0x11] = "ack_complete",
340 [0x12] = "ack_pending ", [0x13] = "-reserved-",
341 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
342 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
343 [0x18] = "-reserved-", [0x19] = "-reserved-",
344 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
345 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
346 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
347 [0x20] = "pending/cancelled",
349 static const char *tcodes
[] = {
350 [0x0] = "QW req", [0x1] = "BW req",
351 [0x2] = "W resp", [0x3] = "-reserved-",
352 [0x4] = "QR req", [0x5] = "BR req",
353 [0x6] = "QR resp", [0x7] = "BR resp",
354 [0x8] = "cycle start", [0x9] = "Lk req",
355 [0xa] = "async stream packet", [0xb] = "Lk resp",
356 [0xc] = "-reserved-", [0xd] = "-reserved-",
357 [0xe] = "link internal", [0xf] = "-reserved-",
359 static const char *phys
[] = {
360 [0x0] = "phy config packet", [0x1] = "link-on packet",
361 [0x2] = "self-id packet", [0x3] = "-reserved-",
364 static void log_ar_at_event(char dir
, int speed
, u32
*header
, int evt
)
366 int tcode
= header
[0] >> 4 & 0xf;
369 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_AT_AR
)))
372 if (unlikely(evt
>= ARRAY_SIZE(evts
)))
375 if (evt
== OHCI1394_evt_bus_reset
) {
376 fw_notify("A%c evt_bus_reset, generation %d\n",
377 dir
, (header
[2] >> 16) & 0xff);
381 if (header
[0] == ~header
[1]) {
382 fw_notify("A%c %s, %s, %08x\n",
383 dir
, evts
[evt
], phys
[header
[0] >> 30 & 0x3], header
[0]);
388 case 0x0: case 0x6: case 0x8:
389 snprintf(specific
, sizeof(specific
), " = %08x",
390 be32_to_cpu((__force __be32
)header
[3]));
392 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
393 snprintf(specific
, sizeof(specific
), " %x,%x",
394 header
[3] >> 16, header
[3] & 0xffff);
402 fw_notify("A%c %s, %s\n", dir
, evts
[evt
], tcodes
[tcode
]);
404 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
405 fw_notify("A%c spd %x tl %02x, "
408 dir
, speed
, header
[0] >> 10 & 0x3f,
409 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
410 tcodes
[tcode
], header
[1] & 0xffff, header
[2], specific
);
413 fw_notify("A%c spd %x tl %02x, "
416 dir
, speed
, header
[0] >> 10 & 0x3f,
417 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
418 tcodes
[tcode
], specific
);
424 #define log_irqs(evt)
425 #define log_selfids(node_id, generation, self_id_count, sid)
426 #define log_ar_at_event(dir, speed, header, evt)
428 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
430 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
432 writel(data
, ohci
->registers
+ offset
);
435 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
437 return readl(ohci
->registers
+ offset
);
440 static inline void flush_writes(const struct fw_ohci
*ohci
)
442 /* Do a dummy read to flush writes. */
443 reg_read(ohci
, OHCI1394_Version
);
446 static int ohci_update_phy_reg(struct fw_card
*card
, int addr
,
447 int clear_bits
, int set_bits
)
449 struct fw_ohci
*ohci
= fw_ohci(card
);
452 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
455 val
= reg_read(ohci
, OHCI1394_PhyControl
);
456 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
457 fw_error("failed to set phy reg bits.\n");
461 old
= OHCI1394_PhyControl_ReadData(val
);
462 old
= (old
& ~clear_bits
) | set_bits
;
463 reg_write(ohci
, OHCI1394_PhyControl
,
464 OHCI1394_PhyControl_Write(addr
, old
));
469 static int ar_context_add_page(struct ar_context
*ctx
)
471 struct device
*dev
= ctx
->ohci
->card
.device
;
472 struct ar_buffer
*ab
;
473 dma_addr_t
uninitialized_var(ab_bus
);
476 ab
= dma_alloc_coherent(dev
, PAGE_SIZE
, &ab_bus
, GFP_ATOMIC
);
481 memset(&ab
->descriptor
, 0, sizeof(ab
->descriptor
));
482 ab
->descriptor
.control
= cpu_to_le16(DESCRIPTOR_INPUT_MORE
|
484 DESCRIPTOR_BRANCH_ALWAYS
);
485 offset
= offsetof(struct ar_buffer
, data
);
486 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
487 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
488 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
489 ab
->descriptor
.branch_address
= 0;
491 ctx
->last_buffer
->descriptor
.branch_address
= cpu_to_le32(ab_bus
| 1);
492 ctx
->last_buffer
->next
= ab
;
493 ctx
->last_buffer
= ab
;
495 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
496 flush_writes(ctx
->ohci
);
501 static void ar_context_release(struct ar_context
*ctx
)
503 struct ar_buffer
*ab
, *ab_next
;
507 for (ab
= ctx
->current_buffer
; ab
; ab
= ab_next
) {
509 offset
= offsetof(struct ar_buffer
, data
);
510 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
511 dma_free_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
516 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
517 #define cond_le32_to_cpu(v) \
518 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
520 #define cond_le32_to_cpu(v) le32_to_cpu(v)
523 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
525 struct fw_ohci
*ohci
= ctx
->ohci
;
527 u32 status
, length
, tcode
;
530 p
.header
[0] = cond_le32_to_cpu(buffer
[0]);
531 p
.header
[1] = cond_le32_to_cpu(buffer
[1]);
532 p
.header
[2] = cond_le32_to_cpu(buffer
[2]);
534 tcode
= (p
.header
[0] >> 4) & 0x0f;
536 case TCODE_WRITE_QUADLET_REQUEST
:
537 case TCODE_READ_QUADLET_RESPONSE
:
538 p
.header
[3] = (__force __u32
) buffer
[3];
539 p
.header_length
= 16;
540 p
.payload_length
= 0;
543 case TCODE_READ_BLOCK_REQUEST
:
544 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
545 p
.header_length
= 16;
546 p
.payload_length
= 0;
549 case TCODE_WRITE_BLOCK_REQUEST
:
550 case TCODE_READ_BLOCK_RESPONSE
:
551 case TCODE_LOCK_REQUEST
:
552 case TCODE_LOCK_RESPONSE
:
553 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
554 p
.header_length
= 16;
555 p
.payload_length
= p
.header
[3] >> 16;
558 case TCODE_WRITE_RESPONSE
:
559 case TCODE_READ_QUADLET_REQUEST
:
560 case OHCI_TCODE_PHY_PACKET
:
561 p
.header_length
= 12;
562 p
.payload_length
= 0;
566 /* FIXME: Stop context, discard everything, and restart? */
568 p
.payload_length
= 0;
571 p
.payload
= (void *) buffer
+ p
.header_length
;
573 /* FIXME: What to do about evt_* errors? */
574 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
575 status
= cond_le32_to_cpu(buffer
[length
]);
576 evt
= (status
>> 16) & 0x1f;
579 p
.speed
= (status
>> 21) & 0x7;
580 p
.timestamp
= status
& 0xffff;
581 p
.generation
= ohci
->request_generation
;
583 log_ar_at_event('R', p
.speed
, p
.header
, evt
);
586 * The OHCI bus reset handler synthesizes a phy packet with
587 * the new generation number when a bus reset happens (see
588 * section 8.4.2.3). This helps us determine when a request
589 * was received and make sure we send the response in the same
590 * generation. We only need this for requests; for responses
591 * we use the unique tlabel for finding the matching
594 * Alas some chips sometimes emit bus reset packets with a
595 * wrong generation. We set the correct generation for these
596 * at a slightly incorrect time (in bus_reset_tasklet).
598 if (evt
== OHCI1394_evt_bus_reset
) {
599 if (!ohci
->bus_reset_packet_quirk
)
600 ohci
->request_generation
= (p
.header
[2] >> 16) & 0xff;
601 } else if (ctx
== &ohci
->ar_request_ctx
) {
602 fw_core_handle_request(&ohci
->card
, &p
);
604 fw_core_handle_response(&ohci
->card
, &p
);
607 return buffer
+ length
+ 1;
610 static void ar_context_tasklet(unsigned long data
)
612 struct ar_context
*ctx
= (struct ar_context
*)data
;
613 struct fw_ohci
*ohci
= ctx
->ohci
;
614 struct ar_buffer
*ab
;
615 struct descriptor
*d
;
618 ab
= ctx
->current_buffer
;
621 if (d
->res_count
== 0) {
622 size_t size
, rest
, offset
;
623 dma_addr_t start_bus
;
627 * This descriptor is finished and we may have a
628 * packet split across this and the next buffer. We
629 * reuse the page for reassembling the split packet.
632 offset
= offsetof(struct ar_buffer
, data
);
634 start_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
638 size
= buffer
+ PAGE_SIZE
- ctx
->pointer
;
639 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
640 memmove(buffer
, ctx
->pointer
, size
);
641 memcpy(buffer
+ size
, ab
->data
, rest
);
642 ctx
->current_buffer
= ab
;
643 ctx
->pointer
= (void *) ab
->data
+ rest
;
644 end
= buffer
+ size
+ rest
;
647 buffer
= handle_ar_packet(ctx
, buffer
);
649 dma_free_coherent(ohci
->card
.device
, PAGE_SIZE
,
651 ar_context_add_page(ctx
);
653 buffer
= ctx
->pointer
;
655 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
658 buffer
= handle_ar_packet(ctx
, buffer
);
662 static int ar_context_init(struct ar_context
*ctx
,
663 struct fw_ohci
*ohci
, u32 regs
)
669 ctx
->last_buffer
= &ab
;
670 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
672 ar_context_add_page(ctx
);
673 ar_context_add_page(ctx
);
674 ctx
->current_buffer
= ab
.next
;
675 ctx
->pointer
= ctx
->current_buffer
->data
;
680 static void ar_context_run(struct ar_context
*ctx
)
682 struct ar_buffer
*ab
= ctx
->current_buffer
;
686 offset
= offsetof(struct ar_buffer
, data
);
687 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
689 reg_write(ctx
->ohci
, COMMAND_PTR(ctx
->regs
), ab_bus
| 1);
690 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
);
691 flush_writes(ctx
->ohci
);
694 static struct descriptor
*find_branch_descriptor(struct descriptor
*d
, int z
)
698 b
= (le16_to_cpu(d
->control
) & DESCRIPTOR_BRANCH_ALWAYS
) >> 2;
699 key
= (le16_to_cpu(d
->control
) & DESCRIPTOR_KEY_IMMEDIATE
) >> 8;
701 /* figure out which descriptor the branch address goes in */
702 if (z
== 2 && (b
== 3 || key
== 2))
708 static void context_tasklet(unsigned long data
)
710 struct context
*ctx
= (struct context
*) data
;
711 struct descriptor
*d
, *last
;
714 struct descriptor_buffer
*desc
;
716 desc
= list_entry(ctx
->buffer_list
.next
,
717 struct descriptor_buffer
, list
);
719 while (last
->branch_address
!= 0) {
720 struct descriptor_buffer
*old_desc
= desc
;
721 address
= le32_to_cpu(last
->branch_address
);
725 /* If the branch address points to a buffer outside of the
726 * current buffer, advance to the next buffer. */
727 if (address
< desc
->buffer_bus
||
728 address
>= desc
->buffer_bus
+ desc
->used
)
729 desc
= list_entry(desc
->list
.next
,
730 struct descriptor_buffer
, list
);
731 d
= desc
->buffer
+ (address
- desc
->buffer_bus
) / sizeof(*d
);
732 last
= find_branch_descriptor(d
, z
);
734 if (!ctx
->callback(ctx
, d
, last
))
737 if (old_desc
!= desc
) {
738 /* If we've advanced to the next buffer, move the
739 * previous buffer to the free list. */
742 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
743 list_move_tail(&old_desc
->list
, &ctx
->buffer_list
);
744 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
751 * Allocate a new buffer and add it to the list of free buffers for this
752 * context. Must be called with ohci->lock held.
754 static int context_add_buffer(struct context
*ctx
)
756 struct descriptor_buffer
*desc
;
757 dma_addr_t
uninitialized_var(bus_addr
);
761 * 16MB of descriptors should be far more than enough for any DMA
762 * program. This will catch run-away userspace or DoS attacks.
764 if (ctx
->total_allocation
>= 16*1024*1024)
767 desc
= dma_alloc_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
768 &bus_addr
, GFP_ATOMIC
);
772 offset
= (void *)&desc
->buffer
- (void *)desc
;
773 desc
->buffer_size
= PAGE_SIZE
- offset
;
774 desc
->buffer_bus
= bus_addr
+ offset
;
777 list_add_tail(&desc
->list
, &ctx
->buffer_list
);
778 ctx
->total_allocation
+= PAGE_SIZE
;
783 static int context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
784 u32 regs
, descriptor_callback_t callback
)
788 ctx
->total_allocation
= 0;
790 INIT_LIST_HEAD(&ctx
->buffer_list
);
791 if (context_add_buffer(ctx
) < 0)
794 ctx
->buffer_tail
= list_entry(ctx
->buffer_list
.next
,
795 struct descriptor_buffer
, list
);
797 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
798 ctx
->callback
= callback
;
801 * We put a dummy descriptor in the buffer that has a NULL
802 * branch address and looks like it's been sent. That way we
803 * have a descriptor to append DMA programs to.
805 memset(ctx
->buffer_tail
->buffer
, 0, sizeof(*ctx
->buffer_tail
->buffer
));
806 ctx
->buffer_tail
->buffer
->control
= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
);
807 ctx
->buffer_tail
->buffer
->transfer_status
= cpu_to_le16(0x8011);
808 ctx
->buffer_tail
->used
+= sizeof(*ctx
->buffer_tail
->buffer
);
809 ctx
->last
= ctx
->buffer_tail
->buffer
;
810 ctx
->prev
= ctx
->buffer_tail
->buffer
;
815 static void context_release(struct context
*ctx
)
817 struct fw_card
*card
= &ctx
->ohci
->card
;
818 struct descriptor_buffer
*desc
, *tmp
;
820 list_for_each_entry_safe(desc
, tmp
, &ctx
->buffer_list
, list
)
821 dma_free_coherent(card
->device
, PAGE_SIZE
, desc
,
823 ((void *)&desc
->buffer
- (void *)desc
));
826 /* Must be called with ohci->lock held */
827 static struct descriptor
*context_get_descriptors(struct context
*ctx
,
828 int z
, dma_addr_t
*d_bus
)
830 struct descriptor
*d
= NULL
;
831 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
833 if (z
* sizeof(*d
) > desc
->buffer_size
)
836 if (z
* sizeof(*d
) > desc
->buffer_size
- desc
->used
) {
837 /* No room for the descriptor in this buffer, so advance to the
840 if (desc
->list
.next
== &ctx
->buffer_list
) {
841 /* If there is no free buffer next in the list,
843 if (context_add_buffer(ctx
) < 0)
846 desc
= list_entry(desc
->list
.next
,
847 struct descriptor_buffer
, list
);
848 ctx
->buffer_tail
= desc
;
851 d
= desc
->buffer
+ desc
->used
/ sizeof(*d
);
852 memset(d
, 0, z
* sizeof(*d
));
853 *d_bus
= desc
->buffer_bus
+ desc
->used
;
858 static void context_run(struct context
*ctx
, u32 extra
)
860 struct fw_ohci
*ohci
= ctx
->ohci
;
862 reg_write(ohci
, COMMAND_PTR(ctx
->regs
),
863 le32_to_cpu(ctx
->last
->branch_address
));
864 reg_write(ohci
, CONTROL_CLEAR(ctx
->regs
), ~0);
865 reg_write(ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
| extra
);
869 static void context_append(struct context
*ctx
,
870 struct descriptor
*d
, int z
, int extra
)
873 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
875 d_bus
= desc
->buffer_bus
+ (d
- desc
->buffer
) * sizeof(*d
);
877 desc
->used
+= (z
+ extra
) * sizeof(*d
);
878 ctx
->prev
->branch_address
= cpu_to_le32(d_bus
| z
);
879 ctx
->prev
= find_branch_descriptor(d
, z
);
881 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
882 flush_writes(ctx
->ohci
);
885 static void context_stop(struct context
*ctx
)
890 reg_write(ctx
->ohci
, CONTROL_CLEAR(ctx
->regs
), CONTEXT_RUN
);
891 flush_writes(ctx
->ohci
);
893 for (i
= 0; i
< 10; i
++) {
894 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
895 if ((reg
& CONTEXT_ACTIVE
) == 0)
900 fw_error("Error: DMA context still active (0x%08x)\n", reg
);
904 struct fw_packet
*packet
;
908 * This function apppends a packet to the DMA queue for transmission.
909 * Must always be called with the ochi->lock held to ensure proper
910 * generation handling and locking around packet queue manipulation.
912 static int at_context_queue_packet(struct context
*ctx
,
913 struct fw_packet
*packet
)
915 struct fw_ohci
*ohci
= ctx
->ohci
;
916 dma_addr_t d_bus
, uninitialized_var(payload_bus
);
917 struct driver_data
*driver_data
;
918 struct descriptor
*d
, *last
;
923 d
= context_get_descriptors(ctx
, 4, &d_bus
);
925 packet
->ack
= RCODE_SEND_ERROR
;
929 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
930 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
933 * The DMA format for asyncronous link packets is different
934 * from the IEEE1394 layout, so shift the fields around
935 * accordingly. If header_length is 8, it's a PHY packet, to
936 * which we need to prepend an extra quadlet.
939 header
= (__le32
*) &d
[1];
940 switch (packet
->header_length
) {
943 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
944 (packet
->speed
<< 16));
945 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
946 (packet
->header
[0] & 0xffff0000));
947 header
[2] = cpu_to_le32(packet
->header
[2]);
949 tcode
= (packet
->header
[0] >> 4) & 0x0f;
950 if (TCODE_IS_BLOCK_PACKET(tcode
))
951 header
[3] = cpu_to_le32(packet
->header
[3]);
953 header
[3] = (__force __le32
) packet
->header
[3];
955 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
959 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
960 (packet
->speed
<< 16));
961 header
[1] = cpu_to_le32(packet
->header
[0]);
962 header
[2] = cpu_to_le32(packet
->header
[1]);
963 d
[0].req_count
= cpu_to_le16(12);
967 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
968 (packet
->speed
<< 16));
969 header
[1] = cpu_to_le32(packet
->header
[0] & 0xffff0000);
970 d
[0].req_count
= cpu_to_le16(8);
975 packet
->ack
= RCODE_SEND_ERROR
;
979 driver_data
= (struct driver_data
*) &d
[3];
980 driver_data
->packet
= packet
;
981 packet
->driver_data
= driver_data
;
983 if (packet
->payload_length
> 0) {
985 dma_map_single(ohci
->card
.device
, packet
->payload
,
986 packet
->payload_length
, DMA_TO_DEVICE
);
987 if (dma_mapping_error(ohci
->card
.device
, payload_bus
)) {
988 packet
->ack
= RCODE_SEND_ERROR
;
991 packet
->payload_bus
= payload_bus
;
993 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
994 d
[2].data_address
= cpu_to_le32(payload_bus
);
1002 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
1003 DESCRIPTOR_IRQ_ALWAYS
|
1004 DESCRIPTOR_BRANCH_ALWAYS
);
1007 * If the controller and packet generations don't match, we need to
1008 * bail out and try again. If IntEvent.busReset is set, the AT context
1009 * is halted, so appending to the context and trying to run it is
1010 * futile. Most controllers do the right thing and just flush the AT
1011 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1012 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1013 * up stalling out. So we just bail out in software and try again
1014 * later, and everyone is happy.
1015 * FIXME: Document how the locking works.
1017 if (ohci
->generation
!= packet
->generation
||
1018 reg_read(ohci
, OHCI1394_IntEventSet
) & OHCI1394_busReset
) {
1019 if (packet
->payload_length
> 0)
1020 dma_unmap_single(ohci
->card
.device
, payload_bus
,
1021 packet
->payload_length
, DMA_TO_DEVICE
);
1022 packet
->ack
= RCODE_GENERATION
;
1026 context_append(ctx
, d
, z
, 4 - z
);
1028 /* If the context isn't already running, start it up. */
1029 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
1030 if ((reg
& CONTEXT_RUN
) == 0)
1031 context_run(ctx
, 0);
1036 static int handle_at_packet(struct context
*context
,
1037 struct descriptor
*d
,
1038 struct descriptor
*last
)
1040 struct driver_data
*driver_data
;
1041 struct fw_packet
*packet
;
1042 struct fw_ohci
*ohci
= context
->ohci
;
1045 if (last
->transfer_status
== 0)
1046 /* This descriptor isn't done yet, stop iteration. */
1049 driver_data
= (struct driver_data
*) &d
[3];
1050 packet
= driver_data
->packet
;
1052 /* This packet was cancelled, just continue. */
1055 if (packet
->payload_bus
)
1056 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1057 packet
->payload_length
, DMA_TO_DEVICE
);
1059 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
1060 packet
->timestamp
= le16_to_cpu(last
->res_count
);
1062 log_ar_at_event('T', packet
->speed
, packet
->header
, evt
);
1065 case OHCI1394_evt_timeout
:
1066 /* Async response transmit timed out. */
1067 packet
->ack
= RCODE_CANCELLED
;
1070 case OHCI1394_evt_flushed
:
1072 * The packet was flushed should give same error as
1073 * when we try to use a stale generation count.
1075 packet
->ack
= RCODE_GENERATION
;
1078 case OHCI1394_evt_missing_ack
:
1080 * Using a valid (current) generation count, but the
1081 * node is not on the bus or not sending acks.
1083 packet
->ack
= RCODE_NO_ACK
;
1086 case ACK_COMPLETE
+ 0x10:
1087 case ACK_PENDING
+ 0x10:
1088 case ACK_BUSY_X
+ 0x10:
1089 case ACK_BUSY_A
+ 0x10:
1090 case ACK_BUSY_B
+ 0x10:
1091 case ACK_DATA_ERROR
+ 0x10:
1092 case ACK_TYPE_ERROR
+ 0x10:
1093 packet
->ack
= evt
- 0x10;
1097 packet
->ack
= RCODE_SEND_ERROR
;
1101 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1106 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1107 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1108 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1109 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1110 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1112 static void handle_local_rom(struct fw_ohci
*ohci
,
1113 struct fw_packet
*packet
, u32 csr
)
1115 struct fw_packet response
;
1116 int tcode
, length
, i
;
1118 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1119 if (TCODE_IS_BLOCK_PACKET(tcode
))
1120 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1124 i
= csr
- CSR_CONFIG_ROM
;
1125 if (i
+ length
> CONFIG_ROM_SIZE
) {
1126 fw_fill_response(&response
, packet
->header
,
1127 RCODE_ADDRESS_ERROR
, NULL
, 0);
1128 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
1129 fw_fill_response(&response
, packet
->header
,
1130 RCODE_TYPE_ERROR
, NULL
, 0);
1132 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
1133 (void *) ohci
->config_rom
+ i
, length
);
1136 fw_core_handle_response(&ohci
->card
, &response
);
1139 static void handle_local_lock(struct fw_ohci
*ohci
,
1140 struct fw_packet
*packet
, u32 csr
)
1142 struct fw_packet response
;
1143 int tcode
, length
, ext_tcode
, sel
;
1144 __be32
*payload
, lock_old
;
1145 u32 lock_arg
, lock_data
;
1147 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1148 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1149 payload
= packet
->payload
;
1150 ext_tcode
= HEADER_GET_EXTENDED_TCODE(packet
->header
[3]);
1152 if (tcode
== TCODE_LOCK_REQUEST
&&
1153 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
1154 lock_arg
= be32_to_cpu(payload
[0]);
1155 lock_data
= be32_to_cpu(payload
[1]);
1156 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
1160 fw_fill_response(&response
, packet
->header
,
1161 RCODE_TYPE_ERROR
, NULL
, 0);
1165 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
1166 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
1167 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
1168 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
1170 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
1171 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
1173 fw_notify("swap not done yet\n");
1175 fw_fill_response(&response
, packet
->header
,
1176 RCODE_COMPLETE
, &lock_old
, sizeof(lock_old
));
1178 fw_core_handle_response(&ohci
->card
, &response
);
1181 static void handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
1186 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
1187 packet
->ack
= ACK_PENDING
;
1188 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1192 ((unsigned long long)
1193 HEADER_GET_OFFSET_HIGH(packet
->header
[1]) << 32) |
1195 csr
= offset
- CSR_REGISTER_BASE
;
1197 /* Handle config rom reads. */
1198 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
1199 handle_local_rom(ctx
->ohci
, packet
, csr
);
1201 case CSR_BUS_MANAGER_ID
:
1202 case CSR_BANDWIDTH_AVAILABLE
:
1203 case CSR_CHANNELS_AVAILABLE_HI
:
1204 case CSR_CHANNELS_AVAILABLE_LO
:
1205 handle_local_lock(ctx
->ohci
, packet
, csr
);
1208 if (ctx
== &ctx
->ohci
->at_request_ctx
)
1209 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
1211 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
1215 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
1216 packet
->ack
= ACK_COMPLETE
;
1217 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1221 static void at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
1223 unsigned long flags
;
1226 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
1228 if (HEADER_GET_DESTINATION(packet
->header
[0]) == ctx
->ohci
->node_id
&&
1229 ctx
->ohci
->generation
== packet
->generation
) {
1230 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1231 handle_local_request(ctx
, packet
);
1235 ret
= at_context_queue_packet(ctx
, packet
);
1236 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1239 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1243 static void bus_reset_tasklet(unsigned long data
)
1245 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
1246 int self_id_count
, i
, j
, reg
;
1247 int generation
, new_generation
;
1248 unsigned long flags
;
1249 void *free_rom
= NULL
;
1250 dma_addr_t free_rom_bus
= 0;
1252 reg
= reg_read(ohci
, OHCI1394_NodeID
);
1253 if (!(reg
& OHCI1394_NodeID_idValid
)) {
1254 fw_notify("node ID not valid, new bus reset in progress\n");
1257 if ((reg
& OHCI1394_NodeID_nodeNumber
) == 63) {
1258 fw_notify("malconfigured bus\n");
1261 ohci
->node_id
= reg
& (OHCI1394_NodeID_busNumber
|
1262 OHCI1394_NodeID_nodeNumber
);
1264 reg
= reg_read(ohci
, OHCI1394_SelfIDCount
);
1265 if (reg
& OHCI1394_SelfIDCount_selfIDError
) {
1266 fw_notify("inconsistent self IDs\n");
1270 * The count in the SelfIDCount register is the number of
1271 * bytes in the self ID receive buffer. Since we also receive
1272 * the inverted quadlets and a header quadlet, we shift one
1273 * bit extra to get the actual number of self IDs.
1275 self_id_count
= (reg
>> 3) & 0x3ff;
1276 if (self_id_count
== 0) {
1277 fw_notify("inconsistent self IDs\n");
1280 generation
= (cond_le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
1283 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
1284 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1]) {
1285 fw_notify("inconsistent self IDs\n");
1288 ohci
->self_id_buffer
[j
] =
1289 cond_le32_to_cpu(ohci
->self_id_cpu
[i
]);
1294 * Check the consistency of the self IDs we just read. The
1295 * problem we face is that a new bus reset can start while we
1296 * read out the self IDs from the DMA buffer. If this happens,
1297 * the DMA buffer will be overwritten with new self IDs and we
1298 * will read out inconsistent data. The OHCI specification
1299 * (section 11.2) recommends a technique similar to
1300 * linux/seqlock.h, where we remember the generation of the
1301 * self IDs in the buffer before reading them out and compare
1302 * it to the current generation after reading them out. If
1303 * the two generations match we know we have a consistent set
1307 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
1308 if (new_generation
!= generation
) {
1309 fw_notify("recursive bus reset detected, "
1310 "discarding self ids\n");
1314 /* FIXME: Document how the locking works. */
1315 spin_lock_irqsave(&ohci
->lock
, flags
);
1317 ohci
->generation
= generation
;
1318 context_stop(&ohci
->at_request_ctx
);
1319 context_stop(&ohci
->at_response_ctx
);
1320 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
1322 if (ohci
->bus_reset_packet_quirk
)
1323 ohci
->request_generation
= generation
;
1326 * This next bit is unrelated to the AT context stuff but we
1327 * have to do it under the spinlock also. If a new config rom
1328 * was set up before this reset, the old one is now no longer
1329 * in use and we can free it. Update the config rom pointers
1330 * to point to the current config rom and clear the
1331 * next_config_rom pointer so a new udpate can take place.
1334 if (ohci
->next_config_rom
!= NULL
) {
1335 if (ohci
->next_config_rom
!= ohci
->config_rom
) {
1336 free_rom
= ohci
->config_rom
;
1337 free_rom_bus
= ohci
->config_rom_bus
;
1339 ohci
->config_rom
= ohci
->next_config_rom
;
1340 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
1341 ohci
->next_config_rom
= NULL
;
1344 * Restore config_rom image and manually update
1345 * config_rom registers. Writing the header quadlet
1346 * will indicate that the config rom is ready, so we
1349 reg_write(ohci
, OHCI1394_BusOptions
,
1350 be32_to_cpu(ohci
->config_rom
[2]));
1351 ohci
->config_rom
[0] = cpu_to_be32(ohci
->next_header
);
1352 reg_write(ohci
, OHCI1394_ConfigROMhdr
, ohci
->next_header
);
1355 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1356 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, ~0);
1357 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, ~0);
1360 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1363 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1364 free_rom
, free_rom_bus
);
1366 log_selfids(ohci
->node_id
, generation
,
1367 self_id_count
, ohci
->self_id_buffer
);
1369 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
1370 self_id_count
, ohci
->self_id_buffer
);
1373 static irqreturn_t
irq_handler(int irq
, void *data
)
1375 struct fw_ohci
*ohci
= data
;
1376 u32 event
, iso_event
, cycle_time
;
1379 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
1381 if (!event
|| !~event
)
1384 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1385 reg_write(ohci
, OHCI1394_IntEventClear
, event
& ~OHCI1394_busReset
);
1388 if (event
& OHCI1394_selfIDComplete
)
1389 tasklet_schedule(&ohci
->bus_reset_tasklet
);
1391 if (event
& OHCI1394_RQPkt
)
1392 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
1394 if (event
& OHCI1394_RSPkt
)
1395 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
1397 if (event
& OHCI1394_reqTxComplete
)
1398 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
1400 if (event
& OHCI1394_respTxComplete
)
1401 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
1403 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
1404 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
1407 i
= ffs(iso_event
) - 1;
1408 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
1409 iso_event
&= ~(1 << i
);
1412 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
1413 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1416 i
= ffs(iso_event
) - 1;
1417 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1418 iso_event
&= ~(1 << i
);
1421 if (unlikely(event
& OHCI1394_regAccessFail
))
1422 fw_error("Register access failure - "
1423 "please notify linux1394-devel@lists.sf.net\n");
1425 if (unlikely(event
& OHCI1394_postedWriteErr
))
1426 fw_error("PCI posted write error\n");
1428 if (unlikely(event
& OHCI1394_cycleTooLong
)) {
1429 if (printk_ratelimit())
1430 fw_notify("isochronous cycle too long\n");
1431 reg_write(ohci
, OHCI1394_LinkControlSet
,
1432 OHCI1394_LinkControl_cycleMaster
);
1435 if (event
& OHCI1394_cycle64Seconds
) {
1436 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1437 if ((cycle_time
& 0x80000000) == 0)
1438 atomic_inc(&ohci
->bus_seconds
);
1444 static int software_reset(struct fw_ohci
*ohci
)
1448 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1450 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1451 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1452 OHCI1394_HCControl_softReset
) == 0)
1460 static int ohci_enable(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1462 struct fw_ohci
*ohci
= fw_ohci(card
);
1463 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1467 if (software_reset(ohci
)) {
1468 fw_error("Failed to reset ohci card.\n");
1473 * Now enable LPS, which we need in order to start accessing
1474 * most of the registers. In fact, on some cards (ALI M5251),
1475 * accessing registers in the SClk domain without LPS enabled
1476 * will lock up the machine. Wait 50msec to make sure we have
1477 * full link enabled. However, with some cards (well, at least
1478 * a JMicron PCIe card), we have to try again sometimes.
1480 reg_write(ohci
, OHCI1394_HCControlSet
,
1481 OHCI1394_HCControl_LPS
|
1482 OHCI1394_HCControl_postedWriteEnable
);
1485 for (lps
= 0, i
= 0; !lps
&& i
< 3; i
++) {
1487 lps
= reg_read(ohci
, OHCI1394_HCControlSet
) &
1488 OHCI1394_HCControl_LPS
;
1492 fw_error("Failed to set Link Power Status\n");
1496 reg_write(ohci
, OHCI1394_HCControlClear
,
1497 OHCI1394_HCControl_noByteSwapData
);
1499 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1500 reg_write(ohci
, OHCI1394_LinkControlClear
,
1501 OHCI1394_LinkControl_rcvPhyPkt
);
1502 reg_write(ohci
, OHCI1394_LinkControlSet
,
1503 OHCI1394_LinkControl_rcvSelfID
|
1504 OHCI1394_LinkControl_cycleTimerEnable
|
1505 OHCI1394_LinkControl_cycleMaster
);
1507 reg_write(ohci
, OHCI1394_ATRetries
,
1508 OHCI1394_MAX_AT_REQ_RETRIES
|
1509 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1510 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1512 ar_context_run(&ohci
->ar_request_ctx
);
1513 ar_context_run(&ohci
->ar_response_ctx
);
1515 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1516 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1517 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1518 reg_write(ohci
, OHCI1394_IntMaskSet
,
1519 OHCI1394_selfIDComplete
|
1520 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1521 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1522 OHCI1394_isochRx
| OHCI1394_isochTx
|
1523 OHCI1394_postedWriteErr
| OHCI1394_cycleTooLong
|
1524 OHCI1394_cycle64Seconds
| OHCI1394_regAccessFail
|
1525 OHCI1394_masterIntEnable
);
1526 if (param_debug
& OHCI_PARAM_DEBUG_BUSRESETS
)
1527 reg_write(ohci
, OHCI1394_IntMaskSet
, OHCI1394_busReset
);
1529 /* Activate link_on bit and contender bit in our self ID packets.*/
1530 if (ohci_update_phy_reg(card
, 4, 0,
1531 PHY_LINK_ACTIVE
| PHY_CONTENDER
) < 0)
1535 * When the link is not yet enabled, the atomic config rom
1536 * update mechanism described below in ohci_set_config_rom()
1537 * is not active. We have to update ConfigRomHeader and
1538 * BusOptions manually, and the write to ConfigROMmap takes
1539 * effect immediately. We tie this to the enabling of the
1540 * link, so we have a valid config rom before enabling - the
1541 * OHCI requires that ConfigROMhdr and BusOptions have valid
1542 * values before enabling.
1544 * However, when the ConfigROMmap is written, some controllers
1545 * always read back quadlets 0 and 2 from the config rom to
1546 * the ConfigRomHeader and BusOptions registers on bus reset.
1547 * They shouldn't do that in this initial case where the link
1548 * isn't enabled. This means we have to use the same
1549 * workaround here, setting the bus header to 0 and then write
1550 * the right values in the bus reset tasklet.
1554 ohci
->next_config_rom
=
1555 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1556 &ohci
->next_config_rom_bus
,
1558 if (ohci
->next_config_rom
== NULL
)
1561 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1562 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
, length
* 4);
1565 * In the suspend case, config_rom is NULL, which
1566 * means that we just reuse the old config rom.
1568 ohci
->next_config_rom
= ohci
->config_rom
;
1569 ohci
->next_config_rom_bus
= ohci
->config_rom_bus
;
1572 ohci
->next_header
= be32_to_cpu(ohci
->next_config_rom
[0]);
1573 ohci
->next_config_rom
[0] = 0;
1574 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1575 reg_write(ohci
, OHCI1394_BusOptions
,
1576 be32_to_cpu(ohci
->next_config_rom
[2]));
1577 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1579 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1581 if (request_irq(dev
->irq
, irq_handler
,
1582 IRQF_SHARED
, ohci_driver_name
, ohci
)) {
1583 fw_error("Failed to allocate shared interrupt %d.\n",
1585 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1586 ohci
->config_rom
, ohci
->config_rom_bus
);
1590 reg_write(ohci
, OHCI1394_HCControlSet
,
1591 OHCI1394_HCControl_linkEnable
|
1592 OHCI1394_HCControl_BIBimageValid
);
1596 * We are ready to go, initiate bus reset to finish the
1600 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1605 static int ohci_set_config_rom(struct fw_card
*card
,
1606 u32
*config_rom
, size_t length
)
1608 struct fw_ohci
*ohci
;
1609 unsigned long flags
;
1611 __be32
*next_config_rom
;
1612 dma_addr_t
uninitialized_var(next_config_rom_bus
);
1614 ohci
= fw_ohci(card
);
1617 * When the OHCI controller is enabled, the config rom update
1618 * mechanism is a bit tricky, but easy enough to use. See
1619 * section 5.5.6 in the OHCI specification.
1621 * The OHCI controller caches the new config rom address in a
1622 * shadow register (ConfigROMmapNext) and needs a bus reset
1623 * for the changes to take place. When the bus reset is
1624 * detected, the controller loads the new values for the
1625 * ConfigRomHeader and BusOptions registers from the specified
1626 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1627 * shadow register. All automatically and atomically.
1629 * Now, there's a twist to this story. The automatic load of
1630 * ConfigRomHeader and BusOptions doesn't honor the
1631 * noByteSwapData bit, so with a be32 config rom, the
1632 * controller will load be32 values in to these registers
1633 * during the atomic update, even on litte endian
1634 * architectures. The workaround we use is to put a 0 in the
1635 * header quadlet; 0 is endian agnostic and means that the
1636 * config rom isn't ready yet. In the bus reset tasklet we
1637 * then set up the real values for the two registers.
1639 * We use ohci->lock to avoid racing with the code that sets
1640 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1644 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1645 &next_config_rom_bus
, GFP_KERNEL
);
1646 if (next_config_rom
== NULL
)
1649 spin_lock_irqsave(&ohci
->lock
, flags
);
1651 if (ohci
->next_config_rom
== NULL
) {
1652 ohci
->next_config_rom
= next_config_rom
;
1653 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1655 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1656 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
,
1659 ohci
->next_header
= config_rom
[0];
1660 ohci
->next_config_rom
[0] = 0;
1662 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1663 ohci
->next_config_rom_bus
);
1667 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1670 * Now initiate a bus reset to have the changes take
1671 * effect. We clean up the old config rom memory and DMA
1672 * mappings in the bus reset tasklet, since the OHCI
1673 * controller could need to access it before the bus reset
1677 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1679 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1680 next_config_rom
, next_config_rom_bus
);
1685 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1687 struct fw_ohci
*ohci
= fw_ohci(card
);
1689 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1692 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1694 struct fw_ohci
*ohci
= fw_ohci(card
);
1696 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1699 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1701 struct fw_ohci
*ohci
= fw_ohci(card
);
1702 struct context
*ctx
= &ohci
->at_request_ctx
;
1703 struct driver_data
*driver_data
= packet
->driver_data
;
1706 tasklet_disable(&ctx
->tasklet
);
1708 if (packet
->ack
!= 0)
1711 if (packet
->payload_bus
)
1712 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1713 packet
->payload_length
, DMA_TO_DEVICE
);
1715 log_ar_at_event('T', packet
->speed
, packet
->header
, 0x20);
1716 driver_data
->packet
= NULL
;
1717 packet
->ack
= RCODE_CANCELLED
;
1718 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1721 tasklet_enable(&ctx
->tasklet
);
1726 static int ohci_enable_phys_dma(struct fw_card
*card
,
1727 int node_id
, int generation
)
1729 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1732 struct fw_ohci
*ohci
= fw_ohci(card
);
1733 unsigned long flags
;
1737 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1738 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1741 spin_lock_irqsave(&ohci
->lock
, flags
);
1743 if (ohci
->generation
!= generation
) {
1749 * Note, if the node ID contains a non-local bus ID, physical DMA is
1750 * enabled for _all_ nodes on remote buses.
1753 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
1755 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
1757 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
1761 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1764 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1767 static u64
ohci_get_bus_time(struct fw_card
*card
)
1769 struct fw_ohci
*ohci
= fw_ohci(card
);
1773 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1774 bus_time
= ((u64
)atomic_read(&ohci
->bus_seconds
) << 32) | cycle_time
;
1779 static void copy_iso_headers(struct iso_context
*ctx
, void *p
)
1781 int i
= ctx
->header_length
;
1783 if (i
+ ctx
->base
.header_size
> PAGE_SIZE
)
1787 * The iso header is byteswapped to little endian by
1788 * the controller, but the remaining header quadlets
1789 * are big endian. We want to present all the headers
1790 * as big endian, so we have to swap the first quadlet.
1792 if (ctx
->base
.header_size
> 0)
1793 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1794 if (ctx
->base
.header_size
> 4)
1795 *(u32
*) (ctx
->header
+ i
+ 4) = __swab32(*(u32
*) p
);
1796 if (ctx
->base
.header_size
> 8)
1797 memcpy(ctx
->header
+ i
+ 8, p
+ 8, ctx
->base
.header_size
- 8);
1798 ctx
->header_length
+= ctx
->base
.header_size
;
1801 static int handle_ir_dualbuffer_packet(struct context
*context
,
1802 struct descriptor
*d
,
1803 struct descriptor
*last
)
1805 struct iso_context
*ctx
=
1806 container_of(context
, struct iso_context
, context
);
1807 struct db_descriptor
*db
= (struct db_descriptor
*) d
;
1809 size_t header_length
;
1812 if (db
->first_res_count
!= 0 && db
->second_res_count
!= 0) {
1813 if (ctx
->excess_bytes
<= le16_to_cpu(db
->second_req_count
)) {
1814 /* This descriptor isn't done yet, stop iteration. */
1817 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
);
1820 header_length
= le16_to_cpu(db
->first_req_count
) -
1821 le16_to_cpu(db
->first_res_count
);
1824 end
= p
+ header_length
;
1826 copy_iso_headers(ctx
, p
);
1827 ctx
->excess_bytes
+=
1828 (le32_to_cpu(*(__le32
*)(p
+ 4)) >> 16) & 0xffff;
1829 p
+= max(ctx
->base
.header_size
, (size_t)8);
1832 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
) -
1833 le16_to_cpu(db
->second_res_count
);
1835 if (le16_to_cpu(db
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1836 ir_header
= (__le32
*) (db
+ 1);
1837 ctx
->base
.callback(&ctx
->base
,
1838 le32_to_cpu(ir_header
[0]) & 0xffff,
1839 ctx
->header_length
, ctx
->header
,
1840 ctx
->base
.callback_data
);
1841 ctx
->header_length
= 0;
1847 static int handle_ir_packet_per_buffer(struct context
*context
,
1848 struct descriptor
*d
,
1849 struct descriptor
*last
)
1851 struct iso_context
*ctx
=
1852 container_of(context
, struct iso_context
, context
);
1853 struct descriptor
*pd
;
1857 for (pd
= d
; pd
<= last
; pd
++) {
1858 if (pd
->transfer_status
)
1862 /* Descriptor(s) not done yet, stop iteration */
1866 copy_iso_headers(ctx
, p
);
1868 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1869 ir_header
= (__le32
*) p
;
1870 ctx
->base
.callback(&ctx
->base
,
1871 le32_to_cpu(ir_header
[0]) & 0xffff,
1872 ctx
->header_length
, ctx
->header
,
1873 ctx
->base
.callback_data
);
1874 ctx
->header_length
= 0;
1880 static int handle_it_packet(struct context
*context
,
1881 struct descriptor
*d
,
1882 struct descriptor
*last
)
1884 struct iso_context
*ctx
=
1885 container_of(context
, struct iso_context
, context
);
1887 if (last
->transfer_status
== 0)
1888 /* This descriptor isn't done yet, stop iteration. */
1891 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
)
1892 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
1893 0, NULL
, ctx
->base
.callback_data
);
1898 static struct fw_iso_context
*ohci_allocate_iso_context(struct fw_card
*card
,
1899 int type
, int channel
, size_t header_size
)
1901 struct fw_ohci
*ohci
= fw_ohci(card
);
1902 struct iso_context
*ctx
, *list
;
1903 descriptor_callback_t callback
;
1904 u64
*channels
, dont_care
= ~0ULL;
1906 unsigned long flags
;
1907 int index
, ret
= -ENOMEM
;
1909 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
1910 channels
= &dont_care
;
1911 mask
= &ohci
->it_context_mask
;
1912 list
= ohci
->it_context_list
;
1913 callback
= handle_it_packet
;
1915 channels
= &ohci
->ir_context_channels
;
1916 mask
= &ohci
->ir_context_mask
;
1917 list
= ohci
->ir_context_list
;
1918 if (ohci
->use_dualbuffer
)
1919 callback
= handle_ir_dualbuffer_packet
;
1921 callback
= handle_ir_packet_per_buffer
;
1924 spin_lock_irqsave(&ohci
->lock
, flags
);
1925 index
= *channels
& 1ULL << channel
? ffs(*mask
) - 1 : -1;
1927 *channels
&= ~(1ULL << channel
);
1928 *mask
&= ~(1 << index
);
1930 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1933 return ERR_PTR(-EBUSY
);
1935 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
1936 regs
= OHCI1394_IsoXmitContextBase(index
);
1938 regs
= OHCI1394_IsoRcvContextBase(index
);
1941 memset(ctx
, 0, sizeof(*ctx
));
1942 ctx
->header_length
= 0;
1943 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
1944 if (ctx
->header
== NULL
)
1947 ret
= context_init(&ctx
->context
, ohci
, regs
, callback
);
1949 goto out_with_header
;
1954 free_page((unsigned long)ctx
->header
);
1956 spin_lock_irqsave(&ohci
->lock
, flags
);
1957 *mask
|= 1 << index
;
1958 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1960 return ERR_PTR(ret
);
1963 static int ohci_start_iso(struct fw_iso_context
*base
,
1964 s32 cycle
, u32 sync
, u32 tags
)
1966 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1967 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
1971 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1972 index
= ctx
- ohci
->it_context_list
;
1975 match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
1976 (cycle
& 0x7fff) << 16;
1978 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
1979 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
1980 context_run(&ctx
->context
, match
);
1982 index
= ctx
- ohci
->ir_context_list
;
1983 control
= IR_CONTEXT_ISOCH_HEADER
;
1984 if (ohci
->use_dualbuffer
)
1985 control
|= IR_CONTEXT_DUAL_BUFFER_MODE
;
1986 match
= (tags
<< 28) | (sync
<< 8) | ctx
->base
.channel
;
1988 match
|= (cycle
& 0x07fff) << 12;
1989 control
|= IR_CONTEXT_CYCLE_MATCH_ENABLE
;
1992 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
1993 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
1994 reg_write(ohci
, CONTEXT_MATCH(ctx
->context
.regs
), match
);
1995 context_run(&ctx
->context
, control
);
2001 static int ohci_stop_iso(struct fw_iso_context
*base
)
2003 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
2004 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2007 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2008 index
= ctx
- ohci
->it_context_list
;
2009 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
2011 index
= ctx
- ohci
->ir_context_list
;
2012 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
2015 context_stop(&ctx
->context
);
2020 static void ohci_free_iso_context(struct fw_iso_context
*base
)
2022 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
2023 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2024 unsigned long flags
;
2027 ohci_stop_iso(base
);
2028 context_release(&ctx
->context
);
2029 free_page((unsigned long)ctx
->header
);
2031 spin_lock_irqsave(&ohci
->lock
, flags
);
2033 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2034 index
= ctx
- ohci
->it_context_list
;
2035 ohci
->it_context_mask
|= 1 << index
;
2037 index
= ctx
- ohci
->ir_context_list
;
2038 ohci
->ir_context_mask
|= 1 << index
;
2039 ohci
->ir_context_channels
|= 1ULL << base
->channel
;
2042 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2045 static int ohci_queue_iso_transmit(struct fw_iso_context
*base
,
2046 struct fw_iso_packet
*packet
,
2047 struct fw_iso_buffer
*buffer
,
2048 unsigned long payload
)
2050 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2051 struct descriptor
*d
, *last
, *pd
;
2052 struct fw_iso_packet
*p
;
2054 dma_addr_t d_bus
, page_bus
;
2055 u32 z
, header_z
, payload_z
, irq
;
2056 u32 payload_index
, payload_end_index
, next_page_index
;
2057 int page
, end_page
, i
, length
, offset
;
2060 * FIXME: Cycle lost behavior should be configurable: lose
2061 * packet, retransmit or terminate..
2065 payload_index
= payload
;
2071 if (p
->header_length
> 0)
2074 /* Determine the first page the payload isn't contained in. */
2075 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
2076 if (p
->payload_length
> 0)
2077 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
2083 /* Get header size in number of descriptors. */
2084 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof(*d
));
2086 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
2091 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
2092 d
[0].req_count
= cpu_to_le16(8);
2094 header
= (__le32
*) &d
[1];
2095 header
[0] = cpu_to_le32(IT_HEADER_SY(p
->sy
) |
2096 IT_HEADER_TAG(p
->tag
) |
2097 IT_HEADER_TCODE(TCODE_STREAM_DATA
) |
2098 IT_HEADER_CHANNEL(ctx
->base
.channel
) |
2099 IT_HEADER_SPEED(ctx
->base
.speed
));
2101 cpu_to_le32(IT_HEADER_DATA_LENGTH(p
->header_length
+
2102 p
->payload_length
));
2105 if (p
->header_length
> 0) {
2106 d
[2].req_count
= cpu_to_le16(p
->header_length
);
2107 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof(*d
));
2108 memcpy(&d
[z
], p
->header
, p
->header_length
);
2111 pd
= d
+ z
- payload_z
;
2112 payload_end_index
= payload_index
+ p
->payload_length
;
2113 for (i
= 0; i
< payload_z
; i
++) {
2114 page
= payload_index
>> PAGE_SHIFT
;
2115 offset
= payload_index
& ~PAGE_MASK
;
2116 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
2118 min(next_page_index
, payload_end_index
) - payload_index
;
2119 pd
[i
].req_count
= cpu_to_le16(length
);
2121 page_bus
= page_private(buffer
->pages
[page
]);
2122 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
2124 payload_index
+= length
;
2128 irq
= DESCRIPTOR_IRQ_ALWAYS
;
2130 irq
= DESCRIPTOR_NO_IRQ
;
2132 last
= z
== 2 ? d
: d
+ z
- 1;
2133 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
2135 DESCRIPTOR_BRANCH_ALWAYS
|
2138 context_append(&ctx
->context
, d
, z
, header_z
);
2143 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context
*base
,
2144 struct fw_iso_packet
*packet
,
2145 struct fw_iso_buffer
*buffer
,
2146 unsigned long payload
)
2148 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2149 struct db_descriptor
*db
= NULL
;
2150 struct descriptor
*d
;
2151 struct fw_iso_packet
*p
;
2152 dma_addr_t d_bus
, page_bus
;
2153 u32 z
, header_z
, length
, rest
;
2154 int page
, offset
, packet_count
, header_size
;
2157 * FIXME: Cycle lost behavior should be configurable: lose
2158 * packet, retransmit or terminate..
2165 * The OHCI controller puts the isochronous header and trailer in the
2166 * buffer, so we need at least 8 bytes.
2168 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
2169 header_size
= packet_count
* max(ctx
->base
.header_size
, (size_t)8);
2171 /* Get header size in number of descriptors. */
2172 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
2173 page
= payload
>> PAGE_SHIFT
;
2174 offset
= payload
& ~PAGE_MASK
;
2175 rest
= p
->payload_length
;
2177 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2179 d
= context_get_descriptors(&ctx
->context
,
2180 z
+ header_z
, &d_bus
);
2184 db
= (struct db_descriptor
*) d
;
2185 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2186 DESCRIPTOR_BRANCH_ALWAYS
);
2188 cpu_to_le16(max(ctx
->base
.header_size
, (size_t)8));
2189 if (p
->skip
&& rest
== p
->payload_length
) {
2190 db
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
2191 db
->first_req_count
= db
->first_size
;
2193 db
->first_req_count
= cpu_to_le16(header_size
);
2195 db
->first_res_count
= db
->first_req_count
;
2196 db
->first_buffer
= cpu_to_le32(d_bus
+ sizeof(*db
));
2198 if (p
->skip
&& rest
== p
->payload_length
)
2200 else if (offset
+ rest
< PAGE_SIZE
)
2203 length
= PAGE_SIZE
- offset
;
2205 db
->second_req_count
= cpu_to_le16(length
);
2206 db
->second_res_count
= db
->second_req_count
;
2207 page_bus
= page_private(buffer
->pages
[page
]);
2208 db
->second_buffer
= cpu_to_le32(page_bus
+ offset
);
2210 if (p
->interrupt
&& length
== rest
)
2211 db
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2213 context_append(&ctx
->context
, d
, z
, header_z
);
2214 offset
= (offset
+ length
) & ~PAGE_MASK
;
2223 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context
*base
,
2224 struct fw_iso_packet
*packet
,
2225 struct fw_iso_buffer
*buffer
,
2226 unsigned long payload
)
2228 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2229 struct descriptor
*d
= NULL
, *pd
= NULL
;
2230 struct fw_iso_packet
*p
= packet
;
2231 dma_addr_t d_bus
, page_bus
;
2232 u32 z
, header_z
, rest
;
2234 int page
, offset
, packet_count
, header_size
, payload_per_buffer
;
2237 * The OHCI controller puts the isochronous header and trailer in the
2238 * buffer, so we need at least 8 bytes.
2240 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
2241 header_size
= max(ctx
->base
.header_size
, (size_t)8);
2243 /* Get header size in number of descriptors. */
2244 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
2245 page
= payload
>> PAGE_SHIFT
;
2246 offset
= payload
& ~PAGE_MASK
;
2247 payload_per_buffer
= p
->payload_length
/ packet_count
;
2249 for (i
= 0; i
< packet_count
; i
++) {
2250 /* d points to the header descriptor */
2251 z
= DIV_ROUND_UP(payload_per_buffer
+ offset
, PAGE_SIZE
) + 1;
2252 d
= context_get_descriptors(&ctx
->context
,
2253 z
+ header_z
, &d_bus
);
2257 d
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2258 DESCRIPTOR_INPUT_MORE
);
2259 if (p
->skip
&& i
== 0)
2260 d
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
2261 d
->req_count
= cpu_to_le16(header_size
);
2262 d
->res_count
= d
->req_count
;
2263 d
->transfer_status
= 0;
2264 d
->data_address
= cpu_to_le32(d_bus
+ (z
* sizeof(*d
)));
2266 rest
= payload_per_buffer
;
2267 for (j
= 1; j
< z
; j
++) {
2269 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2270 DESCRIPTOR_INPUT_MORE
);
2272 if (offset
+ rest
< PAGE_SIZE
)
2275 length
= PAGE_SIZE
- offset
;
2276 pd
->req_count
= cpu_to_le16(length
);
2277 pd
->res_count
= pd
->req_count
;
2278 pd
->transfer_status
= 0;
2280 page_bus
= page_private(buffer
->pages
[page
]);
2281 pd
->data_address
= cpu_to_le32(page_bus
+ offset
);
2283 offset
= (offset
+ length
) & ~PAGE_MASK
;
2288 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2289 DESCRIPTOR_INPUT_LAST
|
2290 DESCRIPTOR_BRANCH_ALWAYS
);
2291 if (p
->interrupt
&& i
== packet_count
- 1)
2292 pd
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2294 context_append(&ctx
->context
, d
, z
, header_z
);
2300 static int ohci_queue_iso(struct fw_iso_context
*base
,
2301 struct fw_iso_packet
*packet
,
2302 struct fw_iso_buffer
*buffer
,
2303 unsigned long payload
)
2305 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2306 unsigned long flags
;
2309 spin_lock_irqsave(&ctx
->context
.ohci
->lock
, flags
);
2310 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
2311 ret
= ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
2312 else if (ctx
->context
.ohci
->use_dualbuffer
)
2313 ret
= ohci_queue_iso_receive_dualbuffer(base
, packet
,
2316 ret
= ohci_queue_iso_receive_packet_per_buffer(base
, packet
,
2318 spin_unlock_irqrestore(&ctx
->context
.ohci
->lock
, flags
);
2323 static const struct fw_card_driver ohci_driver
= {
2324 .enable
= ohci_enable
,
2325 .update_phy_reg
= ohci_update_phy_reg
,
2326 .set_config_rom
= ohci_set_config_rom
,
2327 .send_request
= ohci_send_request
,
2328 .send_response
= ohci_send_response
,
2329 .cancel_packet
= ohci_cancel_packet
,
2330 .enable_phys_dma
= ohci_enable_phys_dma
,
2331 .get_bus_time
= ohci_get_bus_time
,
2333 .allocate_iso_context
= ohci_allocate_iso_context
,
2334 .free_iso_context
= ohci_free_iso_context
,
2335 .queue_iso
= ohci_queue_iso
,
2336 .start_iso
= ohci_start_iso
,
2337 .stop_iso
= ohci_stop_iso
,
2340 #ifdef CONFIG_PPC_PMAC
2341 static void ohci_pmac_on(struct pci_dev
*dev
)
2343 if (machine_is(powermac
)) {
2344 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2347 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 1);
2348 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 1);
2353 static void ohci_pmac_off(struct pci_dev
*dev
)
2355 if (machine_is(powermac
)) {
2356 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2359 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 0);
2360 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 0);
2365 #define ohci_pmac_on(dev)
2366 #define ohci_pmac_off(dev)
2367 #endif /* CONFIG_PPC_PMAC */
2369 static int __devinit
pci_probe(struct pci_dev
*dev
,
2370 const struct pci_device_id
*ent
)
2372 struct fw_ohci
*ohci
;
2373 u32 bus_options
, max_receive
, link_speed
, version
;
2378 ohci
= kzalloc(sizeof(*ohci
), GFP_KERNEL
);
2384 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
2388 err
= pci_enable_device(dev
);
2390 fw_error("Failed to enable OHCI hardware\n");
2394 pci_set_master(dev
);
2395 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
2396 pci_set_drvdata(dev
, ohci
);
2398 spin_lock_init(&ohci
->lock
);
2400 tasklet_init(&ohci
->bus_reset_tasklet
,
2401 bus_reset_tasklet
, (unsigned long)ohci
);
2403 err
= pci_request_region(dev
, 0, ohci_driver_name
);
2405 fw_error("MMIO resource unavailable\n");
2409 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
2410 if (ohci
->registers
== NULL
) {
2411 fw_error("Failed to remap registers\n");
2416 version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
2417 ohci
->use_dualbuffer
= version
>= OHCI_VERSION_1_1
;
2419 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2420 #if !defined(CONFIG_X86_32)
2421 /* dual-buffer mode is broken with descriptor addresses above 2G */
2422 if (dev
->vendor
== PCI_VENDOR_ID_TI
&&
2423 dev
->device
== PCI_DEVICE_ID_TI_TSB43AB22
)
2424 ohci
->use_dualbuffer
= false;
2427 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2428 ohci
->old_uninorth
= dev
->vendor
== PCI_VENDOR_ID_APPLE
&&
2429 dev
->device
== PCI_DEVICE_ID_APPLE_UNI_N_FW
;
2431 ohci
->bus_reset_packet_quirk
= dev
->vendor
== PCI_VENDOR_ID_TI
;
2433 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
2434 OHCI1394_AsReqRcvContextControlSet
);
2436 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
2437 OHCI1394_AsRspRcvContextControlSet
);
2439 context_init(&ohci
->at_request_ctx
, ohci
,
2440 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
2442 context_init(&ohci
->at_response_ctx
, ohci
,
2443 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
2445 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
2446 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
2447 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
2448 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
2449 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
2451 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
2452 ohci
->ir_context_channels
= ~0ULL;
2453 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
2454 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
2455 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
2456 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
2458 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
2463 /* self-id dma buffer allocation */
2464 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
2468 if (ohci
->self_id_cpu
== NULL
) {
2473 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
2474 max_receive
= (bus_options
>> 12) & 0xf;
2475 link_speed
= bus_options
& 0x7;
2476 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
2477 reg_read(ohci
, OHCI1394_GUIDLo
);
2479 err
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
2483 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2484 dev_name(&dev
->dev
), version
>> 16, version
& 0xff);
2489 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2490 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2492 kfree(ohci
->ir_context_list
);
2493 kfree(ohci
->it_context_list
);
2494 context_release(&ohci
->at_response_ctx
);
2495 context_release(&ohci
->at_request_ctx
);
2496 ar_context_release(&ohci
->ar_response_ctx
);
2497 ar_context_release(&ohci
->ar_request_ctx
);
2498 pci_iounmap(dev
, ohci
->registers
);
2500 pci_release_region(dev
, 0);
2502 pci_disable_device(dev
);
2508 fw_error("Out of memory\n");
2513 static void pci_remove(struct pci_dev
*dev
)
2515 struct fw_ohci
*ohci
;
2517 ohci
= pci_get_drvdata(dev
);
2518 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
2520 fw_core_remove_card(&ohci
->card
);
2523 * FIXME: Fail all pending packets here, now that the upper
2524 * layers can't queue any more.
2527 software_reset(ohci
);
2528 free_irq(dev
->irq
, ohci
);
2530 if (ohci
->next_config_rom
&& ohci
->next_config_rom
!= ohci
->config_rom
)
2531 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
2532 ohci
->next_config_rom
, ohci
->next_config_rom_bus
);
2533 if (ohci
->config_rom
)
2534 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
2535 ohci
->config_rom
, ohci
->config_rom_bus
);
2536 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2537 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2538 ar_context_release(&ohci
->ar_request_ctx
);
2539 ar_context_release(&ohci
->ar_response_ctx
);
2540 context_release(&ohci
->at_request_ctx
);
2541 context_release(&ohci
->at_response_ctx
);
2542 kfree(ohci
->it_context_list
);
2543 kfree(ohci
->ir_context_list
);
2544 pci_iounmap(dev
, ohci
->registers
);
2545 pci_release_region(dev
, 0);
2546 pci_disable_device(dev
);
2550 fw_notify("Removed fw-ohci device.\n");
2554 static int pci_suspend(struct pci_dev
*dev
, pm_message_t state
)
2556 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2559 software_reset(ohci
);
2560 free_irq(dev
->irq
, ohci
);
2561 err
= pci_save_state(dev
);
2563 fw_error("pci_save_state failed\n");
2566 err
= pci_set_power_state(dev
, pci_choose_state(dev
, state
));
2568 fw_error("pci_set_power_state failed with %d\n", err
);
2574 static int pci_resume(struct pci_dev
*dev
)
2576 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2580 pci_set_power_state(dev
, PCI_D0
);
2581 pci_restore_state(dev
);
2582 err
= pci_enable_device(dev
);
2584 fw_error("pci_enable_device failed\n");
2588 return ohci_enable(&ohci
->card
, NULL
, 0);
2592 static struct pci_device_id pci_table
[] = {
2593 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
2597 MODULE_DEVICE_TABLE(pci
, pci_table
);
2599 static struct pci_driver fw_ohci_pci_driver
= {
2600 .name
= ohci_driver_name
,
2601 .id_table
= pci_table
,
2603 .remove
= pci_remove
,
2605 .resume
= pci_resume
,
2606 .suspend
= pci_suspend
,
2610 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2611 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2612 MODULE_LICENSE("GPL");
2614 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2615 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2616 MODULE_ALIAS("ohci1394");
2619 static int __init
fw_ohci_init(void)
2621 return pci_register_driver(&fw_ohci_pci_driver
);
2624 static void __exit
fw_ohci_cleanup(void)
2626 pci_unregister_driver(&fw_ohci_pci_driver
);
2629 module_init(fw_ohci_init
);
2630 module_exit(fw_ohci_cleanup
);