2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/bug.h>
22 #include <linux/compiler.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/firewire.h>
27 #include <linux/firewire-constants.h>
28 #include <linux/gfp.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/pci_ids.h>
39 #include <linux/spinlock.h>
40 #include <linux/string.h>
42 #include <asm/byteorder.h>
44 #include <asm/system.h>
46 #ifdef CONFIG_PPC_PMAC
47 #include <asm/pmac_feature.h>
53 #define DESCRIPTOR_OUTPUT_MORE 0
54 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
55 #define DESCRIPTOR_INPUT_MORE (2 << 12)
56 #define DESCRIPTOR_INPUT_LAST (3 << 12)
57 #define DESCRIPTOR_STATUS (1 << 11)
58 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
59 #define DESCRIPTOR_PING (1 << 7)
60 #define DESCRIPTOR_YY (1 << 6)
61 #define DESCRIPTOR_NO_IRQ (0 << 4)
62 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
63 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
64 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
65 #define DESCRIPTOR_WAIT (3 << 0)
71 __le32 branch_address
;
73 __le16 transfer_status
;
74 } __attribute__((aligned(16)));
76 #define CONTROL_SET(regs) (regs)
77 #define CONTROL_CLEAR(regs) ((regs) + 4)
78 #define COMMAND_PTR(regs) ((regs) + 12)
79 #define CONTEXT_MATCH(regs) ((regs) + 16)
82 struct descriptor descriptor
;
83 struct ar_buffer
*next
;
89 struct ar_buffer
*current_buffer
;
90 struct ar_buffer
*last_buffer
;
93 struct tasklet_struct tasklet
;
98 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
100 struct descriptor
*last
);
103 * A buffer that contains a block of DMA-able coherent memory used for
104 * storing a portion of a DMA descriptor program.
106 struct descriptor_buffer
{
107 struct list_head list
;
108 dma_addr_t buffer_bus
;
111 struct descriptor buffer
[0];
115 struct fw_ohci
*ohci
;
117 int total_allocation
;
120 * List of page-sized buffers for storing DMA descriptors.
121 * Head of list contains buffers in use and tail of list contains
124 struct list_head buffer_list
;
127 * Pointer to a buffer inside buffer_list that contains the tail
128 * end of the current DMA program.
130 struct descriptor_buffer
*buffer_tail
;
133 * The descriptor containing the branch address of the first
134 * descriptor that has not yet been filled by the device.
136 struct descriptor
*last
;
139 * The last descriptor in the DMA program. It contains the branch
140 * address that must be updated upon appending a new descriptor.
142 struct descriptor
*prev
;
144 descriptor_callback_t callback
;
146 struct tasklet_struct tasklet
;
149 #define IT_HEADER_SY(v) ((v) << 0)
150 #define IT_HEADER_TCODE(v) ((v) << 4)
151 #define IT_HEADER_CHANNEL(v) ((v) << 8)
152 #define IT_HEADER_TAG(v) ((v) << 14)
153 #define IT_HEADER_SPEED(v) ((v) << 16)
154 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
157 struct fw_iso_context base
;
158 struct context context
;
161 size_t header_length
;
164 #define CONFIG_ROM_SIZE 1024
169 __iomem
char *registers
;
172 int request_generation
; /* for timestamping incoming requests */
174 unsigned int pri_req_max
;
175 unsigned int features
;
180 * Spinlock for accessing fw_ohci data. Never call out of
181 * this driver with this lock held.
185 struct ar_context ar_request_ctx
;
186 struct ar_context ar_response_ctx
;
187 struct context at_request_ctx
;
188 struct context at_response_ctx
;
191 struct iso_context
*it_context_list
;
192 u64 ir_context_channels
;
194 struct iso_context
*ir_context_list
;
197 dma_addr_t config_rom_bus
;
198 __be32
*next_config_rom
;
199 dma_addr_t next_config_rom_bus
;
203 dma_addr_t self_id_bus
;
204 struct tasklet_struct bus_reset_tasklet
;
206 u32 self_id_buffer
[512];
209 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
211 return container_of(card
, struct fw_ohci
, card
);
214 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
215 #define IR_CONTEXT_BUFFER_FILL 0x80000000
216 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
217 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
218 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
219 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
221 #define CONTEXT_RUN 0x8000
222 #define CONTEXT_WAKE 0x1000
223 #define CONTEXT_DEAD 0x0800
224 #define CONTEXT_ACTIVE 0x0400
226 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
227 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
228 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
230 #define OHCI1394_REGISTER_SIZE 0x800
231 #define OHCI_LOOP_COUNT 500
232 #define OHCI1394_PCI_HCI_Control 0x40
233 #define SELF_ID_BUF_SIZE 0x800
234 #define OHCI_TCODE_PHY_PACKET 0x0e
235 #define OHCI_VERSION_1_1 0x010010
237 static char ohci_driver_name
[] = KBUILD_MODNAME
;
239 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
240 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
242 #define QUIRK_CYCLE_TIMER 1
243 #define QUIRK_RESET_PACKET 2
244 #define QUIRK_BE_HEADERS 4
245 #define QUIRK_NO_1394A 8
246 #define QUIRK_NO_MSI 16
248 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
249 static const struct {
250 unsigned short vendor
, device
, flags
;
252 {PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_TSB12LV22
, QUIRK_CYCLE_TIMER
|
255 {PCI_VENDOR_ID_TI
, PCI_ANY_ID
, QUIRK_RESET_PACKET
},
256 {PCI_VENDOR_ID_AL
, PCI_ANY_ID
, QUIRK_CYCLE_TIMER
},
257 {PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB38X_FW
, QUIRK_NO_MSI
},
258 {PCI_VENDOR_ID_NEC
, PCI_ANY_ID
, QUIRK_CYCLE_TIMER
},
259 {PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, QUIRK_CYCLE_TIMER
},
260 {PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_FW
, QUIRK_BE_HEADERS
},
263 /* This overrides anything that was found in ohci_quirks[]. */
264 static int param_quirks
;
265 module_param_named(quirks
, param_quirks
, int, 0644);
266 MODULE_PARM_DESC(quirks
, "Chip quirks (default = 0"
267 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER
)
268 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET
)
269 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS
)
270 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A
)
271 ", disable MSI = " __stringify(QUIRK_NO_MSI
)
274 #define OHCI_PARAM_DEBUG_AT_AR 1
275 #define OHCI_PARAM_DEBUG_SELFIDS 2
276 #define OHCI_PARAM_DEBUG_IRQS 4
277 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
279 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
281 static int param_debug
;
282 module_param_named(debug
, param_debug
, int, 0644);
283 MODULE_PARM_DESC(debug
, "Verbose logging (default = 0"
284 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR
)
285 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS
)
286 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS
)
287 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS
)
288 ", or a combination, or all = -1)");
290 static void log_irqs(u32 evt
)
292 if (likely(!(param_debug
&
293 (OHCI_PARAM_DEBUG_IRQS
| OHCI_PARAM_DEBUG_BUSRESETS
))))
296 if (!(param_debug
& OHCI_PARAM_DEBUG_IRQS
) &&
297 !(evt
& OHCI1394_busReset
))
300 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt
,
301 evt
& OHCI1394_selfIDComplete
? " selfID" : "",
302 evt
& OHCI1394_RQPkt
? " AR_req" : "",
303 evt
& OHCI1394_RSPkt
? " AR_resp" : "",
304 evt
& OHCI1394_reqTxComplete
? " AT_req" : "",
305 evt
& OHCI1394_respTxComplete
? " AT_resp" : "",
306 evt
& OHCI1394_isochRx
? " IR" : "",
307 evt
& OHCI1394_isochTx
? " IT" : "",
308 evt
& OHCI1394_postedWriteErr
? " postedWriteErr" : "",
309 evt
& OHCI1394_cycleTooLong
? " cycleTooLong" : "",
310 evt
& OHCI1394_cycle64Seconds
? " cycle64Seconds" : "",
311 evt
& OHCI1394_cycleInconsistent
? " cycleInconsistent" : "",
312 evt
& OHCI1394_regAccessFail
? " regAccessFail" : "",
313 evt
& OHCI1394_busReset
? " busReset" : "",
314 evt
& ~(OHCI1394_selfIDComplete
| OHCI1394_RQPkt
|
315 OHCI1394_RSPkt
| OHCI1394_reqTxComplete
|
316 OHCI1394_respTxComplete
| OHCI1394_isochRx
|
317 OHCI1394_isochTx
| OHCI1394_postedWriteErr
|
318 OHCI1394_cycleTooLong
| OHCI1394_cycle64Seconds
|
319 OHCI1394_cycleInconsistent
|
320 OHCI1394_regAccessFail
| OHCI1394_busReset
)
324 static const char *speed
[] = {
325 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
327 static const char *power
[] = {
328 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
329 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
331 static const char port
[] = { '.', '-', 'p', 'c', };
333 static char _p(u32
*s
, int shift
)
335 return port
[*s
>> shift
& 3];
338 static void log_selfids(int node_id
, int generation
, int self_id_count
, u32
*s
)
340 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_SELFIDS
)))
343 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
344 self_id_count
, generation
, node_id
);
346 for (; self_id_count
--; ++s
)
347 if ((*s
& 1 << 23) == 0)
348 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
349 "%s gc=%d %s %s%s%s\n",
350 *s
, *s
>> 24 & 63, _p(s
, 6), _p(s
, 4), _p(s
, 2),
351 speed
[*s
>> 14 & 3], *s
>> 16 & 63,
352 power
[*s
>> 8 & 7], *s
>> 22 & 1 ? "L" : "",
353 *s
>> 11 & 1 ? "c" : "", *s
& 2 ? "i" : "");
355 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
357 _p(s
, 16), _p(s
, 14), _p(s
, 12), _p(s
, 10),
358 _p(s
, 8), _p(s
, 6), _p(s
, 4), _p(s
, 2));
361 static const char *evts
[] = {
362 [0x00] = "evt_no_status", [0x01] = "-reserved-",
363 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
364 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
365 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
366 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
367 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
368 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
369 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
370 [0x10] = "-reserved-", [0x11] = "ack_complete",
371 [0x12] = "ack_pending ", [0x13] = "-reserved-",
372 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
373 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
374 [0x18] = "-reserved-", [0x19] = "-reserved-",
375 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
376 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
377 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
378 [0x20] = "pending/cancelled",
380 static const char *tcodes
[] = {
381 [0x0] = "QW req", [0x1] = "BW req",
382 [0x2] = "W resp", [0x3] = "-reserved-",
383 [0x4] = "QR req", [0x5] = "BR req",
384 [0x6] = "QR resp", [0x7] = "BR resp",
385 [0x8] = "cycle start", [0x9] = "Lk req",
386 [0xa] = "async stream packet", [0xb] = "Lk resp",
387 [0xc] = "-reserved-", [0xd] = "-reserved-",
388 [0xe] = "link internal", [0xf] = "-reserved-",
390 static const char *phys
[] = {
391 [0x0] = "phy config packet", [0x1] = "link-on packet",
392 [0x2] = "self-id packet", [0x3] = "-reserved-",
395 static void log_ar_at_event(char dir
, int speed
, u32
*header
, int evt
)
397 int tcode
= header
[0] >> 4 & 0xf;
400 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_AT_AR
)))
403 if (unlikely(evt
>= ARRAY_SIZE(evts
)))
406 if (evt
== OHCI1394_evt_bus_reset
) {
407 fw_notify("A%c evt_bus_reset, generation %d\n",
408 dir
, (header
[2] >> 16) & 0xff);
412 if (header
[0] == ~header
[1]) {
413 fw_notify("A%c %s, %s, %08x\n",
414 dir
, evts
[evt
], phys
[header
[0] >> 30 & 0x3], header
[0]);
419 case 0x0: case 0x6: case 0x8:
420 snprintf(specific
, sizeof(specific
), " = %08x",
421 be32_to_cpu((__force __be32
)header
[3]));
423 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
424 snprintf(specific
, sizeof(specific
), " %x,%x",
425 header
[3] >> 16, header
[3] & 0xffff);
433 fw_notify("A%c %s, %s\n", dir
, evts
[evt
], tcodes
[tcode
]);
435 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
436 fw_notify("A%c spd %x tl %02x, "
439 dir
, speed
, header
[0] >> 10 & 0x3f,
440 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
441 tcodes
[tcode
], header
[1] & 0xffff, header
[2], specific
);
444 fw_notify("A%c spd %x tl %02x, "
447 dir
, speed
, header
[0] >> 10 & 0x3f,
448 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
449 tcodes
[tcode
], specific
);
455 #define param_debug 0
456 static inline void log_irqs(u32 evt
) {}
457 static inline void log_selfids(int node_id
, int generation
, int self_id_count
, u32
*s
) {}
458 static inline void log_ar_at_event(char dir
, int speed
, u32
*header
, int evt
) {}
460 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
462 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
464 writel(data
, ohci
->registers
+ offset
);
467 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
469 return readl(ohci
->registers
+ offset
);
472 static inline void flush_writes(const struct fw_ohci
*ohci
)
474 /* Do a dummy read to flush writes. */
475 reg_read(ohci
, OHCI1394_Version
);
478 static int read_phy_reg(struct fw_ohci
*ohci
, int addr
)
483 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
484 for (i
= 0; i
< 3 + 100; i
++) {
485 val
= reg_read(ohci
, OHCI1394_PhyControl
);
486 if (val
& OHCI1394_PhyControl_ReadDone
)
487 return OHCI1394_PhyControl_ReadData(val
);
490 * Try a few times without waiting. Sleeping is necessary
491 * only when the link/PHY interface is busy.
496 fw_error("failed to read phy reg\n");
501 static int write_phy_reg(const struct fw_ohci
*ohci
, int addr
, u32 val
)
505 reg_write(ohci
, OHCI1394_PhyControl
,
506 OHCI1394_PhyControl_Write(addr
, val
));
507 for (i
= 0; i
< 3 + 100; i
++) {
508 val
= reg_read(ohci
, OHCI1394_PhyControl
);
509 if (!(val
& OHCI1394_PhyControl_WritePending
))
515 fw_error("failed to write phy reg\n");
520 static int ohci_update_phy_reg(struct fw_card
*card
, int addr
,
521 int clear_bits
, int set_bits
)
523 struct fw_ohci
*ohci
= fw_ohci(card
);
526 ret
= read_phy_reg(ohci
, addr
);
531 * The interrupt status bits are cleared by writing a one bit.
532 * Avoid clearing them unless explicitly requested in set_bits.
535 clear_bits
|= PHY_INT_STATUS_BITS
;
537 return write_phy_reg(ohci
, addr
, (ret
& ~clear_bits
) | set_bits
);
540 static int read_paged_phy_reg(struct fw_ohci
*ohci
, int page
, int addr
)
544 ret
= ohci_update_phy_reg(&ohci
->card
, 7, PHY_PAGE_SELECT
, page
<< 5);
548 return read_phy_reg(ohci
, addr
);
551 static int ar_context_add_page(struct ar_context
*ctx
)
553 struct device
*dev
= ctx
->ohci
->card
.device
;
554 struct ar_buffer
*ab
;
555 dma_addr_t
uninitialized_var(ab_bus
);
558 ab
= dma_alloc_coherent(dev
, PAGE_SIZE
, &ab_bus
, GFP_ATOMIC
);
563 memset(&ab
->descriptor
, 0, sizeof(ab
->descriptor
));
564 ab
->descriptor
.control
= cpu_to_le16(DESCRIPTOR_INPUT_MORE
|
566 DESCRIPTOR_BRANCH_ALWAYS
);
567 offset
= offsetof(struct ar_buffer
, data
);
568 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
569 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
570 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
571 ab
->descriptor
.branch_address
= 0;
573 ctx
->last_buffer
->descriptor
.branch_address
= cpu_to_le32(ab_bus
| 1);
574 ctx
->last_buffer
->next
= ab
;
575 ctx
->last_buffer
= ab
;
577 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
578 flush_writes(ctx
->ohci
);
583 static void ar_context_release(struct ar_context
*ctx
)
585 struct ar_buffer
*ab
, *ab_next
;
589 for (ab
= ctx
->current_buffer
; ab
; ab
= ab_next
) {
591 offset
= offsetof(struct ar_buffer
, data
);
592 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
593 dma_free_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
598 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
599 #define cond_le32_to_cpu(v) \
600 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
602 #define cond_le32_to_cpu(v) le32_to_cpu(v)
605 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
607 struct fw_ohci
*ohci
= ctx
->ohci
;
609 u32 status
, length
, tcode
;
612 p
.header
[0] = cond_le32_to_cpu(buffer
[0]);
613 p
.header
[1] = cond_le32_to_cpu(buffer
[1]);
614 p
.header
[2] = cond_le32_to_cpu(buffer
[2]);
616 tcode
= (p
.header
[0] >> 4) & 0x0f;
618 case TCODE_WRITE_QUADLET_REQUEST
:
619 case TCODE_READ_QUADLET_RESPONSE
:
620 p
.header
[3] = (__force __u32
) buffer
[3];
621 p
.header_length
= 16;
622 p
.payload_length
= 0;
625 case TCODE_READ_BLOCK_REQUEST
:
626 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
627 p
.header_length
= 16;
628 p
.payload_length
= 0;
631 case TCODE_WRITE_BLOCK_REQUEST
:
632 case TCODE_READ_BLOCK_RESPONSE
:
633 case TCODE_LOCK_REQUEST
:
634 case TCODE_LOCK_RESPONSE
:
635 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
636 p
.header_length
= 16;
637 p
.payload_length
= p
.header
[3] >> 16;
640 case TCODE_WRITE_RESPONSE
:
641 case TCODE_READ_QUADLET_REQUEST
:
642 case OHCI_TCODE_PHY_PACKET
:
643 p
.header_length
= 12;
644 p
.payload_length
= 0;
648 /* FIXME: Stop context, discard everything, and restart? */
650 p
.payload_length
= 0;
653 p
.payload
= (void *) buffer
+ p
.header_length
;
655 /* FIXME: What to do about evt_* errors? */
656 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
657 status
= cond_le32_to_cpu(buffer
[length
]);
658 evt
= (status
>> 16) & 0x1f;
661 p
.speed
= (status
>> 21) & 0x7;
662 p
.timestamp
= status
& 0xffff;
663 p
.generation
= ohci
->request_generation
;
665 log_ar_at_event('R', p
.speed
, p
.header
, evt
);
668 * The OHCI bus reset handler synthesizes a phy packet with
669 * the new generation number when a bus reset happens (see
670 * section 8.4.2.3). This helps us determine when a request
671 * was received and make sure we send the response in the same
672 * generation. We only need this for requests; for responses
673 * we use the unique tlabel for finding the matching
676 * Alas some chips sometimes emit bus reset packets with a
677 * wrong generation. We set the correct generation for these
678 * at a slightly incorrect time (in bus_reset_tasklet).
680 if (evt
== OHCI1394_evt_bus_reset
) {
681 if (!(ohci
->quirks
& QUIRK_RESET_PACKET
))
682 ohci
->request_generation
= (p
.header
[2] >> 16) & 0xff;
683 } else if (ctx
== &ohci
->ar_request_ctx
) {
684 fw_core_handle_request(&ohci
->card
, &p
);
686 fw_core_handle_response(&ohci
->card
, &p
);
689 return buffer
+ length
+ 1;
692 static void ar_context_tasklet(unsigned long data
)
694 struct ar_context
*ctx
= (struct ar_context
*)data
;
695 struct fw_ohci
*ohci
= ctx
->ohci
;
696 struct ar_buffer
*ab
;
697 struct descriptor
*d
;
700 ab
= ctx
->current_buffer
;
703 if (d
->res_count
== 0) {
704 size_t size
, rest
, offset
;
705 dma_addr_t start_bus
;
709 * This descriptor is finished and we may have a
710 * packet split across this and the next buffer. We
711 * reuse the page for reassembling the split packet.
714 offset
= offsetof(struct ar_buffer
, data
);
716 start_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
720 size
= buffer
+ PAGE_SIZE
- ctx
->pointer
;
721 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
722 memmove(buffer
, ctx
->pointer
, size
);
723 memcpy(buffer
+ size
, ab
->data
, rest
);
724 ctx
->current_buffer
= ab
;
725 ctx
->pointer
= (void *) ab
->data
+ rest
;
726 end
= buffer
+ size
+ rest
;
729 buffer
= handle_ar_packet(ctx
, buffer
);
731 dma_free_coherent(ohci
->card
.device
, PAGE_SIZE
,
733 ar_context_add_page(ctx
);
735 buffer
= ctx
->pointer
;
737 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
740 buffer
= handle_ar_packet(ctx
, buffer
);
744 static int ar_context_init(struct ar_context
*ctx
,
745 struct fw_ohci
*ohci
, u32 regs
)
751 ctx
->last_buffer
= &ab
;
752 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
754 ar_context_add_page(ctx
);
755 ar_context_add_page(ctx
);
756 ctx
->current_buffer
= ab
.next
;
757 ctx
->pointer
= ctx
->current_buffer
->data
;
762 static void ar_context_run(struct ar_context
*ctx
)
764 struct ar_buffer
*ab
= ctx
->current_buffer
;
768 offset
= offsetof(struct ar_buffer
, data
);
769 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
771 reg_write(ctx
->ohci
, COMMAND_PTR(ctx
->regs
), ab_bus
| 1);
772 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
);
773 flush_writes(ctx
->ohci
);
776 static struct descriptor
*find_branch_descriptor(struct descriptor
*d
, int z
)
780 b
= (le16_to_cpu(d
->control
) & DESCRIPTOR_BRANCH_ALWAYS
) >> 2;
781 key
= (le16_to_cpu(d
->control
) & DESCRIPTOR_KEY_IMMEDIATE
) >> 8;
783 /* figure out which descriptor the branch address goes in */
784 if (z
== 2 && (b
== 3 || key
== 2))
790 static void context_tasklet(unsigned long data
)
792 struct context
*ctx
= (struct context
*) data
;
793 struct descriptor
*d
, *last
;
796 struct descriptor_buffer
*desc
;
798 desc
= list_entry(ctx
->buffer_list
.next
,
799 struct descriptor_buffer
, list
);
801 while (last
->branch_address
!= 0) {
802 struct descriptor_buffer
*old_desc
= desc
;
803 address
= le32_to_cpu(last
->branch_address
);
807 /* If the branch address points to a buffer outside of the
808 * current buffer, advance to the next buffer. */
809 if (address
< desc
->buffer_bus
||
810 address
>= desc
->buffer_bus
+ desc
->used
)
811 desc
= list_entry(desc
->list
.next
,
812 struct descriptor_buffer
, list
);
813 d
= desc
->buffer
+ (address
- desc
->buffer_bus
) / sizeof(*d
);
814 last
= find_branch_descriptor(d
, z
);
816 if (!ctx
->callback(ctx
, d
, last
))
819 if (old_desc
!= desc
) {
820 /* If we've advanced to the next buffer, move the
821 * previous buffer to the free list. */
824 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
825 list_move_tail(&old_desc
->list
, &ctx
->buffer_list
);
826 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
833 * Allocate a new buffer and add it to the list of free buffers for this
834 * context. Must be called with ohci->lock held.
836 static int context_add_buffer(struct context
*ctx
)
838 struct descriptor_buffer
*desc
;
839 dma_addr_t
uninitialized_var(bus_addr
);
843 * 16MB of descriptors should be far more than enough for any DMA
844 * program. This will catch run-away userspace or DoS attacks.
846 if (ctx
->total_allocation
>= 16*1024*1024)
849 desc
= dma_alloc_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
850 &bus_addr
, GFP_ATOMIC
);
854 offset
= (void *)&desc
->buffer
- (void *)desc
;
855 desc
->buffer_size
= PAGE_SIZE
- offset
;
856 desc
->buffer_bus
= bus_addr
+ offset
;
859 list_add_tail(&desc
->list
, &ctx
->buffer_list
);
860 ctx
->total_allocation
+= PAGE_SIZE
;
865 static int context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
866 u32 regs
, descriptor_callback_t callback
)
870 ctx
->total_allocation
= 0;
872 INIT_LIST_HEAD(&ctx
->buffer_list
);
873 if (context_add_buffer(ctx
) < 0)
876 ctx
->buffer_tail
= list_entry(ctx
->buffer_list
.next
,
877 struct descriptor_buffer
, list
);
879 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
880 ctx
->callback
= callback
;
883 * We put a dummy descriptor in the buffer that has a NULL
884 * branch address and looks like it's been sent. That way we
885 * have a descriptor to append DMA programs to.
887 memset(ctx
->buffer_tail
->buffer
, 0, sizeof(*ctx
->buffer_tail
->buffer
));
888 ctx
->buffer_tail
->buffer
->control
= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
);
889 ctx
->buffer_tail
->buffer
->transfer_status
= cpu_to_le16(0x8011);
890 ctx
->buffer_tail
->used
+= sizeof(*ctx
->buffer_tail
->buffer
);
891 ctx
->last
= ctx
->buffer_tail
->buffer
;
892 ctx
->prev
= ctx
->buffer_tail
->buffer
;
897 static void context_release(struct context
*ctx
)
899 struct fw_card
*card
= &ctx
->ohci
->card
;
900 struct descriptor_buffer
*desc
, *tmp
;
902 list_for_each_entry_safe(desc
, tmp
, &ctx
->buffer_list
, list
)
903 dma_free_coherent(card
->device
, PAGE_SIZE
, desc
,
905 ((void *)&desc
->buffer
- (void *)desc
));
908 /* Must be called with ohci->lock held */
909 static struct descriptor
*context_get_descriptors(struct context
*ctx
,
910 int z
, dma_addr_t
*d_bus
)
912 struct descriptor
*d
= NULL
;
913 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
915 if (z
* sizeof(*d
) > desc
->buffer_size
)
918 if (z
* sizeof(*d
) > desc
->buffer_size
- desc
->used
) {
919 /* No room for the descriptor in this buffer, so advance to the
922 if (desc
->list
.next
== &ctx
->buffer_list
) {
923 /* If there is no free buffer next in the list,
925 if (context_add_buffer(ctx
) < 0)
928 desc
= list_entry(desc
->list
.next
,
929 struct descriptor_buffer
, list
);
930 ctx
->buffer_tail
= desc
;
933 d
= desc
->buffer
+ desc
->used
/ sizeof(*d
);
934 memset(d
, 0, z
* sizeof(*d
));
935 *d_bus
= desc
->buffer_bus
+ desc
->used
;
940 static void context_run(struct context
*ctx
, u32 extra
)
942 struct fw_ohci
*ohci
= ctx
->ohci
;
944 reg_write(ohci
, COMMAND_PTR(ctx
->regs
),
945 le32_to_cpu(ctx
->last
->branch_address
));
946 reg_write(ohci
, CONTROL_CLEAR(ctx
->regs
), ~0);
947 reg_write(ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
| extra
);
951 static void context_append(struct context
*ctx
,
952 struct descriptor
*d
, int z
, int extra
)
955 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
957 d_bus
= desc
->buffer_bus
+ (d
- desc
->buffer
) * sizeof(*d
);
959 desc
->used
+= (z
+ extra
) * sizeof(*d
);
960 ctx
->prev
->branch_address
= cpu_to_le32(d_bus
| z
);
961 ctx
->prev
= find_branch_descriptor(d
, z
);
963 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
964 flush_writes(ctx
->ohci
);
967 static void context_stop(struct context
*ctx
)
972 reg_write(ctx
->ohci
, CONTROL_CLEAR(ctx
->regs
), CONTEXT_RUN
);
973 flush_writes(ctx
->ohci
);
975 for (i
= 0; i
< 10; i
++) {
976 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
977 if ((reg
& CONTEXT_ACTIVE
) == 0)
982 fw_error("Error: DMA context still active (0x%08x)\n", reg
);
986 struct fw_packet
*packet
;
990 * This function apppends a packet to the DMA queue for transmission.
991 * Must always be called with the ochi->lock held to ensure proper
992 * generation handling and locking around packet queue manipulation.
994 static int at_context_queue_packet(struct context
*ctx
,
995 struct fw_packet
*packet
)
997 struct fw_ohci
*ohci
= ctx
->ohci
;
998 dma_addr_t d_bus
, uninitialized_var(payload_bus
);
999 struct driver_data
*driver_data
;
1000 struct descriptor
*d
, *last
;
1005 d
= context_get_descriptors(ctx
, 4, &d_bus
);
1007 packet
->ack
= RCODE_SEND_ERROR
;
1011 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
1012 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
1015 * The DMA format for asyncronous link packets is different
1016 * from the IEEE1394 layout, so shift the fields around
1017 * accordingly. If header_length is 8, it's a PHY packet, to
1018 * which we need to prepend an extra quadlet.
1021 header
= (__le32
*) &d
[1];
1022 switch (packet
->header_length
) {
1025 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
1026 (packet
->speed
<< 16));
1027 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
1028 (packet
->header
[0] & 0xffff0000));
1029 header
[2] = cpu_to_le32(packet
->header
[2]);
1031 tcode
= (packet
->header
[0] >> 4) & 0x0f;
1032 if (TCODE_IS_BLOCK_PACKET(tcode
))
1033 header
[3] = cpu_to_le32(packet
->header
[3]);
1035 header
[3] = (__force __le32
) packet
->header
[3];
1037 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
1041 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
1042 (packet
->speed
<< 16));
1043 header
[1] = cpu_to_le32(packet
->header
[0]);
1044 header
[2] = cpu_to_le32(packet
->header
[1]);
1045 d
[0].req_count
= cpu_to_le16(12);
1049 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
1050 (packet
->speed
<< 16));
1051 header
[1] = cpu_to_le32(packet
->header
[0] & 0xffff0000);
1052 d
[0].req_count
= cpu_to_le16(8);
1057 packet
->ack
= RCODE_SEND_ERROR
;
1061 driver_data
= (struct driver_data
*) &d
[3];
1062 driver_data
->packet
= packet
;
1063 packet
->driver_data
= driver_data
;
1065 if (packet
->payload_length
> 0) {
1067 dma_map_single(ohci
->card
.device
, packet
->payload
,
1068 packet
->payload_length
, DMA_TO_DEVICE
);
1069 if (dma_mapping_error(ohci
->card
.device
, payload_bus
)) {
1070 packet
->ack
= RCODE_SEND_ERROR
;
1073 packet
->payload_bus
= payload_bus
;
1074 packet
->payload_mapped
= true;
1076 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
1077 d
[2].data_address
= cpu_to_le32(payload_bus
);
1085 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
1086 DESCRIPTOR_IRQ_ALWAYS
|
1087 DESCRIPTOR_BRANCH_ALWAYS
);
1090 * If the controller and packet generations don't match, we need to
1091 * bail out and try again. If IntEvent.busReset is set, the AT context
1092 * is halted, so appending to the context and trying to run it is
1093 * futile. Most controllers do the right thing and just flush the AT
1094 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1095 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1096 * up stalling out. So we just bail out in software and try again
1097 * later, and everyone is happy.
1098 * FIXME: Document how the locking works.
1100 if (ohci
->generation
!= packet
->generation
||
1101 reg_read(ohci
, OHCI1394_IntEventSet
) & OHCI1394_busReset
) {
1102 if (packet
->payload_mapped
)
1103 dma_unmap_single(ohci
->card
.device
, payload_bus
,
1104 packet
->payload_length
, DMA_TO_DEVICE
);
1105 packet
->ack
= RCODE_GENERATION
;
1109 context_append(ctx
, d
, z
, 4 - z
);
1111 /* If the context isn't already running, start it up. */
1112 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
1113 if ((reg
& CONTEXT_RUN
) == 0)
1114 context_run(ctx
, 0);
1119 static int handle_at_packet(struct context
*context
,
1120 struct descriptor
*d
,
1121 struct descriptor
*last
)
1123 struct driver_data
*driver_data
;
1124 struct fw_packet
*packet
;
1125 struct fw_ohci
*ohci
= context
->ohci
;
1128 if (last
->transfer_status
== 0)
1129 /* This descriptor isn't done yet, stop iteration. */
1132 driver_data
= (struct driver_data
*) &d
[3];
1133 packet
= driver_data
->packet
;
1135 /* This packet was cancelled, just continue. */
1138 if (packet
->payload_mapped
)
1139 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1140 packet
->payload_length
, DMA_TO_DEVICE
);
1142 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
1143 packet
->timestamp
= le16_to_cpu(last
->res_count
);
1145 log_ar_at_event('T', packet
->speed
, packet
->header
, evt
);
1148 case OHCI1394_evt_timeout
:
1149 /* Async response transmit timed out. */
1150 packet
->ack
= RCODE_CANCELLED
;
1153 case OHCI1394_evt_flushed
:
1155 * The packet was flushed should give same error as
1156 * when we try to use a stale generation count.
1158 packet
->ack
= RCODE_GENERATION
;
1161 case OHCI1394_evt_missing_ack
:
1163 * Using a valid (current) generation count, but the
1164 * node is not on the bus or not sending acks.
1166 packet
->ack
= RCODE_NO_ACK
;
1169 case ACK_COMPLETE
+ 0x10:
1170 case ACK_PENDING
+ 0x10:
1171 case ACK_BUSY_X
+ 0x10:
1172 case ACK_BUSY_A
+ 0x10:
1173 case ACK_BUSY_B
+ 0x10:
1174 case ACK_DATA_ERROR
+ 0x10:
1175 case ACK_TYPE_ERROR
+ 0x10:
1176 packet
->ack
= evt
- 0x10;
1180 packet
->ack
= RCODE_SEND_ERROR
;
1184 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1189 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1190 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1191 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1192 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1193 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1195 static void handle_local_rom(struct fw_ohci
*ohci
,
1196 struct fw_packet
*packet
, u32 csr
)
1198 struct fw_packet response
;
1199 int tcode
, length
, i
;
1201 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1202 if (TCODE_IS_BLOCK_PACKET(tcode
))
1203 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1207 i
= csr
- CSR_CONFIG_ROM
;
1208 if (i
+ length
> CONFIG_ROM_SIZE
) {
1209 fw_fill_response(&response
, packet
->header
,
1210 RCODE_ADDRESS_ERROR
, NULL
, 0);
1211 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
1212 fw_fill_response(&response
, packet
->header
,
1213 RCODE_TYPE_ERROR
, NULL
, 0);
1215 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
1216 (void *) ohci
->config_rom
+ i
, length
);
1219 fw_core_handle_response(&ohci
->card
, &response
);
1222 static void handle_local_lock(struct fw_ohci
*ohci
,
1223 struct fw_packet
*packet
, u32 csr
)
1225 struct fw_packet response
;
1226 int tcode
, length
, ext_tcode
, sel
;
1227 __be32
*payload
, lock_old
;
1228 u32 lock_arg
, lock_data
;
1230 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1231 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1232 payload
= packet
->payload
;
1233 ext_tcode
= HEADER_GET_EXTENDED_TCODE(packet
->header
[3]);
1235 if (tcode
== TCODE_LOCK_REQUEST
&&
1236 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
1237 lock_arg
= be32_to_cpu(payload
[0]);
1238 lock_data
= be32_to_cpu(payload
[1]);
1239 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
1243 fw_fill_response(&response
, packet
->header
,
1244 RCODE_TYPE_ERROR
, NULL
, 0);
1248 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
1249 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
1250 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
1251 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
1253 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
1254 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
1256 fw_notify("swap not done yet\n");
1258 fw_fill_response(&response
, packet
->header
,
1259 RCODE_COMPLETE
, &lock_old
, sizeof(lock_old
));
1261 fw_core_handle_response(&ohci
->card
, &response
);
1264 static void handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
1269 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
1270 packet
->ack
= ACK_PENDING
;
1271 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1275 ((unsigned long long)
1276 HEADER_GET_OFFSET_HIGH(packet
->header
[1]) << 32) |
1278 csr
= offset
- CSR_REGISTER_BASE
;
1280 /* Handle config rom reads. */
1281 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
1282 handle_local_rom(ctx
->ohci
, packet
, csr
);
1284 case CSR_BUS_MANAGER_ID
:
1285 case CSR_BANDWIDTH_AVAILABLE
:
1286 case CSR_CHANNELS_AVAILABLE_HI
:
1287 case CSR_CHANNELS_AVAILABLE_LO
:
1288 handle_local_lock(ctx
->ohci
, packet
, csr
);
1291 if (ctx
== &ctx
->ohci
->at_request_ctx
)
1292 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
1294 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
1298 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
1299 packet
->ack
= ACK_COMPLETE
;
1300 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1304 static void at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
1306 unsigned long flags
;
1309 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
1311 if (HEADER_GET_DESTINATION(packet
->header
[0]) == ctx
->ohci
->node_id
&&
1312 ctx
->ohci
->generation
== packet
->generation
) {
1313 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1314 handle_local_request(ctx
, packet
);
1318 ret
= at_context_queue_packet(ctx
, packet
);
1319 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1322 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1326 static u32
cycle_timer_ticks(u32 cycle_timer
)
1330 ticks
= cycle_timer
& 0xfff;
1331 ticks
+= 3072 * ((cycle_timer
>> 12) & 0x1fff);
1332 ticks
+= (3072 * 8000) * (cycle_timer
>> 25);
1338 * Some controllers exhibit one or more of the following bugs when updating the
1339 * iso cycle timer register:
1340 * - When the lowest six bits are wrapping around to zero, a read that happens
1341 * at the same time will return garbage in the lowest ten bits.
1342 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1343 * not incremented for about 60 ns.
1344 * - Occasionally, the entire register reads zero.
1346 * To catch these, we read the register three times and ensure that the
1347 * difference between each two consecutive reads is approximately the same, i.e.
1348 * less than twice the other. Furthermore, any negative difference indicates an
1349 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1350 * execute, so we have enough precision to compute the ratio of the differences.)
1352 static u32
get_cycle_time(struct fw_ohci
*ohci
)
1359 c2
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1361 if (ohci
->quirks
& QUIRK_CYCLE_TIMER
) {
1364 c2
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1368 c2
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1369 t0
= cycle_timer_ticks(c0
);
1370 t1
= cycle_timer_ticks(c1
);
1371 t2
= cycle_timer_ticks(c2
);
1374 } while ((diff01
<= 0 || diff12
<= 0 ||
1375 diff01
/ diff12
>= 2 || diff12
/ diff01
>= 2)
1383 * This function has to be called at least every 64 seconds. The bus_time
1384 * field stores not only the upper 25 bits of the BUS_TIME register but also
1385 * the most significant bit of the cycle timer in bit 6 so that we can detect
1386 * changes in this bit.
1388 static u32
update_bus_time(struct fw_ohci
*ohci
)
1390 u32 cycle_time_seconds
= get_cycle_time(ohci
) >> 25;
1392 if ((ohci
->bus_time
& 0x40) != (cycle_time_seconds
& 0x40))
1393 ohci
->bus_time
+= 0x40;
1395 return ohci
->bus_time
| cycle_time_seconds
;
1398 static void bus_reset_tasklet(unsigned long data
)
1400 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
1401 int self_id_count
, i
, j
, reg
;
1402 int generation
, new_generation
;
1403 unsigned long flags
;
1404 void *free_rom
= NULL
;
1405 dma_addr_t free_rom_bus
= 0;
1408 reg
= reg_read(ohci
, OHCI1394_NodeID
);
1409 if (!(reg
& OHCI1394_NodeID_idValid
)) {
1410 fw_notify("node ID not valid, new bus reset in progress\n");
1413 if ((reg
& OHCI1394_NodeID_nodeNumber
) == 63) {
1414 fw_notify("malconfigured bus\n");
1417 ohci
->node_id
= reg
& (OHCI1394_NodeID_busNumber
|
1418 OHCI1394_NodeID_nodeNumber
);
1420 is_new_root
= (reg
& OHCI1394_NodeID_root
) != 0;
1421 if (!(ohci
->is_root
&& is_new_root
))
1422 reg_write(ohci
, OHCI1394_LinkControlSet
,
1423 OHCI1394_LinkControl_cycleMaster
);
1424 ohci
->is_root
= is_new_root
;
1426 reg
= reg_read(ohci
, OHCI1394_SelfIDCount
);
1427 if (reg
& OHCI1394_SelfIDCount_selfIDError
) {
1428 fw_notify("inconsistent self IDs\n");
1432 * The count in the SelfIDCount register is the number of
1433 * bytes in the self ID receive buffer. Since we also receive
1434 * the inverted quadlets and a header quadlet, we shift one
1435 * bit extra to get the actual number of self IDs.
1437 self_id_count
= (reg
>> 3) & 0xff;
1438 if (self_id_count
== 0 || self_id_count
> 252) {
1439 fw_notify("inconsistent self IDs\n");
1442 generation
= (cond_le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
1445 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
1446 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1]) {
1447 fw_notify("inconsistent self IDs\n");
1450 ohci
->self_id_buffer
[j
] =
1451 cond_le32_to_cpu(ohci
->self_id_cpu
[i
]);
1456 * Check the consistency of the self IDs we just read. The
1457 * problem we face is that a new bus reset can start while we
1458 * read out the self IDs from the DMA buffer. If this happens,
1459 * the DMA buffer will be overwritten with new self IDs and we
1460 * will read out inconsistent data. The OHCI specification
1461 * (section 11.2) recommends a technique similar to
1462 * linux/seqlock.h, where we remember the generation of the
1463 * self IDs in the buffer before reading them out and compare
1464 * it to the current generation after reading them out. If
1465 * the two generations match we know we have a consistent set
1469 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
1470 if (new_generation
!= generation
) {
1471 fw_notify("recursive bus reset detected, "
1472 "discarding self ids\n");
1476 /* FIXME: Document how the locking works. */
1477 spin_lock_irqsave(&ohci
->lock
, flags
);
1479 ohci
->generation
= generation
;
1480 context_stop(&ohci
->at_request_ctx
);
1481 context_stop(&ohci
->at_response_ctx
);
1482 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
1484 if (ohci
->quirks
& QUIRK_RESET_PACKET
)
1485 ohci
->request_generation
= generation
;
1488 * This next bit is unrelated to the AT context stuff but we
1489 * have to do it under the spinlock also. If a new config rom
1490 * was set up before this reset, the old one is now no longer
1491 * in use and we can free it. Update the config rom pointers
1492 * to point to the current config rom and clear the
1493 * next_config_rom pointer so a new udpate can take place.
1496 if (ohci
->next_config_rom
!= NULL
) {
1497 if (ohci
->next_config_rom
!= ohci
->config_rom
) {
1498 free_rom
= ohci
->config_rom
;
1499 free_rom_bus
= ohci
->config_rom_bus
;
1501 ohci
->config_rom
= ohci
->next_config_rom
;
1502 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
1503 ohci
->next_config_rom
= NULL
;
1506 * Restore config_rom image and manually update
1507 * config_rom registers. Writing the header quadlet
1508 * will indicate that the config rom is ready, so we
1511 reg_write(ohci
, OHCI1394_BusOptions
,
1512 be32_to_cpu(ohci
->config_rom
[2]));
1513 ohci
->config_rom
[0] = ohci
->next_header
;
1514 reg_write(ohci
, OHCI1394_ConfigROMhdr
,
1515 be32_to_cpu(ohci
->next_header
));
1518 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1519 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, ~0);
1520 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, ~0);
1523 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1526 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1527 free_rom
, free_rom_bus
);
1529 log_selfids(ohci
->node_id
, generation
,
1530 self_id_count
, ohci
->self_id_buffer
);
1532 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
1533 self_id_count
, ohci
->self_id_buffer
);
1536 static irqreturn_t
irq_handler(int irq
, void *data
)
1538 struct fw_ohci
*ohci
= data
;
1539 u32 event
, iso_event
;
1542 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
1544 if (!event
|| !~event
)
1547 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1548 reg_write(ohci
, OHCI1394_IntEventClear
, event
& ~OHCI1394_busReset
);
1551 if (event
& OHCI1394_selfIDComplete
)
1552 tasklet_schedule(&ohci
->bus_reset_tasklet
);
1554 if (event
& OHCI1394_RQPkt
)
1555 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
1557 if (event
& OHCI1394_RSPkt
)
1558 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
1560 if (event
& OHCI1394_reqTxComplete
)
1561 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
1563 if (event
& OHCI1394_respTxComplete
)
1564 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
1566 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
1567 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
1570 i
= ffs(iso_event
) - 1;
1571 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
1572 iso_event
&= ~(1 << i
);
1575 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
1576 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1579 i
= ffs(iso_event
) - 1;
1580 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1581 iso_event
&= ~(1 << i
);
1584 if (unlikely(event
& OHCI1394_regAccessFail
))
1585 fw_error("Register access failure - "
1586 "please notify linux1394-devel@lists.sf.net\n");
1588 if (unlikely(event
& OHCI1394_postedWriteErr
))
1589 fw_error("PCI posted write error\n");
1591 if (unlikely(event
& OHCI1394_cycleTooLong
)) {
1592 if (printk_ratelimit())
1593 fw_notify("isochronous cycle too long\n");
1594 reg_write(ohci
, OHCI1394_LinkControlSet
,
1595 OHCI1394_LinkControl_cycleMaster
);
1598 if (unlikely(event
& OHCI1394_cycleInconsistent
)) {
1600 * We need to clear this event bit in order to make
1601 * cycleMatch isochronous I/O work. In theory we should
1602 * stop active cycleMatch iso contexts now and restart
1603 * them at least two cycles later. (FIXME?)
1605 if (printk_ratelimit())
1606 fw_notify("isochronous cycle inconsistent\n");
1609 if (event
& OHCI1394_cycle64Seconds
) {
1610 spin_lock(&ohci
->lock
);
1611 update_bus_time(ohci
);
1612 spin_unlock(&ohci
->lock
);
1618 static int software_reset(struct fw_ohci
*ohci
)
1622 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1624 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1625 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1626 OHCI1394_HCControl_softReset
) == 0)
1634 static void copy_config_rom(__be32
*dest
, const __be32
*src
, size_t length
)
1636 size_t size
= length
* 4;
1638 memcpy(dest
, src
, size
);
1639 if (size
< CONFIG_ROM_SIZE
)
1640 memset(&dest
[length
], 0, CONFIG_ROM_SIZE
- size
);
1643 static int configure_1394a_enhancements(struct fw_ohci
*ohci
)
1646 int ret
, clear
, set
, offset
;
1648 /* Check if the driver should configure link and PHY. */
1649 if (!(reg_read(ohci
, OHCI1394_HCControlSet
) &
1650 OHCI1394_HCControl_programPhyEnable
))
1653 /* Paranoia: check whether the PHY supports 1394a, too. */
1654 enable_1394a
= false;
1655 ret
= read_phy_reg(ohci
, 2);
1658 if ((ret
& PHY_EXTENDED_REGISTERS
) == PHY_EXTENDED_REGISTERS
) {
1659 ret
= read_paged_phy_reg(ohci
, 1, 8);
1663 enable_1394a
= true;
1666 if (ohci
->quirks
& QUIRK_NO_1394A
)
1667 enable_1394a
= false;
1669 /* Configure PHY and link consistently. */
1672 set
= PHY_ENABLE_ACCEL
| PHY_ENABLE_MULTI
;
1674 clear
= PHY_ENABLE_ACCEL
| PHY_ENABLE_MULTI
;
1677 ret
= ohci_update_phy_reg(&ohci
->card
, 5, clear
, set
);
1682 offset
= OHCI1394_HCControlSet
;
1684 offset
= OHCI1394_HCControlClear
;
1685 reg_write(ohci
, offset
, OHCI1394_HCControl_aPhyEnhanceEnable
);
1687 /* Clean up: configuration has been taken care of. */
1688 reg_write(ohci
, OHCI1394_HCControlClear
,
1689 OHCI1394_HCControl_programPhyEnable
);
1694 static int ohci_enable(struct fw_card
*card
,
1695 const __be32
*config_rom
, size_t length
)
1697 struct fw_ohci
*ohci
= fw_ohci(card
);
1698 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1699 u32 lps
, seconds
, version
, irqs
;
1702 if (software_reset(ohci
)) {
1703 fw_error("Failed to reset ohci card.\n");
1708 * Now enable LPS, which we need in order to start accessing
1709 * most of the registers. In fact, on some cards (ALI M5251),
1710 * accessing registers in the SClk domain without LPS enabled
1711 * will lock up the machine. Wait 50msec to make sure we have
1712 * full link enabled. However, with some cards (well, at least
1713 * a JMicron PCIe card), we have to try again sometimes.
1715 reg_write(ohci
, OHCI1394_HCControlSet
,
1716 OHCI1394_HCControl_LPS
|
1717 OHCI1394_HCControl_postedWriteEnable
);
1720 for (lps
= 0, i
= 0; !lps
&& i
< 3; i
++) {
1722 lps
= reg_read(ohci
, OHCI1394_HCControlSet
) &
1723 OHCI1394_HCControl_LPS
;
1727 fw_error("Failed to set Link Power Status\n");
1731 reg_write(ohci
, OHCI1394_HCControlClear
,
1732 OHCI1394_HCControl_noByteSwapData
);
1734 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1735 reg_write(ohci
, OHCI1394_LinkControlClear
,
1736 OHCI1394_LinkControl_rcvPhyPkt
);
1737 reg_write(ohci
, OHCI1394_LinkControlSet
,
1738 OHCI1394_LinkControl_rcvSelfID
|
1739 OHCI1394_LinkControl_cycleTimerEnable
|
1740 OHCI1394_LinkControl_cycleMaster
);
1742 reg_write(ohci
, OHCI1394_ATRetries
,
1743 OHCI1394_MAX_AT_REQ_RETRIES
|
1744 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1745 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8) |
1748 seconds
= lower_32_bits(get_seconds());
1749 reg_write(ohci
, OHCI1394_IsochronousCycleTimer
, seconds
<< 25);
1750 ohci
->bus_time
= seconds
& ~0x3f;
1752 version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
1753 if (version
>= OHCI_VERSION_1_1
) {
1754 reg_write(ohci
, OHCI1394_InitialChannelsAvailableHi
,
1756 ohci
->features
|= FEATURE_CHANNEL_31_ALLOCATED
;
1759 /* Get implemented bits of the priority arbitration request counter. */
1760 reg_write(ohci
, OHCI1394_FairnessControl
, 0x3f);
1761 ohci
->pri_req_max
= reg_read(ohci
, OHCI1394_FairnessControl
) & 0x3f;
1762 reg_write(ohci
, OHCI1394_FairnessControl
, 0);
1763 if (ohci
->pri_req_max
!= 0)
1764 ohci
->features
|= FEATURE_PRIORITY_BUDGET
;
1766 ar_context_run(&ohci
->ar_request_ctx
);
1767 ar_context_run(&ohci
->ar_response_ctx
);
1769 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1770 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1771 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1773 ret
= configure_1394a_enhancements(ohci
);
1777 /* Activate link_on bit and contender bit in our self ID packets.*/
1778 ret
= ohci_update_phy_reg(card
, 4, 0, PHY_LINK_ACTIVE
| PHY_CONTENDER
);
1783 * When the link is not yet enabled, the atomic config rom
1784 * update mechanism described below in ohci_set_config_rom()
1785 * is not active. We have to update ConfigRomHeader and
1786 * BusOptions manually, and the write to ConfigROMmap takes
1787 * effect immediately. We tie this to the enabling of the
1788 * link, so we have a valid config rom before enabling - the
1789 * OHCI requires that ConfigROMhdr and BusOptions have valid
1790 * values before enabling.
1792 * However, when the ConfigROMmap is written, some controllers
1793 * always read back quadlets 0 and 2 from the config rom to
1794 * the ConfigRomHeader and BusOptions registers on bus reset.
1795 * They shouldn't do that in this initial case where the link
1796 * isn't enabled. This means we have to use the same
1797 * workaround here, setting the bus header to 0 and then write
1798 * the right values in the bus reset tasklet.
1802 ohci
->next_config_rom
=
1803 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1804 &ohci
->next_config_rom_bus
,
1806 if (ohci
->next_config_rom
== NULL
)
1809 copy_config_rom(ohci
->next_config_rom
, config_rom
, length
);
1812 * In the suspend case, config_rom is NULL, which
1813 * means that we just reuse the old config rom.
1815 ohci
->next_config_rom
= ohci
->config_rom
;
1816 ohci
->next_config_rom_bus
= ohci
->config_rom_bus
;
1819 ohci
->next_header
= ohci
->next_config_rom
[0];
1820 ohci
->next_config_rom
[0] = 0;
1821 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1822 reg_write(ohci
, OHCI1394_BusOptions
,
1823 be32_to_cpu(ohci
->next_config_rom
[2]));
1824 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1826 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1828 if (!(ohci
->quirks
& QUIRK_NO_MSI
))
1829 pci_enable_msi(dev
);
1830 if (request_irq(dev
->irq
, irq_handler
,
1831 pci_dev_msi_enabled(dev
) ? 0 : IRQF_SHARED
,
1832 ohci_driver_name
, ohci
)) {
1833 fw_error("Failed to allocate interrupt %d.\n", dev
->irq
);
1834 pci_disable_msi(dev
);
1835 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1836 ohci
->config_rom
, ohci
->config_rom_bus
);
1840 irqs
= OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1841 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1842 OHCI1394_isochTx
| OHCI1394_isochRx
|
1843 OHCI1394_postedWriteErr
|
1844 OHCI1394_selfIDComplete
|
1845 OHCI1394_regAccessFail
|
1846 OHCI1394_cycle64Seconds
|
1847 OHCI1394_cycleInconsistent
| OHCI1394_cycleTooLong
|
1848 OHCI1394_masterIntEnable
;
1849 if (param_debug
& OHCI_PARAM_DEBUG_BUSRESETS
)
1850 irqs
|= OHCI1394_busReset
;
1851 reg_write(ohci
, OHCI1394_IntMaskSet
, irqs
);
1853 reg_write(ohci
, OHCI1394_HCControlSet
,
1854 OHCI1394_HCControl_linkEnable
|
1855 OHCI1394_HCControl_BIBimageValid
);
1859 * We are ready to go, initiate bus reset to finish the
1863 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1868 static int ohci_set_config_rom(struct fw_card
*card
,
1869 const __be32
*config_rom
, size_t length
)
1871 struct fw_ohci
*ohci
;
1872 unsigned long flags
;
1874 __be32
*next_config_rom
;
1875 dma_addr_t
uninitialized_var(next_config_rom_bus
);
1877 ohci
= fw_ohci(card
);
1880 * When the OHCI controller is enabled, the config rom update
1881 * mechanism is a bit tricky, but easy enough to use. See
1882 * section 5.5.6 in the OHCI specification.
1884 * The OHCI controller caches the new config rom address in a
1885 * shadow register (ConfigROMmapNext) and needs a bus reset
1886 * for the changes to take place. When the bus reset is
1887 * detected, the controller loads the new values for the
1888 * ConfigRomHeader and BusOptions registers from the specified
1889 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1890 * shadow register. All automatically and atomically.
1892 * Now, there's a twist to this story. The automatic load of
1893 * ConfigRomHeader and BusOptions doesn't honor the
1894 * noByteSwapData bit, so with a be32 config rom, the
1895 * controller will load be32 values in to these registers
1896 * during the atomic update, even on litte endian
1897 * architectures. The workaround we use is to put a 0 in the
1898 * header quadlet; 0 is endian agnostic and means that the
1899 * config rom isn't ready yet. In the bus reset tasklet we
1900 * then set up the real values for the two registers.
1902 * We use ohci->lock to avoid racing with the code that sets
1903 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1907 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1908 &next_config_rom_bus
, GFP_KERNEL
);
1909 if (next_config_rom
== NULL
)
1912 spin_lock_irqsave(&ohci
->lock
, flags
);
1914 if (ohci
->next_config_rom
== NULL
) {
1915 ohci
->next_config_rom
= next_config_rom
;
1916 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1918 copy_config_rom(ohci
->next_config_rom
, config_rom
, length
);
1920 ohci
->next_header
= config_rom
[0];
1921 ohci
->next_config_rom
[0] = 0;
1923 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1924 ohci
->next_config_rom_bus
);
1928 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1931 * Now initiate a bus reset to have the changes take
1932 * effect. We clean up the old config rom memory and DMA
1933 * mappings in the bus reset tasklet, since the OHCI
1934 * controller could need to access it before the bus reset
1938 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1940 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1941 next_config_rom
, next_config_rom_bus
);
1946 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1948 struct fw_ohci
*ohci
= fw_ohci(card
);
1950 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1953 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1955 struct fw_ohci
*ohci
= fw_ohci(card
);
1957 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1960 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1962 struct fw_ohci
*ohci
= fw_ohci(card
);
1963 struct context
*ctx
= &ohci
->at_request_ctx
;
1964 struct driver_data
*driver_data
= packet
->driver_data
;
1967 tasklet_disable(&ctx
->tasklet
);
1969 if (packet
->ack
!= 0)
1972 if (packet
->payload_mapped
)
1973 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1974 packet
->payload_length
, DMA_TO_DEVICE
);
1976 log_ar_at_event('T', packet
->speed
, packet
->header
, 0x20);
1977 driver_data
->packet
= NULL
;
1978 packet
->ack
= RCODE_CANCELLED
;
1979 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1982 tasklet_enable(&ctx
->tasklet
);
1987 static int ohci_enable_phys_dma(struct fw_card
*card
,
1988 int node_id
, int generation
)
1990 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1993 struct fw_ohci
*ohci
= fw_ohci(card
);
1994 unsigned long flags
;
1998 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1999 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2002 spin_lock_irqsave(&ohci
->lock
, flags
);
2004 if (ohci
->generation
!= generation
) {
2010 * Note, if the node ID contains a non-local bus ID, physical DMA is
2011 * enabled for _all_ nodes on remote buses.
2014 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
2016 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
2018 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
2022 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2025 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2028 static u32
ohci_read_csr_reg(struct fw_card
*card
, int csr_offset
)
2030 struct fw_ohci
*ohci
= fw_ohci(card
);
2031 unsigned long flags
;
2034 switch (csr_offset
) {
2035 case CSR_STATE_CLEAR
:
2037 /* the controller driver handles only the cmstr bit */
2038 if (ohci
->is_root
&&
2039 (reg_read(ohci
, OHCI1394_LinkControlSet
) &
2040 OHCI1394_LinkControl_cycleMaster
))
2041 return CSR_STATE_BIT_CMSTR
;
2046 return reg_read(ohci
, OHCI1394_NodeID
) << 16;
2048 case CSR_CYCLE_TIME
:
2049 return get_cycle_time(ohci
);
2053 * We might be called just after the cycle timer has wrapped
2054 * around but just before the cycle64Seconds handler, so we
2055 * better check here, too, if the bus time needs to be updated.
2057 spin_lock_irqsave(&ohci
->lock
, flags
);
2058 value
= update_bus_time(ohci
);
2059 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2062 case CSR_BUSY_TIMEOUT
:
2063 value
= reg_read(ohci
, OHCI1394_ATRetries
);
2064 return (value
>> 4) & 0x0ffff00f;
2066 case CSR_PRIORITY_BUDGET
:
2067 return (reg_read(ohci
, OHCI1394_FairnessControl
) & 0x3f) |
2068 (ohci
->pri_req_max
<< 8);
2076 static void ohci_write_csr_reg(struct fw_card
*card
, int csr_offset
, u32 value
)
2078 struct fw_ohci
*ohci
= fw_ohci(card
);
2079 unsigned long flags
;
2081 switch (csr_offset
) {
2082 case CSR_STATE_CLEAR
:
2083 /* the controller driver handles only the cmstr bit */
2084 if ((value
& CSR_STATE_BIT_CMSTR
) && ohci
->is_root
) {
2085 reg_write(ohci
, OHCI1394_LinkControlClear
,
2086 OHCI1394_LinkControl_cycleMaster
);
2092 if ((value
& CSR_STATE_BIT_CMSTR
) && ohci
->is_root
) {
2093 reg_write(ohci
, OHCI1394_LinkControlSet
,
2094 OHCI1394_LinkControl_cycleMaster
);
2100 reg_write(ohci
, OHCI1394_NodeID
, value
>> 16);
2104 case CSR_CYCLE_TIME
:
2105 reg_write(ohci
, OHCI1394_IsochronousCycleTimer
, value
);
2106 reg_write(ohci
, OHCI1394_IntEventSet
,
2107 OHCI1394_cycleInconsistent
);
2112 spin_lock_irqsave(&ohci
->lock
, flags
);
2113 ohci
->bus_time
= (ohci
->bus_time
& 0x7f) | (value
& ~0x7f);
2114 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2117 case CSR_BUSY_TIMEOUT
:
2118 value
= (value
& 0xf) | ((value
& 0xf) << 4) |
2119 ((value
& 0xf) << 8) | ((value
& 0x0ffff000) << 4);
2120 reg_write(ohci
, OHCI1394_ATRetries
, value
);
2124 case CSR_PRIORITY_BUDGET
:
2125 reg_write(ohci
, OHCI1394_FairnessControl
, value
& 0x3f);
2135 static unsigned int ohci_get_features(struct fw_card
*card
)
2137 struct fw_ohci
*ohci
= fw_ohci(card
);
2139 return ohci
->features
;
2142 static void copy_iso_headers(struct iso_context
*ctx
, void *p
)
2144 int i
= ctx
->header_length
;
2146 if (i
+ ctx
->base
.header_size
> PAGE_SIZE
)
2150 * The iso header is byteswapped to little endian by
2151 * the controller, but the remaining header quadlets
2152 * are big endian. We want to present all the headers
2153 * as big endian, so we have to swap the first quadlet.
2155 if (ctx
->base
.header_size
> 0)
2156 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
2157 if (ctx
->base
.header_size
> 4)
2158 *(u32
*) (ctx
->header
+ i
+ 4) = __swab32(*(u32
*) p
);
2159 if (ctx
->base
.header_size
> 8)
2160 memcpy(ctx
->header
+ i
+ 8, p
+ 8, ctx
->base
.header_size
- 8);
2161 ctx
->header_length
+= ctx
->base
.header_size
;
2164 static int handle_ir_packet_per_buffer(struct context
*context
,
2165 struct descriptor
*d
,
2166 struct descriptor
*last
)
2168 struct iso_context
*ctx
=
2169 container_of(context
, struct iso_context
, context
);
2170 struct descriptor
*pd
;
2174 for (pd
= d
; pd
<= last
; pd
++) {
2175 if (pd
->transfer_status
)
2179 /* Descriptor(s) not done yet, stop iteration */
2183 copy_iso_headers(ctx
, p
);
2185 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
2186 ir_header
= (__le32
*) p
;
2187 ctx
->base
.callback(&ctx
->base
,
2188 le32_to_cpu(ir_header
[0]) & 0xffff,
2189 ctx
->header_length
, ctx
->header
,
2190 ctx
->base
.callback_data
);
2191 ctx
->header_length
= 0;
2197 static int handle_it_packet(struct context
*context
,
2198 struct descriptor
*d
,
2199 struct descriptor
*last
)
2201 struct iso_context
*ctx
=
2202 container_of(context
, struct iso_context
, context
);
2204 struct descriptor
*pd
;
2206 for (pd
= d
; pd
<= last
; pd
++)
2207 if (pd
->transfer_status
)
2210 /* Descriptor(s) not done yet, stop iteration */
2213 i
= ctx
->header_length
;
2214 if (i
+ 4 < PAGE_SIZE
) {
2215 /* Present this value as big-endian to match the receive code */
2216 *(__be32
*)(ctx
->header
+ i
) = cpu_to_be32(
2217 ((u32
)le16_to_cpu(pd
->transfer_status
) << 16) |
2218 le16_to_cpu(pd
->res_count
));
2219 ctx
->header_length
+= 4;
2221 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
2222 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
2223 ctx
->header_length
, ctx
->header
,
2224 ctx
->base
.callback_data
);
2225 ctx
->header_length
= 0;
2230 static struct fw_iso_context
*ohci_allocate_iso_context(struct fw_card
*card
,
2231 int type
, int channel
, size_t header_size
)
2233 struct fw_ohci
*ohci
= fw_ohci(card
);
2234 struct iso_context
*ctx
, *list
;
2235 descriptor_callback_t callback
;
2236 u64
*channels
, dont_care
= ~0ULL;
2238 unsigned long flags
;
2239 int index
, ret
= -ENOMEM
;
2241 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
2242 channels
= &dont_care
;
2243 mask
= &ohci
->it_context_mask
;
2244 list
= ohci
->it_context_list
;
2245 callback
= handle_it_packet
;
2247 channels
= &ohci
->ir_context_channels
;
2248 mask
= &ohci
->ir_context_mask
;
2249 list
= ohci
->ir_context_list
;
2250 callback
= handle_ir_packet_per_buffer
;
2253 spin_lock_irqsave(&ohci
->lock
, flags
);
2254 index
= *channels
& 1ULL << channel
? ffs(*mask
) - 1 : -1;
2256 *channels
&= ~(1ULL << channel
);
2257 *mask
&= ~(1 << index
);
2259 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2262 return ERR_PTR(-EBUSY
);
2264 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
2265 regs
= OHCI1394_IsoXmitContextBase(index
);
2267 regs
= OHCI1394_IsoRcvContextBase(index
);
2270 memset(ctx
, 0, sizeof(*ctx
));
2271 ctx
->header_length
= 0;
2272 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
2273 if (ctx
->header
== NULL
)
2276 ret
= context_init(&ctx
->context
, ohci
, regs
, callback
);
2278 goto out_with_header
;
2283 free_page((unsigned long)ctx
->header
);
2285 spin_lock_irqsave(&ohci
->lock
, flags
);
2286 *mask
|= 1 << index
;
2287 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2289 return ERR_PTR(ret
);
2292 static int ohci_start_iso(struct fw_iso_context
*base
,
2293 s32 cycle
, u32 sync
, u32 tags
)
2295 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2296 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
2300 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2301 index
= ctx
- ohci
->it_context_list
;
2304 match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
2305 (cycle
& 0x7fff) << 16;
2307 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
2308 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
2309 context_run(&ctx
->context
, match
);
2311 index
= ctx
- ohci
->ir_context_list
;
2312 control
= IR_CONTEXT_ISOCH_HEADER
;
2313 match
= (tags
<< 28) | (sync
<< 8) | ctx
->base
.channel
;
2315 match
|= (cycle
& 0x07fff) << 12;
2316 control
|= IR_CONTEXT_CYCLE_MATCH_ENABLE
;
2319 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
2320 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
2321 reg_write(ohci
, CONTEXT_MATCH(ctx
->context
.regs
), match
);
2322 context_run(&ctx
->context
, control
);
2328 static int ohci_stop_iso(struct fw_iso_context
*base
)
2330 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
2331 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2334 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2335 index
= ctx
- ohci
->it_context_list
;
2336 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
2338 index
= ctx
- ohci
->ir_context_list
;
2339 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
2342 context_stop(&ctx
->context
);
2347 static void ohci_free_iso_context(struct fw_iso_context
*base
)
2349 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
2350 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2351 unsigned long flags
;
2354 ohci_stop_iso(base
);
2355 context_release(&ctx
->context
);
2356 free_page((unsigned long)ctx
->header
);
2358 spin_lock_irqsave(&ohci
->lock
, flags
);
2360 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2361 index
= ctx
- ohci
->it_context_list
;
2362 ohci
->it_context_mask
|= 1 << index
;
2364 index
= ctx
- ohci
->ir_context_list
;
2365 ohci
->ir_context_mask
|= 1 << index
;
2366 ohci
->ir_context_channels
|= 1ULL << base
->channel
;
2369 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2372 static int ohci_queue_iso_transmit(struct fw_iso_context
*base
,
2373 struct fw_iso_packet
*packet
,
2374 struct fw_iso_buffer
*buffer
,
2375 unsigned long payload
)
2377 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2378 struct descriptor
*d
, *last
, *pd
;
2379 struct fw_iso_packet
*p
;
2381 dma_addr_t d_bus
, page_bus
;
2382 u32 z
, header_z
, payload_z
, irq
;
2383 u32 payload_index
, payload_end_index
, next_page_index
;
2384 int page
, end_page
, i
, length
, offset
;
2387 payload_index
= payload
;
2393 if (p
->header_length
> 0)
2396 /* Determine the first page the payload isn't contained in. */
2397 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
2398 if (p
->payload_length
> 0)
2399 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
2405 /* Get header size in number of descriptors. */
2406 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof(*d
));
2408 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
2413 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
2414 d
[0].req_count
= cpu_to_le16(8);
2416 * Link the skip address to this descriptor itself. This causes
2417 * a context to skip a cycle whenever lost cycles or FIFO
2418 * overruns occur, without dropping the data. The application
2419 * should then decide whether this is an error condition or not.
2420 * FIXME: Make the context's cycle-lost behaviour configurable?
2422 d
[0].branch_address
= cpu_to_le32(d_bus
| z
);
2424 header
= (__le32
*) &d
[1];
2425 header
[0] = cpu_to_le32(IT_HEADER_SY(p
->sy
) |
2426 IT_HEADER_TAG(p
->tag
) |
2427 IT_HEADER_TCODE(TCODE_STREAM_DATA
) |
2428 IT_HEADER_CHANNEL(ctx
->base
.channel
) |
2429 IT_HEADER_SPEED(ctx
->base
.speed
));
2431 cpu_to_le32(IT_HEADER_DATA_LENGTH(p
->header_length
+
2432 p
->payload_length
));
2435 if (p
->header_length
> 0) {
2436 d
[2].req_count
= cpu_to_le16(p
->header_length
);
2437 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof(*d
));
2438 memcpy(&d
[z
], p
->header
, p
->header_length
);
2441 pd
= d
+ z
- payload_z
;
2442 payload_end_index
= payload_index
+ p
->payload_length
;
2443 for (i
= 0; i
< payload_z
; i
++) {
2444 page
= payload_index
>> PAGE_SHIFT
;
2445 offset
= payload_index
& ~PAGE_MASK
;
2446 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
2448 min(next_page_index
, payload_end_index
) - payload_index
;
2449 pd
[i
].req_count
= cpu_to_le16(length
);
2451 page_bus
= page_private(buffer
->pages
[page
]);
2452 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
2454 payload_index
+= length
;
2458 irq
= DESCRIPTOR_IRQ_ALWAYS
;
2460 irq
= DESCRIPTOR_NO_IRQ
;
2462 last
= z
== 2 ? d
: d
+ z
- 1;
2463 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
2465 DESCRIPTOR_BRANCH_ALWAYS
|
2468 context_append(&ctx
->context
, d
, z
, header_z
);
2473 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context
*base
,
2474 struct fw_iso_packet
*packet
,
2475 struct fw_iso_buffer
*buffer
,
2476 unsigned long payload
)
2478 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2479 struct descriptor
*d
, *pd
;
2480 struct fw_iso_packet
*p
= packet
;
2481 dma_addr_t d_bus
, page_bus
;
2482 u32 z
, header_z
, rest
;
2484 int page
, offset
, packet_count
, header_size
, payload_per_buffer
;
2487 * The OHCI controller puts the isochronous header and trailer in the
2488 * buffer, so we need at least 8 bytes.
2490 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
2491 header_size
= max(ctx
->base
.header_size
, (size_t)8);
2493 /* Get header size in number of descriptors. */
2494 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
2495 page
= payload
>> PAGE_SHIFT
;
2496 offset
= payload
& ~PAGE_MASK
;
2497 payload_per_buffer
= p
->payload_length
/ packet_count
;
2499 for (i
= 0; i
< packet_count
; i
++) {
2500 /* d points to the header descriptor */
2501 z
= DIV_ROUND_UP(payload_per_buffer
+ offset
, PAGE_SIZE
) + 1;
2502 d
= context_get_descriptors(&ctx
->context
,
2503 z
+ header_z
, &d_bus
);
2507 d
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2508 DESCRIPTOR_INPUT_MORE
);
2509 if (p
->skip
&& i
== 0)
2510 d
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
2511 d
->req_count
= cpu_to_le16(header_size
);
2512 d
->res_count
= d
->req_count
;
2513 d
->transfer_status
= 0;
2514 d
->data_address
= cpu_to_le32(d_bus
+ (z
* sizeof(*d
)));
2516 rest
= payload_per_buffer
;
2518 for (j
= 1; j
< z
; j
++) {
2520 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2521 DESCRIPTOR_INPUT_MORE
);
2523 if (offset
+ rest
< PAGE_SIZE
)
2526 length
= PAGE_SIZE
- offset
;
2527 pd
->req_count
= cpu_to_le16(length
);
2528 pd
->res_count
= pd
->req_count
;
2529 pd
->transfer_status
= 0;
2531 page_bus
= page_private(buffer
->pages
[page
]);
2532 pd
->data_address
= cpu_to_le32(page_bus
+ offset
);
2534 offset
= (offset
+ length
) & ~PAGE_MASK
;
2539 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2540 DESCRIPTOR_INPUT_LAST
|
2541 DESCRIPTOR_BRANCH_ALWAYS
);
2542 if (p
->interrupt
&& i
== packet_count
- 1)
2543 pd
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2545 context_append(&ctx
->context
, d
, z
, header_z
);
2551 static int ohci_queue_iso(struct fw_iso_context
*base
,
2552 struct fw_iso_packet
*packet
,
2553 struct fw_iso_buffer
*buffer
,
2554 unsigned long payload
)
2556 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2557 unsigned long flags
;
2560 spin_lock_irqsave(&ctx
->context
.ohci
->lock
, flags
);
2561 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
2562 ret
= ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
2564 ret
= ohci_queue_iso_receive_packet_per_buffer(base
, packet
,
2566 spin_unlock_irqrestore(&ctx
->context
.ohci
->lock
, flags
);
2571 static const struct fw_card_driver ohci_driver
= {
2572 .enable
= ohci_enable
,
2573 .update_phy_reg
= ohci_update_phy_reg
,
2574 .set_config_rom
= ohci_set_config_rom
,
2575 .send_request
= ohci_send_request
,
2576 .send_response
= ohci_send_response
,
2577 .cancel_packet
= ohci_cancel_packet
,
2578 .enable_phys_dma
= ohci_enable_phys_dma
,
2579 .read_csr_reg
= ohci_read_csr_reg
,
2580 .write_csr_reg
= ohci_write_csr_reg
,
2581 .get_features
= ohci_get_features
,
2583 .allocate_iso_context
= ohci_allocate_iso_context
,
2584 .free_iso_context
= ohci_free_iso_context
,
2585 .queue_iso
= ohci_queue_iso
,
2586 .start_iso
= ohci_start_iso
,
2587 .stop_iso
= ohci_stop_iso
,
2590 #ifdef CONFIG_PPC_PMAC
2591 static void pmac_ohci_on(struct pci_dev
*dev
)
2593 if (machine_is(powermac
)) {
2594 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2597 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 1);
2598 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 1);
2603 static void pmac_ohci_off(struct pci_dev
*dev
)
2605 if (machine_is(powermac
)) {
2606 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2609 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 0);
2610 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 0);
2615 static inline void pmac_ohci_on(struct pci_dev
*dev
) {}
2616 static inline void pmac_ohci_off(struct pci_dev
*dev
) {}
2617 #endif /* CONFIG_PPC_PMAC */
2619 static int __devinit
pci_probe(struct pci_dev
*dev
,
2620 const struct pci_device_id
*ent
)
2622 struct fw_ohci
*ohci
;
2623 u32 bus_options
, max_receive
, link_speed
, version
, link_enh
;
2625 int i
, err
, n_ir
, n_it
;
2628 ohci
= kzalloc(sizeof(*ohci
), GFP_KERNEL
);
2634 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
2638 err
= pci_enable_device(dev
);
2640 fw_error("Failed to enable OHCI hardware\n");
2644 pci_set_master(dev
);
2645 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
2646 pci_set_drvdata(dev
, ohci
);
2648 spin_lock_init(&ohci
->lock
);
2650 tasklet_init(&ohci
->bus_reset_tasklet
,
2651 bus_reset_tasklet
, (unsigned long)ohci
);
2653 err
= pci_request_region(dev
, 0, ohci_driver_name
);
2655 fw_error("MMIO resource unavailable\n");
2659 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
2660 if (ohci
->registers
== NULL
) {
2661 fw_error("Failed to remap registers\n");
2666 for (i
= 0; i
< ARRAY_SIZE(ohci_quirks
); i
++)
2667 if (ohci_quirks
[i
].vendor
== dev
->vendor
&&
2668 (ohci_quirks
[i
].device
== dev
->device
||
2669 ohci_quirks
[i
].device
== (unsigned short)PCI_ANY_ID
)) {
2670 ohci
->quirks
= ohci_quirks
[i
].flags
;
2674 ohci
->quirks
= param_quirks
;
2676 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2677 if (dev
->vendor
== PCI_VENDOR_ID_TI
) {
2678 pci_read_config_dword(dev
, PCI_CFG_TI_LinkEnh
, &link_enh
);
2680 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2681 link_enh
&= ~TI_LinkEnh_atx_thresh_mask
;
2682 link_enh
|= TI_LinkEnh_atx_thresh_1_7K
;
2684 /* use priority arbitration for asynchronous responses */
2685 link_enh
|= TI_LinkEnh_enab_unfair
;
2687 /* required for aPhyEnhanceEnable to work */
2688 link_enh
|= TI_LinkEnh_enab_accel
;
2690 pci_write_config_dword(dev
, PCI_CFG_TI_LinkEnh
, link_enh
);
2693 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
2694 OHCI1394_AsReqRcvContextControlSet
);
2696 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
2697 OHCI1394_AsRspRcvContextControlSet
);
2699 context_init(&ohci
->at_request_ctx
, ohci
,
2700 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
2702 context_init(&ohci
->at_response_ctx
, ohci
,
2703 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
2705 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
2706 ohci
->ir_context_channels
= ~0ULL;
2707 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
2708 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
2709 n_ir
= hweight32(ohci
->ir_context_mask
);
2710 size
= sizeof(struct iso_context
) * n_ir
;
2711 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
2713 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
2714 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
2715 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
2716 n_it
= hweight32(ohci
->it_context_mask
);
2717 size
= sizeof(struct iso_context
) * n_it
;
2718 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
2720 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
2725 /* self-id dma buffer allocation */
2726 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
2730 if (ohci
->self_id_cpu
== NULL
) {
2735 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
2736 max_receive
= (bus_options
>> 12) & 0xf;
2737 link_speed
= bus_options
& 0x7;
2738 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
2739 reg_read(ohci
, OHCI1394_GUIDLo
);
2741 err
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
2745 version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
2746 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2747 "%d IR + %d IT contexts, quirks 0x%x\n",
2748 dev_name(&dev
->dev
), version
>> 16, version
& 0xff,
2749 n_ir
, n_it
, ohci
->quirks
);
2754 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2755 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2757 kfree(ohci
->ir_context_list
);
2758 kfree(ohci
->it_context_list
);
2759 context_release(&ohci
->at_response_ctx
);
2760 context_release(&ohci
->at_request_ctx
);
2761 ar_context_release(&ohci
->ar_response_ctx
);
2762 ar_context_release(&ohci
->ar_request_ctx
);
2763 pci_iounmap(dev
, ohci
->registers
);
2765 pci_release_region(dev
, 0);
2767 pci_disable_device(dev
);
2773 fw_error("Out of memory\n");
2778 static void pci_remove(struct pci_dev
*dev
)
2780 struct fw_ohci
*ohci
;
2782 ohci
= pci_get_drvdata(dev
);
2783 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
2785 fw_core_remove_card(&ohci
->card
);
2788 * FIXME: Fail all pending packets here, now that the upper
2789 * layers can't queue any more.
2792 software_reset(ohci
);
2793 free_irq(dev
->irq
, ohci
);
2795 if (ohci
->next_config_rom
&& ohci
->next_config_rom
!= ohci
->config_rom
)
2796 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
2797 ohci
->next_config_rom
, ohci
->next_config_rom_bus
);
2798 if (ohci
->config_rom
)
2799 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
2800 ohci
->config_rom
, ohci
->config_rom_bus
);
2801 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2802 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2803 ar_context_release(&ohci
->ar_request_ctx
);
2804 ar_context_release(&ohci
->ar_response_ctx
);
2805 context_release(&ohci
->at_request_ctx
);
2806 context_release(&ohci
->at_response_ctx
);
2807 kfree(ohci
->it_context_list
);
2808 kfree(ohci
->ir_context_list
);
2809 pci_disable_msi(dev
);
2810 pci_iounmap(dev
, ohci
->registers
);
2811 pci_release_region(dev
, 0);
2812 pci_disable_device(dev
);
2816 fw_notify("Removed fw-ohci device.\n");
2820 static int pci_suspend(struct pci_dev
*dev
, pm_message_t state
)
2822 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2825 software_reset(ohci
);
2826 free_irq(dev
->irq
, ohci
);
2827 pci_disable_msi(dev
);
2828 err
= pci_save_state(dev
);
2830 fw_error("pci_save_state failed\n");
2833 err
= pci_set_power_state(dev
, pci_choose_state(dev
, state
));
2835 fw_error("pci_set_power_state failed with %d\n", err
);
2841 static int pci_resume(struct pci_dev
*dev
)
2843 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2847 pci_set_power_state(dev
, PCI_D0
);
2848 pci_restore_state(dev
);
2849 err
= pci_enable_device(dev
);
2851 fw_error("pci_enable_device failed\n");
2855 return ohci_enable(&ohci
->card
, NULL
, 0);
2859 static const struct pci_device_id pci_table
[] = {
2860 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
2864 MODULE_DEVICE_TABLE(pci
, pci_table
);
2866 static struct pci_driver fw_ohci_pci_driver
= {
2867 .name
= ohci_driver_name
,
2868 .id_table
= pci_table
,
2870 .remove
= pci_remove
,
2872 .resume
= pci_resume
,
2873 .suspend
= pci_suspend
,
2877 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2878 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2879 MODULE_LICENSE("GPL");
2881 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2882 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2883 MODULE_ALIAS("ohci1394");
2886 static int __init
fw_ohci_init(void)
2888 return pci_register_driver(&fw_ohci_pci_driver
);
2891 static void __exit
fw_ohci_cleanup(void)
2893 pci_unregister_driver(&fw_ohci_pci_driver
);
2896 module_init(fw_ohci_init
);
2897 module_exit(fw_ohci_cleanup
);