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firewire: ohci: Fix 'failed to read phy reg' on FW643 rev8
[deliverable/linux.git] / drivers / firewire / ohci.c
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45 #include <linux/workqueue.h>
46
47 #include <asm/byteorder.h>
48 #include <asm/page.h>
49
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/pmac_feature.h>
52 #endif
53
54 #include "core.h"
55 #include "ohci.h"
56
57 #define DESCRIPTOR_OUTPUT_MORE 0
58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59 #define DESCRIPTOR_INPUT_MORE (2 << 12)
60 #define DESCRIPTOR_INPUT_LAST (3 << 12)
61 #define DESCRIPTOR_STATUS (1 << 11)
62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63 #define DESCRIPTOR_PING (1 << 7)
64 #define DESCRIPTOR_YY (1 << 6)
65 #define DESCRIPTOR_NO_IRQ (0 << 4)
66 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69 #define DESCRIPTOR_WAIT (3 << 0)
70
71 #define DESCRIPTOR_CMD (0xf << 12)
72
73 struct descriptor {
74 __le16 req_count;
75 __le16 control;
76 __le32 data_address;
77 __le32 branch_address;
78 __le16 res_count;
79 __le16 transfer_status;
80 } __attribute__((aligned(16)));
81
82 #define CONTROL_SET(regs) (regs)
83 #define CONTROL_CLEAR(regs) ((regs) + 4)
84 #define COMMAND_PTR(regs) ((regs) + 12)
85 #define CONTEXT_MATCH(regs) ((regs) + 16)
86
87 #define AR_BUFFER_SIZE (32*1024)
88 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
89 /* we need at least two pages for proper list management */
90 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
91
92 #define MAX_ASYNC_PAYLOAD 4096
93 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
94 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
95
96 struct ar_context {
97 struct fw_ohci *ohci;
98 struct page *pages[AR_BUFFERS];
99 void *buffer;
100 struct descriptor *descriptors;
101 dma_addr_t descriptors_bus;
102 void *pointer;
103 unsigned int last_buffer_index;
104 u32 regs;
105 struct tasklet_struct tasklet;
106 };
107
108 struct context;
109
110 typedef int (*descriptor_callback_t)(struct context *ctx,
111 struct descriptor *d,
112 struct descriptor *last);
113
114 /*
115 * A buffer that contains a block of DMA-able coherent memory used for
116 * storing a portion of a DMA descriptor program.
117 */
118 struct descriptor_buffer {
119 struct list_head list;
120 dma_addr_t buffer_bus;
121 size_t buffer_size;
122 size_t used;
123 struct descriptor buffer[0];
124 };
125
126 struct context {
127 struct fw_ohci *ohci;
128 u32 regs;
129 int total_allocation;
130 u32 current_bus;
131 bool running;
132 bool flushing;
133
134 /*
135 * List of page-sized buffers for storing DMA descriptors.
136 * Head of list contains buffers in use and tail of list contains
137 * free buffers.
138 */
139 struct list_head buffer_list;
140
141 /*
142 * Pointer to a buffer inside buffer_list that contains the tail
143 * end of the current DMA program.
144 */
145 struct descriptor_buffer *buffer_tail;
146
147 /*
148 * The descriptor containing the branch address of the first
149 * descriptor that has not yet been filled by the device.
150 */
151 struct descriptor *last;
152
153 /*
154 * The last descriptor block in the DMA program. It contains the branch
155 * address that must be updated upon appending a new descriptor.
156 */
157 struct descriptor *prev;
158 int prev_z;
159
160 descriptor_callback_t callback;
161
162 struct tasklet_struct tasklet;
163 };
164
165 #define IT_HEADER_SY(v) ((v) << 0)
166 #define IT_HEADER_TCODE(v) ((v) << 4)
167 #define IT_HEADER_CHANNEL(v) ((v) << 8)
168 #define IT_HEADER_TAG(v) ((v) << 14)
169 #define IT_HEADER_SPEED(v) ((v) << 16)
170 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
171
172 struct iso_context {
173 struct fw_iso_context base;
174 struct context context;
175 void *header;
176 size_t header_length;
177 unsigned long flushing_completions;
178 u32 mc_buffer_bus;
179 u16 mc_completed;
180 u16 last_timestamp;
181 u8 sync;
182 u8 tags;
183 };
184
185 #define CONFIG_ROM_SIZE 1024
186
187 struct fw_ohci {
188 struct fw_card card;
189
190 __iomem char *registers;
191 int node_id;
192 int generation;
193 int request_generation; /* for timestamping incoming requests */
194 unsigned quirks;
195 unsigned int pri_req_max;
196 u32 bus_time;
197 bool bus_time_running;
198 bool is_root;
199 bool csr_state_setclear_abdicate;
200 int n_ir;
201 int n_it;
202 /*
203 * Spinlock for accessing fw_ohci data. Never call out of
204 * this driver with this lock held.
205 */
206 spinlock_t lock;
207
208 struct mutex phy_reg_mutex;
209
210 void *misc_buffer;
211 dma_addr_t misc_buffer_bus;
212
213 struct ar_context ar_request_ctx;
214 struct ar_context ar_response_ctx;
215 struct context at_request_ctx;
216 struct context at_response_ctx;
217
218 u32 it_context_support;
219 u32 it_context_mask; /* unoccupied IT contexts */
220 struct iso_context *it_context_list;
221 u64 ir_context_channels; /* unoccupied channels */
222 u32 ir_context_support;
223 u32 ir_context_mask; /* unoccupied IR contexts */
224 struct iso_context *ir_context_list;
225 u64 mc_channels; /* channels in use by the multichannel IR context */
226 bool mc_allocated;
227
228 __be32 *config_rom;
229 dma_addr_t config_rom_bus;
230 __be32 *next_config_rom;
231 dma_addr_t next_config_rom_bus;
232 __be32 next_header;
233
234 __le32 *self_id_cpu;
235 dma_addr_t self_id_bus;
236 struct work_struct bus_reset_work;
237
238 u32 self_id_buffer[512];
239 };
240
241 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
242 {
243 return container_of(card, struct fw_ohci, card);
244 }
245
246 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
247 #define IR_CONTEXT_BUFFER_FILL 0x80000000
248 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
249 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
250 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
251 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
252
253 #define CONTEXT_RUN 0x8000
254 #define CONTEXT_WAKE 0x1000
255 #define CONTEXT_DEAD 0x0800
256 #define CONTEXT_ACTIVE 0x0400
257
258 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
259 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
260 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
261
262 #define OHCI1394_REGISTER_SIZE 0x800
263 #define OHCI1394_PCI_HCI_Control 0x40
264 #define SELF_ID_BUF_SIZE 0x800
265 #define OHCI_TCODE_PHY_PACKET 0x0e
266 #define OHCI_VERSION_1_1 0x010010
267
268 static char ohci_driver_name[] = KBUILD_MODNAME;
269
270 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
271 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
272 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
273 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
274 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
275 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
276 #define PCI_DEVICE_ID_VIA_VT630X 0x3044
277 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
278 #define PCI_REV_ID_VIA_VT6306 0x46
279
280 #define QUIRK_CYCLE_TIMER 1
281 #define QUIRK_RESET_PACKET 2
282 #define QUIRK_BE_HEADERS 4
283 #define QUIRK_NO_1394A 8
284 #define QUIRK_NO_MSI 16
285 #define QUIRK_TI_SLLZ059 32
286 #define QUIRK_IR_WAKE 64
287 #define QUIRK_PHY_LCTRL_TIMEOUT 128
288
289 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
290 static const struct {
291 unsigned short vendor, device, revision, flags;
292 } ohci_quirks[] = {
293 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
294 QUIRK_CYCLE_TIMER},
295
296 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
297 QUIRK_BE_HEADERS},
298
299 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
300 QUIRK_PHY_LCTRL_TIMEOUT | QUIRK_NO_MSI},
301
302 {PCI_VENDOR_ID_ATT, PCI_ANY_ID, PCI_ANY_ID,
303 QUIRK_PHY_LCTRL_TIMEOUT},
304
305 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
306 QUIRK_RESET_PACKET},
307
308 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
309 QUIRK_NO_MSI},
310
311 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
312 QUIRK_CYCLE_TIMER},
313
314 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
315 QUIRK_NO_MSI},
316
317 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
318 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
319
320 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
321 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
322
323 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
324 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
325
326 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
327 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
328
329 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
330 QUIRK_RESET_PACKET},
331
332 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
333 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
334
335 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
336 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
337 };
338
339 /* This overrides anything that was found in ohci_quirks[]. */
340 static int param_quirks;
341 module_param_named(quirks, param_quirks, int, 0644);
342 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
343 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
344 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
345 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
346 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
347 ", disable MSI = " __stringify(QUIRK_NO_MSI)
348 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
349 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
350 ", phy LCtrl timeout = " __stringify(QUIRK_PHY_LCTRL_TIMEOUT)
351 ")");
352
353 #define OHCI_PARAM_DEBUG_AT_AR 1
354 #define OHCI_PARAM_DEBUG_SELFIDS 2
355 #define OHCI_PARAM_DEBUG_IRQS 4
356 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
357
358 static int param_debug;
359 module_param_named(debug, param_debug, int, 0644);
360 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
361 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
362 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
363 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
364 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
365 ", or a combination, or all = -1)");
366
367 static void log_irqs(struct fw_ohci *ohci, u32 evt)
368 {
369 if (likely(!(param_debug &
370 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
371 return;
372
373 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
374 !(evt & OHCI1394_busReset))
375 return;
376
377 dev_notice(ohci->card.device,
378 "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
379 evt & OHCI1394_selfIDComplete ? " selfID" : "",
380 evt & OHCI1394_RQPkt ? " AR_req" : "",
381 evt & OHCI1394_RSPkt ? " AR_resp" : "",
382 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
383 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
384 evt & OHCI1394_isochRx ? " IR" : "",
385 evt & OHCI1394_isochTx ? " IT" : "",
386 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
387 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
388 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
389 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
390 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
391 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
392 evt & OHCI1394_busReset ? " busReset" : "",
393 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
394 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
395 OHCI1394_respTxComplete | OHCI1394_isochRx |
396 OHCI1394_isochTx | OHCI1394_postedWriteErr |
397 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
398 OHCI1394_cycleInconsistent |
399 OHCI1394_regAccessFail | OHCI1394_busReset)
400 ? " ?" : "");
401 }
402
403 static const char *speed[] = {
404 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
405 };
406 static const char *power[] = {
407 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
408 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
409 };
410 static const char port[] = { '.', '-', 'p', 'c', };
411
412 static char _p(u32 *s, int shift)
413 {
414 return port[*s >> shift & 3];
415 }
416
417 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
418 {
419 u32 *s;
420
421 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
422 return;
423
424 dev_notice(ohci->card.device,
425 "%d selfIDs, generation %d, local node ID %04x\n",
426 self_id_count, generation, ohci->node_id);
427
428 for (s = ohci->self_id_buffer; self_id_count--; ++s)
429 if ((*s & 1 << 23) == 0)
430 dev_notice(ohci->card.device,
431 "selfID 0: %08x, phy %d [%c%c%c] "
432 "%s gc=%d %s %s%s%s\n",
433 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
434 speed[*s >> 14 & 3], *s >> 16 & 63,
435 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
436 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
437 else
438 dev_notice(ohci->card.device,
439 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
440 *s, *s >> 24 & 63,
441 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
442 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
443 }
444
445 static const char *evts[] = {
446 [0x00] = "evt_no_status", [0x01] = "-reserved-",
447 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
448 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
449 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
450 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
451 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
452 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
453 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
454 [0x10] = "-reserved-", [0x11] = "ack_complete",
455 [0x12] = "ack_pending ", [0x13] = "-reserved-",
456 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
457 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
458 [0x18] = "-reserved-", [0x19] = "-reserved-",
459 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
460 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
461 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
462 [0x20] = "pending/cancelled",
463 };
464 static const char *tcodes[] = {
465 [0x0] = "QW req", [0x1] = "BW req",
466 [0x2] = "W resp", [0x3] = "-reserved-",
467 [0x4] = "QR req", [0x5] = "BR req",
468 [0x6] = "QR resp", [0x7] = "BR resp",
469 [0x8] = "cycle start", [0x9] = "Lk req",
470 [0xa] = "async stream packet", [0xb] = "Lk resp",
471 [0xc] = "-reserved-", [0xd] = "-reserved-",
472 [0xe] = "link internal", [0xf] = "-reserved-",
473 };
474
475 static void log_ar_at_event(struct fw_ohci *ohci,
476 char dir, int speed, u32 *header, int evt)
477 {
478 int tcode = header[0] >> 4 & 0xf;
479 char specific[12];
480
481 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
482 return;
483
484 if (unlikely(evt >= ARRAY_SIZE(evts)))
485 evt = 0x1f;
486
487 if (evt == OHCI1394_evt_bus_reset) {
488 dev_notice(ohci->card.device,
489 "A%c evt_bus_reset, generation %d\n",
490 dir, (header[2] >> 16) & 0xff);
491 return;
492 }
493
494 switch (tcode) {
495 case 0x0: case 0x6: case 0x8:
496 snprintf(specific, sizeof(specific), " = %08x",
497 be32_to_cpu((__force __be32)header[3]));
498 break;
499 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
500 snprintf(specific, sizeof(specific), " %x,%x",
501 header[3] >> 16, header[3] & 0xffff);
502 break;
503 default:
504 specific[0] = '\0';
505 }
506
507 switch (tcode) {
508 case 0xa:
509 dev_notice(ohci->card.device,
510 "A%c %s, %s\n",
511 dir, evts[evt], tcodes[tcode]);
512 break;
513 case 0xe:
514 dev_notice(ohci->card.device,
515 "A%c %s, PHY %08x %08x\n",
516 dir, evts[evt], header[1], header[2]);
517 break;
518 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
519 dev_notice(ohci->card.device,
520 "A%c spd %x tl %02x, "
521 "%04x -> %04x, %s, "
522 "%s, %04x%08x%s\n",
523 dir, speed, header[0] >> 10 & 0x3f,
524 header[1] >> 16, header[0] >> 16, evts[evt],
525 tcodes[tcode], header[1] & 0xffff, header[2], specific);
526 break;
527 default:
528 dev_notice(ohci->card.device,
529 "A%c spd %x tl %02x, "
530 "%04x -> %04x, %s, "
531 "%s%s\n",
532 dir, speed, header[0] >> 10 & 0x3f,
533 header[1] >> 16, header[0] >> 16, evts[evt],
534 tcodes[tcode], specific);
535 }
536 }
537
538 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
539 {
540 writel(data, ohci->registers + offset);
541 }
542
543 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
544 {
545 return readl(ohci->registers + offset);
546 }
547
548 static inline void flush_writes(const struct fw_ohci *ohci)
549 {
550 /* Do a dummy read to flush writes. */
551 reg_read(ohci, OHCI1394_Version);
552 }
553
554 /*
555 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
556 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
557 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
558 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
559 */
560 static int read_phy_reg(struct fw_ohci *ohci, int addr)
561 {
562 u32 val;
563 int i;
564
565 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
566 for (i = 0; i < 3 + 100; i++) {
567 val = reg_read(ohci, OHCI1394_PhyControl);
568 if (!~val)
569 return -ENODEV; /* Card was ejected. */
570
571 if (val & OHCI1394_PhyControl_ReadDone)
572 return OHCI1394_PhyControl_ReadData(val);
573
574 /*
575 * Try a few times without waiting. Sleeping is necessary
576 * only when the link/PHY interface is busy.
577 */
578 if (i >= 3)
579 msleep(1);
580 }
581 dev_err(ohci->card.device, "failed to read phy reg\n");
582
583 return -EBUSY;
584 }
585
586 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
587 {
588 int i;
589
590 reg_write(ohci, OHCI1394_PhyControl,
591 OHCI1394_PhyControl_Write(addr, val));
592 for (i = 0; i < 3 + 100; i++) {
593 val = reg_read(ohci, OHCI1394_PhyControl);
594 if (!~val)
595 return -ENODEV; /* Card was ejected. */
596
597 if (!(val & OHCI1394_PhyControl_WritePending))
598 return 0;
599
600 if (i >= 3)
601 msleep(1);
602 }
603 dev_err(ohci->card.device, "failed to write phy reg\n");
604
605 return -EBUSY;
606 }
607
608 static int update_phy_reg(struct fw_ohci *ohci, int addr,
609 int clear_bits, int set_bits)
610 {
611 int ret = read_phy_reg(ohci, addr);
612 if (ret < 0)
613 return ret;
614
615 /*
616 * The interrupt status bits are cleared by writing a one bit.
617 * Avoid clearing them unless explicitly requested in set_bits.
618 */
619 if (addr == 5)
620 clear_bits |= PHY_INT_STATUS_BITS;
621
622 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
623 }
624
625 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
626 {
627 int ret;
628
629 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
630 if (ret < 0)
631 return ret;
632
633 return read_phy_reg(ohci, addr);
634 }
635
636 static int ohci_read_phy_reg(struct fw_card *card, int addr)
637 {
638 struct fw_ohci *ohci = fw_ohci(card);
639 int ret;
640
641 mutex_lock(&ohci->phy_reg_mutex);
642 ret = read_phy_reg(ohci, addr);
643 mutex_unlock(&ohci->phy_reg_mutex);
644
645 return ret;
646 }
647
648 static int ohci_update_phy_reg(struct fw_card *card, int addr,
649 int clear_bits, int set_bits)
650 {
651 struct fw_ohci *ohci = fw_ohci(card);
652 int ret;
653
654 mutex_lock(&ohci->phy_reg_mutex);
655 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
656 mutex_unlock(&ohci->phy_reg_mutex);
657
658 return ret;
659 }
660
661 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
662 {
663 return page_private(ctx->pages[i]);
664 }
665
666 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
667 {
668 struct descriptor *d;
669
670 d = &ctx->descriptors[index];
671 d->branch_address &= cpu_to_le32(~0xf);
672 d->res_count = cpu_to_le16(PAGE_SIZE);
673 d->transfer_status = 0;
674
675 wmb(); /* finish init of new descriptors before branch_address update */
676 d = &ctx->descriptors[ctx->last_buffer_index];
677 d->branch_address |= cpu_to_le32(1);
678
679 ctx->last_buffer_index = index;
680
681 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
682 }
683
684 static void ar_context_release(struct ar_context *ctx)
685 {
686 unsigned int i;
687
688 if (ctx->buffer)
689 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
690
691 for (i = 0; i < AR_BUFFERS; i++)
692 if (ctx->pages[i]) {
693 dma_unmap_page(ctx->ohci->card.device,
694 ar_buffer_bus(ctx, i),
695 PAGE_SIZE, DMA_FROM_DEVICE);
696 __free_page(ctx->pages[i]);
697 }
698 }
699
700 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
701 {
702 struct fw_ohci *ohci = ctx->ohci;
703
704 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
705 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
706 flush_writes(ohci);
707
708 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n",
709 error_msg);
710 }
711 /* FIXME: restart? */
712 }
713
714 static inline unsigned int ar_next_buffer_index(unsigned int index)
715 {
716 return (index + 1) % AR_BUFFERS;
717 }
718
719 static inline unsigned int ar_prev_buffer_index(unsigned int index)
720 {
721 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
722 }
723
724 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
725 {
726 return ar_next_buffer_index(ctx->last_buffer_index);
727 }
728
729 /*
730 * We search for the buffer that contains the last AR packet DMA data written
731 * by the controller.
732 */
733 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
734 unsigned int *buffer_offset)
735 {
736 unsigned int i, next_i, last = ctx->last_buffer_index;
737 __le16 res_count, next_res_count;
738
739 i = ar_first_buffer_index(ctx);
740 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
741
742 /* A buffer that is not yet completely filled must be the last one. */
743 while (i != last && res_count == 0) {
744
745 /* Peek at the next descriptor. */
746 next_i = ar_next_buffer_index(i);
747 rmb(); /* read descriptors in order */
748 next_res_count = ACCESS_ONCE(
749 ctx->descriptors[next_i].res_count);
750 /*
751 * If the next descriptor is still empty, we must stop at this
752 * descriptor.
753 */
754 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
755 /*
756 * The exception is when the DMA data for one packet is
757 * split over three buffers; in this case, the middle
758 * buffer's descriptor might be never updated by the
759 * controller and look still empty, and we have to peek
760 * at the third one.
761 */
762 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
763 next_i = ar_next_buffer_index(next_i);
764 rmb();
765 next_res_count = ACCESS_ONCE(
766 ctx->descriptors[next_i].res_count);
767 if (next_res_count != cpu_to_le16(PAGE_SIZE))
768 goto next_buffer_is_active;
769 }
770
771 break;
772 }
773
774 next_buffer_is_active:
775 i = next_i;
776 res_count = next_res_count;
777 }
778
779 rmb(); /* read res_count before the DMA data */
780
781 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
782 if (*buffer_offset > PAGE_SIZE) {
783 *buffer_offset = 0;
784 ar_context_abort(ctx, "corrupted descriptor");
785 }
786
787 return i;
788 }
789
790 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
791 unsigned int end_buffer_index,
792 unsigned int end_buffer_offset)
793 {
794 unsigned int i;
795
796 i = ar_first_buffer_index(ctx);
797 while (i != end_buffer_index) {
798 dma_sync_single_for_cpu(ctx->ohci->card.device,
799 ar_buffer_bus(ctx, i),
800 PAGE_SIZE, DMA_FROM_DEVICE);
801 i = ar_next_buffer_index(i);
802 }
803 if (end_buffer_offset > 0)
804 dma_sync_single_for_cpu(ctx->ohci->card.device,
805 ar_buffer_bus(ctx, i),
806 end_buffer_offset, DMA_FROM_DEVICE);
807 }
808
809 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
810 #define cond_le32_to_cpu(v) \
811 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
812 #else
813 #define cond_le32_to_cpu(v) le32_to_cpu(v)
814 #endif
815
816 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
817 {
818 struct fw_ohci *ohci = ctx->ohci;
819 struct fw_packet p;
820 u32 status, length, tcode;
821 int evt;
822
823 p.header[0] = cond_le32_to_cpu(buffer[0]);
824 p.header[1] = cond_le32_to_cpu(buffer[1]);
825 p.header[2] = cond_le32_to_cpu(buffer[2]);
826
827 tcode = (p.header[0] >> 4) & 0x0f;
828 switch (tcode) {
829 case TCODE_WRITE_QUADLET_REQUEST:
830 case TCODE_READ_QUADLET_RESPONSE:
831 p.header[3] = (__force __u32) buffer[3];
832 p.header_length = 16;
833 p.payload_length = 0;
834 break;
835
836 case TCODE_READ_BLOCK_REQUEST :
837 p.header[3] = cond_le32_to_cpu(buffer[3]);
838 p.header_length = 16;
839 p.payload_length = 0;
840 break;
841
842 case TCODE_WRITE_BLOCK_REQUEST:
843 case TCODE_READ_BLOCK_RESPONSE:
844 case TCODE_LOCK_REQUEST:
845 case TCODE_LOCK_RESPONSE:
846 p.header[3] = cond_le32_to_cpu(buffer[3]);
847 p.header_length = 16;
848 p.payload_length = p.header[3] >> 16;
849 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
850 ar_context_abort(ctx, "invalid packet length");
851 return NULL;
852 }
853 break;
854
855 case TCODE_WRITE_RESPONSE:
856 case TCODE_READ_QUADLET_REQUEST:
857 case OHCI_TCODE_PHY_PACKET:
858 p.header_length = 12;
859 p.payload_length = 0;
860 break;
861
862 default:
863 ar_context_abort(ctx, "invalid tcode");
864 return NULL;
865 }
866
867 p.payload = (void *) buffer + p.header_length;
868
869 /* FIXME: What to do about evt_* errors? */
870 length = (p.header_length + p.payload_length + 3) / 4;
871 status = cond_le32_to_cpu(buffer[length]);
872 evt = (status >> 16) & 0x1f;
873
874 p.ack = evt - 16;
875 p.speed = (status >> 21) & 0x7;
876 p.timestamp = status & 0xffff;
877 p.generation = ohci->request_generation;
878
879 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
880
881 /*
882 * Several controllers, notably from NEC and VIA, forget to
883 * write ack_complete status at PHY packet reception.
884 */
885 if (evt == OHCI1394_evt_no_status &&
886 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
887 p.ack = ACK_COMPLETE;
888
889 /*
890 * The OHCI bus reset handler synthesizes a PHY packet with
891 * the new generation number when a bus reset happens (see
892 * section 8.4.2.3). This helps us determine when a request
893 * was received and make sure we send the response in the same
894 * generation. We only need this for requests; for responses
895 * we use the unique tlabel for finding the matching
896 * request.
897 *
898 * Alas some chips sometimes emit bus reset packets with a
899 * wrong generation. We set the correct generation for these
900 * at a slightly incorrect time (in bus_reset_work).
901 */
902 if (evt == OHCI1394_evt_bus_reset) {
903 if (!(ohci->quirks & QUIRK_RESET_PACKET))
904 ohci->request_generation = (p.header[2] >> 16) & 0xff;
905 } else if (ctx == &ohci->ar_request_ctx) {
906 fw_core_handle_request(&ohci->card, &p);
907 } else {
908 fw_core_handle_response(&ohci->card, &p);
909 }
910
911 return buffer + length + 1;
912 }
913
914 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
915 {
916 void *next;
917
918 while (p < end) {
919 next = handle_ar_packet(ctx, p);
920 if (!next)
921 return p;
922 p = next;
923 }
924
925 return p;
926 }
927
928 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
929 {
930 unsigned int i;
931
932 i = ar_first_buffer_index(ctx);
933 while (i != end_buffer) {
934 dma_sync_single_for_device(ctx->ohci->card.device,
935 ar_buffer_bus(ctx, i),
936 PAGE_SIZE, DMA_FROM_DEVICE);
937 ar_context_link_page(ctx, i);
938 i = ar_next_buffer_index(i);
939 }
940 }
941
942 static void ar_context_tasklet(unsigned long data)
943 {
944 struct ar_context *ctx = (struct ar_context *)data;
945 unsigned int end_buffer_index, end_buffer_offset;
946 void *p, *end;
947
948 p = ctx->pointer;
949 if (!p)
950 return;
951
952 end_buffer_index = ar_search_last_active_buffer(ctx,
953 &end_buffer_offset);
954 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
955 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
956
957 if (end_buffer_index < ar_first_buffer_index(ctx)) {
958 /*
959 * The filled part of the overall buffer wraps around; handle
960 * all packets up to the buffer end here. If the last packet
961 * wraps around, its tail will be visible after the buffer end
962 * because the buffer start pages are mapped there again.
963 */
964 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
965 p = handle_ar_packets(ctx, p, buffer_end);
966 if (p < buffer_end)
967 goto error;
968 /* adjust p to point back into the actual buffer */
969 p -= AR_BUFFERS * PAGE_SIZE;
970 }
971
972 p = handle_ar_packets(ctx, p, end);
973 if (p != end) {
974 if (p > end)
975 ar_context_abort(ctx, "inconsistent descriptor");
976 goto error;
977 }
978
979 ctx->pointer = p;
980 ar_recycle_buffers(ctx, end_buffer_index);
981
982 return;
983
984 error:
985 ctx->pointer = NULL;
986 }
987
988 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
989 unsigned int descriptors_offset, u32 regs)
990 {
991 unsigned int i;
992 dma_addr_t dma_addr;
993 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
994 struct descriptor *d;
995
996 ctx->regs = regs;
997 ctx->ohci = ohci;
998 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
999
1000 for (i = 0; i < AR_BUFFERS; i++) {
1001 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
1002 if (!ctx->pages[i])
1003 goto out_of_memory;
1004 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1005 0, PAGE_SIZE, DMA_FROM_DEVICE);
1006 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1007 __free_page(ctx->pages[i]);
1008 ctx->pages[i] = NULL;
1009 goto out_of_memory;
1010 }
1011 set_page_private(ctx->pages[i], dma_addr);
1012 }
1013
1014 for (i = 0; i < AR_BUFFERS; i++)
1015 pages[i] = ctx->pages[i];
1016 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1017 pages[AR_BUFFERS + i] = ctx->pages[i];
1018 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
1019 -1, PAGE_KERNEL);
1020 if (!ctx->buffer)
1021 goto out_of_memory;
1022
1023 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1024 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1025
1026 for (i = 0; i < AR_BUFFERS; i++) {
1027 d = &ctx->descriptors[i];
1028 d->req_count = cpu_to_le16(PAGE_SIZE);
1029 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1030 DESCRIPTOR_STATUS |
1031 DESCRIPTOR_BRANCH_ALWAYS);
1032 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1033 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1034 ar_next_buffer_index(i) * sizeof(struct descriptor));
1035 }
1036
1037 return 0;
1038
1039 out_of_memory:
1040 ar_context_release(ctx);
1041
1042 return -ENOMEM;
1043 }
1044
1045 static void ar_context_run(struct ar_context *ctx)
1046 {
1047 unsigned int i;
1048
1049 for (i = 0; i < AR_BUFFERS; i++)
1050 ar_context_link_page(ctx, i);
1051
1052 ctx->pointer = ctx->buffer;
1053
1054 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1055 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1056 }
1057
1058 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1059 {
1060 __le16 branch;
1061
1062 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1063
1064 /* figure out which descriptor the branch address goes in */
1065 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1066 return d;
1067 else
1068 return d + z - 1;
1069 }
1070
1071 static void context_tasklet(unsigned long data)
1072 {
1073 struct context *ctx = (struct context *) data;
1074 struct descriptor *d, *last;
1075 u32 address;
1076 int z;
1077 struct descriptor_buffer *desc;
1078
1079 desc = list_entry(ctx->buffer_list.next,
1080 struct descriptor_buffer, list);
1081 last = ctx->last;
1082 while (last->branch_address != 0) {
1083 struct descriptor_buffer *old_desc = desc;
1084 address = le32_to_cpu(last->branch_address);
1085 z = address & 0xf;
1086 address &= ~0xf;
1087 ctx->current_bus = address;
1088
1089 /* If the branch address points to a buffer outside of the
1090 * current buffer, advance to the next buffer. */
1091 if (address < desc->buffer_bus ||
1092 address >= desc->buffer_bus + desc->used)
1093 desc = list_entry(desc->list.next,
1094 struct descriptor_buffer, list);
1095 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1096 last = find_branch_descriptor(d, z);
1097
1098 if (!ctx->callback(ctx, d, last))
1099 break;
1100
1101 if (old_desc != desc) {
1102 /* If we've advanced to the next buffer, move the
1103 * previous buffer to the free list. */
1104 unsigned long flags;
1105 old_desc->used = 0;
1106 spin_lock_irqsave(&ctx->ohci->lock, flags);
1107 list_move_tail(&old_desc->list, &ctx->buffer_list);
1108 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1109 }
1110 ctx->last = last;
1111 }
1112 }
1113
1114 /*
1115 * Allocate a new buffer and add it to the list of free buffers for this
1116 * context. Must be called with ohci->lock held.
1117 */
1118 static int context_add_buffer(struct context *ctx)
1119 {
1120 struct descriptor_buffer *desc;
1121 dma_addr_t uninitialized_var(bus_addr);
1122 int offset;
1123
1124 /*
1125 * 16MB of descriptors should be far more than enough for any DMA
1126 * program. This will catch run-away userspace or DoS attacks.
1127 */
1128 if (ctx->total_allocation >= 16*1024*1024)
1129 return -ENOMEM;
1130
1131 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1132 &bus_addr, GFP_ATOMIC);
1133 if (!desc)
1134 return -ENOMEM;
1135
1136 offset = (void *)&desc->buffer - (void *)desc;
1137 desc->buffer_size = PAGE_SIZE - offset;
1138 desc->buffer_bus = bus_addr + offset;
1139 desc->used = 0;
1140
1141 list_add_tail(&desc->list, &ctx->buffer_list);
1142 ctx->total_allocation += PAGE_SIZE;
1143
1144 return 0;
1145 }
1146
1147 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1148 u32 regs, descriptor_callback_t callback)
1149 {
1150 ctx->ohci = ohci;
1151 ctx->regs = regs;
1152 ctx->total_allocation = 0;
1153
1154 INIT_LIST_HEAD(&ctx->buffer_list);
1155 if (context_add_buffer(ctx) < 0)
1156 return -ENOMEM;
1157
1158 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1159 struct descriptor_buffer, list);
1160
1161 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1162 ctx->callback = callback;
1163
1164 /*
1165 * We put a dummy descriptor in the buffer that has a NULL
1166 * branch address and looks like it's been sent. That way we
1167 * have a descriptor to append DMA programs to.
1168 */
1169 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1170 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1171 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1172 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1173 ctx->last = ctx->buffer_tail->buffer;
1174 ctx->prev = ctx->buffer_tail->buffer;
1175 ctx->prev_z = 1;
1176
1177 return 0;
1178 }
1179
1180 static void context_release(struct context *ctx)
1181 {
1182 struct fw_card *card = &ctx->ohci->card;
1183 struct descriptor_buffer *desc, *tmp;
1184
1185 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1186 dma_free_coherent(card->device, PAGE_SIZE, desc,
1187 desc->buffer_bus -
1188 ((void *)&desc->buffer - (void *)desc));
1189 }
1190
1191 /* Must be called with ohci->lock held */
1192 static struct descriptor *context_get_descriptors(struct context *ctx,
1193 int z, dma_addr_t *d_bus)
1194 {
1195 struct descriptor *d = NULL;
1196 struct descriptor_buffer *desc = ctx->buffer_tail;
1197
1198 if (z * sizeof(*d) > desc->buffer_size)
1199 return NULL;
1200
1201 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1202 /* No room for the descriptor in this buffer, so advance to the
1203 * next one. */
1204
1205 if (desc->list.next == &ctx->buffer_list) {
1206 /* If there is no free buffer next in the list,
1207 * allocate one. */
1208 if (context_add_buffer(ctx) < 0)
1209 return NULL;
1210 }
1211 desc = list_entry(desc->list.next,
1212 struct descriptor_buffer, list);
1213 ctx->buffer_tail = desc;
1214 }
1215
1216 d = desc->buffer + desc->used / sizeof(*d);
1217 memset(d, 0, z * sizeof(*d));
1218 *d_bus = desc->buffer_bus + desc->used;
1219
1220 return d;
1221 }
1222
1223 static void context_run(struct context *ctx, u32 extra)
1224 {
1225 struct fw_ohci *ohci = ctx->ohci;
1226
1227 reg_write(ohci, COMMAND_PTR(ctx->regs),
1228 le32_to_cpu(ctx->last->branch_address));
1229 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1230 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1231 ctx->running = true;
1232 flush_writes(ohci);
1233 }
1234
1235 static void context_append(struct context *ctx,
1236 struct descriptor *d, int z, int extra)
1237 {
1238 dma_addr_t d_bus;
1239 struct descriptor_buffer *desc = ctx->buffer_tail;
1240 struct descriptor *d_branch;
1241
1242 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1243
1244 desc->used += (z + extra) * sizeof(*d);
1245
1246 wmb(); /* finish init of new descriptors before branch_address update */
1247
1248 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1249 d_branch->branch_address = cpu_to_le32(d_bus | z);
1250
1251 /*
1252 * VT6306 incorrectly checks only the single descriptor at the
1253 * CommandPtr when the wake bit is written, so if it's a
1254 * multi-descriptor block starting with an INPUT_MORE, put a copy of
1255 * the branch address in the first descriptor.
1256 *
1257 * Not doing this for transmit contexts since not sure how it interacts
1258 * with skip addresses.
1259 */
1260 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1261 d_branch != ctx->prev &&
1262 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1263 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1264 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1265 }
1266
1267 ctx->prev = d;
1268 ctx->prev_z = z;
1269 }
1270
1271 static void context_stop(struct context *ctx)
1272 {
1273 struct fw_ohci *ohci = ctx->ohci;
1274 u32 reg;
1275 int i;
1276
1277 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1278 ctx->running = false;
1279
1280 for (i = 0; i < 1000; i++) {
1281 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1282 if ((reg & CONTEXT_ACTIVE) == 0)
1283 return;
1284
1285 if (i)
1286 udelay(10);
1287 }
1288 dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg);
1289 }
1290
1291 struct driver_data {
1292 u8 inline_data[8];
1293 struct fw_packet *packet;
1294 };
1295
1296 /*
1297 * This function apppends a packet to the DMA queue for transmission.
1298 * Must always be called with the ochi->lock held to ensure proper
1299 * generation handling and locking around packet queue manipulation.
1300 */
1301 static int at_context_queue_packet(struct context *ctx,
1302 struct fw_packet *packet)
1303 {
1304 struct fw_ohci *ohci = ctx->ohci;
1305 dma_addr_t d_bus, uninitialized_var(payload_bus);
1306 struct driver_data *driver_data;
1307 struct descriptor *d, *last;
1308 __le32 *header;
1309 int z, tcode;
1310
1311 d = context_get_descriptors(ctx, 4, &d_bus);
1312 if (d == NULL) {
1313 packet->ack = RCODE_SEND_ERROR;
1314 return -1;
1315 }
1316
1317 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1318 d[0].res_count = cpu_to_le16(packet->timestamp);
1319
1320 /*
1321 * The DMA format for asynchronous link packets is different
1322 * from the IEEE1394 layout, so shift the fields around
1323 * accordingly.
1324 */
1325
1326 tcode = (packet->header[0] >> 4) & 0x0f;
1327 header = (__le32 *) &d[1];
1328 switch (tcode) {
1329 case TCODE_WRITE_QUADLET_REQUEST:
1330 case TCODE_WRITE_BLOCK_REQUEST:
1331 case TCODE_WRITE_RESPONSE:
1332 case TCODE_READ_QUADLET_REQUEST:
1333 case TCODE_READ_BLOCK_REQUEST:
1334 case TCODE_READ_QUADLET_RESPONSE:
1335 case TCODE_READ_BLOCK_RESPONSE:
1336 case TCODE_LOCK_REQUEST:
1337 case TCODE_LOCK_RESPONSE:
1338 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1339 (packet->speed << 16));
1340 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1341 (packet->header[0] & 0xffff0000));
1342 header[2] = cpu_to_le32(packet->header[2]);
1343
1344 if (TCODE_IS_BLOCK_PACKET(tcode))
1345 header[3] = cpu_to_le32(packet->header[3]);
1346 else
1347 header[3] = (__force __le32) packet->header[3];
1348
1349 d[0].req_count = cpu_to_le16(packet->header_length);
1350 break;
1351
1352 case TCODE_LINK_INTERNAL:
1353 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1354 (packet->speed << 16));
1355 header[1] = cpu_to_le32(packet->header[1]);
1356 header[2] = cpu_to_le32(packet->header[2]);
1357 d[0].req_count = cpu_to_le16(12);
1358
1359 if (is_ping_packet(&packet->header[1]))
1360 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1361 break;
1362
1363 case TCODE_STREAM_DATA:
1364 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1365 (packet->speed << 16));
1366 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1367 d[0].req_count = cpu_to_le16(8);
1368 break;
1369
1370 default:
1371 /* BUG(); */
1372 packet->ack = RCODE_SEND_ERROR;
1373 return -1;
1374 }
1375
1376 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1377 driver_data = (struct driver_data *) &d[3];
1378 driver_data->packet = packet;
1379 packet->driver_data = driver_data;
1380
1381 if (packet->payload_length > 0) {
1382 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1383 payload_bus = dma_map_single(ohci->card.device,
1384 packet->payload,
1385 packet->payload_length,
1386 DMA_TO_DEVICE);
1387 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1388 packet->ack = RCODE_SEND_ERROR;
1389 return -1;
1390 }
1391 packet->payload_bus = payload_bus;
1392 packet->payload_mapped = true;
1393 } else {
1394 memcpy(driver_data->inline_data, packet->payload,
1395 packet->payload_length);
1396 payload_bus = d_bus + 3 * sizeof(*d);
1397 }
1398
1399 d[2].req_count = cpu_to_le16(packet->payload_length);
1400 d[2].data_address = cpu_to_le32(payload_bus);
1401 last = &d[2];
1402 z = 3;
1403 } else {
1404 last = &d[0];
1405 z = 2;
1406 }
1407
1408 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1409 DESCRIPTOR_IRQ_ALWAYS |
1410 DESCRIPTOR_BRANCH_ALWAYS);
1411
1412 /* FIXME: Document how the locking works. */
1413 if (ohci->generation != packet->generation) {
1414 if (packet->payload_mapped)
1415 dma_unmap_single(ohci->card.device, payload_bus,
1416 packet->payload_length, DMA_TO_DEVICE);
1417 packet->ack = RCODE_GENERATION;
1418 return -1;
1419 }
1420
1421 context_append(ctx, d, z, 4 - z);
1422
1423 if (ctx->running)
1424 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1425 else
1426 context_run(ctx, 0);
1427
1428 return 0;
1429 }
1430
1431 static void at_context_flush(struct context *ctx)
1432 {
1433 tasklet_disable(&ctx->tasklet);
1434
1435 ctx->flushing = true;
1436 context_tasklet((unsigned long)ctx);
1437 ctx->flushing = false;
1438
1439 tasklet_enable(&ctx->tasklet);
1440 }
1441
1442 static int handle_at_packet(struct context *context,
1443 struct descriptor *d,
1444 struct descriptor *last)
1445 {
1446 struct driver_data *driver_data;
1447 struct fw_packet *packet;
1448 struct fw_ohci *ohci = context->ohci;
1449 int evt;
1450
1451 if (last->transfer_status == 0 && !context->flushing)
1452 /* This descriptor isn't done yet, stop iteration. */
1453 return 0;
1454
1455 driver_data = (struct driver_data *) &d[3];
1456 packet = driver_data->packet;
1457 if (packet == NULL)
1458 /* This packet was cancelled, just continue. */
1459 return 1;
1460
1461 if (packet->payload_mapped)
1462 dma_unmap_single(ohci->card.device, packet->payload_bus,
1463 packet->payload_length, DMA_TO_DEVICE);
1464
1465 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1466 packet->timestamp = le16_to_cpu(last->res_count);
1467
1468 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1469
1470 switch (evt) {
1471 case OHCI1394_evt_timeout:
1472 /* Async response transmit timed out. */
1473 packet->ack = RCODE_CANCELLED;
1474 break;
1475
1476 case OHCI1394_evt_flushed:
1477 /*
1478 * The packet was flushed should give same error as
1479 * when we try to use a stale generation count.
1480 */
1481 packet->ack = RCODE_GENERATION;
1482 break;
1483
1484 case OHCI1394_evt_missing_ack:
1485 if (context->flushing)
1486 packet->ack = RCODE_GENERATION;
1487 else {
1488 /*
1489 * Using a valid (current) generation count, but the
1490 * node is not on the bus or not sending acks.
1491 */
1492 packet->ack = RCODE_NO_ACK;
1493 }
1494 break;
1495
1496 case ACK_COMPLETE + 0x10:
1497 case ACK_PENDING + 0x10:
1498 case ACK_BUSY_X + 0x10:
1499 case ACK_BUSY_A + 0x10:
1500 case ACK_BUSY_B + 0x10:
1501 case ACK_DATA_ERROR + 0x10:
1502 case ACK_TYPE_ERROR + 0x10:
1503 packet->ack = evt - 0x10;
1504 break;
1505
1506 case OHCI1394_evt_no_status:
1507 if (context->flushing) {
1508 packet->ack = RCODE_GENERATION;
1509 break;
1510 }
1511 /* fall through */
1512
1513 default:
1514 packet->ack = RCODE_SEND_ERROR;
1515 break;
1516 }
1517
1518 packet->callback(packet, &ohci->card, packet->ack);
1519
1520 return 1;
1521 }
1522
1523 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1524 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1525 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1526 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1527 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1528
1529 static void handle_local_rom(struct fw_ohci *ohci,
1530 struct fw_packet *packet, u32 csr)
1531 {
1532 struct fw_packet response;
1533 int tcode, length, i;
1534
1535 tcode = HEADER_GET_TCODE(packet->header[0]);
1536 if (TCODE_IS_BLOCK_PACKET(tcode))
1537 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1538 else
1539 length = 4;
1540
1541 i = csr - CSR_CONFIG_ROM;
1542 if (i + length > CONFIG_ROM_SIZE) {
1543 fw_fill_response(&response, packet->header,
1544 RCODE_ADDRESS_ERROR, NULL, 0);
1545 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1546 fw_fill_response(&response, packet->header,
1547 RCODE_TYPE_ERROR, NULL, 0);
1548 } else {
1549 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1550 (void *) ohci->config_rom + i, length);
1551 }
1552
1553 fw_core_handle_response(&ohci->card, &response);
1554 }
1555
1556 static void handle_local_lock(struct fw_ohci *ohci,
1557 struct fw_packet *packet, u32 csr)
1558 {
1559 struct fw_packet response;
1560 int tcode, length, ext_tcode, sel, try;
1561 __be32 *payload, lock_old;
1562 u32 lock_arg, lock_data;
1563
1564 tcode = HEADER_GET_TCODE(packet->header[0]);
1565 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1566 payload = packet->payload;
1567 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1568
1569 if (tcode == TCODE_LOCK_REQUEST &&
1570 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1571 lock_arg = be32_to_cpu(payload[0]);
1572 lock_data = be32_to_cpu(payload[1]);
1573 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1574 lock_arg = 0;
1575 lock_data = 0;
1576 } else {
1577 fw_fill_response(&response, packet->header,
1578 RCODE_TYPE_ERROR, NULL, 0);
1579 goto out;
1580 }
1581
1582 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1583 reg_write(ohci, OHCI1394_CSRData, lock_data);
1584 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1585 reg_write(ohci, OHCI1394_CSRControl, sel);
1586
1587 for (try = 0; try < 20; try++)
1588 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1589 lock_old = cpu_to_be32(reg_read(ohci,
1590 OHCI1394_CSRData));
1591 fw_fill_response(&response, packet->header,
1592 RCODE_COMPLETE,
1593 &lock_old, sizeof(lock_old));
1594 goto out;
1595 }
1596
1597 dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
1598 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1599
1600 out:
1601 fw_core_handle_response(&ohci->card, &response);
1602 }
1603
1604 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1605 {
1606 u64 offset, csr;
1607
1608 if (ctx == &ctx->ohci->at_request_ctx) {
1609 packet->ack = ACK_PENDING;
1610 packet->callback(packet, &ctx->ohci->card, packet->ack);
1611 }
1612
1613 offset =
1614 ((unsigned long long)
1615 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1616 packet->header[2];
1617 csr = offset - CSR_REGISTER_BASE;
1618
1619 /* Handle config rom reads. */
1620 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1621 handle_local_rom(ctx->ohci, packet, csr);
1622 else switch (csr) {
1623 case CSR_BUS_MANAGER_ID:
1624 case CSR_BANDWIDTH_AVAILABLE:
1625 case CSR_CHANNELS_AVAILABLE_HI:
1626 case CSR_CHANNELS_AVAILABLE_LO:
1627 handle_local_lock(ctx->ohci, packet, csr);
1628 break;
1629 default:
1630 if (ctx == &ctx->ohci->at_request_ctx)
1631 fw_core_handle_request(&ctx->ohci->card, packet);
1632 else
1633 fw_core_handle_response(&ctx->ohci->card, packet);
1634 break;
1635 }
1636
1637 if (ctx == &ctx->ohci->at_response_ctx) {
1638 packet->ack = ACK_COMPLETE;
1639 packet->callback(packet, &ctx->ohci->card, packet->ack);
1640 }
1641 }
1642
1643 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1644 {
1645 unsigned long flags;
1646 int ret;
1647
1648 spin_lock_irqsave(&ctx->ohci->lock, flags);
1649
1650 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1651 ctx->ohci->generation == packet->generation) {
1652 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1653 handle_local_request(ctx, packet);
1654 return;
1655 }
1656
1657 ret = at_context_queue_packet(ctx, packet);
1658 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1659
1660 if (ret < 0)
1661 packet->callback(packet, &ctx->ohci->card, packet->ack);
1662
1663 }
1664
1665 static void detect_dead_context(struct fw_ohci *ohci,
1666 const char *name, unsigned int regs)
1667 {
1668 u32 ctl;
1669
1670 ctl = reg_read(ohci, CONTROL_SET(regs));
1671 if (ctl & CONTEXT_DEAD)
1672 dev_err(ohci->card.device,
1673 "DMA context %s has stopped, error code: %s\n",
1674 name, evts[ctl & 0x1f]);
1675 }
1676
1677 static void handle_dead_contexts(struct fw_ohci *ohci)
1678 {
1679 unsigned int i;
1680 char name[8];
1681
1682 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1683 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1684 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1685 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1686 for (i = 0; i < 32; ++i) {
1687 if (!(ohci->it_context_support & (1 << i)))
1688 continue;
1689 sprintf(name, "IT%u", i);
1690 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1691 }
1692 for (i = 0; i < 32; ++i) {
1693 if (!(ohci->ir_context_support & (1 << i)))
1694 continue;
1695 sprintf(name, "IR%u", i);
1696 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1697 }
1698 /* TODO: maybe try to flush and restart the dead contexts */
1699 }
1700
1701 static u32 cycle_timer_ticks(u32 cycle_timer)
1702 {
1703 u32 ticks;
1704
1705 ticks = cycle_timer & 0xfff;
1706 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1707 ticks += (3072 * 8000) * (cycle_timer >> 25);
1708
1709 return ticks;
1710 }
1711
1712 /*
1713 * Some controllers exhibit one or more of the following bugs when updating the
1714 * iso cycle timer register:
1715 * - When the lowest six bits are wrapping around to zero, a read that happens
1716 * at the same time will return garbage in the lowest ten bits.
1717 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1718 * not incremented for about 60 ns.
1719 * - Occasionally, the entire register reads zero.
1720 *
1721 * To catch these, we read the register three times and ensure that the
1722 * difference between each two consecutive reads is approximately the same, i.e.
1723 * less than twice the other. Furthermore, any negative difference indicates an
1724 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1725 * execute, so we have enough precision to compute the ratio of the differences.)
1726 */
1727 static u32 get_cycle_time(struct fw_ohci *ohci)
1728 {
1729 u32 c0, c1, c2;
1730 u32 t0, t1, t2;
1731 s32 diff01, diff12;
1732 int i;
1733
1734 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1735
1736 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1737 i = 0;
1738 c1 = c2;
1739 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1740 do {
1741 c0 = c1;
1742 c1 = c2;
1743 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1744 t0 = cycle_timer_ticks(c0);
1745 t1 = cycle_timer_ticks(c1);
1746 t2 = cycle_timer_ticks(c2);
1747 diff01 = t1 - t0;
1748 diff12 = t2 - t1;
1749 } while ((diff01 <= 0 || diff12 <= 0 ||
1750 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1751 && i++ < 20);
1752 }
1753
1754 return c2;
1755 }
1756
1757 /*
1758 * This function has to be called at least every 64 seconds. The bus_time
1759 * field stores not only the upper 25 bits of the BUS_TIME register but also
1760 * the most significant bit of the cycle timer in bit 6 so that we can detect
1761 * changes in this bit.
1762 */
1763 static u32 update_bus_time(struct fw_ohci *ohci)
1764 {
1765 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1766
1767 if (unlikely(!ohci->bus_time_running)) {
1768 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1769 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1770 (cycle_time_seconds & 0x40);
1771 ohci->bus_time_running = true;
1772 }
1773
1774 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1775 ohci->bus_time += 0x40;
1776
1777 return ohci->bus_time | cycle_time_seconds;
1778 }
1779
1780 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1781 {
1782 int reg;
1783
1784 mutex_lock(&ohci->phy_reg_mutex);
1785 reg = write_phy_reg(ohci, 7, port_index);
1786 if (reg >= 0)
1787 reg = read_phy_reg(ohci, 8);
1788 mutex_unlock(&ohci->phy_reg_mutex);
1789 if (reg < 0)
1790 return reg;
1791
1792 switch (reg & 0x0f) {
1793 case 0x06:
1794 return 2; /* is child node (connected to parent node) */
1795 case 0x0e:
1796 return 3; /* is parent node (connected to child node) */
1797 }
1798 return 1; /* not connected */
1799 }
1800
1801 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1802 int self_id_count)
1803 {
1804 int i;
1805 u32 entry;
1806
1807 for (i = 0; i < self_id_count; i++) {
1808 entry = ohci->self_id_buffer[i];
1809 if ((self_id & 0xff000000) == (entry & 0xff000000))
1810 return -1;
1811 if ((self_id & 0xff000000) < (entry & 0xff000000))
1812 return i;
1813 }
1814 return i;
1815 }
1816
1817 static int initiated_reset(struct fw_ohci *ohci)
1818 {
1819 int reg;
1820 int ret = 0;
1821
1822 mutex_lock(&ohci->phy_reg_mutex);
1823 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1824 if (reg >= 0) {
1825 reg = read_phy_reg(ohci, 8);
1826 reg |= 0x40;
1827 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1828 if (reg >= 0) {
1829 reg = read_phy_reg(ohci, 12); /* read register 12 */
1830 if (reg >= 0) {
1831 if ((reg & 0x08) == 0x08) {
1832 /* bit 3 indicates "initiated reset" */
1833 ret = 0x2;
1834 }
1835 }
1836 }
1837 }
1838 mutex_unlock(&ohci->phy_reg_mutex);
1839 return ret;
1840 }
1841
1842 /*
1843 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1844 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1845 * Construct the selfID from phy register contents.
1846 */
1847 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1848 {
1849 int reg, i, pos, status;
1850 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1851 u32 self_id = 0x8040c800;
1852
1853 reg = reg_read(ohci, OHCI1394_NodeID);
1854 if (!(reg & OHCI1394_NodeID_idValid)) {
1855 dev_notice(ohci->card.device,
1856 "node ID not valid, new bus reset in progress\n");
1857 return -EBUSY;
1858 }
1859 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1860
1861 reg = ohci_read_phy_reg(&ohci->card, 4);
1862 if (reg < 0)
1863 return reg;
1864 self_id |= ((reg & 0x07) << 8); /* power class */
1865
1866 reg = ohci_read_phy_reg(&ohci->card, 1);
1867 if (reg < 0)
1868 return reg;
1869 self_id |= ((reg & 0x3f) << 16); /* gap count */
1870
1871 for (i = 0; i < 3; i++) {
1872 status = get_status_for_port(ohci, i);
1873 if (status < 0)
1874 return status;
1875 self_id |= ((status & 0x3) << (6 - (i * 2)));
1876 }
1877
1878 self_id |= initiated_reset(ohci);
1879
1880 pos = get_self_id_pos(ohci, self_id, self_id_count);
1881 if (pos >= 0) {
1882 memmove(&(ohci->self_id_buffer[pos+1]),
1883 &(ohci->self_id_buffer[pos]),
1884 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1885 ohci->self_id_buffer[pos] = self_id;
1886 self_id_count++;
1887 }
1888 return self_id_count;
1889 }
1890
1891 static void bus_reset_work(struct work_struct *work)
1892 {
1893 struct fw_ohci *ohci =
1894 container_of(work, struct fw_ohci, bus_reset_work);
1895 int self_id_count, generation, new_generation, i, j;
1896 u32 reg;
1897 void *free_rom = NULL;
1898 dma_addr_t free_rom_bus = 0;
1899 bool is_new_root;
1900
1901 reg = reg_read(ohci, OHCI1394_NodeID);
1902 if (!(reg & OHCI1394_NodeID_idValid)) {
1903 dev_notice(ohci->card.device,
1904 "node ID not valid, new bus reset in progress\n");
1905 return;
1906 }
1907 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1908 dev_notice(ohci->card.device, "malconfigured bus\n");
1909 return;
1910 }
1911 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1912 OHCI1394_NodeID_nodeNumber);
1913
1914 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1915 if (!(ohci->is_root && is_new_root))
1916 reg_write(ohci, OHCI1394_LinkControlSet,
1917 OHCI1394_LinkControl_cycleMaster);
1918 ohci->is_root = is_new_root;
1919
1920 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1921 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1922 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1923 return;
1924 }
1925 /*
1926 * The count in the SelfIDCount register is the number of
1927 * bytes in the self ID receive buffer. Since we also receive
1928 * the inverted quadlets and a header quadlet, we shift one
1929 * bit extra to get the actual number of self IDs.
1930 */
1931 self_id_count = (reg >> 3) & 0xff;
1932
1933 if (self_id_count > 252) {
1934 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1935 return;
1936 }
1937
1938 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1939 rmb();
1940
1941 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1942 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1943 /*
1944 * If the invalid data looks like a cycle start packet,
1945 * it's likely to be the result of the cycle master
1946 * having a wrong gap count. In this case, the self IDs
1947 * so far are valid and should be processed so that the
1948 * bus manager can then correct the gap count.
1949 */
1950 if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1951 == 0xffff008f) {
1952 dev_notice(ohci->card.device,
1953 "ignoring spurious self IDs\n");
1954 self_id_count = j;
1955 break;
1956 } else {
1957 dev_notice(ohci->card.device,
1958 "inconsistent self IDs\n");
1959 return;
1960 }
1961 }
1962 ohci->self_id_buffer[j] =
1963 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1964 }
1965
1966 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1967 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1968 if (self_id_count < 0) {
1969 dev_notice(ohci->card.device,
1970 "could not construct local self ID\n");
1971 return;
1972 }
1973 }
1974
1975 if (self_id_count == 0) {
1976 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1977 return;
1978 }
1979 rmb();
1980
1981 /*
1982 * Check the consistency of the self IDs we just read. The
1983 * problem we face is that a new bus reset can start while we
1984 * read out the self IDs from the DMA buffer. If this happens,
1985 * the DMA buffer will be overwritten with new self IDs and we
1986 * will read out inconsistent data. The OHCI specification
1987 * (section 11.2) recommends a technique similar to
1988 * linux/seqlock.h, where we remember the generation of the
1989 * self IDs in the buffer before reading them out and compare
1990 * it to the current generation after reading them out. If
1991 * the two generations match we know we have a consistent set
1992 * of self IDs.
1993 */
1994
1995 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1996 if (new_generation != generation) {
1997 dev_notice(ohci->card.device,
1998 "new bus reset, discarding self ids\n");
1999 return;
2000 }
2001
2002 /* FIXME: Document how the locking works. */
2003 spin_lock_irq(&ohci->lock);
2004
2005 ohci->generation = -1; /* prevent AT packet queueing */
2006 context_stop(&ohci->at_request_ctx);
2007 context_stop(&ohci->at_response_ctx);
2008
2009 spin_unlock_irq(&ohci->lock);
2010
2011 /*
2012 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2013 * packets in the AT queues and software needs to drain them.
2014 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2015 */
2016 at_context_flush(&ohci->at_request_ctx);
2017 at_context_flush(&ohci->at_response_ctx);
2018
2019 spin_lock_irq(&ohci->lock);
2020
2021 ohci->generation = generation;
2022 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2023
2024 if (ohci->quirks & QUIRK_RESET_PACKET)
2025 ohci->request_generation = generation;
2026
2027 /*
2028 * This next bit is unrelated to the AT context stuff but we
2029 * have to do it under the spinlock also. If a new config rom
2030 * was set up before this reset, the old one is now no longer
2031 * in use and we can free it. Update the config rom pointers
2032 * to point to the current config rom and clear the
2033 * next_config_rom pointer so a new update can take place.
2034 */
2035
2036 if (ohci->next_config_rom != NULL) {
2037 if (ohci->next_config_rom != ohci->config_rom) {
2038 free_rom = ohci->config_rom;
2039 free_rom_bus = ohci->config_rom_bus;
2040 }
2041 ohci->config_rom = ohci->next_config_rom;
2042 ohci->config_rom_bus = ohci->next_config_rom_bus;
2043 ohci->next_config_rom = NULL;
2044
2045 /*
2046 * Restore config_rom image and manually update
2047 * config_rom registers. Writing the header quadlet
2048 * will indicate that the config rom is ready, so we
2049 * do that last.
2050 */
2051 reg_write(ohci, OHCI1394_BusOptions,
2052 be32_to_cpu(ohci->config_rom[2]));
2053 ohci->config_rom[0] = ohci->next_header;
2054 reg_write(ohci, OHCI1394_ConfigROMhdr,
2055 be32_to_cpu(ohci->next_header));
2056 }
2057
2058 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2059 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2060 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2061 #endif
2062
2063 spin_unlock_irq(&ohci->lock);
2064
2065 if (free_rom)
2066 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2067 free_rom, free_rom_bus);
2068
2069 log_selfids(ohci, generation, self_id_count);
2070
2071 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2072 self_id_count, ohci->self_id_buffer,
2073 ohci->csr_state_setclear_abdicate);
2074 ohci->csr_state_setclear_abdicate = false;
2075 }
2076
2077 static irqreturn_t irq_handler(int irq, void *data)
2078 {
2079 struct fw_ohci *ohci = data;
2080 u32 event, iso_event;
2081 int i;
2082
2083 event = reg_read(ohci, OHCI1394_IntEventClear);
2084
2085 if (!event || !~event)
2086 return IRQ_NONE;
2087
2088 /*
2089 * busReset and postedWriteErr must not be cleared yet
2090 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2091 */
2092 reg_write(ohci, OHCI1394_IntEventClear,
2093 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2094 log_irqs(ohci, event);
2095
2096 if (event & OHCI1394_selfIDComplete)
2097 queue_work(fw_workqueue, &ohci->bus_reset_work);
2098
2099 if (event & OHCI1394_RQPkt)
2100 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2101
2102 if (event & OHCI1394_RSPkt)
2103 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2104
2105 if (event & OHCI1394_reqTxComplete)
2106 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2107
2108 if (event & OHCI1394_respTxComplete)
2109 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2110
2111 if (event & OHCI1394_isochRx) {
2112 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2113 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2114
2115 while (iso_event) {
2116 i = ffs(iso_event) - 1;
2117 tasklet_schedule(
2118 &ohci->ir_context_list[i].context.tasklet);
2119 iso_event &= ~(1 << i);
2120 }
2121 }
2122
2123 if (event & OHCI1394_isochTx) {
2124 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2125 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2126
2127 while (iso_event) {
2128 i = ffs(iso_event) - 1;
2129 tasklet_schedule(
2130 &ohci->it_context_list[i].context.tasklet);
2131 iso_event &= ~(1 << i);
2132 }
2133 }
2134
2135 if (unlikely(event & OHCI1394_regAccessFail))
2136 dev_err(ohci->card.device, "register access failure\n");
2137
2138 if (unlikely(event & OHCI1394_postedWriteErr)) {
2139 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2140 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2141 reg_write(ohci, OHCI1394_IntEventClear,
2142 OHCI1394_postedWriteErr);
2143 if (printk_ratelimit())
2144 dev_err(ohci->card.device, "PCI posted write error\n");
2145 }
2146
2147 if (unlikely(event & OHCI1394_cycleTooLong)) {
2148 if (printk_ratelimit())
2149 dev_notice(ohci->card.device,
2150 "isochronous cycle too long\n");
2151 reg_write(ohci, OHCI1394_LinkControlSet,
2152 OHCI1394_LinkControl_cycleMaster);
2153 }
2154
2155 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2156 /*
2157 * We need to clear this event bit in order to make
2158 * cycleMatch isochronous I/O work. In theory we should
2159 * stop active cycleMatch iso contexts now and restart
2160 * them at least two cycles later. (FIXME?)
2161 */
2162 if (printk_ratelimit())
2163 dev_notice(ohci->card.device,
2164 "isochronous cycle inconsistent\n");
2165 }
2166
2167 if (unlikely(event & OHCI1394_unrecoverableError))
2168 handle_dead_contexts(ohci);
2169
2170 if (event & OHCI1394_cycle64Seconds) {
2171 spin_lock(&ohci->lock);
2172 update_bus_time(ohci);
2173 spin_unlock(&ohci->lock);
2174 } else
2175 flush_writes(ohci);
2176
2177 return IRQ_HANDLED;
2178 }
2179
2180 static int software_reset(struct fw_ohci *ohci)
2181 {
2182 u32 val;
2183 int i;
2184
2185 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2186 for (i = 0; i < 500; i++) {
2187 val = reg_read(ohci, OHCI1394_HCControlSet);
2188 if (!~val)
2189 return -ENODEV; /* Card was ejected. */
2190
2191 if (!(val & OHCI1394_HCControl_softReset))
2192 return 0;
2193
2194 msleep(1);
2195 }
2196
2197 return -EBUSY;
2198 }
2199
2200 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2201 {
2202 size_t size = length * 4;
2203
2204 memcpy(dest, src, size);
2205 if (size < CONFIG_ROM_SIZE)
2206 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2207 }
2208
2209 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2210 {
2211 bool enable_1394a;
2212 int ret, clear, set, offset;
2213
2214 /* Check if the driver should configure link and PHY. */
2215 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2216 OHCI1394_HCControl_programPhyEnable))
2217 return 0;
2218
2219 /* Paranoia: check whether the PHY supports 1394a, too. */
2220 enable_1394a = false;
2221 ret = read_phy_reg(ohci, 2);
2222 if (ret < 0)
2223 return ret;
2224 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2225 ret = read_paged_phy_reg(ohci, 1, 8);
2226 if (ret < 0)
2227 return ret;
2228 if (ret >= 1)
2229 enable_1394a = true;
2230 }
2231
2232 if (ohci->quirks & QUIRK_NO_1394A)
2233 enable_1394a = false;
2234
2235 /* Configure PHY and link consistently. */
2236 if (enable_1394a) {
2237 clear = 0;
2238 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2239 } else {
2240 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2241 set = 0;
2242 }
2243 ret = update_phy_reg(ohci, 5, clear, set);
2244 if (ret < 0)
2245 return ret;
2246
2247 if (enable_1394a)
2248 offset = OHCI1394_HCControlSet;
2249 else
2250 offset = OHCI1394_HCControlClear;
2251 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2252
2253 /* Clean up: configuration has been taken care of. */
2254 reg_write(ohci, OHCI1394_HCControlClear,
2255 OHCI1394_HCControl_programPhyEnable);
2256
2257 return 0;
2258 }
2259
2260 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2261 {
2262 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2263 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2264 int reg, i;
2265
2266 reg = read_phy_reg(ohci, 2);
2267 if (reg < 0)
2268 return reg;
2269 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2270 return 0;
2271
2272 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2273 reg = read_paged_phy_reg(ohci, 1, i + 10);
2274 if (reg < 0)
2275 return reg;
2276 if (reg != id[i])
2277 return 0;
2278 }
2279 return 1;
2280 }
2281
2282 static int ohci_enable(struct fw_card *card,
2283 const __be32 *config_rom, size_t length)
2284 {
2285 struct fw_ohci *ohci = fw_ohci(card);
2286 u32 lps, version, irqs;
2287 int i, ret;
2288
2289 if (software_reset(ohci)) {
2290 dev_err(card->device, "failed to reset ohci card\n");
2291 return -EBUSY;
2292 }
2293
2294 /*
2295 * Now enable LPS, which we need in order to start accessing
2296 * most of the registers. In fact, on some cards (ALI M5251),
2297 * accessing registers in the SClk domain without LPS enabled
2298 * will lock up the machine. Wait 50msec to make sure we have
2299 * full link enabled. However, with some cards (well, at least
2300 * a JMicron PCIe card), we have to try again sometimes.
2301 *
2302 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2303 * cannot actually use the phy at that time. These need tens of
2304 * millisecods pause between LPS write and first phy access too.
2305 *
2306 * But do not wait for 50msec on Agere/LSI cards. Their phy
2307 * arbitration state machine may time out during such a long wait.
2308 */
2309
2310 reg_write(ohci, OHCI1394_HCControlSet,
2311 OHCI1394_HCControl_LPS |
2312 OHCI1394_HCControl_postedWriteEnable);
2313 flush_writes(ohci);
2314
2315 if (!(ohci->quirks & QUIRK_PHY_LCTRL_TIMEOUT))
2316 msleep(50);
2317
2318 for (lps = 0, i = 0; !lps && i < 150; i++) {
2319 msleep(1);
2320 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2321 OHCI1394_HCControl_LPS;
2322 }
2323
2324 if (!lps) {
2325 dev_err(card->device, "failed to set Link Power Status\n");
2326 return -EIO;
2327 }
2328
2329 if (ohci->quirks & QUIRK_TI_SLLZ059) {
2330 ret = probe_tsb41ba3d(ohci);
2331 if (ret < 0)
2332 return ret;
2333 if (ret)
2334 dev_notice(card->device, "local TSB41BA3D phy\n");
2335 else
2336 ohci->quirks &= ~QUIRK_TI_SLLZ059;
2337 }
2338
2339 reg_write(ohci, OHCI1394_HCControlClear,
2340 OHCI1394_HCControl_noByteSwapData);
2341
2342 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2343 reg_write(ohci, OHCI1394_LinkControlSet,
2344 OHCI1394_LinkControl_cycleTimerEnable |
2345 OHCI1394_LinkControl_cycleMaster);
2346
2347 reg_write(ohci, OHCI1394_ATRetries,
2348 OHCI1394_MAX_AT_REQ_RETRIES |
2349 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2350 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2351 (200 << 16));
2352
2353 ohci->bus_time_running = false;
2354
2355 for (i = 0; i < 32; i++)
2356 if (ohci->ir_context_support & (1 << i))
2357 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2358 IR_CONTEXT_MULTI_CHANNEL_MODE);
2359
2360 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2361 if (version >= OHCI_VERSION_1_1) {
2362 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2363 0xfffffffe);
2364 card->broadcast_channel_auto_allocated = true;
2365 }
2366
2367 /* Get implemented bits of the priority arbitration request counter. */
2368 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2369 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2370 reg_write(ohci, OHCI1394_FairnessControl, 0);
2371 card->priority_budget_implemented = ohci->pri_req_max != 0;
2372
2373 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2374 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2375 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2376
2377 ret = configure_1394a_enhancements(ohci);
2378 if (ret < 0)
2379 return ret;
2380
2381 /* Activate link_on bit and contender bit in our self ID packets.*/
2382 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2383 if (ret < 0)
2384 return ret;
2385
2386 /*
2387 * When the link is not yet enabled, the atomic config rom
2388 * update mechanism described below in ohci_set_config_rom()
2389 * is not active. We have to update ConfigRomHeader and
2390 * BusOptions manually, and the write to ConfigROMmap takes
2391 * effect immediately. We tie this to the enabling of the
2392 * link, so we have a valid config rom before enabling - the
2393 * OHCI requires that ConfigROMhdr and BusOptions have valid
2394 * values before enabling.
2395 *
2396 * However, when the ConfigROMmap is written, some controllers
2397 * always read back quadlets 0 and 2 from the config rom to
2398 * the ConfigRomHeader and BusOptions registers on bus reset.
2399 * They shouldn't do that in this initial case where the link
2400 * isn't enabled. This means we have to use the same
2401 * workaround here, setting the bus header to 0 and then write
2402 * the right values in the bus reset tasklet.
2403 */
2404
2405 if (config_rom) {
2406 ohci->next_config_rom =
2407 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2408 &ohci->next_config_rom_bus,
2409 GFP_KERNEL);
2410 if (ohci->next_config_rom == NULL)
2411 return -ENOMEM;
2412
2413 copy_config_rom(ohci->next_config_rom, config_rom, length);
2414 } else {
2415 /*
2416 * In the suspend case, config_rom is NULL, which
2417 * means that we just reuse the old config rom.
2418 */
2419 ohci->next_config_rom = ohci->config_rom;
2420 ohci->next_config_rom_bus = ohci->config_rom_bus;
2421 }
2422
2423 ohci->next_header = ohci->next_config_rom[0];
2424 ohci->next_config_rom[0] = 0;
2425 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2426 reg_write(ohci, OHCI1394_BusOptions,
2427 be32_to_cpu(ohci->next_config_rom[2]));
2428 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2429
2430 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2431
2432 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2433 OHCI1394_RQPkt | OHCI1394_RSPkt |
2434 OHCI1394_isochTx | OHCI1394_isochRx |
2435 OHCI1394_postedWriteErr |
2436 OHCI1394_selfIDComplete |
2437 OHCI1394_regAccessFail |
2438 OHCI1394_cycleInconsistent |
2439 OHCI1394_unrecoverableError |
2440 OHCI1394_cycleTooLong |
2441 OHCI1394_masterIntEnable;
2442 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2443 irqs |= OHCI1394_busReset;
2444 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2445
2446 reg_write(ohci, OHCI1394_HCControlSet,
2447 OHCI1394_HCControl_linkEnable |
2448 OHCI1394_HCControl_BIBimageValid);
2449
2450 reg_write(ohci, OHCI1394_LinkControlSet,
2451 OHCI1394_LinkControl_rcvSelfID |
2452 OHCI1394_LinkControl_rcvPhyPkt);
2453
2454 ar_context_run(&ohci->ar_request_ctx);
2455 ar_context_run(&ohci->ar_response_ctx);
2456
2457 flush_writes(ohci);
2458
2459 /* We are ready to go, reset bus to finish initialization. */
2460 fw_schedule_bus_reset(&ohci->card, false, true);
2461
2462 return 0;
2463 }
2464
2465 static int ohci_set_config_rom(struct fw_card *card,
2466 const __be32 *config_rom, size_t length)
2467 {
2468 struct fw_ohci *ohci;
2469 __be32 *next_config_rom;
2470 dma_addr_t uninitialized_var(next_config_rom_bus);
2471
2472 ohci = fw_ohci(card);
2473
2474 /*
2475 * When the OHCI controller is enabled, the config rom update
2476 * mechanism is a bit tricky, but easy enough to use. See
2477 * section 5.5.6 in the OHCI specification.
2478 *
2479 * The OHCI controller caches the new config rom address in a
2480 * shadow register (ConfigROMmapNext) and needs a bus reset
2481 * for the changes to take place. When the bus reset is
2482 * detected, the controller loads the new values for the
2483 * ConfigRomHeader and BusOptions registers from the specified
2484 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2485 * shadow register. All automatically and atomically.
2486 *
2487 * Now, there's a twist to this story. The automatic load of
2488 * ConfigRomHeader and BusOptions doesn't honor the
2489 * noByteSwapData bit, so with a be32 config rom, the
2490 * controller will load be32 values in to these registers
2491 * during the atomic update, even on litte endian
2492 * architectures. The workaround we use is to put a 0 in the
2493 * header quadlet; 0 is endian agnostic and means that the
2494 * config rom isn't ready yet. In the bus reset tasklet we
2495 * then set up the real values for the two registers.
2496 *
2497 * We use ohci->lock to avoid racing with the code that sets
2498 * ohci->next_config_rom to NULL (see bus_reset_work).
2499 */
2500
2501 next_config_rom =
2502 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2503 &next_config_rom_bus, GFP_KERNEL);
2504 if (next_config_rom == NULL)
2505 return -ENOMEM;
2506
2507 spin_lock_irq(&ohci->lock);
2508
2509 /*
2510 * If there is not an already pending config_rom update,
2511 * push our new allocation into the ohci->next_config_rom
2512 * and then mark the local variable as null so that we
2513 * won't deallocate the new buffer.
2514 *
2515 * OTOH, if there is a pending config_rom update, just
2516 * use that buffer with the new config_rom data, and
2517 * let this routine free the unused DMA allocation.
2518 */
2519
2520 if (ohci->next_config_rom == NULL) {
2521 ohci->next_config_rom = next_config_rom;
2522 ohci->next_config_rom_bus = next_config_rom_bus;
2523 next_config_rom = NULL;
2524 }
2525
2526 copy_config_rom(ohci->next_config_rom, config_rom, length);
2527
2528 ohci->next_header = config_rom[0];
2529 ohci->next_config_rom[0] = 0;
2530
2531 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2532
2533 spin_unlock_irq(&ohci->lock);
2534
2535 /* If we didn't use the DMA allocation, delete it. */
2536 if (next_config_rom != NULL)
2537 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2538 next_config_rom, next_config_rom_bus);
2539
2540 /*
2541 * Now initiate a bus reset to have the changes take
2542 * effect. We clean up the old config rom memory and DMA
2543 * mappings in the bus reset tasklet, since the OHCI
2544 * controller could need to access it before the bus reset
2545 * takes effect.
2546 */
2547
2548 fw_schedule_bus_reset(&ohci->card, true, true);
2549
2550 return 0;
2551 }
2552
2553 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2554 {
2555 struct fw_ohci *ohci = fw_ohci(card);
2556
2557 at_context_transmit(&ohci->at_request_ctx, packet);
2558 }
2559
2560 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2561 {
2562 struct fw_ohci *ohci = fw_ohci(card);
2563
2564 at_context_transmit(&ohci->at_response_ctx, packet);
2565 }
2566
2567 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2568 {
2569 struct fw_ohci *ohci = fw_ohci(card);
2570 struct context *ctx = &ohci->at_request_ctx;
2571 struct driver_data *driver_data = packet->driver_data;
2572 int ret = -ENOENT;
2573
2574 tasklet_disable(&ctx->tasklet);
2575
2576 if (packet->ack != 0)
2577 goto out;
2578
2579 if (packet->payload_mapped)
2580 dma_unmap_single(ohci->card.device, packet->payload_bus,
2581 packet->payload_length, DMA_TO_DEVICE);
2582
2583 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2584 driver_data->packet = NULL;
2585 packet->ack = RCODE_CANCELLED;
2586 packet->callback(packet, &ohci->card, packet->ack);
2587 ret = 0;
2588 out:
2589 tasklet_enable(&ctx->tasklet);
2590
2591 return ret;
2592 }
2593
2594 static int ohci_enable_phys_dma(struct fw_card *card,
2595 int node_id, int generation)
2596 {
2597 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2598 return 0;
2599 #else
2600 struct fw_ohci *ohci = fw_ohci(card);
2601 unsigned long flags;
2602 int n, ret = 0;
2603
2604 /*
2605 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2606 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2607 */
2608
2609 spin_lock_irqsave(&ohci->lock, flags);
2610
2611 if (ohci->generation != generation) {
2612 ret = -ESTALE;
2613 goto out;
2614 }
2615
2616 /*
2617 * Note, if the node ID contains a non-local bus ID, physical DMA is
2618 * enabled for _all_ nodes on remote buses.
2619 */
2620
2621 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2622 if (n < 32)
2623 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2624 else
2625 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2626
2627 flush_writes(ohci);
2628 out:
2629 spin_unlock_irqrestore(&ohci->lock, flags);
2630
2631 return ret;
2632 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2633 }
2634
2635 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2636 {
2637 struct fw_ohci *ohci = fw_ohci(card);
2638 unsigned long flags;
2639 u32 value;
2640
2641 switch (csr_offset) {
2642 case CSR_STATE_CLEAR:
2643 case CSR_STATE_SET:
2644 if (ohci->is_root &&
2645 (reg_read(ohci, OHCI1394_LinkControlSet) &
2646 OHCI1394_LinkControl_cycleMaster))
2647 value = CSR_STATE_BIT_CMSTR;
2648 else
2649 value = 0;
2650 if (ohci->csr_state_setclear_abdicate)
2651 value |= CSR_STATE_BIT_ABDICATE;
2652
2653 return value;
2654
2655 case CSR_NODE_IDS:
2656 return reg_read(ohci, OHCI1394_NodeID) << 16;
2657
2658 case CSR_CYCLE_TIME:
2659 return get_cycle_time(ohci);
2660
2661 case CSR_BUS_TIME:
2662 /*
2663 * We might be called just after the cycle timer has wrapped
2664 * around but just before the cycle64Seconds handler, so we
2665 * better check here, too, if the bus time needs to be updated.
2666 */
2667 spin_lock_irqsave(&ohci->lock, flags);
2668 value = update_bus_time(ohci);
2669 spin_unlock_irqrestore(&ohci->lock, flags);
2670 return value;
2671
2672 case CSR_BUSY_TIMEOUT:
2673 value = reg_read(ohci, OHCI1394_ATRetries);
2674 return (value >> 4) & 0x0ffff00f;
2675
2676 case CSR_PRIORITY_BUDGET:
2677 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2678 (ohci->pri_req_max << 8);
2679
2680 default:
2681 WARN_ON(1);
2682 return 0;
2683 }
2684 }
2685
2686 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2687 {
2688 struct fw_ohci *ohci = fw_ohci(card);
2689 unsigned long flags;
2690
2691 switch (csr_offset) {
2692 case CSR_STATE_CLEAR:
2693 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2694 reg_write(ohci, OHCI1394_LinkControlClear,
2695 OHCI1394_LinkControl_cycleMaster);
2696 flush_writes(ohci);
2697 }
2698 if (value & CSR_STATE_BIT_ABDICATE)
2699 ohci->csr_state_setclear_abdicate = false;
2700 break;
2701
2702 case CSR_STATE_SET:
2703 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2704 reg_write(ohci, OHCI1394_LinkControlSet,
2705 OHCI1394_LinkControl_cycleMaster);
2706 flush_writes(ohci);
2707 }
2708 if (value & CSR_STATE_BIT_ABDICATE)
2709 ohci->csr_state_setclear_abdicate = true;
2710 break;
2711
2712 case CSR_NODE_IDS:
2713 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2714 flush_writes(ohci);
2715 break;
2716
2717 case CSR_CYCLE_TIME:
2718 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2719 reg_write(ohci, OHCI1394_IntEventSet,
2720 OHCI1394_cycleInconsistent);
2721 flush_writes(ohci);
2722 break;
2723
2724 case CSR_BUS_TIME:
2725 spin_lock_irqsave(&ohci->lock, flags);
2726 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2727 (value & ~0x7f);
2728 spin_unlock_irqrestore(&ohci->lock, flags);
2729 break;
2730
2731 case CSR_BUSY_TIMEOUT:
2732 value = (value & 0xf) | ((value & 0xf) << 4) |
2733 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2734 reg_write(ohci, OHCI1394_ATRetries, value);
2735 flush_writes(ohci);
2736 break;
2737
2738 case CSR_PRIORITY_BUDGET:
2739 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2740 flush_writes(ohci);
2741 break;
2742
2743 default:
2744 WARN_ON(1);
2745 break;
2746 }
2747 }
2748
2749 static void flush_iso_completions(struct iso_context *ctx)
2750 {
2751 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2752 ctx->header_length, ctx->header,
2753 ctx->base.callback_data);
2754 ctx->header_length = 0;
2755 }
2756
2757 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2758 {
2759 u32 *ctx_hdr;
2760
2761 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE)
2762 flush_iso_completions(ctx);
2763
2764 ctx_hdr = ctx->header + ctx->header_length;
2765 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2766
2767 /*
2768 * The two iso header quadlets are byteswapped to little
2769 * endian by the controller, but we want to present them
2770 * as big endian for consistency with the bus endianness.
2771 */
2772 if (ctx->base.header_size > 0)
2773 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2774 if (ctx->base.header_size > 4)
2775 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2776 if (ctx->base.header_size > 8)
2777 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2778 ctx->header_length += ctx->base.header_size;
2779 }
2780
2781 static int handle_ir_packet_per_buffer(struct context *context,
2782 struct descriptor *d,
2783 struct descriptor *last)
2784 {
2785 struct iso_context *ctx =
2786 container_of(context, struct iso_context, context);
2787 struct descriptor *pd;
2788 u32 buffer_dma;
2789
2790 for (pd = d; pd <= last; pd++)
2791 if (pd->transfer_status)
2792 break;
2793 if (pd > last)
2794 /* Descriptor(s) not done yet, stop iteration */
2795 return 0;
2796
2797 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2798 d++;
2799 buffer_dma = le32_to_cpu(d->data_address);
2800 dma_sync_single_range_for_cpu(context->ohci->card.device,
2801 buffer_dma & PAGE_MASK,
2802 buffer_dma & ~PAGE_MASK,
2803 le16_to_cpu(d->req_count),
2804 DMA_FROM_DEVICE);
2805 }
2806
2807 copy_iso_headers(ctx, (u32 *) (last + 1));
2808
2809 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2810 flush_iso_completions(ctx);
2811
2812 return 1;
2813 }
2814
2815 /* d == last because each descriptor block is only a single descriptor. */
2816 static int handle_ir_buffer_fill(struct context *context,
2817 struct descriptor *d,
2818 struct descriptor *last)
2819 {
2820 struct iso_context *ctx =
2821 container_of(context, struct iso_context, context);
2822 unsigned int req_count, res_count, completed;
2823 u32 buffer_dma;
2824
2825 req_count = le16_to_cpu(last->req_count);
2826 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2827 completed = req_count - res_count;
2828 buffer_dma = le32_to_cpu(last->data_address);
2829
2830 if (completed > 0) {
2831 ctx->mc_buffer_bus = buffer_dma;
2832 ctx->mc_completed = completed;
2833 }
2834
2835 if (res_count != 0)
2836 /* Descriptor(s) not done yet, stop iteration */
2837 return 0;
2838
2839 dma_sync_single_range_for_cpu(context->ohci->card.device,
2840 buffer_dma & PAGE_MASK,
2841 buffer_dma & ~PAGE_MASK,
2842 completed, DMA_FROM_DEVICE);
2843
2844 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2845 ctx->base.callback.mc(&ctx->base,
2846 buffer_dma + completed,
2847 ctx->base.callback_data);
2848 ctx->mc_completed = 0;
2849 }
2850
2851 return 1;
2852 }
2853
2854 static void flush_ir_buffer_fill(struct iso_context *ctx)
2855 {
2856 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2857 ctx->mc_buffer_bus & PAGE_MASK,
2858 ctx->mc_buffer_bus & ~PAGE_MASK,
2859 ctx->mc_completed, DMA_FROM_DEVICE);
2860
2861 ctx->base.callback.mc(&ctx->base,
2862 ctx->mc_buffer_bus + ctx->mc_completed,
2863 ctx->base.callback_data);
2864 ctx->mc_completed = 0;
2865 }
2866
2867 static inline void sync_it_packet_for_cpu(struct context *context,
2868 struct descriptor *pd)
2869 {
2870 __le16 control;
2871 u32 buffer_dma;
2872
2873 /* only packets beginning with OUTPUT_MORE* have data buffers */
2874 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2875 return;
2876
2877 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2878 pd += 2;
2879
2880 /*
2881 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2882 * data buffer is in the context program's coherent page and must not
2883 * be synced.
2884 */
2885 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2886 (context->current_bus & PAGE_MASK)) {
2887 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2888 return;
2889 pd++;
2890 }
2891
2892 do {
2893 buffer_dma = le32_to_cpu(pd->data_address);
2894 dma_sync_single_range_for_cpu(context->ohci->card.device,
2895 buffer_dma & PAGE_MASK,
2896 buffer_dma & ~PAGE_MASK,
2897 le16_to_cpu(pd->req_count),
2898 DMA_TO_DEVICE);
2899 control = pd->control;
2900 pd++;
2901 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2902 }
2903
2904 static int handle_it_packet(struct context *context,
2905 struct descriptor *d,
2906 struct descriptor *last)
2907 {
2908 struct iso_context *ctx =
2909 container_of(context, struct iso_context, context);
2910 struct descriptor *pd;
2911 __be32 *ctx_hdr;
2912
2913 for (pd = d; pd <= last; pd++)
2914 if (pd->transfer_status)
2915 break;
2916 if (pd > last)
2917 /* Descriptor(s) not done yet, stop iteration */
2918 return 0;
2919
2920 sync_it_packet_for_cpu(context, d);
2921
2922 if (ctx->header_length + 4 > PAGE_SIZE)
2923 flush_iso_completions(ctx);
2924
2925 ctx_hdr = ctx->header + ctx->header_length;
2926 ctx->last_timestamp = le16_to_cpu(last->res_count);
2927 /* Present this value as big-endian to match the receive code */
2928 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2929 le16_to_cpu(pd->res_count));
2930 ctx->header_length += 4;
2931
2932 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2933 flush_iso_completions(ctx);
2934
2935 return 1;
2936 }
2937
2938 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2939 {
2940 u32 hi = channels >> 32, lo = channels;
2941
2942 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2943 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2944 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2945 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2946 mmiowb();
2947 ohci->mc_channels = channels;
2948 }
2949
2950 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2951 int type, int channel, size_t header_size)
2952 {
2953 struct fw_ohci *ohci = fw_ohci(card);
2954 struct iso_context *uninitialized_var(ctx);
2955 descriptor_callback_t uninitialized_var(callback);
2956 u64 *uninitialized_var(channels);
2957 u32 *uninitialized_var(mask), uninitialized_var(regs);
2958 int index, ret = -EBUSY;
2959
2960 spin_lock_irq(&ohci->lock);
2961
2962 switch (type) {
2963 case FW_ISO_CONTEXT_TRANSMIT:
2964 mask = &ohci->it_context_mask;
2965 callback = handle_it_packet;
2966 index = ffs(*mask) - 1;
2967 if (index >= 0) {
2968 *mask &= ~(1 << index);
2969 regs = OHCI1394_IsoXmitContextBase(index);
2970 ctx = &ohci->it_context_list[index];
2971 }
2972 break;
2973
2974 case FW_ISO_CONTEXT_RECEIVE:
2975 channels = &ohci->ir_context_channels;
2976 mask = &ohci->ir_context_mask;
2977 callback = handle_ir_packet_per_buffer;
2978 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2979 if (index >= 0) {
2980 *channels &= ~(1ULL << channel);
2981 *mask &= ~(1 << index);
2982 regs = OHCI1394_IsoRcvContextBase(index);
2983 ctx = &ohci->ir_context_list[index];
2984 }
2985 break;
2986
2987 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2988 mask = &ohci->ir_context_mask;
2989 callback = handle_ir_buffer_fill;
2990 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2991 if (index >= 0) {
2992 ohci->mc_allocated = true;
2993 *mask &= ~(1 << index);
2994 regs = OHCI1394_IsoRcvContextBase(index);
2995 ctx = &ohci->ir_context_list[index];
2996 }
2997 break;
2998
2999 default:
3000 index = -1;
3001 ret = -ENOSYS;
3002 }
3003
3004 spin_unlock_irq(&ohci->lock);
3005
3006 if (index < 0)
3007 return ERR_PTR(ret);
3008
3009 memset(ctx, 0, sizeof(*ctx));
3010 ctx->header_length = 0;
3011 ctx->header = (void *) __get_free_page(GFP_KERNEL);
3012 if (ctx->header == NULL) {
3013 ret = -ENOMEM;
3014 goto out;
3015 }
3016 ret = context_init(&ctx->context, ohci, regs, callback);
3017 if (ret < 0)
3018 goto out_with_header;
3019
3020 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3021 set_multichannel_mask(ohci, 0);
3022 ctx->mc_completed = 0;
3023 }
3024
3025 return &ctx->base;
3026
3027 out_with_header:
3028 free_page((unsigned long)ctx->header);
3029 out:
3030 spin_lock_irq(&ohci->lock);
3031
3032 switch (type) {
3033 case FW_ISO_CONTEXT_RECEIVE:
3034 *channels |= 1ULL << channel;
3035 break;
3036
3037 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3038 ohci->mc_allocated = false;
3039 break;
3040 }
3041 *mask |= 1 << index;
3042
3043 spin_unlock_irq(&ohci->lock);
3044
3045 return ERR_PTR(ret);
3046 }
3047
3048 static int ohci_start_iso(struct fw_iso_context *base,
3049 s32 cycle, u32 sync, u32 tags)
3050 {
3051 struct iso_context *ctx = container_of(base, struct iso_context, base);
3052 struct fw_ohci *ohci = ctx->context.ohci;
3053 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3054 int index;
3055
3056 /* the controller cannot start without any queued packets */
3057 if (ctx->context.last->branch_address == 0)
3058 return -ENODATA;
3059
3060 switch (ctx->base.type) {
3061 case FW_ISO_CONTEXT_TRANSMIT:
3062 index = ctx - ohci->it_context_list;
3063 match = 0;
3064 if (cycle >= 0)
3065 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3066 (cycle & 0x7fff) << 16;
3067
3068 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3069 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3070 context_run(&ctx->context, match);
3071 break;
3072
3073 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3074 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3075 /* fall through */
3076 case FW_ISO_CONTEXT_RECEIVE:
3077 index = ctx - ohci->ir_context_list;
3078 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3079 if (cycle >= 0) {
3080 match |= (cycle & 0x07fff) << 12;
3081 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3082 }
3083
3084 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3085 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3086 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3087 context_run(&ctx->context, control);
3088
3089 ctx->sync = sync;
3090 ctx->tags = tags;
3091
3092 break;
3093 }
3094
3095 return 0;
3096 }
3097
3098 static int ohci_stop_iso(struct fw_iso_context *base)
3099 {
3100 struct fw_ohci *ohci = fw_ohci(base->card);
3101 struct iso_context *ctx = container_of(base, struct iso_context, base);
3102 int index;
3103
3104 switch (ctx->base.type) {
3105 case FW_ISO_CONTEXT_TRANSMIT:
3106 index = ctx - ohci->it_context_list;
3107 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3108 break;
3109
3110 case FW_ISO_CONTEXT_RECEIVE:
3111 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3112 index = ctx - ohci->ir_context_list;
3113 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3114 break;
3115 }
3116 flush_writes(ohci);
3117 context_stop(&ctx->context);
3118 tasklet_kill(&ctx->context.tasklet);
3119
3120 return 0;
3121 }
3122
3123 static void ohci_free_iso_context(struct fw_iso_context *base)
3124 {
3125 struct fw_ohci *ohci = fw_ohci(base->card);
3126 struct iso_context *ctx = container_of(base, struct iso_context, base);
3127 unsigned long flags;
3128 int index;
3129
3130 ohci_stop_iso(base);
3131 context_release(&ctx->context);
3132 free_page((unsigned long)ctx->header);
3133
3134 spin_lock_irqsave(&ohci->lock, flags);
3135
3136 switch (base->type) {
3137 case FW_ISO_CONTEXT_TRANSMIT:
3138 index = ctx - ohci->it_context_list;
3139 ohci->it_context_mask |= 1 << index;
3140 break;
3141
3142 case FW_ISO_CONTEXT_RECEIVE:
3143 index = ctx - ohci->ir_context_list;
3144 ohci->ir_context_mask |= 1 << index;
3145 ohci->ir_context_channels |= 1ULL << base->channel;
3146 break;
3147
3148 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3149 index = ctx - ohci->ir_context_list;
3150 ohci->ir_context_mask |= 1 << index;
3151 ohci->ir_context_channels |= ohci->mc_channels;
3152 ohci->mc_channels = 0;
3153 ohci->mc_allocated = false;
3154 break;
3155 }
3156
3157 spin_unlock_irqrestore(&ohci->lock, flags);
3158 }
3159
3160 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3161 {
3162 struct fw_ohci *ohci = fw_ohci(base->card);
3163 unsigned long flags;
3164 int ret;
3165
3166 switch (base->type) {
3167 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3168
3169 spin_lock_irqsave(&ohci->lock, flags);
3170
3171 /* Don't allow multichannel to grab other contexts' channels. */
3172 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3173 *channels = ohci->ir_context_channels;
3174 ret = -EBUSY;
3175 } else {
3176 set_multichannel_mask(ohci, *channels);
3177 ret = 0;
3178 }
3179
3180 spin_unlock_irqrestore(&ohci->lock, flags);
3181
3182 break;
3183 default:
3184 ret = -EINVAL;
3185 }
3186
3187 return ret;
3188 }
3189
3190 #ifdef CONFIG_PM
3191 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3192 {
3193 int i;
3194 struct iso_context *ctx;
3195
3196 for (i = 0 ; i < ohci->n_ir ; i++) {
3197 ctx = &ohci->ir_context_list[i];
3198 if (ctx->context.running)
3199 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3200 }
3201
3202 for (i = 0 ; i < ohci->n_it ; i++) {
3203 ctx = &ohci->it_context_list[i];
3204 if (ctx->context.running)
3205 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3206 }
3207 }
3208 #endif
3209
3210 static int queue_iso_transmit(struct iso_context *ctx,
3211 struct fw_iso_packet *packet,
3212 struct fw_iso_buffer *buffer,
3213 unsigned long payload)
3214 {
3215 struct descriptor *d, *last, *pd;
3216 struct fw_iso_packet *p;
3217 __le32 *header;
3218 dma_addr_t d_bus, page_bus;
3219 u32 z, header_z, payload_z, irq;
3220 u32 payload_index, payload_end_index, next_page_index;
3221 int page, end_page, i, length, offset;
3222
3223 p = packet;
3224 payload_index = payload;
3225
3226 if (p->skip)
3227 z = 1;
3228 else
3229 z = 2;
3230 if (p->header_length > 0)
3231 z++;
3232
3233 /* Determine the first page the payload isn't contained in. */
3234 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3235 if (p->payload_length > 0)
3236 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3237 else
3238 payload_z = 0;
3239
3240 z += payload_z;
3241
3242 /* Get header size in number of descriptors. */
3243 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3244
3245 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3246 if (d == NULL)
3247 return -ENOMEM;
3248
3249 if (!p->skip) {
3250 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3251 d[0].req_count = cpu_to_le16(8);
3252 /*
3253 * Link the skip address to this descriptor itself. This causes
3254 * a context to skip a cycle whenever lost cycles or FIFO
3255 * overruns occur, without dropping the data. The application
3256 * should then decide whether this is an error condition or not.
3257 * FIXME: Make the context's cycle-lost behaviour configurable?
3258 */
3259 d[0].branch_address = cpu_to_le32(d_bus | z);
3260
3261 header = (__le32 *) &d[1];
3262 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3263 IT_HEADER_TAG(p->tag) |
3264 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3265 IT_HEADER_CHANNEL(ctx->base.channel) |
3266 IT_HEADER_SPEED(ctx->base.speed));
3267 header[1] =
3268 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3269 p->payload_length));
3270 }
3271
3272 if (p->header_length > 0) {
3273 d[2].req_count = cpu_to_le16(p->header_length);
3274 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3275 memcpy(&d[z], p->header, p->header_length);
3276 }
3277
3278 pd = d + z - payload_z;
3279 payload_end_index = payload_index + p->payload_length;
3280 for (i = 0; i < payload_z; i++) {
3281 page = payload_index >> PAGE_SHIFT;
3282 offset = payload_index & ~PAGE_MASK;
3283 next_page_index = (page + 1) << PAGE_SHIFT;
3284 length =
3285 min(next_page_index, payload_end_index) - payload_index;
3286 pd[i].req_count = cpu_to_le16(length);
3287
3288 page_bus = page_private(buffer->pages[page]);
3289 pd[i].data_address = cpu_to_le32(page_bus + offset);
3290
3291 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3292 page_bus, offset, length,
3293 DMA_TO_DEVICE);
3294
3295 payload_index += length;
3296 }
3297
3298 if (p->interrupt)
3299 irq = DESCRIPTOR_IRQ_ALWAYS;
3300 else
3301 irq = DESCRIPTOR_NO_IRQ;
3302
3303 last = z == 2 ? d : d + z - 1;
3304 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3305 DESCRIPTOR_STATUS |
3306 DESCRIPTOR_BRANCH_ALWAYS |
3307 irq);
3308
3309 context_append(&ctx->context, d, z, header_z);
3310
3311 return 0;
3312 }
3313
3314 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3315 struct fw_iso_packet *packet,
3316 struct fw_iso_buffer *buffer,
3317 unsigned long payload)
3318 {
3319 struct device *device = ctx->context.ohci->card.device;
3320 struct descriptor *d, *pd;
3321 dma_addr_t d_bus, page_bus;
3322 u32 z, header_z, rest;
3323 int i, j, length;
3324 int page, offset, packet_count, header_size, payload_per_buffer;
3325
3326 /*
3327 * The OHCI controller puts the isochronous header and trailer in the
3328 * buffer, so we need at least 8 bytes.
3329 */
3330 packet_count = packet->header_length / ctx->base.header_size;
3331 header_size = max(ctx->base.header_size, (size_t)8);
3332
3333 /* Get header size in number of descriptors. */
3334 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3335 page = payload >> PAGE_SHIFT;
3336 offset = payload & ~PAGE_MASK;
3337 payload_per_buffer = packet->payload_length / packet_count;
3338
3339 for (i = 0; i < packet_count; i++) {
3340 /* d points to the header descriptor */
3341 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3342 d = context_get_descriptors(&ctx->context,
3343 z + header_z, &d_bus);
3344 if (d == NULL)
3345 return -ENOMEM;
3346
3347 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3348 DESCRIPTOR_INPUT_MORE);
3349 if (packet->skip && i == 0)
3350 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3351 d->req_count = cpu_to_le16(header_size);
3352 d->res_count = d->req_count;
3353 d->transfer_status = 0;
3354 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3355
3356 rest = payload_per_buffer;
3357 pd = d;
3358 for (j = 1; j < z; j++) {
3359 pd++;
3360 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3361 DESCRIPTOR_INPUT_MORE);
3362
3363 if (offset + rest < PAGE_SIZE)
3364 length = rest;
3365 else
3366 length = PAGE_SIZE - offset;
3367 pd->req_count = cpu_to_le16(length);
3368 pd->res_count = pd->req_count;
3369 pd->transfer_status = 0;
3370
3371 page_bus = page_private(buffer->pages[page]);
3372 pd->data_address = cpu_to_le32(page_bus + offset);
3373
3374 dma_sync_single_range_for_device(device, page_bus,
3375 offset, length,
3376 DMA_FROM_DEVICE);
3377
3378 offset = (offset + length) & ~PAGE_MASK;
3379 rest -= length;
3380 if (offset == 0)
3381 page++;
3382 }
3383 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3384 DESCRIPTOR_INPUT_LAST |
3385 DESCRIPTOR_BRANCH_ALWAYS);
3386 if (packet->interrupt && i == packet_count - 1)
3387 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3388
3389 context_append(&ctx->context, d, z, header_z);
3390 }
3391
3392 return 0;
3393 }
3394
3395 static int queue_iso_buffer_fill(struct iso_context *ctx,
3396 struct fw_iso_packet *packet,
3397 struct fw_iso_buffer *buffer,
3398 unsigned long payload)
3399 {
3400 struct descriptor *d;
3401 dma_addr_t d_bus, page_bus;
3402 int page, offset, rest, z, i, length;
3403
3404 page = payload >> PAGE_SHIFT;
3405 offset = payload & ~PAGE_MASK;
3406 rest = packet->payload_length;
3407
3408 /* We need one descriptor for each page in the buffer. */
3409 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3410
3411 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3412 return -EFAULT;
3413
3414 for (i = 0; i < z; i++) {
3415 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3416 if (d == NULL)
3417 return -ENOMEM;
3418
3419 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3420 DESCRIPTOR_BRANCH_ALWAYS);
3421 if (packet->skip && i == 0)
3422 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3423 if (packet->interrupt && i == z - 1)
3424 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3425
3426 if (offset + rest < PAGE_SIZE)
3427 length = rest;
3428 else
3429 length = PAGE_SIZE - offset;
3430 d->req_count = cpu_to_le16(length);
3431 d->res_count = d->req_count;
3432 d->transfer_status = 0;
3433
3434 page_bus = page_private(buffer->pages[page]);
3435 d->data_address = cpu_to_le32(page_bus + offset);
3436
3437 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3438 page_bus, offset, length,
3439 DMA_FROM_DEVICE);
3440
3441 rest -= length;
3442 offset = 0;
3443 page++;
3444
3445 context_append(&ctx->context, d, 1, 0);
3446 }
3447
3448 return 0;
3449 }
3450
3451 static int ohci_queue_iso(struct fw_iso_context *base,
3452 struct fw_iso_packet *packet,
3453 struct fw_iso_buffer *buffer,
3454 unsigned long payload)
3455 {
3456 struct iso_context *ctx = container_of(base, struct iso_context, base);
3457 unsigned long flags;
3458 int ret = -ENOSYS;
3459
3460 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3461 switch (base->type) {
3462 case FW_ISO_CONTEXT_TRANSMIT:
3463 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3464 break;
3465 case FW_ISO_CONTEXT_RECEIVE:
3466 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3467 break;
3468 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3469 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3470 break;
3471 }
3472 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3473
3474 return ret;
3475 }
3476
3477 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3478 {
3479 struct context *ctx =
3480 &container_of(base, struct iso_context, base)->context;
3481
3482 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3483 }
3484
3485 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3486 {
3487 struct iso_context *ctx = container_of(base, struct iso_context, base);
3488 int ret = 0;
3489
3490 tasklet_disable(&ctx->context.tasklet);
3491
3492 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3493 context_tasklet((unsigned long)&ctx->context);
3494
3495 switch (base->type) {
3496 case FW_ISO_CONTEXT_TRANSMIT:
3497 case FW_ISO_CONTEXT_RECEIVE:
3498 if (ctx->header_length != 0)
3499 flush_iso_completions(ctx);
3500 break;
3501 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3502 if (ctx->mc_completed != 0)
3503 flush_ir_buffer_fill(ctx);
3504 break;
3505 default:
3506 ret = -ENOSYS;
3507 }
3508
3509 clear_bit_unlock(0, &ctx->flushing_completions);
3510 smp_mb__after_clear_bit();
3511 }
3512
3513 tasklet_enable(&ctx->context.tasklet);
3514
3515 return ret;
3516 }
3517
3518 static const struct fw_card_driver ohci_driver = {
3519 .enable = ohci_enable,
3520 .read_phy_reg = ohci_read_phy_reg,
3521 .update_phy_reg = ohci_update_phy_reg,
3522 .set_config_rom = ohci_set_config_rom,
3523 .send_request = ohci_send_request,
3524 .send_response = ohci_send_response,
3525 .cancel_packet = ohci_cancel_packet,
3526 .enable_phys_dma = ohci_enable_phys_dma,
3527 .read_csr = ohci_read_csr,
3528 .write_csr = ohci_write_csr,
3529
3530 .allocate_iso_context = ohci_allocate_iso_context,
3531 .free_iso_context = ohci_free_iso_context,
3532 .set_iso_channels = ohci_set_iso_channels,
3533 .queue_iso = ohci_queue_iso,
3534 .flush_queue_iso = ohci_flush_queue_iso,
3535 .flush_iso_completions = ohci_flush_iso_completions,
3536 .start_iso = ohci_start_iso,
3537 .stop_iso = ohci_stop_iso,
3538 };
3539
3540 #ifdef CONFIG_PPC_PMAC
3541 static void pmac_ohci_on(struct pci_dev *dev)
3542 {
3543 if (machine_is(powermac)) {
3544 struct device_node *ofn = pci_device_to_OF_node(dev);
3545
3546 if (ofn) {
3547 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3548 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3549 }
3550 }
3551 }
3552
3553 static void pmac_ohci_off(struct pci_dev *dev)
3554 {
3555 if (machine_is(powermac)) {
3556 struct device_node *ofn = pci_device_to_OF_node(dev);
3557
3558 if (ofn) {
3559 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3560 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3561 }
3562 }
3563 }
3564 #else
3565 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3566 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3567 #endif /* CONFIG_PPC_PMAC */
3568
3569 static int pci_probe(struct pci_dev *dev,
3570 const struct pci_device_id *ent)
3571 {
3572 struct fw_ohci *ohci;
3573 u32 bus_options, max_receive, link_speed, version;
3574 u64 guid;
3575 int i, err;
3576 size_t size;
3577
3578 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3579 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3580 return -ENOSYS;
3581 }
3582
3583 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3584 if (ohci == NULL) {
3585 err = -ENOMEM;
3586 goto fail;
3587 }
3588
3589 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3590
3591 pmac_ohci_on(dev);
3592
3593 err = pci_enable_device(dev);
3594 if (err) {
3595 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3596 goto fail_free;
3597 }
3598
3599 pci_set_master(dev);
3600 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3601 pci_set_drvdata(dev, ohci);
3602
3603 spin_lock_init(&ohci->lock);
3604 mutex_init(&ohci->phy_reg_mutex);
3605
3606 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3607
3608 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3609 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3610 dev_err(&dev->dev, "invalid MMIO resource\n");
3611 err = -ENXIO;
3612 goto fail_disable;
3613 }
3614
3615 err = pci_request_region(dev, 0, ohci_driver_name);
3616 if (err) {
3617 dev_err(&dev->dev, "MMIO resource unavailable\n");
3618 goto fail_disable;
3619 }
3620
3621 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3622 if (ohci->registers == NULL) {
3623 dev_err(&dev->dev, "failed to remap registers\n");
3624 err = -ENXIO;
3625 goto fail_iomem;
3626 }
3627
3628 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3629 if ((ohci_quirks[i].vendor == dev->vendor) &&
3630 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3631 ohci_quirks[i].device == dev->device) &&
3632 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3633 ohci_quirks[i].revision >= dev->revision)) {
3634 ohci->quirks = ohci_quirks[i].flags;
3635 break;
3636 }
3637 if (param_quirks)
3638 ohci->quirks = param_quirks;
3639
3640 /*
3641 * Because dma_alloc_coherent() allocates at least one page,
3642 * we save space by using a common buffer for the AR request/
3643 * response descriptors and the self IDs buffer.
3644 */
3645 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3646 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3647 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3648 PAGE_SIZE,
3649 &ohci->misc_buffer_bus,
3650 GFP_KERNEL);
3651 if (!ohci->misc_buffer) {
3652 err = -ENOMEM;
3653 goto fail_iounmap;
3654 }
3655
3656 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3657 OHCI1394_AsReqRcvContextControlSet);
3658 if (err < 0)
3659 goto fail_misc_buf;
3660
3661 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3662 OHCI1394_AsRspRcvContextControlSet);
3663 if (err < 0)
3664 goto fail_arreq_ctx;
3665
3666 err = context_init(&ohci->at_request_ctx, ohci,
3667 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3668 if (err < 0)
3669 goto fail_arrsp_ctx;
3670
3671 err = context_init(&ohci->at_response_ctx, ohci,
3672 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3673 if (err < 0)
3674 goto fail_atreq_ctx;
3675
3676 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3677 ohci->ir_context_channels = ~0ULL;
3678 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3679 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3680 ohci->ir_context_mask = ohci->ir_context_support;
3681 ohci->n_ir = hweight32(ohci->ir_context_mask);
3682 size = sizeof(struct iso_context) * ohci->n_ir;
3683 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3684
3685 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3686 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3687 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3688 ohci->it_context_mask = ohci->it_context_support;
3689 ohci->n_it = hweight32(ohci->it_context_mask);
3690 size = sizeof(struct iso_context) * ohci->n_it;
3691 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3692
3693 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3694 err = -ENOMEM;
3695 goto fail_contexts;
3696 }
3697
3698 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3699 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3700
3701 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3702 max_receive = (bus_options >> 12) & 0xf;
3703 link_speed = bus_options & 0x7;
3704 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3705 reg_read(ohci, OHCI1394_GUIDLo);
3706
3707 if (!(ohci->quirks & QUIRK_NO_MSI))
3708 pci_enable_msi(dev);
3709 if (request_irq(dev->irq, irq_handler,
3710 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3711 ohci_driver_name, ohci)) {
3712 dev_err(&dev->dev, "failed to allocate interrupt %d\n",
3713 dev->irq);
3714 err = -EIO;
3715 goto fail_msi;
3716 }
3717
3718 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3719 if (err)
3720 goto fail_irq;
3721
3722 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3723 dev_notice(&dev->dev,
3724 "added OHCI v%x.%x device as card %d, "
3725 "%d IR + %d IT contexts, quirks 0x%x\n",
3726 version >> 16, version & 0xff, ohci->card.index,
3727 ohci->n_ir, ohci->n_it, ohci->quirks);
3728
3729 return 0;
3730
3731 fail_irq:
3732 free_irq(dev->irq, ohci);
3733 fail_msi:
3734 pci_disable_msi(dev);
3735 fail_contexts:
3736 kfree(ohci->ir_context_list);
3737 kfree(ohci->it_context_list);
3738 context_release(&ohci->at_response_ctx);
3739 fail_atreq_ctx:
3740 context_release(&ohci->at_request_ctx);
3741 fail_arrsp_ctx:
3742 ar_context_release(&ohci->ar_response_ctx);
3743 fail_arreq_ctx:
3744 ar_context_release(&ohci->ar_request_ctx);
3745 fail_misc_buf:
3746 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3747 ohci->misc_buffer, ohci->misc_buffer_bus);
3748 fail_iounmap:
3749 pci_iounmap(dev, ohci->registers);
3750 fail_iomem:
3751 pci_release_region(dev, 0);
3752 fail_disable:
3753 pci_disable_device(dev);
3754 fail_free:
3755 kfree(ohci);
3756 pmac_ohci_off(dev);
3757 fail:
3758 return err;
3759 }
3760
3761 static void pci_remove(struct pci_dev *dev)
3762 {
3763 struct fw_ohci *ohci = pci_get_drvdata(dev);
3764
3765 /*
3766 * If the removal is happening from the suspend state, LPS won't be
3767 * enabled and host registers (eg., IntMaskClear) won't be accessible.
3768 */
3769 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3770 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3771 flush_writes(ohci);
3772 }
3773 cancel_work_sync(&ohci->bus_reset_work);
3774 fw_core_remove_card(&ohci->card);
3775
3776 /*
3777 * FIXME: Fail all pending packets here, now that the upper
3778 * layers can't queue any more.
3779 */
3780
3781 software_reset(ohci);
3782 free_irq(dev->irq, ohci);
3783
3784 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3785 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3786 ohci->next_config_rom, ohci->next_config_rom_bus);
3787 if (ohci->config_rom)
3788 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3789 ohci->config_rom, ohci->config_rom_bus);
3790 ar_context_release(&ohci->ar_request_ctx);
3791 ar_context_release(&ohci->ar_response_ctx);
3792 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3793 ohci->misc_buffer, ohci->misc_buffer_bus);
3794 context_release(&ohci->at_request_ctx);
3795 context_release(&ohci->at_response_ctx);
3796 kfree(ohci->it_context_list);
3797 kfree(ohci->ir_context_list);
3798 pci_disable_msi(dev);
3799 pci_iounmap(dev, ohci->registers);
3800 pci_release_region(dev, 0);
3801 pci_disable_device(dev);
3802 kfree(ohci);
3803 pmac_ohci_off(dev);
3804
3805 dev_notice(&dev->dev, "removed fw-ohci device\n");
3806 }
3807
3808 #ifdef CONFIG_PM
3809 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3810 {
3811 struct fw_ohci *ohci = pci_get_drvdata(dev);
3812 int err;
3813
3814 software_reset(ohci);
3815 err = pci_save_state(dev);
3816 if (err) {
3817 dev_err(&dev->dev, "pci_save_state failed\n");
3818 return err;
3819 }
3820 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3821 if (err)
3822 dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err);
3823 pmac_ohci_off(dev);
3824
3825 return 0;
3826 }
3827
3828 static int pci_resume(struct pci_dev *dev)
3829 {
3830 struct fw_ohci *ohci = pci_get_drvdata(dev);
3831 int err;
3832
3833 pmac_ohci_on(dev);
3834 pci_set_power_state(dev, PCI_D0);
3835 pci_restore_state(dev);
3836 err = pci_enable_device(dev);
3837 if (err) {
3838 dev_err(&dev->dev, "pci_enable_device failed\n");
3839 return err;
3840 }
3841
3842 /* Some systems don't setup GUID register on resume from ram */
3843 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3844 !reg_read(ohci, OHCI1394_GUIDHi)) {
3845 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3846 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3847 }
3848
3849 err = ohci_enable(&ohci->card, NULL, 0);
3850 if (err)
3851 return err;
3852
3853 ohci_resume_iso_dma(ohci);
3854
3855 return 0;
3856 }
3857 #endif
3858
3859 static const struct pci_device_id pci_table[] = {
3860 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3861 { }
3862 };
3863
3864 MODULE_DEVICE_TABLE(pci, pci_table);
3865
3866 static struct pci_driver fw_ohci_pci_driver = {
3867 .name = ohci_driver_name,
3868 .id_table = pci_table,
3869 .probe = pci_probe,
3870 .remove = pci_remove,
3871 #ifdef CONFIG_PM
3872 .resume = pci_resume,
3873 .suspend = pci_suspend,
3874 #endif
3875 };
3876
3877 module_pci_driver(fw_ohci_pci_driver);
3878
3879 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3880 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3881 MODULE_LICENSE("GPL");
3882
3883 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3884 MODULE_ALIAS("ohci1394");
Linux kernel - Deliverables
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