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Merge git://git.infradead.org/users/cbou/battery-2.6.36
[deliverable/linux.git] / drivers / firewire / ohci.c
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bug.h>
22 #include <linux/compiler.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/firewire.h>
27 #include <linux/firewire-constants.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/mutex.h>
37 #include <linux/pci.h>
38 #include <linux/pci_ids.h>
39 #include <linux/slab.h>
40 #include <linux/spinlock.h>
41 #include <linux/string.h>
42 #include <linux/time.h>
43
44 #include <asm/byteorder.h>
45 #include <asm/page.h>
46 #include <asm/system.h>
47
48 #ifdef CONFIG_PPC_PMAC
49 #include <asm/pmac_feature.h>
50 #endif
51
52 #include "core.h"
53 #include "ohci.h"
54
55 #define DESCRIPTOR_OUTPUT_MORE 0
56 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
57 #define DESCRIPTOR_INPUT_MORE (2 << 12)
58 #define DESCRIPTOR_INPUT_LAST (3 << 12)
59 #define DESCRIPTOR_STATUS (1 << 11)
60 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
61 #define DESCRIPTOR_PING (1 << 7)
62 #define DESCRIPTOR_YY (1 << 6)
63 #define DESCRIPTOR_NO_IRQ (0 << 4)
64 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
65 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
66 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
67 #define DESCRIPTOR_WAIT (3 << 0)
68
69 struct descriptor {
70 __le16 req_count;
71 __le16 control;
72 __le32 data_address;
73 __le32 branch_address;
74 __le16 res_count;
75 __le16 transfer_status;
76 } __attribute__((aligned(16)));
77
78 #define CONTROL_SET(regs) (regs)
79 #define CONTROL_CLEAR(regs) ((regs) + 4)
80 #define COMMAND_PTR(regs) ((regs) + 12)
81 #define CONTEXT_MATCH(regs) ((regs) + 16)
82
83 struct ar_buffer {
84 struct descriptor descriptor;
85 struct ar_buffer *next;
86 __le32 data[0];
87 };
88
89 struct ar_context {
90 struct fw_ohci *ohci;
91 struct ar_buffer *current_buffer;
92 struct ar_buffer *last_buffer;
93 void *pointer;
94 u32 regs;
95 struct tasklet_struct tasklet;
96 };
97
98 struct context;
99
100 typedef int (*descriptor_callback_t)(struct context *ctx,
101 struct descriptor *d,
102 struct descriptor *last);
103
104 /*
105 * A buffer that contains a block of DMA-able coherent memory used for
106 * storing a portion of a DMA descriptor program.
107 */
108 struct descriptor_buffer {
109 struct list_head list;
110 dma_addr_t buffer_bus;
111 size_t buffer_size;
112 size_t used;
113 struct descriptor buffer[0];
114 };
115
116 struct context {
117 struct fw_ohci *ohci;
118 u32 regs;
119 int total_allocation;
120
121 /*
122 * List of page-sized buffers for storing DMA descriptors.
123 * Head of list contains buffers in use and tail of list contains
124 * free buffers.
125 */
126 struct list_head buffer_list;
127
128 /*
129 * Pointer to a buffer inside buffer_list that contains the tail
130 * end of the current DMA program.
131 */
132 struct descriptor_buffer *buffer_tail;
133
134 /*
135 * The descriptor containing the branch address of the first
136 * descriptor that has not yet been filled by the device.
137 */
138 struct descriptor *last;
139
140 /*
141 * The last descriptor in the DMA program. It contains the branch
142 * address that must be updated upon appending a new descriptor.
143 */
144 struct descriptor *prev;
145
146 descriptor_callback_t callback;
147
148 struct tasklet_struct tasklet;
149 };
150
151 #define IT_HEADER_SY(v) ((v) << 0)
152 #define IT_HEADER_TCODE(v) ((v) << 4)
153 #define IT_HEADER_CHANNEL(v) ((v) << 8)
154 #define IT_HEADER_TAG(v) ((v) << 14)
155 #define IT_HEADER_SPEED(v) ((v) << 16)
156 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
157
158 struct iso_context {
159 struct fw_iso_context base;
160 struct context context;
161 int excess_bytes;
162 void *header;
163 size_t header_length;
164 };
165
166 #define CONFIG_ROM_SIZE 1024
167
168 struct fw_ohci {
169 struct fw_card card;
170
171 __iomem char *registers;
172 int node_id;
173 int generation;
174 int request_generation; /* for timestamping incoming requests */
175 unsigned quirks;
176 unsigned int pri_req_max;
177 u32 bus_time;
178 bool is_root;
179 bool csr_state_setclear_abdicate;
180
181 /*
182 * Spinlock for accessing fw_ohci data. Never call out of
183 * this driver with this lock held.
184 */
185 spinlock_t lock;
186
187 struct mutex phy_reg_mutex;
188
189 struct ar_context ar_request_ctx;
190 struct ar_context ar_response_ctx;
191 struct context at_request_ctx;
192 struct context at_response_ctx;
193
194 u32 it_context_mask; /* unoccupied IT contexts */
195 struct iso_context *it_context_list;
196 u64 ir_context_channels; /* unoccupied channels */
197 u32 ir_context_mask; /* unoccupied IR contexts */
198 struct iso_context *ir_context_list;
199 u64 mc_channels; /* channels in use by the multichannel IR context */
200 bool mc_allocated;
201
202 __be32 *config_rom;
203 dma_addr_t config_rom_bus;
204 __be32 *next_config_rom;
205 dma_addr_t next_config_rom_bus;
206 __be32 next_header;
207
208 __le32 *self_id_cpu;
209 dma_addr_t self_id_bus;
210 struct tasklet_struct bus_reset_tasklet;
211
212 u32 self_id_buffer[512];
213 };
214
215 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
216 {
217 return container_of(card, struct fw_ohci, card);
218 }
219
220 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
221 #define IR_CONTEXT_BUFFER_FILL 0x80000000
222 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
223 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
224 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
225 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
226
227 #define CONTEXT_RUN 0x8000
228 #define CONTEXT_WAKE 0x1000
229 #define CONTEXT_DEAD 0x0800
230 #define CONTEXT_ACTIVE 0x0400
231
232 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
233 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
234 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
235
236 #define OHCI1394_REGISTER_SIZE 0x800
237 #define OHCI_LOOP_COUNT 500
238 #define OHCI1394_PCI_HCI_Control 0x40
239 #define SELF_ID_BUF_SIZE 0x800
240 #define OHCI_TCODE_PHY_PACKET 0x0e
241 #define OHCI_VERSION_1_1 0x010010
242
243 static char ohci_driver_name[] = KBUILD_MODNAME;
244
245 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
246 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
247
248 #define QUIRK_CYCLE_TIMER 1
249 #define QUIRK_RESET_PACKET 2
250 #define QUIRK_BE_HEADERS 4
251 #define QUIRK_NO_1394A 8
252 #define QUIRK_NO_MSI 16
253
254 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
255 static const struct {
256 unsigned short vendor, device, flags;
257 } ohci_quirks[] = {
258 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
259 QUIRK_RESET_PACKET |
260 QUIRK_NO_1394A},
261 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
262 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
263 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
264 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
265 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
266 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
267 };
268
269 /* This overrides anything that was found in ohci_quirks[]. */
270 static int param_quirks;
271 module_param_named(quirks, param_quirks, int, 0644);
272 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
273 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
274 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
275 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
276 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
277 ", disable MSI = " __stringify(QUIRK_NO_MSI)
278 ")");
279
280 #define OHCI_PARAM_DEBUG_AT_AR 1
281 #define OHCI_PARAM_DEBUG_SELFIDS 2
282 #define OHCI_PARAM_DEBUG_IRQS 4
283 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
284
285 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
286
287 static int param_debug;
288 module_param_named(debug, param_debug, int, 0644);
289 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
290 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
291 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
292 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
293 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
294 ", or a combination, or all = -1)");
295
296 static void log_irqs(u32 evt)
297 {
298 if (likely(!(param_debug &
299 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
300 return;
301
302 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
303 !(evt & OHCI1394_busReset))
304 return;
305
306 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
307 evt & OHCI1394_selfIDComplete ? " selfID" : "",
308 evt & OHCI1394_RQPkt ? " AR_req" : "",
309 evt & OHCI1394_RSPkt ? " AR_resp" : "",
310 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
311 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
312 evt & OHCI1394_isochRx ? " IR" : "",
313 evt & OHCI1394_isochTx ? " IT" : "",
314 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
315 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
316 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
317 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
318 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
319 evt & OHCI1394_busReset ? " busReset" : "",
320 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
321 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
322 OHCI1394_respTxComplete | OHCI1394_isochRx |
323 OHCI1394_isochTx | OHCI1394_postedWriteErr |
324 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
325 OHCI1394_cycleInconsistent |
326 OHCI1394_regAccessFail | OHCI1394_busReset)
327 ? " ?" : "");
328 }
329
330 static const char *speed[] = {
331 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
332 };
333 static const char *power[] = {
334 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
335 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
336 };
337 static const char port[] = { '.', '-', 'p', 'c', };
338
339 static char _p(u32 *s, int shift)
340 {
341 return port[*s >> shift & 3];
342 }
343
344 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
345 {
346 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
347 return;
348
349 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
350 self_id_count, generation, node_id);
351
352 for (; self_id_count--; ++s)
353 if ((*s & 1 << 23) == 0)
354 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
355 "%s gc=%d %s %s%s%s\n",
356 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
357 speed[*s >> 14 & 3], *s >> 16 & 63,
358 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
359 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
360 else
361 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
362 *s, *s >> 24 & 63,
363 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
364 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
365 }
366
367 static const char *evts[] = {
368 [0x00] = "evt_no_status", [0x01] = "-reserved-",
369 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
370 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
371 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
372 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
373 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
374 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
375 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
376 [0x10] = "-reserved-", [0x11] = "ack_complete",
377 [0x12] = "ack_pending ", [0x13] = "-reserved-",
378 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
379 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
380 [0x18] = "-reserved-", [0x19] = "-reserved-",
381 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
382 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
383 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
384 [0x20] = "pending/cancelled",
385 };
386 static const char *tcodes[] = {
387 [0x0] = "QW req", [0x1] = "BW req",
388 [0x2] = "W resp", [0x3] = "-reserved-",
389 [0x4] = "QR req", [0x5] = "BR req",
390 [0x6] = "QR resp", [0x7] = "BR resp",
391 [0x8] = "cycle start", [0x9] = "Lk req",
392 [0xa] = "async stream packet", [0xb] = "Lk resp",
393 [0xc] = "-reserved-", [0xd] = "-reserved-",
394 [0xe] = "link internal", [0xf] = "-reserved-",
395 };
396 static const char *phys[] = {
397 [0x0] = "phy config packet", [0x1] = "link-on packet",
398 [0x2] = "self-id packet", [0x3] = "-reserved-",
399 };
400
401 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
402 {
403 int tcode = header[0] >> 4 & 0xf;
404 char specific[12];
405
406 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
407 return;
408
409 if (unlikely(evt >= ARRAY_SIZE(evts)))
410 evt = 0x1f;
411
412 if (evt == OHCI1394_evt_bus_reset) {
413 fw_notify("A%c evt_bus_reset, generation %d\n",
414 dir, (header[2] >> 16) & 0xff);
415 return;
416 }
417
418 if (header[0] == ~header[1]) {
419 fw_notify("A%c %s, %s, %08x\n",
420 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
421 return;
422 }
423
424 switch (tcode) {
425 case 0x0: case 0x6: case 0x8:
426 snprintf(specific, sizeof(specific), " = %08x",
427 be32_to_cpu((__force __be32)header[3]));
428 break;
429 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
430 snprintf(specific, sizeof(specific), " %x,%x",
431 header[3] >> 16, header[3] & 0xffff);
432 break;
433 default:
434 specific[0] = '\0';
435 }
436
437 switch (tcode) {
438 case 0xe: case 0xa:
439 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
440 break;
441 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
442 fw_notify("A%c spd %x tl %02x, "
443 "%04x -> %04x, %s, "
444 "%s, %04x%08x%s\n",
445 dir, speed, header[0] >> 10 & 0x3f,
446 header[1] >> 16, header[0] >> 16, evts[evt],
447 tcodes[tcode], header[1] & 0xffff, header[2], specific);
448 break;
449 default:
450 fw_notify("A%c spd %x tl %02x, "
451 "%04x -> %04x, %s, "
452 "%s%s\n",
453 dir, speed, header[0] >> 10 & 0x3f,
454 header[1] >> 16, header[0] >> 16, evts[evt],
455 tcodes[tcode], specific);
456 }
457 }
458
459 #else
460
461 #define param_debug 0
462 static inline void log_irqs(u32 evt) {}
463 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
464 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
465
466 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
467
468 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
469 {
470 writel(data, ohci->registers + offset);
471 }
472
473 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
474 {
475 return readl(ohci->registers + offset);
476 }
477
478 static inline void flush_writes(const struct fw_ohci *ohci)
479 {
480 /* Do a dummy read to flush writes. */
481 reg_read(ohci, OHCI1394_Version);
482 }
483
484 static int read_phy_reg(struct fw_ohci *ohci, int addr)
485 {
486 u32 val;
487 int i;
488
489 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
490 for (i = 0; i < 3 + 100; i++) {
491 val = reg_read(ohci, OHCI1394_PhyControl);
492 if (val & OHCI1394_PhyControl_ReadDone)
493 return OHCI1394_PhyControl_ReadData(val);
494
495 /*
496 * Try a few times without waiting. Sleeping is necessary
497 * only when the link/PHY interface is busy.
498 */
499 if (i >= 3)
500 msleep(1);
501 }
502 fw_error("failed to read phy reg\n");
503
504 return -EBUSY;
505 }
506
507 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
508 {
509 int i;
510
511 reg_write(ohci, OHCI1394_PhyControl,
512 OHCI1394_PhyControl_Write(addr, val));
513 for (i = 0; i < 3 + 100; i++) {
514 val = reg_read(ohci, OHCI1394_PhyControl);
515 if (!(val & OHCI1394_PhyControl_WritePending))
516 return 0;
517
518 if (i >= 3)
519 msleep(1);
520 }
521 fw_error("failed to write phy reg\n");
522
523 return -EBUSY;
524 }
525
526 static int update_phy_reg(struct fw_ohci *ohci, int addr,
527 int clear_bits, int set_bits)
528 {
529 int ret = read_phy_reg(ohci, addr);
530 if (ret < 0)
531 return ret;
532
533 /*
534 * The interrupt status bits are cleared by writing a one bit.
535 * Avoid clearing them unless explicitly requested in set_bits.
536 */
537 if (addr == 5)
538 clear_bits |= PHY_INT_STATUS_BITS;
539
540 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
541 }
542
543 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
544 {
545 int ret;
546
547 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
548 if (ret < 0)
549 return ret;
550
551 return read_phy_reg(ohci, addr);
552 }
553
554 static int ohci_read_phy_reg(struct fw_card *card, int addr)
555 {
556 struct fw_ohci *ohci = fw_ohci(card);
557 int ret;
558
559 mutex_lock(&ohci->phy_reg_mutex);
560 ret = read_phy_reg(ohci, addr);
561 mutex_unlock(&ohci->phy_reg_mutex);
562
563 return ret;
564 }
565
566 static int ohci_update_phy_reg(struct fw_card *card, int addr,
567 int clear_bits, int set_bits)
568 {
569 struct fw_ohci *ohci = fw_ohci(card);
570 int ret;
571
572 mutex_lock(&ohci->phy_reg_mutex);
573 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
574 mutex_unlock(&ohci->phy_reg_mutex);
575
576 return ret;
577 }
578
579 static int ar_context_add_page(struct ar_context *ctx)
580 {
581 struct device *dev = ctx->ohci->card.device;
582 struct ar_buffer *ab;
583 dma_addr_t uninitialized_var(ab_bus);
584 size_t offset;
585
586 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
587 if (ab == NULL)
588 return -ENOMEM;
589
590 ab->next = NULL;
591 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
592 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
593 DESCRIPTOR_STATUS |
594 DESCRIPTOR_BRANCH_ALWAYS);
595 offset = offsetof(struct ar_buffer, data);
596 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
597 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
598 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
599 ab->descriptor.branch_address = 0;
600
601 wmb(); /* finish init of new descriptors before branch_address update */
602 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
603 ctx->last_buffer->next = ab;
604 ctx->last_buffer = ab;
605
606 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
607 flush_writes(ctx->ohci);
608
609 return 0;
610 }
611
612 static void ar_context_release(struct ar_context *ctx)
613 {
614 struct ar_buffer *ab, *ab_next;
615 size_t offset;
616 dma_addr_t ab_bus;
617
618 for (ab = ctx->current_buffer; ab; ab = ab_next) {
619 ab_next = ab->next;
620 offset = offsetof(struct ar_buffer, data);
621 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
622 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
623 ab, ab_bus);
624 }
625 }
626
627 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
628 #define cond_le32_to_cpu(v) \
629 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
630 #else
631 #define cond_le32_to_cpu(v) le32_to_cpu(v)
632 #endif
633
634 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
635 {
636 struct fw_ohci *ohci = ctx->ohci;
637 struct fw_packet p;
638 u32 status, length, tcode;
639 int evt;
640
641 p.header[0] = cond_le32_to_cpu(buffer[0]);
642 p.header[1] = cond_le32_to_cpu(buffer[1]);
643 p.header[2] = cond_le32_to_cpu(buffer[2]);
644
645 tcode = (p.header[0] >> 4) & 0x0f;
646 switch (tcode) {
647 case TCODE_WRITE_QUADLET_REQUEST:
648 case TCODE_READ_QUADLET_RESPONSE:
649 p.header[3] = (__force __u32) buffer[3];
650 p.header_length = 16;
651 p.payload_length = 0;
652 break;
653
654 case TCODE_READ_BLOCK_REQUEST :
655 p.header[3] = cond_le32_to_cpu(buffer[3]);
656 p.header_length = 16;
657 p.payload_length = 0;
658 break;
659
660 case TCODE_WRITE_BLOCK_REQUEST:
661 case TCODE_READ_BLOCK_RESPONSE:
662 case TCODE_LOCK_REQUEST:
663 case TCODE_LOCK_RESPONSE:
664 p.header[3] = cond_le32_to_cpu(buffer[3]);
665 p.header_length = 16;
666 p.payload_length = p.header[3] >> 16;
667 break;
668
669 case TCODE_WRITE_RESPONSE:
670 case TCODE_READ_QUADLET_REQUEST:
671 case OHCI_TCODE_PHY_PACKET:
672 p.header_length = 12;
673 p.payload_length = 0;
674 break;
675
676 default:
677 /* FIXME: Stop context, discard everything, and restart? */
678 p.header_length = 0;
679 p.payload_length = 0;
680 }
681
682 p.payload = (void *) buffer + p.header_length;
683
684 /* FIXME: What to do about evt_* errors? */
685 length = (p.header_length + p.payload_length + 3) / 4;
686 status = cond_le32_to_cpu(buffer[length]);
687 evt = (status >> 16) & 0x1f;
688
689 p.ack = evt - 16;
690 p.speed = (status >> 21) & 0x7;
691 p.timestamp = status & 0xffff;
692 p.generation = ohci->request_generation;
693
694 log_ar_at_event('R', p.speed, p.header, evt);
695
696 /*
697 * Several controllers, notably from NEC and VIA, forget to
698 * write ack_complete status at PHY packet reception.
699 */
700 if (evt == OHCI1394_evt_no_status &&
701 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
702 p.ack = ACK_COMPLETE;
703
704 /*
705 * The OHCI bus reset handler synthesizes a PHY packet with
706 * the new generation number when a bus reset happens (see
707 * section 8.4.2.3). This helps us determine when a request
708 * was received and make sure we send the response in the same
709 * generation. We only need this for requests; for responses
710 * we use the unique tlabel for finding the matching
711 * request.
712 *
713 * Alas some chips sometimes emit bus reset packets with a
714 * wrong generation. We set the correct generation for these
715 * at a slightly incorrect time (in bus_reset_tasklet).
716 */
717 if (evt == OHCI1394_evt_bus_reset) {
718 if (!(ohci->quirks & QUIRK_RESET_PACKET))
719 ohci->request_generation = (p.header[2] >> 16) & 0xff;
720 } else if (ctx == &ohci->ar_request_ctx) {
721 fw_core_handle_request(&ohci->card, &p);
722 } else {
723 fw_core_handle_response(&ohci->card, &p);
724 }
725
726 return buffer + length + 1;
727 }
728
729 static void ar_context_tasklet(unsigned long data)
730 {
731 struct ar_context *ctx = (struct ar_context *)data;
732 struct fw_ohci *ohci = ctx->ohci;
733 struct ar_buffer *ab;
734 struct descriptor *d;
735 void *buffer, *end;
736
737 ab = ctx->current_buffer;
738 d = &ab->descriptor;
739
740 if (d->res_count == 0) {
741 size_t size, rest, offset;
742 dma_addr_t start_bus;
743 void *start;
744
745 /*
746 * This descriptor is finished and we may have a
747 * packet split across this and the next buffer. We
748 * reuse the page for reassembling the split packet.
749 */
750
751 offset = offsetof(struct ar_buffer, data);
752 start = buffer = ab;
753 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
754
755 ab = ab->next;
756 d = &ab->descriptor;
757 size = buffer + PAGE_SIZE - ctx->pointer;
758 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
759 memmove(buffer, ctx->pointer, size);
760 memcpy(buffer + size, ab->data, rest);
761 ctx->current_buffer = ab;
762 ctx->pointer = (void *) ab->data + rest;
763 end = buffer + size + rest;
764
765 while (buffer < end)
766 buffer = handle_ar_packet(ctx, buffer);
767
768 dma_free_coherent(ohci->card.device, PAGE_SIZE,
769 start, start_bus);
770 ar_context_add_page(ctx);
771 } else {
772 buffer = ctx->pointer;
773 ctx->pointer = end =
774 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
775
776 while (buffer < end)
777 buffer = handle_ar_packet(ctx, buffer);
778 }
779 }
780
781 static int ar_context_init(struct ar_context *ctx,
782 struct fw_ohci *ohci, u32 regs)
783 {
784 struct ar_buffer ab;
785
786 ctx->regs = regs;
787 ctx->ohci = ohci;
788 ctx->last_buffer = &ab;
789 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
790
791 ar_context_add_page(ctx);
792 ar_context_add_page(ctx);
793 ctx->current_buffer = ab.next;
794 ctx->pointer = ctx->current_buffer->data;
795
796 return 0;
797 }
798
799 static void ar_context_run(struct ar_context *ctx)
800 {
801 struct ar_buffer *ab = ctx->current_buffer;
802 dma_addr_t ab_bus;
803 size_t offset;
804
805 offset = offsetof(struct ar_buffer, data);
806 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
807
808 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
809 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
810 flush_writes(ctx->ohci);
811 }
812
813 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
814 {
815 int b, key;
816
817 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
818 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
819
820 /* figure out which descriptor the branch address goes in */
821 if (z == 2 && (b == 3 || key == 2))
822 return d;
823 else
824 return d + z - 1;
825 }
826
827 static void context_tasklet(unsigned long data)
828 {
829 struct context *ctx = (struct context *) data;
830 struct descriptor *d, *last;
831 u32 address;
832 int z;
833 struct descriptor_buffer *desc;
834
835 desc = list_entry(ctx->buffer_list.next,
836 struct descriptor_buffer, list);
837 last = ctx->last;
838 while (last->branch_address != 0) {
839 struct descriptor_buffer *old_desc = desc;
840 address = le32_to_cpu(last->branch_address);
841 z = address & 0xf;
842 address &= ~0xf;
843
844 /* If the branch address points to a buffer outside of the
845 * current buffer, advance to the next buffer. */
846 if (address < desc->buffer_bus ||
847 address >= desc->buffer_bus + desc->used)
848 desc = list_entry(desc->list.next,
849 struct descriptor_buffer, list);
850 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
851 last = find_branch_descriptor(d, z);
852
853 if (!ctx->callback(ctx, d, last))
854 break;
855
856 if (old_desc != desc) {
857 /* If we've advanced to the next buffer, move the
858 * previous buffer to the free list. */
859 unsigned long flags;
860 old_desc->used = 0;
861 spin_lock_irqsave(&ctx->ohci->lock, flags);
862 list_move_tail(&old_desc->list, &ctx->buffer_list);
863 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
864 }
865 ctx->last = last;
866 }
867 }
868
869 /*
870 * Allocate a new buffer and add it to the list of free buffers for this
871 * context. Must be called with ohci->lock held.
872 */
873 static int context_add_buffer(struct context *ctx)
874 {
875 struct descriptor_buffer *desc;
876 dma_addr_t uninitialized_var(bus_addr);
877 int offset;
878
879 /*
880 * 16MB of descriptors should be far more than enough for any DMA
881 * program. This will catch run-away userspace or DoS attacks.
882 */
883 if (ctx->total_allocation >= 16*1024*1024)
884 return -ENOMEM;
885
886 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
887 &bus_addr, GFP_ATOMIC);
888 if (!desc)
889 return -ENOMEM;
890
891 offset = (void *)&desc->buffer - (void *)desc;
892 desc->buffer_size = PAGE_SIZE - offset;
893 desc->buffer_bus = bus_addr + offset;
894 desc->used = 0;
895
896 list_add_tail(&desc->list, &ctx->buffer_list);
897 ctx->total_allocation += PAGE_SIZE;
898
899 return 0;
900 }
901
902 static int context_init(struct context *ctx, struct fw_ohci *ohci,
903 u32 regs, descriptor_callback_t callback)
904 {
905 ctx->ohci = ohci;
906 ctx->regs = regs;
907 ctx->total_allocation = 0;
908
909 INIT_LIST_HEAD(&ctx->buffer_list);
910 if (context_add_buffer(ctx) < 0)
911 return -ENOMEM;
912
913 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
914 struct descriptor_buffer, list);
915
916 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
917 ctx->callback = callback;
918
919 /*
920 * We put a dummy descriptor in the buffer that has a NULL
921 * branch address and looks like it's been sent. That way we
922 * have a descriptor to append DMA programs to.
923 */
924 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
925 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
926 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
927 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
928 ctx->last = ctx->buffer_tail->buffer;
929 ctx->prev = ctx->buffer_tail->buffer;
930
931 return 0;
932 }
933
934 static void context_release(struct context *ctx)
935 {
936 struct fw_card *card = &ctx->ohci->card;
937 struct descriptor_buffer *desc, *tmp;
938
939 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
940 dma_free_coherent(card->device, PAGE_SIZE, desc,
941 desc->buffer_bus -
942 ((void *)&desc->buffer - (void *)desc));
943 }
944
945 /* Must be called with ohci->lock held */
946 static struct descriptor *context_get_descriptors(struct context *ctx,
947 int z, dma_addr_t *d_bus)
948 {
949 struct descriptor *d = NULL;
950 struct descriptor_buffer *desc = ctx->buffer_tail;
951
952 if (z * sizeof(*d) > desc->buffer_size)
953 return NULL;
954
955 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
956 /* No room for the descriptor in this buffer, so advance to the
957 * next one. */
958
959 if (desc->list.next == &ctx->buffer_list) {
960 /* If there is no free buffer next in the list,
961 * allocate one. */
962 if (context_add_buffer(ctx) < 0)
963 return NULL;
964 }
965 desc = list_entry(desc->list.next,
966 struct descriptor_buffer, list);
967 ctx->buffer_tail = desc;
968 }
969
970 d = desc->buffer + desc->used / sizeof(*d);
971 memset(d, 0, z * sizeof(*d));
972 *d_bus = desc->buffer_bus + desc->used;
973
974 return d;
975 }
976
977 static void context_run(struct context *ctx, u32 extra)
978 {
979 struct fw_ohci *ohci = ctx->ohci;
980
981 reg_write(ohci, COMMAND_PTR(ctx->regs),
982 le32_to_cpu(ctx->last->branch_address));
983 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
984 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
985 flush_writes(ohci);
986 }
987
988 static void context_append(struct context *ctx,
989 struct descriptor *d, int z, int extra)
990 {
991 dma_addr_t d_bus;
992 struct descriptor_buffer *desc = ctx->buffer_tail;
993
994 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
995
996 desc->used += (z + extra) * sizeof(*d);
997
998 wmb(); /* finish init of new descriptors before branch_address update */
999 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1000 ctx->prev = find_branch_descriptor(d, z);
1001
1002 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1003 flush_writes(ctx->ohci);
1004 }
1005
1006 static void context_stop(struct context *ctx)
1007 {
1008 u32 reg;
1009 int i;
1010
1011 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1012 flush_writes(ctx->ohci);
1013
1014 for (i = 0; i < 10; i++) {
1015 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1016 if ((reg & CONTEXT_ACTIVE) == 0)
1017 return;
1018
1019 mdelay(1);
1020 }
1021 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1022 }
1023
1024 struct driver_data {
1025 struct fw_packet *packet;
1026 };
1027
1028 /*
1029 * This function apppends a packet to the DMA queue for transmission.
1030 * Must always be called with the ochi->lock held to ensure proper
1031 * generation handling and locking around packet queue manipulation.
1032 */
1033 static int at_context_queue_packet(struct context *ctx,
1034 struct fw_packet *packet)
1035 {
1036 struct fw_ohci *ohci = ctx->ohci;
1037 dma_addr_t d_bus, uninitialized_var(payload_bus);
1038 struct driver_data *driver_data;
1039 struct descriptor *d, *last;
1040 __le32 *header;
1041 int z, tcode;
1042 u32 reg;
1043
1044 d = context_get_descriptors(ctx, 4, &d_bus);
1045 if (d == NULL) {
1046 packet->ack = RCODE_SEND_ERROR;
1047 return -1;
1048 }
1049
1050 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1051 d[0].res_count = cpu_to_le16(packet->timestamp);
1052
1053 /*
1054 * The DMA format for asyncronous link packets is different
1055 * from the IEEE1394 layout, so shift the fields around
1056 * accordingly. If header_length is 8, it's a PHY packet, to
1057 * which we need to prepend an extra quadlet.
1058 */
1059
1060 header = (__le32 *) &d[1];
1061 switch (packet->header_length) {
1062 case 16:
1063 case 12:
1064 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1065 (packet->speed << 16));
1066 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1067 (packet->header[0] & 0xffff0000));
1068 header[2] = cpu_to_le32(packet->header[2]);
1069
1070 tcode = (packet->header[0] >> 4) & 0x0f;
1071 if (TCODE_IS_BLOCK_PACKET(tcode))
1072 header[3] = cpu_to_le32(packet->header[3]);
1073 else
1074 header[3] = (__force __le32) packet->header[3];
1075
1076 d[0].req_count = cpu_to_le16(packet->header_length);
1077 break;
1078
1079 case 8:
1080 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1081 (packet->speed << 16));
1082 header[1] = cpu_to_le32(packet->header[0]);
1083 header[2] = cpu_to_le32(packet->header[1]);
1084 d[0].req_count = cpu_to_le16(12);
1085
1086 if (is_ping_packet(packet->header))
1087 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1088 break;
1089
1090 case 4:
1091 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1092 (packet->speed << 16));
1093 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1094 d[0].req_count = cpu_to_le16(8);
1095 break;
1096
1097 default:
1098 /* BUG(); */
1099 packet->ack = RCODE_SEND_ERROR;
1100 return -1;
1101 }
1102
1103 driver_data = (struct driver_data *) &d[3];
1104 driver_data->packet = packet;
1105 packet->driver_data = driver_data;
1106
1107 if (packet->payload_length > 0) {
1108 payload_bus =
1109 dma_map_single(ohci->card.device, packet->payload,
1110 packet->payload_length, DMA_TO_DEVICE);
1111 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1112 packet->ack = RCODE_SEND_ERROR;
1113 return -1;
1114 }
1115 packet->payload_bus = payload_bus;
1116 packet->payload_mapped = true;
1117
1118 d[2].req_count = cpu_to_le16(packet->payload_length);
1119 d[2].data_address = cpu_to_le32(payload_bus);
1120 last = &d[2];
1121 z = 3;
1122 } else {
1123 last = &d[0];
1124 z = 2;
1125 }
1126
1127 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1128 DESCRIPTOR_IRQ_ALWAYS |
1129 DESCRIPTOR_BRANCH_ALWAYS);
1130
1131 /*
1132 * If the controller and packet generations don't match, we need to
1133 * bail out and try again. If IntEvent.busReset is set, the AT context
1134 * is halted, so appending to the context and trying to run it is
1135 * futile. Most controllers do the right thing and just flush the AT
1136 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1137 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1138 * up stalling out. So we just bail out in software and try again
1139 * later, and everyone is happy.
1140 * FIXME: Document how the locking works.
1141 */
1142 if (ohci->generation != packet->generation ||
1143 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1144 if (packet->payload_mapped)
1145 dma_unmap_single(ohci->card.device, payload_bus,
1146 packet->payload_length, DMA_TO_DEVICE);
1147 packet->ack = RCODE_GENERATION;
1148 return -1;
1149 }
1150
1151 context_append(ctx, d, z, 4 - z);
1152
1153 /* If the context isn't already running, start it up. */
1154 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1155 if ((reg & CONTEXT_RUN) == 0)
1156 context_run(ctx, 0);
1157
1158 return 0;
1159 }
1160
1161 static int handle_at_packet(struct context *context,
1162 struct descriptor *d,
1163 struct descriptor *last)
1164 {
1165 struct driver_data *driver_data;
1166 struct fw_packet *packet;
1167 struct fw_ohci *ohci = context->ohci;
1168 int evt;
1169
1170 if (last->transfer_status == 0)
1171 /* This descriptor isn't done yet, stop iteration. */
1172 return 0;
1173
1174 driver_data = (struct driver_data *) &d[3];
1175 packet = driver_data->packet;
1176 if (packet == NULL)
1177 /* This packet was cancelled, just continue. */
1178 return 1;
1179
1180 if (packet->payload_mapped)
1181 dma_unmap_single(ohci->card.device, packet->payload_bus,
1182 packet->payload_length, DMA_TO_DEVICE);
1183
1184 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1185 packet->timestamp = le16_to_cpu(last->res_count);
1186
1187 log_ar_at_event('T', packet->speed, packet->header, evt);
1188
1189 switch (evt) {
1190 case OHCI1394_evt_timeout:
1191 /* Async response transmit timed out. */
1192 packet->ack = RCODE_CANCELLED;
1193 break;
1194
1195 case OHCI1394_evt_flushed:
1196 /*
1197 * The packet was flushed should give same error as
1198 * when we try to use a stale generation count.
1199 */
1200 packet->ack = RCODE_GENERATION;
1201 break;
1202
1203 case OHCI1394_evt_missing_ack:
1204 /*
1205 * Using a valid (current) generation count, but the
1206 * node is not on the bus or not sending acks.
1207 */
1208 packet->ack = RCODE_NO_ACK;
1209 break;
1210
1211 case ACK_COMPLETE + 0x10:
1212 case ACK_PENDING + 0x10:
1213 case ACK_BUSY_X + 0x10:
1214 case ACK_BUSY_A + 0x10:
1215 case ACK_BUSY_B + 0x10:
1216 case ACK_DATA_ERROR + 0x10:
1217 case ACK_TYPE_ERROR + 0x10:
1218 packet->ack = evt - 0x10;
1219 break;
1220
1221 default:
1222 packet->ack = RCODE_SEND_ERROR;
1223 break;
1224 }
1225
1226 packet->callback(packet, &ohci->card, packet->ack);
1227
1228 return 1;
1229 }
1230
1231 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1232 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1233 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1234 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1235 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1236
1237 static void handle_local_rom(struct fw_ohci *ohci,
1238 struct fw_packet *packet, u32 csr)
1239 {
1240 struct fw_packet response;
1241 int tcode, length, i;
1242
1243 tcode = HEADER_GET_TCODE(packet->header[0]);
1244 if (TCODE_IS_BLOCK_PACKET(tcode))
1245 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1246 else
1247 length = 4;
1248
1249 i = csr - CSR_CONFIG_ROM;
1250 if (i + length > CONFIG_ROM_SIZE) {
1251 fw_fill_response(&response, packet->header,
1252 RCODE_ADDRESS_ERROR, NULL, 0);
1253 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1254 fw_fill_response(&response, packet->header,
1255 RCODE_TYPE_ERROR, NULL, 0);
1256 } else {
1257 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1258 (void *) ohci->config_rom + i, length);
1259 }
1260
1261 fw_core_handle_response(&ohci->card, &response);
1262 }
1263
1264 static void handle_local_lock(struct fw_ohci *ohci,
1265 struct fw_packet *packet, u32 csr)
1266 {
1267 struct fw_packet response;
1268 int tcode, length, ext_tcode, sel, try;
1269 __be32 *payload, lock_old;
1270 u32 lock_arg, lock_data;
1271
1272 tcode = HEADER_GET_TCODE(packet->header[0]);
1273 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1274 payload = packet->payload;
1275 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1276
1277 if (tcode == TCODE_LOCK_REQUEST &&
1278 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1279 lock_arg = be32_to_cpu(payload[0]);
1280 lock_data = be32_to_cpu(payload[1]);
1281 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1282 lock_arg = 0;
1283 lock_data = 0;
1284 } else {
1285 fw_fill_response(&response, packet->header,
1286 RCODE_TYPE_ERROR, NULL, 0);
1287 goto out;
1288 }
1289
1290 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1291 reg_write(ohci, OHCI1394_CSRData, lock_data);
1292 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1293 reg_write(ohci, OHCI1394_CSRControl, sel);
1294
1295 for (try = 0; try < 20; try++)
1296 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1297 lock_old = cpu_to_be32(reg_read(ohci,
1298 OHCI1394_CSRData));
1299 fw_fill_response(&response, packet->header,
1300 RCODE_COMPLETE,
1301 &lock_old, sizeof(lock_old));
1302 goto out;
1303 }
1304
1305 fw_error("swap not done (CSR lock timeout)\n");
1306 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1307
1308 out:
1309 fw_core_handle_response(&ohci->card, &response);
1310 }
1311
1312 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1313 {
1314 u64 offset, csr;
1315
1316 if (ctx == &ctx->ohci->at_request_ctx) {
1317 packet->ack = ACK_PENDING;
1318 packet->callback(packet, &ctx->ohci->card, packet->ack);
1319 }
1320
1321 offset =
1322 ((unsigned long long)
1323 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1324 packet->header[2];
1325 csr = offset - CSR_REGISTER_BASE;
1326
1327 /* Handle config rom reads. */
1328 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1329 handle_local_rom(ctx->ohci, packet, csr);
1330 else switch (csr) {
1331 case CSR_BUS_MANAGER_ID:
1332 case CSR_BANDWIDTH_AVAILABLE:
1333 case CSR_CHANNELS_AVAILABLE_HI:
1334 case CSR_CHANNELS_AVAILABLE_LO:
1335 handle_local_lock(ctx->ohci, packet, csr);
1336 break;
1337 default:
1338 if (ctx == &ctx->ohci->at_request_ctx)
1339 fw_core_handle_request(&ctx->ohci->card, packet);
1340 else
1341 fw_core_handle_response(&ctx->ohci->card, packet);
1342 break;
1343 }
1344
1345 if (ctx == &ctx->ohci->at_response_ctx) {
1346 packet->ack = ACK_COMPLETE;
1347 packet->callback(packet, &ctx->ohci->card, packet->ack);
1348 }
1349 }
1350
1351 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1352 {
1353 unsigned long flags;
1354 int ret;
1355
1356 spin_lock_irqsave(&ctx->ohci->lock, flags);
1357
1358 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1359 ctx->ohci->generation == packet->generation) {
1360 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1361 handle_local_request(ctx, packet);
1362 return;
1363 }
1364
1365 ret = at_context_queue_packet(ctx, packet);
1366 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1367
1368 if (ret < 0)
1369 packet->callback(packet, &ctx->ohci->card, packet->ack);
1370
1371 }
1372
1373 static u32 cycle_timer_ticks(u32 cycle_timer)
1374 {
1375 u32 ticks;
1376
1377 ticks = cycle_timer & 0xfff;
1378 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1379 ticks += (3072 * 8000) * (cycle_timer >> 25);
1380
1381 return ticks;
1382 }
1383
1384 /*
1385 * Some controllers exhibit one or more of the following bugs when updating the
1386 * iso cycle timer register:
1387 * - When the lowest six bits are wrapping around to zero, a read that happens
1388 * at the same time will return garbage in the lowest ten bits.
1389 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1390 * not incremented for about 60 ns.
1391 * - Occasionally, the entire register reads zero.
1392 *
1393 * To catch these, we read the register three times and ensure that the
1394 * difference between each two consecutive reads is approximately the same, i.e.
1395 * less than twice the other. Furthermore, any negative difference indicates an
1396 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1397 * execute, so we have enough precision to compute the ratio of the differences.)
1398 */
1399 static u32 get_cycle_time(struct fw_ohci *ohci)
1400 {
1401 u32 c0, c1, c2;
1402 u32 t0, t1, t2;
1403 s32 diff01, diff12;
1404 int i;
1405
1406 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1407
1408 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1409 i = 0;
1410 c1 = c2;
1411 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1412 do {
1413 c0 = c1;
1414 c1 = c2;
1415 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1416 t0 = cycle_timer_ticks(c0);
1417 t1 = cycle_timer_ticks(c1);
1418 t2 = cycle_timer_ticks(c2);
1419 diff01 = t1 - t0;
1420 diff12 = t2 - t1;
1421 } while ((diff01 <= 0 || diff12 <= 0 ||
1422 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1423 && i++ < 20);
1424 }
1425
1426 return c2;
1427 }
1428
1429 /*
1430 * This function has to be called at least every 64 seconds. The bus_time
1431 * field stores not only the upper 25 bits of the BUS_TIME register but also
1432 * the most significant bit of the cycle timer in bit 6 so that we can detect
1433 * changes in this bit.
1434 */
1435 static u32 update_bus_time(struct fw_ohci *ohci)
1436 {
1437 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1438
1439 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1440 ohci->bus_time += 0x40;
1441
1442 return ohci->bus_time | cycle_time_seconds;
1443 }
1444
1445 static void bus_reset_tasklet(unsigned long data)
1446 {
1447 struct fw_ohci *ohci = (struct fw_ohci *)data;
1448 int self_id_count, i, j, reg;
1449 int generation, new_generation;
1450 unsigned long flags;
1451 void *free_rom = NULL;
1452 dma_addr_t free_rom_bus = 0;
1453 bool is_new_root;
1454
1455 reg = reg_read(ohci, OHCI1394_NodeID);
1456 if (!(reg & OHCI1394_NodeID_idValid)) {
1457 fw_notify("node ID not valid, new bus reset in progress\n");
1458 return;
1459 }
1460 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1461 fw_notify("malconfigured bus\n");
1462 return;
1463 }
1464 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1465 OHCI1394_NodeID_nodeNumber);
1466
1467 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1468 if (!(ohci->is_root && is_new_root))
1469 reg_write(ohci, OHCI1394_LinkControlSet,
1470 OHCI1394_LinkControl_cycleMaster);
1471 ohci->is_root = is_new_root;
1472
1473 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1474 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1475 fw_notify("inconsistent self IDs\n");
1476 return;
1477 }
1478 /*
1479 * The count in the SelfIDCount register is the number of
1480 * bytes in the self ID receive buffer. Since we also receive
1481 * the inverted quadlets and a header quadlet, we shift one
1482 * bit extra to get the actual number of self IDs.
1483 */
1484 self_id_count = (reg >> 3) & 0xff;
1485 if (self_id_count == 0 || self_id_count > 252) {
1486 fw_notify("inconsistent self IDs\n");
1487 return;
1488 }
1489 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1490 rmb();
1491
1492 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1493 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1494 fw_notify("inconsistent self IDs\n");
1495 return;
1496 }
1497 ohci->self_id_buffer[j] =
1498 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1499 }
1500 rmb();
1501
1502 /*
1503 * Check the consistency of the self IDs we just read. The
1504 * problem we face is that a new bus reset can start while we
1505 * read out the self IDs from the DMA buffer. If this happens,
1506 * the DMA buffer will be overwritten with new self IDs and we
1507 * will read out inconsistent data. The OHCI specification
1508 * (section 11.2) recommends a technique similar to
1509 * linux/seqlock.h, where we remember the generation of the
1510 * self IDs in the buffer before reading them out and compare
1511 * it to the current generation after reading them out. If
1512 * the two generations match we know we have a consistent set
1513 * of self IDs.
1514 */
1515
1516 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1517 if (new_generation != generation) {
1518 fw_notify("recursive bus reset detected, "
1519 "discarding self ids\n");
1520 return;
1521 }
1522
1523 /* FIXME: Document how the locking works. */
1524 spin_lock_irqsave(&ohci->lock, flags);
1525
1526 ohci->generation = generation;
1527 context_stop(&ohci->at_request_ctx);
1528 context_stop(&ohci->at_response_ctx);
1529 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1530
1531 if (ohci->quirks & QUIRK_RESET_PACKET)
1532 ohci->request_generation = generation;
1533
1534 /*
1535 * This next bit is unrelated to the AT context stuff but we
1536 * have to do it under the spinlock also. If a new config rom
1537 * was set up before this reset, the old one is now no longer
1538 * in use and we can free it. Update the config rom pointers
1539 * to point to the current config rom and clear the
1540 * next_config_rom pointer so a new update can take place.
1541 */
1542
1543 if (ohci->next_config_rom != NULL) {
1544 if (ohci->next_config_rom != ohci->config_rom) {
1545 free_rom = ohci->config_rom;
1546 free_rom_bus = ohci->config_rom_bus;
1547 }
1548 ohci->config_rom = ohci->next_config_rom;
1549 ohci->config_rom_bus = ohci->next_config_rom_bus;
1550 ohci->next_config_rom = NULL;
1551
1552 /*
1553 * Restore config_rom image and manually update
1554 * config_rom registers. Writing the header quadlet
1555 * will indicate that the config rom is ready, so we
1556 * do that last.
1557 */
1558 reg_write(ohci, OHCI1394_BusOptions,
1559 be32_to_cpu(ohci->config_rom[2]));
1560 ohci->config_rom[0] = ohci->next_header;
1561 reg_write(ohci, OHCI1394_ConfigROMhdr,
1562 be32_to_cpu(ohci->next_header));
1563 }
1564
1565 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1566 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1567 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1568 #endif
1569
1570 spin_unlock_irqrestore(&ohci->lock, flags);
1571
1572 if (free_rom)
1573 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1574 free_rom, free_rom_bus);
1575
1576 log_selfids(ohci->node_id, generation,
1577 self_id_count, ohci->self_id_buffer);
1578
1579 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1580 self_id_count, ohci->self_id_buffer,
1581 ohci->csr_state_setclear_abdicate);
1582 ohci->csr_state_setclear_abdicate = false;
1583 }
1584
1585 static irqreturn_t irq_handler(int irq, void *data)
1586 {
1587 struct fw_ohci *ohci = data;
1588 u32 event, iso_event;
1589 int i;
1590
1591 event = reg_read(ohci, OHCI1394_IntEventClear);
1592
1593 if (!event || !~event)
1594 return IRQ_NONE;
1595
1596 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1597 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1598 log_irqs(event);
1599
1600 if (event & OHCI1394_selfIDComplete)
1601 tasklet_schedule(&ohci->bus_reset_tasklet);
1602
1603 if (event & OHCI1394_RQPkt)
1604 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1605
1606 if (event & OHCI1394_RSPkt)
1607 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1608
1609 if (event & OHCI1394_reqTxComplete)
1610 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1611
1612 if (event & OHCI1394_respTxComplete)
1613 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1614
1615 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1616 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1617
1618 while (iso_event) {
1619 i = ffs(iso_event) - 1;
1620 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1621 iso_event &= ~(1 << i);
1622 }
1623
1624 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1625 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1626
1627 while (iso_event) {
1628 i = ffs(iso_event) - 1;
1629 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1630 iso_event &= ~(1 << i);
1631 }
1632
1633 if (unlikely(event & OHCI1394_regAccessFail))
1634 fw_error("Register access failure - "
1635 "please notify linux1394-devel@lists.sf.net\n");
1636
1637 if (unlikely(event & OHCI1394_postedWriteErr))
1638 fw_error("PCI posted write error\n");
1639
1640 if (unlikely(event & OHCI1394_cycleTooLong)) {
1641 if (printk_ratelimit())
1642 fw_notify("isochronous cycle too long\n");
1643 reg_write(ohci, OHCI1394_LinkControlSet,
1644 OHCI1394_LinkControl_cycleMaster);
1645 }
1646
1647 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1648 /*
1649 * We need to clear this event bit in order to make
1650 * cycleMatch isochronous I/O work. In theory we should
1651 * stop active cycleMatch iso contexts now and restart
1652 * them at least two cycles later. (FIXME?)
1653 */
1654 if (printk_ratelimit())
1655 fw_notify("isochronous cycle inconsistent\n");
1656 }
1657
1658 if (event & OHCI1394_cycle64Seconds) {
1659 spin_lock(&ohci->lock);
1660 update_bus_time(ohci);
1661 spin_unlock(&ohci->lock);
1662 }
1663
1664 return IRQ_HANDLED;
1665 }
1666
1667 static int software_reset(struct fw_ohci *ohci)
1668 {
1669 int i;
1670
1671 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1672
1673 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1674 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1675 OHCI1394_HCControl_softReset) == 0)
1676 return 0;
1677 msleep(1);
1678 }
1679
1680 return -EBUSY;
1681 }
1682
1683 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1684 {
1685 size_t size = length * 4;
1686
1687 memcpy(dest, src, size);
1688 if (size < CONFIG_ROM_SIZE)
1689 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1690 }
1691
1692 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1693 {
1694 bool enable_1394a;
1695 int ret, clear, set, offset;
1696
1697 /* Check if the driver should configure link and PHY. */
1698 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1699 OHCI1394_HCControl_programPhyEnable))
1700 return 0;
1701
1702 /* Paranoia: check whether the PHY supports 1394a, too. */
1703 enable_1394a = false;
1704 ret = read_phy_reg(ohci, 2);
1705 if (ret < 0)
1706 return ret;
1707 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1708 ret = read_paged_phy_reg(ohci, 1, 8);
1709 if (ret < 0)
1710 return ret;
1711 if (ret >= 1)
1712 enable_1394a = true;
1713 }
1714
1715 if (ohci->quirks & QUIRK_NO_1394A)
1716 enable_1394a = false;
1717
1718 /* Configure PHY and link consistently. */
1719 if (enable_1394a) {
1720 clear = 0;
1721 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1722 } else {
1723 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1724 set = 0;
1725 }
1726 ret = update_phy_reg(ohci, 5, clear, set);
1727 if (ret < 0)
1728 return ret;
1729
1730 if (enable_1394a)
1731 offset = OHCI1394_HCControlSet;
1732 else
1733 offset = OHCI1394_HCControlClear;
1734 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1735
1736 /* Clean up: configuration has been taken care of. */
1737 reg_write(ohci, OHCI1394_HCControlClear,
1738 OHCI1394_HCControl_programPhyEnable);
1739
1740 return 0;
1741 }
1742
1743 static int ohci_enable(struct fw_card *card,
1744 const __be32 *config_rom, size_t length)
1745 {
1746 struct fw_ohci *ohci = fw_ohci(card);
1747 struct pci_dev *dev = to_pci_dev(card->device);
1748 u32 lps, seconds, version, irqs;
1749 int i, ret;
1750
1751 if (software_reset(ohci)) {
1752 fw_error("Failed to reset ohci card.\n");
1753 return -EBUSY;
1754 }
1755
1756 /*
1757 * Now enable LPS, which we need in order to start accessing
1758 * most of the registers. In fact, on some cards (ALI M5251),
1759 * accessing registers in the SClk domain without LPS enabled
1760 * will lock up the machine. Wait 50msec to make sure we have
1761 * full link enabled. However, with some cards (well, at least
1762 * a JMicron PCIe card), we have to try again sometimes.
1763 */
1764 reg_write(ohci, OHCI1394_HCControlSet,
1765 OHCI1394_HCControl_LPS |
1766 OHCI1394_HCControl_postedWriteEnable);
1767 flush_writes(ohci);
1768
1769 for (lps = 0, i = 0; !lps && i < 3; i++) {
1770 msleep(50);
1771 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1772 OHCI1394_HCControl_LPS;
1773 }
1774
1775 if (!lps) {
1776 fw_error("Failed to set Link Power Status\n");
1777 return -EIO;
1778 }
1779
1780 reg_write(ohci, OHCI1394_HCControlClear,
1781 OHCI1394_HCControl_noByteSwapData);
1782
1783 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1784 reg_write(ohci, OHCI1394_LinkControlSet,
1785 OHCI1394_LinkControl_rcvSelfID |
1786 OHCI1394_LinkControl_rcvPhyPkt |
1787 OHCI1394_LinkControl_cycleTimerEnable |
1788 OHCI1394_LinkControl_cycleMaster);
1789
1790 reg_write(ohci, OHCI1394_ATRetries,
1791 OHCI1394_MAX_AT_REQ_RETRIES |
1792 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1793 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1794 (200 << 16));
1795
1796 seconds = lower_32_bits(get_seconds());
1797 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1798 ohci->bus_time = seconds & ~0x3f;
1799
1800 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1801 if (version >= OHCI_VERSION_1_1) {
1802 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1803 0xfffffffe);
1804 card->broadcast_channel_auto_allocated = true;
1805 }
1806
1807 /* Get implemented bits of the priority arbitration request counter. */
1808 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1809 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1810 reg_write(ohci, OHCI1394_FairnessControl, 0);
1811 card->priority_budget_implemented = ohci->pri_req_max != 0;
1812
1813 ar_context_run(&ohci->ar_request_ctx);
1814 ar_context_run(&ohci->ar_response_ctx);
1815
1816 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1817 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1818 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1819
1820 ret = configure_1394a_enhancements(ohci);
1821 if (ret < 0)
1822 return ret;
1823
1824 /* Activate link_on bit and contender bit in our self ID packets.*/
1825 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1826 if (ret < 0)
1827 return ret;
1828
1829 /*
1830 * When the link is not yet enabled, the atomic config rom
1831 * update mechanism described below in ohci_set_config_rom()
1832 * is not active. We have to update ConfigRomHeader and
1833 * BusOptions manually, and the write to ConfigROMmap takes
1834 * effect immediately. We tie this to the enabling of the
1835 * link, so we have a valid config rom before enabling - the
1836 * OHCI requires that ConfigROMhdr and BusOptions have valid
1837 * values before enabling.
1838 *
1839 * However, when the ConfigROMmap is written, some controllers
1840 * always read back quadlets 0 and 2 from the config rom to
1841 * the ConfigRomHeader and BusOptions registers on bus reset.
1842 * They shouldn't do that in this initial case where the link
1843 * isn't enabled. This means we have to use the same
1844 * workaround here, setting the bus header to 0 and then write
1845 * the right values in the bus reset tasklet.
1846 */
1847
1848 if (config_rom) {
1849 ohci->next_config_rom =
1850 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1851 &ohci->next_config_rom_bus,
1852 GFP_KERNEL);
1853 if (ohci->next_config_rom == NULL)
1854 return -ENOMEM;
1855
1856 copy_config_rom(ohci->next_config_rom, config_rom, length);
1857 } else {
1858 /*
1859 * In the suspend case, config_rom is NULL, which
1860 * means that we just reuse the old config rom.
1861 */
1862 ohci->next_config_rom = ohci->config_rom;
1863 ohci->next_config_rom_bus = ohci->config_rom_bus;
1864 }
1865
1866 ohci->next_header = ohci->next_config_rom[0];
1867 ohci->next_config_rom[0] = 0;
1868 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1869 reg_write(ohci, OHCI1394_BusOptions,
1870 be32_to_cpu(ohci->next_config_rom[2]));
1871 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1872
1873 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1874
1875 if (!(ohci->quirks & QUIRK_NO_MSI))
1876 pci_enable_msi(dev);
1877 if (request_irq(dev->irq, irq_handler,
1878 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1879 ohci_driver_name, ohci)) {
1880 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1881 pci_disable_msi(dev);
1882 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1883 ohci->config_rom, ohci->config_rom_bus);
1884 return -EIO;
1885 }
1886
1887 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1888 OHCI1394_RQPkt | OHCI1394_RSPkt |
1889 OHCI1394_isochTx | OHCI1394_isochRx |
1890 OHCI1394_postedWriteErr |
1891 OHCI1394_selfIDComplete |
1892 OHCI1394_regAccessFail |
1893 OHCI1394_cycle64Seconds |
1894 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1895 OHCI1394_masterIntEnable;
1896 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1897 irqs |= OHCI1394_busReset;
1898 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1899
1900 reg_write(ohci, OHCI1394_HCControlSet,
1901 OHCI1394_HCControl_linkEnable |
1902 OHCI1394_HCControl_BIBimageValid);
1903 flush_writes(ohci);
1904
1905 /* We are ready to go, reset bus to finish initialization. */
1906 fw_schedule_bus_reset(&ohci->card, false, true);
1907
1908 return 0;
1909 }
1910
1911 static int ohci_set_config_rom(struct fw_card *card,
1912 const __be32 *config_rom, size_t length)
1913 {
1914 struct fw_ohci *ohci;
1915 unsigned long flags;
1916 int ret = -EBUSY;
1917 __be32 *next_config_rom;
1918 dma_addr_t uninitialized_var(next_config_rom_bus);
1919
1920 ohci = fw_ohci(card);
1921
1922 /*
1923 * When the OHCI controller is enabled, the config rom update
1924 * mechanism is a bit tricky, but easy enough to use. See
1925 * section 5.5.6 in the OHCI specification.
1926 *
1927 * The OHCI controller caches the new config rom address in a
1928 * shadow register (ConfigROMmapNext) and needs a bus reset
1929 * for the changes to take place. When the bus reset is
1930 * detected, the controller loads the new values for the
1931 * ConfigRomHeader and BusOptions registers from the specified
1932 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1933 * shadow register. All automatically and atomically.
1934 *
1935 * Now, there's a twist to this story. The automatic load of
1936 * ConfigRomHeader and BusOptions doesn't honor the
1937 * noByteSwapData bit, so with a be32 config rom, the
1938 * controller will load be32 values in to these registers
1939 * during the atomic update, even on litte endian
1940 * architectures. The workaround we use is to put a 0 in the
1941 * header quadlet; 0 is endian agnostic and means that the
1942 * config rom isn't ready yet. In the bus reset tasklet we
1943 * then set up the real values for the two registers.
1944 *
1945 * We use ohci->lock to avoid racing with the code that sets
1946 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1947 */
1948
1949 next_config_rom =
1950 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1951 &next_config_rom_bus, GFP_KERNEL);
1952 if (next_config_rom == NULL)
1953 return -ENOMEM;
1954
1955 spin_lock_irqsave(&ohci->lock, flags);
1956
1957 if (ohci->next_config_rom == NULL) {
1958 ohci->next_config_rom = next_config_rom;
1959 ohci->next_config_rom_bus = next_config_rom_bus;
1960
1961 copy_config_rom(ohci->next_config_rom, config_rom, length);
1962
1963 ohci->next_header = config_rom[0];
1964 ohci->next_config_rom[0] = 0;
1965
1966 reg_write(ohci, OHCI1394_ConfigROMmap,
1967 ohci->next_config_rom_bus);
1968 ret = 0;
1969 }
1970
1971 spin_unlock_irqrestore(&ohci->lock, flags);
1972
1973 /*
1974 * Now initiate a bus reset to have the changes take
1975 * effect. We clean up the old config rom memory and DMA
1976 * mappings in the bus reset tasklet, since the OHCI
1977 * controller could need to access it before the bus reset
1978 * takes effect.
1979 */
1980 if (ret == 0)
1981 fw_schedule_bus_reset(&ohci->card, true, true);
1982 else
1983 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1984 next_config_rom, next_config_rom_bus);
1985
1986 return ret;
1987 }
1988
1989 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1990 {
1991 struct fw_ohci *ohci = fw_ohci(card);
1992
1993 at_context_transmit(&ohci->at_request_ctx, packet);
1994 }
1995
1996 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1997 {
1998 struct fw_ohci *ohci = fw_ohci(card);
1999
2000 at_context_transmit(&ohci->at_response_ctx, packet);
2001 }
2002
2003 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2004 {
2005 struct fw_ohci *ohci = fw_ohci(card);
2006 struct context *ctx = &ohci->at_request_ctx;
2007 struct driver_data *driver_data = packet->driver_data;
2008 int ret = -ENOENT;
2009
2010 tasklet_disable(&ctx->tasklet);
2011
2012 if (packet->ack != 0)
2013 goto out;
2014
2015 if (packet->payload_mapped)
2016 dma_unmap_single(ohci->card.device, packet->payload_bus,
2017 packet->payload_length, DMA_TO_DEVICE);
2018
2019 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2020 driver_data->packet = NULL;
2021 packet->ack = RCODE_CANCELLED;
2022 packet->callback(packet, &ohci->card, packet->ack);
2023 ret = 0;
2024 out:
2025 tasklet_enable(&ctx->tasklet);
2026
2027 return ret;
2028 }
2029
2030 static int ohci_enable_phys_dma(struct fw_card *card,
2031 int node_id, int generation)
2032 {
2033 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2034 return 0;
2035 #else
2036 struct fw_ohci *ohci = fw_ohci(card);
2037 unsigned long flags;
2038 int n, ret = 0;
2039
2040 /*
2041 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2042 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2043 */
2044
2045 spin_lock_irqsave(&ohci->lock, flags);
2046
2047 if (ohci->generation != generation) {
2048 ret = -ESTALE;
2049 goto out;
2050 }
2051
2052 /*
2053 * Note, if the node ID contains a non-local bus ID, physical DMA is
2054 * enabled for _all_ nodes on remote buses.
2055 */
2056
2057 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2058 if (n < 32)
2059 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2060 else
2061 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2062
2063 flush_writes(ohci);
2064 out:
2065 spin_unlock_irqrestore(&ohci->lock, flags);
2066
2067 return ret;
2068 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2069 }
2070
2071 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2072 {
2073 struct fw_ohci *ohci = fw_ohci(card);
2074 unsigned long flags;
2075 u32 value;
2076
2077 switch (csr_offset) {
2078 case CSR_STATE_CLEAR:
2079 case CSR_STATE_SET:
2080 if (ohci->is_root &&
2081 (reg_read(ohci, OHCI1394_LinkControlSet) &
2082 OHCI1394_LinkControl_cycleMaster))
2083 value = CSR_STATE_BIT_CMSTR;
2084 else
2085 value = 0;
2086 if (ohci->csr_state_setclear_abdicate)
2087 value |= CSR_STATE_BIT_ABDICATE;
2088
2089 return value;
2090
2091 case CSR_NODE_IDS:
2092 return reg_read(ohci, OHCI1394_NodeID) << 16;
2093
2094 case CSR_CYCLE_TIME:
2095 return get_cycle_time(ohci);
2096
2097 case CSR_BUS_TIME:
2098 /*
2099 * We might be called just after the cycle timer has wrapped
2100 * around but just before the cycle64Seconds handler, so we
2101 * better check here, too, if the bus time needs to be updated.
2102 */
2103 spin_lock_irqsave(&ohci->lock, flags);
2104 value = update_bus_time(ohci);
2105 spin_unlock_irqrestore(&ohci->lock, flags);
2106 return value;
2107
2108 case CSR_BUSY_TIMEOUT:
2109 value = reg_read(ohci, OHCI1394_ATRetries);
2110 return (value >> 4) & 0x0ffff00f;
2111
2112 case CSR_PRIORITY_BUDGET:
2113 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2114 (ohci->pri_req_max << 8);
2115
2116 default:
2117 WARN_ON(1);
2118 return 0;
2119 }
2120 }
2121
2122 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2123 {
2124 struct fw_ohci *ohci = fw_ohci(card);
2125 unsigned long flags;
2126
2127 switch (csr_offset) {
2128 case CSR_STATE_CLEAR:
2129 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2130 reg_write(ohci, OHCI1394_LinkControlClear,
2131 OHCI1394_LinkControl_cycleMaster);
2132 flush_writes(ohci);
2133 }
2134 if (value & CSR_STATE_BIT_ABDICATE)
2135 ohci->csr_state_setclear_abdicate = false;
2136 break;
2137
2138 case CSR_STATE_SET:
2139 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2140 reg_write(ohci, OHCI1394_LinkControlSet,
2141 OHCI1394_LinkControl_cycleMaster);
2142 flush_writes(ohci);
2143 }
2144 if (value & CSR_STATE_BIT_ABDICATE)
2145 ohci->csr_state_setclear_abdicate = true;
2146 break;
2147
2148 case CSR_NODE_IDS:
2149 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2150 flush_writes(ohci);
2151 break;
2152
2153 case CSR_CYCLE_TIME:
2154 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2155 reg_write(ohci, OHCI1394_IntEventSet,
2156 OHCI1394_cycleInconsistent);
2157 flush_writes(ohci);
2158 break;
2159
2160 case CSR_BUS_TIME:
2161 spin_lock_irqsave(&ohci->lock, flags);
2162 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2163 spin_unlock_irqrestore(&ohci->lock, flags);
2164 break;
2165
2166 case CSR_BUSY_TIMEOUT:
2167 value = (value & 0xf) | ((value & 0xf) << 4) |
2168 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2169 reg_write(ohci, OHCI1394_ATRetries, value);
2170 flush_writes(ohci);
2171 break;
2172
2173 case CSR_PRIORITY_BUDGET:
2174 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2175 flush_writes(ohci);
2176 break;
2177
2178 default:
2179 WARN_ON(1);
2180 break;
2181 }
2182 }
2183
2184 static void copy_iso_headers(struct iso_context *ctx, void *p)
2185 {
2186 int i = ctx->header_length;
2187
2188 if (i + ctx->base.header_size > PAGE_SIZE)
2189 return;
2190
2191 /*
2192 * The iso header is byteswapped to little endian by
2193 * the controller, but the remaining header quadlets
2194 * are big endian. We want to present all the headers
2195 * as big endian, so we have to swap the first quadlet.
2196 */
2197 if (ctx->base.header_size > 0)
2198 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2199 if (ctx->base.header_size > 4)
2200 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2201 if (ctx->base.header_size > 8)
2202 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2203 ctx->header_length += ctx->base.header_size;
2204 }
2205
2206 static int handle_ir_packet_per_buffer(struct context *context,
2207 struct descriptor *d,
2208 struct descriptor *last)
2209 {
2210 struct iso_context *ctx =
2211 container_of(context, struct iso_context, context);
2212 struct descriptor *pd;
2213 __le32 *ir_header;
2214 void *p;
2215
2216 for (pd = d; pd <= last; pd++)
2217 if (pd->transfer_status)
2218 break;
2219 if (pd > last)
2220 /* Descriptor(s) not done yet, stop iteration */
2221 return 0;
2222
2223 p = last + 1;
2224 copy_iso_headers(ctx, p);
2225
2226 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2227 ir_header = (__le32 *) p;
2228 ctx->base.callback.sc(&ctx->base,
2229 le32_to_cpu(ir_header[0]) & 0xffff,
2230 ctx->header_length, ctx->header,
2231 ctx->base.callback_data);
2232 ctx->header_length = 0;
2233 }
2234
2235 return 1;
2236 }
2237
2238 /* d == last because each descriptor block is only a single descriptor. */
2239 static int handle_ir_buffer_fill(struct context *context,
2240 struct descriptor *d,
2241 struct descriptor *last)
2242 {
2243 struct iso_context *ctx =
2244 container_of(context, struct iso_context, context);
2245
2246 if (!last->transfer_status)
2247 /* Descriptor(s) not done yet, stop iteration */
2248 return 0;
2249
2250 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2251 ctx->base.callback.mc(&ctx->base,
2252 le32_to_cpu(last->data_address) +
2253 le16_to_cpu(last->req_count) -
2254 le16_to_cpu(last->res_count),
2255 ctx->base.callback_data);
2256
2257 return 1;
2258 }
2259
2260 static int handle_it_packet(struct context *context,
2261 struct descriptor *d,
2262 struct descriptor *last)
2263 {
2264 struct iso_context *ctx =
2265 container_of(context, struct iso_context, context);
2266 int i;
2267 struct descriptor *pd;
2268
2269 for (pd = d; pd <= last; pd++)
2270 if (pd->transfer_status)
2271 break;
2272 if (pd > last)
2273 /* Descriptor(s) not done yet, stop iteration */
2274 return 0;
2275
2276 i = ctx->header_length;
2277 if (i + 4 < PAGE_SIZE) {
2278 /* Present this value as big-endian to match the receive code */
2279 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2280 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2281 le16_to_cpu(pd->res_count));
2282 ctx->header_length += 4;
2283 }
2284 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2285 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2286 ctx->header_length, ctx->header,
2287 ctx->base.callback_data);
2288 ctx->header_length = 0;
2289 }
2290 return 1;
2291 }
2292
2293 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2294 {
2295 u32 hi = channels >> 32, lo = channels;
2296
2297 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2298 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2299 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2300 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2301 mmiowb();
2302 ohci->mc_channels = channels;
2303 }
2304
2305 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2306 int type, int channel, size_t header_size)
2307 {
2308 struct fw_ohci *ohci = fw_ohci(card);
2309 struct iso_context *uninitialized_var(ctx);
2310 descriptor_callback_t uninitialized_var(callback);
2311 u64 *uninitialized_var(channels);
2312 u32 *uninitialized_var(mask), uninitialized_var(regs);
2313 unsigned long flags;
2314 int index, ret = -EBUSY;
2315
2316 spin_lock_irqsave(&ohci->lock, flags);
2317
2318 switch (type) {
2319 case FW_ISO_CONTEXT_TRANSMIT:
2320 mask = &ohci->it_context_mask;
2321 callback = handle_it_packet;
2322 index = ffs(*mask) - 1;
2323 if (index >= 0) {
2324 *mask &= ~(1 << index);
2325 regs = OHCI1394_IsoXmitContextBase(index);
2326 ctx = &ohci->it_context_list[index];
2327 }
2328 break;
2329
2330 case FW_ISO_CONTEXT_RECEIVE:
2331 channels = &ohci->ir_context_channels;
2332 mask = &ohci->ir_context_mask;
2333 callback = handle_ir_packet_per_buffer;
2334 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2335 if (index >= 0) {
2336 *channels &= ~(1ULL << channel);
2337 *mask &= ~(1 << index);
2338 regs = OHCI1394_IsoRcvContextBase(index);
2339 ctx = &ohci->ir_context_list[index];
2340 }
2341 break;
2342
2343 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2344 mask = &ohci->ir_context_mask;
2345 callback = handle_ir_buffer_fill;
2346 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2347 if (index >= 0) {
2348 ohci->mc_allocated = true;
2349 *mask &= ~(1 << index);
2350 regs = OHCI1394_IsoRcvContextBase(index);
2351 ctx = &ohci->ir_context_list[index];
2352 }
2353 break;
2354
2355 default:
2356 index = -1;
2357 ret = -ENOSYS;
2358 }
2359
2360 spin_unlock_irqrestore(&ohci->lock, flags);
2361
2362 if (index < 0)
2363 return ERR_PTR(ret);
2364
2365 memset(ctx, 0, sizeof(*ctx));
2366 ctx->header_length = 0;
2367 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2368 if (ctx->header == NULL) {
2369 ret = -ENOMEM;
2370 goto out;
2371 }
2372 ret = context_init(&ctx->context, ohci, regs, callback);
2373 if (ret < 0)
2374 goto out_with_header;
2375
2376 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2377 set_multichannel_mask(ohci, 0);
2378
2379 return &ctx->base;
2380
2381 out_with_header:
2382 free_page((unsigned long)ctx->header);
2383 out:
2384 spin_lock_irqsave(&ohci->lock, flags);
2385
2386 switch (type) {
2387 case FW_ISO_CONTEXT_RECEIVE:
2388 *channels |= 1ULL << channel;
2389 break;
2390
2391 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2392 ohci->mc_allocated = false;
2393 break;
2394 }
2395 *mask |= 1 << index;
2396
2397 spin_unlock_irqrestore(&ohci->lock, flags);
2398
2399 return ERR_PTR(ret);
2400 }
2401
2402 static int ohci_start_iso(struct fw_iso_context *base,
2403 s32 cycle, u32 sync, u32 tags)
2404 {
2405 struct iso_context *ctx = container_of(base, struct iso_context, base);
2406 struct fw_ohci *ohci = ctx->context.ohci;
2407 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2408 int index;
2409
2410 switch (ctx->base.type) {
2411 case FW_ISO_CONTEXT_TRANSMIT:
2412 index = ctx - ohci->it_context_list;
2413 match = 0;
2414 if (cycle >= 0)
2415 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2416 (cycle & 0x7fff) << 16;
2417
2418 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2419 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2420 context_run(&ctx->context, match);
2421 break;
2422
2423 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2424 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2425 /* fall through */
2426 case FW_ISO_CONTEXT_RECEIVE:
2427 index = ctx - ohci->ir_context_list;
2428 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2429 if (cycle >= 0) {
2430 match |= (cycle & 0x07fff) << 12;
2431 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2432 }
2433
2434 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2435 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2436 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2437 context_run(&ctx->context, control);
2438 break;
2439 }
2440
2441 return 0;
2442 }
2443
2444 static int ohci_stop_iso(struct fw_iso_context *base)
2445 {
2446 struct fw_ohci *ohci = fw_ohci(base->card);
2447 struct iso_context *ctx = container_of(base, struct iso_context, base);
2448 int index;
2449
2450 switch (ctx->base.type) {
2451 case FW_ISO_CONTEXT_TRANSMIT:
2452 index = ctx - ohci->it_context_list;
2453 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2454 break;
2455
2456 case FW_ISO_CONTEXT_RECEIVE:
2457 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2458 index = ctx - ohci->ir_context_list;
2459 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2460 break;
2461 }
2462 flush_writes(ohci);
2463 context_stop(&ctx->context);
2464
2465 return 0;
2466 }
2467
2468 static void ohci_free_iso_context(struct fw_iso_context *base)
2469 {
2470 struct fw_ohci *ohci = fw_ohci(base->card);
2471 struct iso_context *ctx = container_of(base, struct iso_context, base);
2472 unsigned long flags;
2473 int index;
2474
2475 ohci_stop_iso(base);
2476 context_release(&ctx->context);
2477 free_page((unsigned long)ctx->header);
2478
2479 spin_lock_irqsave(&ohci->lock, flags);
2480
2481 switch (base->type) {
2482 case FW_ISO_CONTEXT_TRANSMIT:
2483 index = ctx - ohci->it_context_list;
2484 ohci->it_context_mask |= 1 << index;
2485 break;
2486
2487 case FW_ISO_CONTEXT_RECEIVE:
2488 index = ctx - ohci->ir_context_list;
2489 ohci->ir_context_mask |= 1 << index;
2490 ohci->ir_context_channels |= 1ULL << base->channel;
2491 break;
2492
2493 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2494 index = ctx - ohci->ir_context_list;
2495 ohci->ir_context_mask |= 1 << index;
2496 ohci->ir_context_channels |= ohci->mc_channels;
2497 ohci->mc_channels = 0;
2498 ohci->mc_allocated = false;
2499 break;
2500 }
2501
2502 spin_unlock_irqrestore(&ohci->lock, flags);
2503 }
2504
2505 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2506 {
2507 struct fw_ohci *ohci = fw_ohci(base->card);
2508 unsigned long flags;
2509 int ret;
2510
2511 switch (base->type) {
2512 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2513
2514 spin_lock_irqsave(&ohci->lock, flags);
2515
2516 /* Don't allow multichannel to grab other contexts' channels. */
2517 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2518 *channels = ohci->ir_context_channels;
2519 ret = -EBUSY;
2520 } else {
2521 set_multichannel_mask(ohci, *channels);
2522 ret = 0;
2523 }
2524
2525 spin_unlock_irqrestore(&ohci->lock, flags);
2526
2527 break;
2528 default:
2529 ret = -EINVAL;
2530 }
2531
2532 return ret;
2533 }
2534
2535 static int queue_iso_transmit(struct iso_context *ctx,
2536 struct fw_iso_packet *packet,
2537 struct fw_iso_buffer *buffer,
2538 unsigned long payload)
2539 {
2540 struct descriptor *d, *last, *pd;
2541 struct fw_iso_packet *p;
2542 __le32 *header;
2543 dma_addr_t d_bus, page_bus;
2544 u32 z, header_z, payload_z, irq;
2545 u32 payload_index, payload_end_index, next_page_index;
2546 int page, end_page, i, length, offset;
2547
2548 p = packet;
2549 payload_index = payload;
2550
2551 if (p->skip)
2552 z = 1;
2553 else
2554 z = 2;
2555 if (p->header_length > 0)
2556 z++;
2557
2558 /* Determine the first page the payload isn't contained in. */
2559 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2560 if (p->payload_length > 0)
2561 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2562 else
2563 payload_z = 0;
2564
2565 z += payload_z;
2566
2567 /* Get header size in number of descriptors. */
2568 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2569
2570 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2571 if (d == NULL)
2572 return -ENOMEM;
2573
2574 if (!p->skip) {
2575 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2576 d[0].req_count = cpu_to_le16(8);
2577 /*
2578 * Link the skip address to this descriptor itself. This causes
2579 * a context to skip a cycle whenever lost cycles or FIFO
2580 * overruns occur, without dropping the data. The application
2581 * should then decide whether this is an error condition or not.
2582 * FIXME: Make the context's cycle-lost behaviour configurable?
2583 */
2584 d[0].branch_address = cpu_to_le32(d_bus | z);
2585
2586 header = (__le32 *) &d[1];
2587 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2588 IT_HEADER_TAG(p->tag) |
2589 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2590 IT_HEADER_CHANNEL(ctx->base.channel) |
2591 IT_HEADER_SPEED(ctx->base.speed));
2592 header[1] =
2593 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2594 p->payload_length));
2595 }
2596
2597 if (p->header_length > 0) {
2598 d[2].req_count = cpu_to_le16(p->header_length);
2599 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2600 memcpy(&d[z], p->header, p->header_length);
2601 }
2602
2603 pd = d + z - payload_z;
2604 payload_end_index = payload_index + p->payload_length;
2605 for (i = 0; i < payload_z; i++) {
2606 page = payload_index >> PAGE_SHIFT;
2607 offset = payload_index & ~PAGE_MASK;
2608 next_page_index = (page + 1) << PAGE_SHIFT;
2609 length =
2610 min(next_page_index, payload_end_index) - payload_index;
2611 pd[i].req_count = cpu_to_le16(length);
2612
2613 page_bus = page_private(buffer->pages[page]);
2614 pd[i].data_address = cpu_to_le32(page_bus + offset);
2615
2616 payload_index += length;
2617 }
2618
2619 if (p->interrupt)
2620 irq = DESCRIPTOR_IRQ_ALWAYS;
2621 else
2622 irq = DESCRIPTOR_NO_IRQ;
2623
2624 last = z == 2 ? d : d + z - 1;
2625 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2626 DESCRIPTOR_STATUS |
2627 DESCRIPTOR_BRANCH_ALWAYS |
2628 irq);
2629
2630 context_append(&ctx->context, d, z, header_z);
2631
2632 return 0;
2633 }
2634
2635 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2636 struct fw_iso_packet *packet,
2637 struct fw_iso_buffer *buffer,
2638 unsigned long payload)
2639 {
2640 struct descriptor *d, *pd;
2641 dma_addr_t d_bus, page_bus;
2642 u32 z, header_z, rest;
2643 int i, j, length;
2644 int page, offset, packet_count, header_size, payload_per_buffer;
2645
2646 /*
2647 * The OHCI controller puts the isochronous header and trailer in the
2648 * buffer, so we need at least 8 bytes.
2649 */
2650 packet_count = packet->header_length / ctx->base.header_size;
2651 header_size = max(ctx->base.header_size, (size_t)8);
2652
2653 /* Get header size in number of descriptors. */
2654 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2655 page = payload >> PAGE_SHIFT;
2656 offset = payload & ~PAGE_MASK;
2657 payload_per_buffer = packet->payload_length / packet_count;
2658
2659 for (i = 0; i < packet_count; i++) {
2660 /* d points to the header descriptor */
2661 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2662 d = context_get_descriptors(&ctx->context,
2663 z + header_z, &d_bus);
2664 if (d == NULL)
2665 return -ENOMEM;
2666
2667 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2668 DESCRIPTOR_INPUT_MORE);
2669 if (packet->skip && i == 0)
2670 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2671 d->req_count = cpu_to_le16(header_size);
2672 d->res_count = d->req_count;
2673 d->transfer_status = 0;
2674 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2675
2676 rest = payload_per_buffer;
2677 pd = d;
2678 for (j = 1; j < z; j++) {
2679 pd++;
2680 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2681 DESCRIPTOR_INPUT_MORE);
2682
2683 if (offset + rest < PAGE_SIZE)
2684 length = rest;
2685 else
2686 length = PAGE_SIZE - offset;
2687 pd->req_count = cpu_to_le16(length);
2688 pd->res_count = pd->req_count;
2689 pd->transfer_status = 0;
2690
2691 page_bus = page_private(buffer->pages[page]);
2692 pd->data_address = cpu_to_le32(page_bus + offset);
2693
2694 offset = (offset + length) & ~PAGE_MASK;
2695 rest -= length;
2696 if (offset == 0)
2697 page++;
2698 }
2699 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2700 DESCRIPTOR_INPUT_LAST |
2701 DESCRIPTOR_BRANCH_ALWAYS);
2702 if (packet->interrupt && i == packet_count - 1)
2703 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2704
2705 context_append(&ctx->context, d, z, header_z);
2706 }
2707
2708 return 0;
2709 }
2710
2711 static int queue_iso_buffer_fill(struct iso_context *ctx,
2712 struct fw_iso_packet *packet,
2713 struct fw_iso_buffer *buffer,
2714 unsigned long payload)
2715 {
2716 struct descriptor *d;
2717 dma_addr_t d_bus, page_bus;
2718 int page, offset, rest, z, i, length;
2719
2720 page = payload >> PAGE_SHIFT;
2721 offset = payload & ~PAGE_MASK;
2722 rest = packet->payload_length;
2723
2724 /* We need one descriptor for each page in the buffer. */
2725 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2726
2727 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2728 return -EFAULT;
2729
2730 for (i = 0; i < z; i++) {
2731 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2732 if (d == NULL)
2733 return -ENOMEM;
2734
2735 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2736 DESCRIPTOR_BRANCH_ALWAYS);
2737 if (packet->skip && i == 0)
2738 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2739 if (packet->interrupt && i == z - 1)
2740 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2741
2742 if (offset + rest < PAGE_SIZE)
2743 length = rest;
2744 else
2745 length = PAGE_SIZE - offset;
2746 d->req_count = cpu_to_le16(length);
2747 d->res_count = d->req_count;
2748 d->transfer_status = 0;
2749
2750 page_bus = page_private(buffer->pages[page]);
2751 d->data_address = cpu_to_le32(page_bus + offset);
2752
2753 rest -= length;
2754 offset = 0;
2755 page++;
2756
2757 context_append(&ctx->context, d, 1, 0);
2758 }
2759
2760 return 0;
2761 }
2762
2763 static int ohci_queue_iso(struct fw_iso_context *base,
2764 struct fw_iso_packet *packet,
2765 struct fw_iso_buffer *buffer,
2766 unsigned long payload)
2767 {
2768 struct iso_context *ctx = container_of(base, struct iso_context, base);
2769 unsigned long flags;
2770 int ret = -ENOSYS;
2771
2772 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2773 switch (base->type) {
2774 case FW_ISO_CONTEXT_TRANSMIT:
2775 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2776 break;
2777 case FW_ISO_CONTEXT_RECEIVE:
2778 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2779 break;
2780 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2781 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2782 break;
2783 }
2784 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2785
2786 return ret;
2787 }
2788
2789 static const struct fw_card_driver ohci_driver = {
2790 .enable = ohci_enable,
2791 .read_phy_reg = ohci_read_phy_reg,
2792 .update_phy_reg = ohci_update_phy_reg,
2793 .set_config_rom = ohci_set_config_rom,
2794 .send_request = ohci_send_request,
2795 .send_response = ohci_send_response,
2796 .cancel_packet = ohci_cancel_packet,
2797 .enable_phys_dma = ohci_enable_phys_dma,
2798 .read_csr = ohci_read_csr,
2799 .write_csr = ohci_write_csr,
2800
2801 .allocate_iso_context = ohci_allocate_iso_context,
2802 .free_iso_context = ohci_free_iso_context,
2803 .set_iso_channels = ohci_set_iso_channels,
2804 .queue_iso = ohci_queue_iso,
2805 .start_iso = ohci_start_iso,
2806 .stop_iso = ohci_stop_iso,
2807 };
2808
2809 #ifdef CONFIG_PPC_PMAC
2810 static void pmac_ohci_on(struct pci_dev *dev)
2811 {
2812 if (machine_is(powermac)) {
2813 struct device_node *ofn = pci_device_to_OF_node(dev);
2814
2815 if (ofn) {
2816 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2817 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2818 }
2819 }
2820 }
2821
2822 static void pmac_ohci_off(struct pci_dev *dev)
2823 {
2824 if (machine_is(powermac)) {
2825 struct device_node *ofn = pci_device_to_OF_node(dev);
2826
2827 if (ofn) {
2828 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2829 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2830 }
2831 }
2832 }
2833 #else
2834 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2835 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2836 #endif /* CONFIG_PPC_PMAC */
2837
2838 static int __devinit pci_probe(struct pci_dev *dev,
2839 const struct pci_device_id *ent)
2840 {
2841 struct fw_ohci *ohci;
2842 u32 bus_options, max_receive, link_speed, version, link_enh;
2843 u64 guid;
2844 int i, err, n_ir, n_it;
2845 size_t size;
2846
2847 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2848 if (ohci == NULL) {
2849 err = -ENOMEM;
2850 goto fail;
2851 }
2852
2853 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2854
2855 pmac_ohci_on(dev);
2856
2857 err = pci_enable_device(dev);
2858 if (err) {
2859 fw_error("Failed to enable OHCI hardware\n");
2860 goto fail_free;
2861 }
2862
2863 pci_set_master(dev);
2864 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2865 pci_set_drvdata(dev, ohci);
2866
2867 spin_lock_init(&ohci->lock);
2868 mutex_init(&ohci->phy_reg_mutex);
2869
2870 tasklet_init(&ohci->bus_reset_tasklet,
2871 bus_reset_tasklet, (unsigned long)ohci);
2872
2873 err = pci_request_region(dev, 0, ohci_driver_name);
2874 if (err) {
2875 fw_error("MMIO resource unavailable\n");
2876 goto fail_disable;
2877 }
2878
2879 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2880 if (ohci->registers == NULL) {
2881 fw_error("Failed to remap registers\n");
2882 err = -ENXIO;
2883 goto fail_iomem;
2884 }
2885
2886 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2887 if (ohci_quirks[i].vendor == dev->vendor &&
2888 (ohci_quirks[i].device == dev->device ||
2889 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2890 ohci->quirks = ohci_quirks[i].flags;
2891 break;
2892 }
2893 if (param_quirks)
2894 ohci->quirks = param_quirks;
2895
2896 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2897 if (dev->vendor == PCI_VENDOR_ID_TI) {
2898 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2899
2900 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2901 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2902 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2903
2904 /* use priority arbitration for asynchronous responses */
2905 link_enh |= TI_LinkEnh_enab_unfair;
2906
2907 /* required for aPhyEnhanceEnable to work */
2908 link_enh |= TI_LinkEnh_enab_accel;
2909
2910 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2911 }
2912
2913 ar_context_init(&ohci->ar_request_ctx, ohci,
2914 OHCI1394_AsReqRcvContextControlSet);
2915
2916 ar_context_init(&ohci->ar_response_ctx, ohci,
2917 OHCI1394_AsRspRcvContextControlSet);
2918
2919 context_init(&ohci->at_request_ctx, ohci,
2920 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2921
2922 context_init(&ohci->at_response_ctx, ohci,
2923 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2924
2925 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2926 ohci->ir_context_channels = ~0ULL;
2927 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2928 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2929 n_ir = hweight32(ohci->ir_context_mask);
2930 size = sizeof(struct iso_context) * n_ir;
2931 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2932
2933 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2934 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2935 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2936 n_it = hweight32(ohci->it_context_mask);
2937 size = sizeof(struct iso_context) * n_it;
2938 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2939
2940 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2941 err = -ENOMEM;
2942 goto fail_contexts;
2943 }
2944
2945 /* self-id dma buffer allocation */
2946 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2947 SELF_ID_BUF_SIZE,
2948 &ohci->self_id_bus,
2949 GFP_KERNEL);
2950 if (ohci->self_id_cpu == NULL) {
2951 err = -ENOMEM;
2952 goto fail_contexts;
2953 }
2954
2955 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2956 max_receive = (bus_options >> 12) & 0xf;
2957 link_speed = bus_options & 0x7;
2958 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2959 reg_read(ohci, OHCI1394_GUIDLo);
2960
2961 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2962 if (err)
2963 goto fail_self_id;
2964
2965 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2966 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2967 "%d IR + %d IT contexts, quirks 0x%x\n",
2968 dev_name(&dev->dev), version >> 16, version & 0xff,
2969 n_ir, n_it, ohci->quirks);
2970
2971 return 0;
2972
2973 fail_self_id:
2974 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2975 ohci->self_id_cpu, ohci->self_id_bus);
2976 fail_contexts:
2977 kfree(ohci->ir_context_list);
2978 kfree(ohci->it_context_list);
2979 context_release(&ohci->at_response_ctx);
2980 context_release(&ohci->at_request_ctx);
2981 ar_context_release(&ohci->ar_response_ctx);
2982 ar_context_release(&ohci->ar_request_ctx);
2983 pci_iounmap(dev, ohci->registers);
2984 fail_iomem:
2985 pci_release_region(dev, 0);
2986 fail_disable:
2987 pci_disable_device(dev);
2988 fail_free:
2989 kfree(&ohci->card);
2990 pmac_ohci_off(dev);
2991 fail:
2992 if (err == -ENOMEM)
2993 fw_error("Out of memory\n");
2994
2995 return err;
2996 }
2997
2998 static void pci_remove(struct pci_dev *dev)
2999 {
3000 struct fw_ohci *ohci;
3001
3002 ohci = pci_get_drvdata(dev);
3003 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3004 flush_writes(ohci);
3005 fw_core_remove_card(&ohci->card);
3006
3007 /*
3008 * FIXME: Fail all pending packets here, now that the upper
3009 * layers can't queue any more.
3010 */
3011
3012 software_reset(ohci);
3013 free_irq(dev->irq, ohci);
3014
3015 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3016 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3017 ohci->next_config_rom, ohci->next_config_rom_bus);
3018 if (ohci->config_rom)
3019 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3020 ohci->config_rom, ohci->config_rom_bus);
3021 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3022 ohci->self_id_cpu, ohci->self_id_bus);
3023 ar_context_release(&ohci->ar_request_ctx);
3024 ar_context_release(&ohci->ar_response_ctx);
3025 context_release(&ohci->at_request_ctx);
3026 context_release(&ohci->at_response_ctx);
3027 kfree(ohci->it_context_list);
3028 kfree(ohci->ir_context_list);
3029 pci_disable_msi(dev);
3030 pci_iounmap(dev, ohci->registers);
3031 pci_release_region(dev, 0);
3032 pci_disable_device(dev);
3033 kfree(&ohci->card);
3034 pmac_ohci_off(dev);
3035
3036 fw_notify("Removed fw-ohci device.\n");
3037 }
3038
3039 #ifdef CONFIG_PM
3040 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3041 {
3042 struct fw_ohci *ohci = pci_get_drvdata(dev);
3043 int err;
3044
3045 software_reset(ohci);
3046 free_irq(dev->irq, ohci);
3047 pci_disable_msi(dev);
3048 err = pci_save_state(dev);
3049 if (err) {
3050 fw_error("pci_save_state failed\n");
3051 return err;
3052 }
3053 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3054 if (err)
3055 fw_error("pci_set_power_state failed with %d\n", err);
3056 pmac_ohci_off(dev);
3057
3058 return 0;
3059 }
3060
3061 static int pci_resume(struct pci_dev *dev)
3062 {
3063 struct fw_ohci *ohci = pci_get_drvdata(dev);
3064 int err;
3065
3066 pmac_ohci_on(dev);
3067 pci_set_power_state(dev, PCI_D0);
3068 pci_restore_state(dev);
3069 err = pci_enable_device(dev);
3070 if (err) {
3071 fw_error("pci_enable_device failed\n");
3072 return err;
3073 }
3074
3075 return ohci_enable(&ohci->card, NULL, 0);
3076 }
3077 #endif
3078
3079 static const struct pci_device_id pci_table[] = {
3080 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3081 { }
3082 };
3083
3084 MODULE_DEVICE_TABLE(pci, pci_table);
3085
3086 static struct pci_driver fw_ohci_pci_driver = {
3087 .name = ohci_driver_name,
3088 .id_table = pci_table,
3089 .probe = pci_probe,
3090 .remove = pci_remove,
3091 #ifdef CONFIG_PM
3092 .resume = pci_resume,
3093 .suspend = pci_suspend,
3094 #endif
3095 };
3096
3097 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3098 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3099 MODULE_LICENSE("GPL");
3100
3101 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3102 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3103 MODULE_ALIAS("ohci1394");
3104 #endif
3105
3106 static int __init fw_ohci_init(void)
3107 {
3108 return pci_register_driver(&fw_ohci_pci_driver);
3109 }
3110
3111 static void __exit fw_ohci_cleanup(void)
3112 {
3113 pci_unregister_driver(&fw_ohci_pci_driver);
3114 }
3115
3116 module_init(fw_ohci_init);
3117 module_exit(fw_ohci_cleanup);
Linux kernel - Deliverables
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