drivers/gpio/gpio-crystalcove.c

   1 /*
   2  * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
   3  *
   4  * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License version
   8  * 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * Author: Yang, Bin <bin.yang@intel.com>
  16  */
  17
  18 #include <linux/interrupt.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/gpio.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/bitops.h>
  23 #include <linux/regmap.h>
  24 #include <linux/mfd/intel_soc_pmic.h>
  25
  26 #define CRYSTALCOVE_GPIO_NUM    16
  27
  28 #define UPDATE_IRQ_TYPE         BIT(0)
  29 #define UPDATE_IRQ_MASK         BIT(1)
  30
  31 #define GPIO0IRQ                0x0b
  32 #define GPIO1IRQ                0x0c
  33 #define MGPIO0IRQS0             0x19
  34 #define MGPIO1IRQS0             0x1a
  35 #define MGPIO0IRQSX             0x1b
  36 #define MGPIO1IRQSX             0x1c
  37 #define GPIO0P0CTLO             0x2b
  38 #define GPIO0P0CTLI             0x33
  39 #define GPIO1P0CTLO             0x3b
  40 #define GPIO1P0CTLI             0x43
  41
  42 #define CTLI_INTCNT_DIS         (0)
  43 #define CTLI_INTCNT_NE          (1 << 1)
  44 #define CTLI_INTCNT_PE          (2 << 1)
  45 #define CTLI_INTCNT_BE          (3 << 1)
  46
  47 #define CTLO_DIR_IN             (0)
  48 #define CTLO_DIR_OUT            (1 << 5)
  49
  50 #define CTLO_DRV_CMOS           (0)
  51 #define CTLO_DRV_OD             (1 << 4)
  52
  53 #define CTLO_DRV_REN            (1 << 3)
  54
  55 #define CTLO_RVAL_2KDW          (0)
  56 #define CTLO_RVAL_2KUP          (1 << 1)
  57 #define CTLO_RVAL_50KDW         (2 << 1)
  58 #define CTLO_RVAL_50KUP         (3 << 1)
  59
  60 #define CTLO_INPUT_SET  (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
  61 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
  62
  63 enum ctrl_register {
  64         CTRL_IN,
  65         CTRL_OUT,
  66 };
  67
  68 /**
  69  * struct crystalcove_gpio - Crystal Cove GPIO controller
  70  * @buslock: for bus lock/sync and unlock.
  71  * @chip: the abstract gpio_chip structure.
  72  * @regmap: the regmap from the parent device.
  73  * @update: pending IRQ setting update, to be written to the chip upon unlock.
  74  * @intcnt_value: the Interrupt Detect value to be written.
  75  * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
  76  */
  77 struct crystalcove_gpio {
  78         struct mutex buslock; /* irq_bus_lock */
  79         struct gpio_chip chip;
  80         struct regmap *regmap;
  81         int update;
  82         int intcnt_value;
  83         bool set_irq_mask;
  84 };
  85
  86 static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc)
  87 {
  88         return container_of(gc, struct crystalcove_gpio, chip);
  89 }
  90
  91 static inline int to_reg(int gpio, enum ctrl_register reg_type)
  92 {
  93         int reg;
  94
  95         if (reg_type == CTRL_IN) {
  96                 if (gpio < 8)
  97                         reg = GPIO0P0CTLI;
  98                 else
  99                         reg = GPIO1P0CTLI;
 100         } else {
 101                 if (gpio < 8)
 102                         reg = GPIO0P0CTLO;
 103                 else
 104                         reg = GPIO1P0CTLO;
 105         }
 106
 107         return reg + gpio % 8;
 108 }
 109
 110 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
 111                                         int gpio)
 112 {
 113         u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
 114         int mask = BIT(gpio % 8);
 115
 116         if (cg->set_irq_mask)
 117                 regmap_update_bits(cg->regmap, mirqs0, mask, mask);
 118         else
 119                 regmap_update_bits(cg->regmap, mirqs0, mask, 0);
 120 }
 121
 122 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
 123 {
 124         int reg = to_reg(gpio, CTRL_IN);
 125
 126         regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
 127 }
 128
 129 static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
 130 {
 131         struct crystalcove_gpio *cg = to_cg(chip);
 132
 133         return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
 134                             CTLO_INPUT_SET);
 135 }
 136
 137 static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
 138                                     int value)
 139 {
 140         struct crystalcove_gpio *cg = to_cg(chip);
 141
 142         return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
 143                             CTLO_OUTPUT_SET | value);
 144 }
 145
 146 static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
 147 {
 148         struct crystalcove_gpio *cg = to_cg(chip);
 149         int ret;
 150         unsigned int val;
 151
 152         ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
 153         if (ret)
 154                 return ret;
 155
 156         return val & 0x1;
 157 }
 158
 159 static void crystalcove_gpio_set(struct gpio_chip *chip,
 160                                  unsigned gpio, int value)
 161 {
 162         struct crystalcove_gpio *cg = to_cg(chip);
 163
 164         if (value)
 165                 regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
 166         else
 167                 regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
 168 }
 169
 170 static int crystalcove_irq_type(struct irq_data *data, unsigned type)
 171 {
 172         struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
 173
 174         switch (type) {
 175         case IRQ_TYPE_NONE:
 176                 cg->intcnt_value = CTLI_INTCNT_DIS;
 177                 break;
 178         case IRQ_TYPE_EDGE_BOTH:
 179                 cg->intcnt_value = CTLI_INTCNT_BE;
 180                 break;
 181         case IRQ_TYPE_EDGE_RISING:
 182                 cg->intcnt_value = CTLI_INTCNT_PE;
 183                 break;
 184         case IRQ_TYPE_EDGE_FALLING:
 185                 cg->intcnt_value = CTLI_INTCNT_NE;
 186                 break;
 187         default:
 188                 return -EINVAL;
 189         }
 190
 191         cg->update |= UPDATE_IRQ_TYPE;
 192
 193         return 0;
 194 }
 195
 196 static void crystalcove_bus_lock(struct irq_data *data)
 197 {
 198         struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
 199
 200         mutex_lock(&cg->buslock);
 201 }
 202
 203 static void crystalcove_bus_sync_unlock(struct irq_data *data)
 204 {
 205         struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
 206         int gpio = data->hwirq;
 207
 208         if (cg->update & UPDATE_IRQ_TYPE)
 209                 crystalcove_update_irq_ctrl(cg, gpio);
 210         if (cg->update & UPDATE_IRQ_MASK)
 211                 crystalcove_update_irq_mask(cg, gpio);
 212         cg->update = 0;
 213
 214         mutex_unlock(&cg->buslock);
 215 }
 216
 217 static void crystalcove_irq_unmask(struct irq_data *data)
 218 {
 219         struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
 220
 221         cg->set_irq_mask = false;
 222         cg->update |= UPDATE_IRQ_MASK;
 223 }
 224
 225 static void crystalcove_irq_mask(struct irq_data *data)
 226 {
 227         struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
 228
 229         cg->set_irq_mask = true;
 230         cg->update |= UPDATE_IRQ_MASK;
 231 }
 232
 233 static struct irq_chip crystalcove_irqchip = {
 234         .name                   = "Crystal Cove",
 235         .irq_mask               = crystalcove_irq_mask,
 236         .irq_unmask             = crystalcove_irq_unmask,
 237         .irq_set_type           = crystalcove_irq_type,
 238         .irq_bus_lock           = crystalcove_bus_lock,
 239         .irq_bus_sync_unlock    = crystalcove_bus_sync_unlock,
 240 };
 241
 242 static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
 243 {
 244         struct crystalcove_gpio *cg = data;
 245         unsigned int p0, p1;
 246         int pending;
 247         int gpio;
 248         unsigned int virq;
 249
 250         if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
 251             regmap_read(cg->regmap, GPIO1IRQ, &p1))
 252                 return IRQ_NONE;
 253
 254         regmap_write(cg->regmap, GPIO0IRQ, p0);
 255         regmap_write(cg->regmap, GPIO1IRQ, p1);
 256
 257         pending = p0 | p1 << 8;
 258
 259         for (gpio = 0; gpio < cg->chip.ngpio; gpio++) {
 260                 if (pending & BIT(gpio)) {
 261                         virq = irq_find_mapping(cg->chip.irqdomain, gpio);
 262                         generic_handle_irq(virq);
 263                 }
 264         }
 265
 266         return IRQ_HANDLED;
 267 }
 268
 269 static void crystalcove_gpio_dbg_show(struct seq_file *s,
 270                                       struct gpio_chip *chip)
 271 {
 272         struct crystalcove_gpio *cg = to_cg(chip);
 273         int gpio, offset;
 274         unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
 275
 276         for (gpio = 0; gpio < cg->chip.ngpio; gpio++) {
 277                 regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
 278                 regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
 279                 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
 280                             &mirqs0);
 281                 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
 282                             &mirqsx);
 283                 regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
 284                             &irq);
 285
 286                 offset = gpio % 8;
 287                 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
 288                            gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
 289                            ctli & 0x1 ? "hi" : "lo",
 290                            ctli & CTLI_INTCNT_NE ? "fall" : "    ",
 291                            ctli & CTLI_INTCNT_PE ? "rise" : "    ",
 292                            ctlo,
 293                            mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
 294                            mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
 295                            irq & BIT(offset) ? "pending" : "       ");
 296         }
 297 }
 298
 299 static int crystalcove_gpio_probe(struct platform_device *pdev)
 300 {
 301         int irq = platform_get_irq(pdev, 0);
 302         struct crystalcove_gpio *cg;
 303         int retval;
 304         struct device *dev = pdev->dev.parent;
 305         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 306
 307         if (irq < 0)
 308                 return irq;
 309
 310         cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
 311         if (!cg)
 312                 return -ENOMEM;
 313
 314         platform_set_drvdata(pdev, cg);
 315
 316         mutex_init(&cg->buslock);
 317         cg->chip.label = KBUILD_MODNAME;
 318         cg->chip.direction_input = crystalcove_gpio_dir_in;
 319         cg->chip.direction_output = crystalcove_gpio_dir_out;
 320         cg->chip.get = crystalcove_gpio_get;
 321         cg->chip.set = crystalcove_gpio_set;
 322         cg->chip.base = -1;
 323         cg->chip.ngpio = CRYSTALCOVE_GPIO_NUM;
 324         cg->chip.can_sleep = true;
 325         cg->chip.dev = dev;
 326         cg->chip.dbg_show = crystalcove_gpio_dbg_show;
 327         cg->regmap = pmic->regmap;
 328
 329         retval = gpiochip_add(&cg->chip);
 330         if (retval) {
 331                 dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
 332                 return retval;
 333         }
 334
 335         gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,
 336                              handle_simple_irq, IRQ_TYPE_NONE);
 337
 338         retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
 339                                       IRQF_ONESHOT, KBUILD_MODNAME, cg);
 340
 341         if (retval) {
 342                 dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
 343                 goto out_remove_gpio;
 344         }
 345
 346         return 0;
 347
 348 out_remove_gpio:
 349         WARN_ON(gpiochip_remove(&cg->chip));
 350         return retval;
 351 }
 352
 353 static int crystalcove_gpio_remove(struct platform_device *pdev)
 354 {
 355         struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
 356         int irq = platform_get_irq(pdev, 0);
 357         int err;
 358
 359         err = gpiochip_remove(&cg->chip);
 360
 361         if (irq >= 0)
 362                 free_irq(irq, cg);
 363
 364         return err;
 365 }
 366
 367 static struct platform_driver crystalcove_gpio_driver = {
 368         .probe = crystalcove_gpio_probe,
 369         .remove = crystalcove_gpio_remove,
 370         .driver = {
 371                 .name = "crystal_cove_gpio",
 372                 .owner = THIS_MODULE,
 373         },
 374 };
 375
 376 module_platform_driver(crystalcove_gpio_driver);
 377
 378 MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
 379 MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
 380 MODULE_LICENSE("GPL v2");