2 * Generic driver for memory-mapped GPIO controllers.
4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
14 * ..The simplest form of a GPIO controller that the driver supports is``
15 * `.just a single "data" register, where GPIO state can be read and/or `
16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
19 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
20 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
21 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
22 `....trivial..'~`.```.```
24 * .```````~~~~`..`.``.``.
25 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
26 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
27 * . register the device with -be`. .with a pair of set/clear-bit registers ,
28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
29 * ``.`.``...``` ```.. output pins are also supported.`
30 * ^^ `````.`````````.,``~``~``~~``````
32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
33 * .. The expectation is that in at least some cases . ,-~~~-,
34 * .this will be used with roll-your-own ASIC/FPGA .` \ /
35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
36 * ..````````......``````````` \o_
40 * ...`````~~`.....``.`..........``````.`.``.```........``.
41 * ` 8, 16, 32 and 64 bits registers are supported, and``.
42 * . the number of GPIOs is determined by the width of ~
43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
47 #include <linux/init.h>
48 #include <linux/err.h>
49 #include <linux/bug.h>
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/spinlock.h>
53 #include <linux/compiler.h>
54 #include <linux/types.h>
55 #include <linux/errno.h>
56 #include <linux/log2.h>
57 #include <linux/ioport.h>
59 #include <linux/gpio.h>
60 #include <linux/slab.h>
61 #include <linux/platform_device.h>
62 #include <linux/mod_devicetable.h>
63 #include <linux/basic_mmio_gpio.h>
65 static void bgpio_write8(void __iomem
*reg
, unsigned long data
)
70 static unsigned long bgpio_read8(void __iomem
*reg
)
75 static void bgpio_write16(void __iomem
*reg
, unsigned long data
)
80 static unsigned long bgpio_read16(void __iomem
*reg
)
85 static void bgpio_write32(void __iomem
*reg
, unsigned long data
)
90 static unsigned long bgpio_read32(void __iomem
*reg
)
95 #if BITS_PER_LONG >= 64
96 static void bgpio_write64(void __iomem
*reg
, unsigned long data
)
101 static unsigned long bgpio_read64(void __iomem
*reg
)
105 #endif /* BITS_PER_LONG >= 64 */
107 static void bgpio_write16be(void __iomem
*reg
, unsigned long data
)
109 iowrite16be(data
, reg
);
112 static unsigned long bgpio_read16be(void __iomem
*reg
)
114 return ioread16be(reg
);
117 static void bgpio_write32be(void __iomem
*reg
, unsigned long data
)
119 iowrite32be(data
, reg
);
122 static unsigned long bgpio_read32be(void __iomem
*reg
)
124 return ioread32be(reg
);
127 static unsigned long bgpio_pin2mask(struct bgpio_chip
*bgc
, unsigned int pin
)
132 static unsigned long bgpio_pin2mask_be(struct bgpio_chip
*bgc
,
135 return 1 << (bgc
->bits
- 1 - pin
);
138 static int bgpio_get_set(struct gpio_chip
*gc
, unsigned int gpio
)
140 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
141 unsigned long pinmask
= bgc
->pin2mask(bgc
, gpio
);
143 if (bgc
->dir
& pinmask
)
144 return bgc
->read_reg(bgc
->reg_set
) & pinmask
;
146 return bgc
->read_reg(bgc
->reg_dat
) & pinmask
;
149 static int bgpio_get(struct gpio_chip
*gc
, unsigned int gpio
)
151 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
153 return !!(bgc
->read_reg(bgc
->reg_dat
) & bgc
->pin2mask(bgc
, gpio
));
156 static void bgpio_set(struct gpio_chip
*gc
, unsigned int gpio
, int val
)
158 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
159 unsigned long mask
= bgc
->pin2mask(bgc
, gpio
);
162 spin_lock_irqsave(&bgc
->lock
, flags
);
169 bgc
->write_reg(bgc
->reg_dat
, bgc
->data
);
171 spin_unlock_irqrestore(&bgc
->lock
, flags
);
174 static void bgpio_set_with_clear(struct gpio_chip
*gc
, unsigned int gpio
,
177 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
178 unsigned long mask
= bgc
->pin2mask(bgc
, gpio
);
181 bgc
->write_reg(bgc
->reg_set
, mask
);
183 bgc
->write_reg(bgc
->reg_clr
, mask
);
186 static void bgpio_set_set(struct gpio_chip
*gc
, unsigned int gpio
, int val
)
188 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
189 unsigned long mask
= bgc
->pin2mask(bgc
, gpio
);
192 spin_lock_irqsave(&bgc
->lock
, flags
);
199 bgc
->write_reg(bgc
->reg_set
, bgc
->data
);
201 spin_unlock_irqrestore(&bgc
->lock
, flags
);
204 static void bgpio_multiple_get_masks(struct bgpio_chip
*bgc
,
205 unsigned long *mask
, unsigned long *bits
,
206 unsigned long *set_mask
,
207 unsigned long *clear_mask
)
214 for (i
= 0; i
< bgc
->bits
; i
++) {
217 if (__test_and_clear_bit(i
, mask
)) {
218 if (test_bit(i
, bits
))
219 *set_mask
|= bgc
->pin2mask(bgc
, i
);
221 *clear_mask
|= bgc
->pin2mask(bgc
, i
);
226 static void bgpio_set_multiple_single_reg(struct bgpio_chip
*bgc
,
232 unsigned long set_mask
, clear_mask
;
234 spin_lock_irqsave(&bgc
->lock
, flags
);
236 bgpio_multiple_get_masks(bgc
, mask
, bits
, &set_mask
, &clear_mask
);
238 bgc
->data
|= set_mask
;
239 bgc
->data
&= ~clear_mask
;
241 bgc
->write_reg(reg
, bgc
->data
);
243 spin_unlock_irqrestore(&bgc
->lock
, flags
);
246 static void bgpio_set_multiple(struct gpio_chip
*gc
, unsigned long *mask
,
249 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
251 bgpio_set_multiple_single_reg(bgc
, mask
, bits
, bgc
->reg_dat
);
254 static void bgpio_set_multiple_set(struct gpio_chip
*gc
, unsigned long *mask
,
257 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
259 bgpio_set_multiple_single_reg(bgc
, mask
, bits
, bgc
->reg_set
);
262 static void bgpio_set_multiple_with_clear(struct gpio_chip
*gc
,
266 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
267 unsigned long set_mask
, clear_mask
;
269 bgpio_multiple_get_masks(bgc
, mask
, bits
, &set_mask
, &clear_mask
);
272 bgc
->write_reg(bgc
->reg_set
, set_mask
);
274 bgc
->write_reg(bgc
->reg_clr
, clear_mask
);
277 static int bgpio_simple_dir_in(struct gpio_chip
*gc
, unsigned int gpio
)
282 static int bgpio_simple_dir_out(struct gpio_chip
*gc
, unsigned int gpio
,
285 gc
->set(gc
, gpio
, val
);
290 static int bgpio_dir_in(struct gpio_chip
*gc
, unsigned int gpio
)
292 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
295 spin_lock_irqsave(&bgc
->lock
, flags
);
297 bgc
->dir
&= ~bgc
->pin2mask(bgc
, gpio
);
298 bgc
->write_reg(bgc
->reg_dir
, bgc
->dir
);
300 spin_unlock_irqrestore(&bgc
->lock
, flags
);
305 static int bgpio_dir_out(struct gpio_chip
*gc
, unsigned int gpio
, int val
)
307 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
310 gc
->set(gc
, gpio
, val
);
312 spin_lock_irqsave(&bgc
->lock
, flags
);
314 bgc
->dir
|= bgc
->pin2mask(bgc
, gpio
);
315 bgc
->write_reg(bgc
->reg_dir
, bgc
->dir
);
317 spin_unlock_irqrestore(&bgc
->lock
, flags
);
322 static int bgpio_dir_in_inv(struct gpio_chip
*gc
, unsigned int gpio
)
324 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
327 spin_lock_irqsave(&bgc
->lock
, flags
);
329 bgc
->dir
|= bgc
->pin2mask(bgc
, gpio
);
330 bgc
->write_reg(bgc
->reg_dir
, bgc
->dir
);
332 spin_unlock_irqrestore(&bgc
->lock
, flags
);
337 static int bgpio_dir_out_inv(struct gpio_chip
*gc
, unsigned int gpio
, int val
)
339 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
342 gc
->set(gc
, gpio
, val
);
344 spin_lock_irqsave(&bgc
->lock
, flags
);
346 bgc
->dir
&= ~bgc
->pin2mask(bgc
, gpio
);
347 bgc
->write_reg(bgc
->reg_dir
, bgc
->dir
);
349 spin_unlock_irqrestore(&bgc
->lock
, flags
);
354 static int bgpio_setup_accessors(struct device
*dev
,
355 struct bgpio_chip
*bgc
,
362 bgc
->read_reg
= bgpio_read8
;
363 bgc
->write_reg
= bgpio_write8
;
367 bgc
->read_reg
= bgpio_read16be
;
368 bgc
->write_reg
= bgpio_write16be
;
370 bgc
->read_reg
= bgpio_read16
;
371 bgc
->write_reg
= bgpio_write16
;
376 bgc
->read_reg
= bgpio_read32be
;
377 bgc
->write_reg
= bgpio_write32be
;
379 bgc
->read_reg
= bgpio_read32
;
380 bgc
->write_reg
= bgpio_write32
;
383 #if BITS_PER_LONG >= 64
387 "64 bit big endian byte order unsupported\n");
390 bgc
->read_reg
= bgpio_read64
;
391 bgc
->write_reg
= bgpio_write64
;
394 #endif /* BITS_PER_LONG >= 64 */
396 dev_err(dev
, "unsupported data width %u bits\n", bgc
->bits
);
400 bgc
->pin2mask
= bit_be
? bgpio_pin2mask_be
: bgpio_pin2mask
;
406 * Create the device and allocate the resources. For setting GPIO's there are
407 * three supported configurations:
409 * - single input/output register resource (named "dat").
410 * - set/clear pair (named "set" and "clr").
411 * - single output register resource and single input resource ("set" and
414 * For the single output register, this drives a 1 by setting a bit and a zero
415 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
416 * in the set register and clears it by setting a bit in the clear register.
417 * The configuration is detected by which resources are present.
419 * For setting the GPIO direction, there are three supported configurations:
421 * - simple bidirection GPIO that requires no configuration.
422 * - an output direction register (named "dirout") where a 1 bit
423 * indicates the GPIO is an output.
424 * - an input direction register (named "dirin") where a 1 bit indicates
425 * the GPIO is an input.
427 static int bgpio_setup_io(struct bgpio_chip
*bgc
,
441 bgc
->gc
.set
= bgpio_set_with_clear
;
442 bgc
->gc
.set_multiple
= bgpio_set_multiple_with_clear
;
443 } else if (set
&& !clr
) {
445 bgc
->gc
.set
= bgpio_set_set
;
446 bgc
->gc
.set_multiple
= bgpio_set_multiple_set
;
448 bgc
->gc
.set
= bgpio_set
;
449 bgc
->gc
.set_multiple
= bgpio_set_multiple
;
452 if (!(flags
& BGPIOF_UNREADABLE_REG_SET
) &&
453 (flags
& BGPIOF_READ_OUTPUT_REG_SET
))
454 bgc
->gc
.get
= bgpio_get_set
;
456 bgc
->gc
.get
= bgpio_get
;
461 static int bgpio_setup_direction(struct bgpio_chip
*bgc
,
462 void __iomem
*dirout
,
465 if (dirout
&& dirin
) {
468 bgc
->reg_dir
= dirout
;
469 bgc
->gc
.direction_output
= bgpio_dir_out
;
470 bgc
->gc
.direction_input
= bgpio_dir_in
;
472 bgc
->reg_dir
= dirin
;
473 bgc
->gc
.direction_output
= bgpio_dir_out_inv
;
474 bgc
->gc
.direction_input
= bgpio_dir_in_inv
;
476 bgc
->gc
.direction_output
= bgpio_simple_dir_out
;
477 bgc
->gc
.direction_input
= bgpio_simple_dir_in
;
483 static int bgpio_request(struct gpio_chip
*chip
, unsigned gpio_pin
)
485 if (gpio_pin
< chip
->ngpio
)
491 int bgpio_remove(struct bgpio_chip
*bgc
)
493 gpiochip_remove(&bgc
->gc
);
496 EXPORT_SYMBOL_GPL(bgpio_remove
);
498 int bgpio_init(struct bgpio_chip
*bgc
, struct device
*dev
,
499 unsigned long sz
, void __iomem
*dat
, void __iomem
*set
,
500 void __iomem
*clr
, void __iomem
*dirout
, void __iomem
*dirin
,
505 if (!is_power_of_2(sz
))
509 if (bgc
->bits
> BITS_PER_LONG
)
512 spin_lock_init(&bgc
->lock
);
514 bgc
->gc
.label
= dev_name(dev
);
516 bgc
->gc
.ngpio
= bgc
->bits
;
517 bgc
->gc
.request
= bgpio_request
;
519 ret
= bgpio_setup_io(bgc
, dat
, set
, clr
, flags
);
523 ret
= bgpio_setup_accessors(dev
, bgc
, flags
& BGPIOF_BIG_ENDIAN
,
524 flags
& BGPIOF_BIG_ENDIAN_BYTE_ORDER
);
528 ret
= bgpio_setup_direction(bgc
, dirout
, dirin
);
532 bgc
->data
= bgc
->read_reg(bgc
->reg_dat
);
533 if (bgc
->gc
.set
== bgpio_set_set
&&
534 !(flags
& BGPIOF_UNREADABLE_REG_SET
))
535 bgc
->data
= bgc
->read_reg(bgc
->reg_set
);
536 if (bgc
->reg_dir
&& !(flags
& BGPIOF_UNREADABLE_REG_DIR
))
537 bgc
->dir
= bgc
->read_reg(bgc
->reg_dir
);
541 EXPORT_SYMBOL_GPL(bgpio_init
);
543 #ifdef CONFIG_GPIO_GENERIC_PLATFORM
545 static void __iomem
*bgpio_map(struct platform_device
*pdev
,
547 resource_size_t sane_sz
,
550 struct device
*dev
= &pdev
->dev
;
552 resource_size_t start
;
558 r
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, name
);
562 sz
= resource_size(r
);
569 if (!devm_request_mem_region(dev
, start
, sz
, r
->name
)) {
574 ret
= devm_ioremap(dev
, start
, sz
);
583 static int bgpio_pdev_probe(struct platform_device
*pdev
)
585 struct device
*dev
= &pdev
->dev
;
590 void __iomem
*dirout
;
593 unsigned long flags
= pdev
->id_entry
->driver_data
;
595 struct bgpio_chip
*bgc
;
596 struct bgpio_pdata
*pdata
= dev_get_platdata(dev
);
598 r
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dat");
602 sz
= resource_size(r
);
604 dat
= bgpio_map(pdev
, "dat", sz
, &err
);
606 return err
? err
: -EINVAL
;
608 set
= bgpio_map(pdev
, "set", sz
, &err
);
612 clr
= bgpio_map(pdev
, "clr", sz
, &err
);
616 dirout
= bgpio_map(pdev
, "dirout", sz
, &err
);
620 dirin
= bgpio_map(pdev
, "dirin", sz
, &err
);
624 bgc
= devm_kzalloc(&pdev
->dev
, sizeof(*bgc
), GFP_KERNEL
);
628 err
= bgpio_init(bgc
, dev
, sz
, dat
, set
, clr
, dirout
, dirin
, flags
);
634 bgc
->gc
.label
= pdata
->label
;
635 bgc
->gc
.base
= pdata
->base
;
636 if (pdata
->ngpio
> 0)
637 bgc
->gc
.ngpio
= pdata
->ngpio
;
640 platform_set_drvdata(pdev
, bgc
);
642 return gpiochip_add(&bgc
->gc
);
645 static int bgpio_pdev_remove(struct platform_device
*pdev
)
647 struct bgpio_chip
*bgc
= platform_get_drvdata(pdev
);
649 return bgpio_remove(bgc
);
652 static const struct platform_device_id bgpio_id_table
[] = {
654 .name
= "basic-mmio-gpio",
657 .name
= "basic-mmio-gpio-be",
658 .driver_data
= BGPIOF_BIG_ENDIAN
,
662 MODULE_DEVICE_TABLE(platform
, bgpio_id_table
);
664 static struct platform_driver bgpio_driver
= {
666 .name
= "basic-mmio-gpio",
668 .id_table
= bgpio_id_table
,
669 .probe
= bgpio_pdev_probe
,
670 .remove
= bgpio_pdev_remove
,
673 module_platform_driver(bgpio_driver
);
675 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
677 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
678 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
679 MODULE_LICENSE("GPL");