drivers/gpio/gpio-mxc.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/irq.h>
  26 #include <linux/gpio.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/slab.h>
  29 #include <mach/hardware.h>
  30 #include <asm-generic/bug.h>
  31
  32 struct mxc_gpio_port {
  33         struct list_head node;
  34         void __iomem *base;
  35         int irq;
  36         int irq_high;
  37         int virtual_irq_start;
  38         struct gpio_chip chip;
  39         u32 both_edges;
  40         spinlock_t lock;
  41 };
  42
  43 /*
  44  * MX2 has one interrupt *for all* gpio ports. The list is used
  45  * to save the references to all ports, so that mx2_gpio_irq_handler
  46  * can walk through all interrupt status registers.
  47  */
  48 static LIST_HEAD(mxc_gpio_ports);
  49
  50 #define cpu_is_mx1_mx2()        (cpu_is_mx1() || cpu_is_mx2())
  51
  52 #define GPIO_DR         (cpu_is_mx1_mx2() ? 0x1c : 0x00)
  53 #define GPIO_GDIR       (cpu_is_mx1_mx2() ? 0x00 : 0x04)
  54 #define GPIO_PSR        (cpu_is_mx1_mx2() ? 0x24 : 0x08)
  55 #define GPIO_ICR1       (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
  56 #define GPIO_ICR2       (cpu_is_mx1_mx2() ? 0x2C : 0x10)
  57 #define GPIO_IMR        (cpu_is_mx1_mx2() ? 0x30 : 0x14)
  58 #define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
  59
  60 #define GPIO_INT_LOW_LEV        (cpu_is_mx1_mx2() ? 0x3 : 0x0)
  61 #define GPIO_INT_HIGH_LEV       (cpu_is_mx1_mx2() ? 0x2 : 0x1)
  62 #define GPIO_INT_RISE_EDGE      (cpu_is_mx1_mx2() ? 0x0 : 0x2)
  63 #define GPIO_INT_FALL_EDGE      (cpu_is_mx1_mx2() ? 0x1 : 0x3)
  64 #define GPIO_INT_NONE           0x4
  65
  66 /* Note: This driver assumes 32 GPIOs are handled in one register */
  67
  68 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
  69 {
  70         writel(1 << index, port->base + GPIO_ISR);
  71 }
  72
  73 static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
  74                                 int enable)
  75 {
  76         u32 l;
  77
  78         l = readl(port->base + GPIO_IMR);
  79         l = (l & (~(1 << index))) | (!!enable << index);
  80         writel(l, port->base + GPIO_IMR);
  81 }
  82
  83 static void gpio_ack_irq(struct irq_data *d)
  84 {
  85         struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
  86         u32 gpio = irq_to_gpio(d->irq);
  87         _clear_gpio_irqstatus(port, gpio & 0x1f);
  88 }
  89
  90 static void gpio_mask_irq(struct irq_data *d)
  91 {
  92         struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
  93         u32 gpio = irq_to_gpio(d->irq);
  94         _set_gpio_irqenable(port, gpio & 0x1f, 0);
  95 }
  96
  97 static void gpio_unmask_irq(struct irq_data *d)
  98 {
  99         struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
 100         u32 gpio = irq_to_gpio(d->irq);
 101         _set_gpio_irqenable(port, gpio & 0x1f, 1);
 102 }
 103
 104 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
 105
 106 static int gpio_set_irq_type(struct irq_data *d, u32 type)
 107 {
 108         u32 gpio = irq_to_gpio(d->irq);
 109         struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
 110         u32 bit, val;
 111         int edge;
 112         void __iomem *reg = port->base;
 113
 114         port->both_edges &= ~(1 << (gpio & 31));
 115         switch (type) {
 116         case IRQ_TYPE_EDGE_RISING:
 117                 edge = GPIO_INT_RISE_EDGE;
 118                 break;
 119         case IRQ_TYPE_EDGE_FALLING:
 120                 edge = GPIO_INT_FALL_EDGE;
 121                 break;
 122         case IRQ_TYPE_EDGE_BOTH:
 123                 val = mxc_gpio_get(&port->chip, gpio & 31);
 124                 if (val) {
 125                         edge = GPIO_INT_LOW_LEV;
 126                         pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
 127                 } else {
 128                         edge = GPIO_INT_HIGH_LEV;
 129                         pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
 130                 }
 131                 port->both_edges |= 1 << (gpio & 31);
 132                 break;
 133         case IRQ_TYPE_LEVEL_LOW:
 134                 edge = GPIO_INT_LOW_LEV;
 135                 break;
 136         case IRQ_TYPE_LEVEL_HIGH:
 137                 edge = GPIO_INT_HIGH_LEV;
 138                 break;
 139         default:
 140                 return -EINVAL;
 141         }
 142
 143         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 144         bit = gpio & 0xf;
 145         val = readl(reg) & ~(0x3 << (bit << 1));
 146         writel(val | (edge << (bit << 1)), reg);
 147         _clear_gpio_irqstatus(port, gpio & 0x1f);
 148
 149         return 0;
 150 }
 151
 152 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 153 {
 154         void __iomem *reg = port->base;
 155         u32 bit, val;
 156         int edge;
 157
 158         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 159         bit = gpio & 0xf;
 160         val = readl(reg);
 161         edge = (val >> (bit << 1)) & 3;
 162         val &= ~(0x3 << (bit << 1));
 163         if (edge == GPIO_INT_HIGH_LEV) {
 164                 edge = GPIO_INT_LOW_LEV;
 165                 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
 166         } else if (edge == GPIO_INT_LOW_LEV) {
 167                 edge = GPIO_INT_HIGH_LEV;
 168                 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
 169         } else {
 170                 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
 171                        gpio, edge);
 172                 return;
 173         }
 174         writel(val | (edge << (bit << 1)), reg);
 175 }
 176
 177 /* handle 32 interrupts in one status register */
 178 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 179 {
 180         u32 gpio_irq_no_base = port->virtual_irq_start;
 181
 182         while (irq_stat != 0) {
 183                 int irqoffset = fls(irq_stat) - 1;
 184
 185                 if (port->both_edges & (1 << irqoffset))
 186                         mxc_flip_edge(port, irqoffset);
 187
 188                 generic_handle_irq(gpio_irq_no_base + irqoffset);
 189
 190                 irq_stat &= ~(1 << irqoffset);
 191         }
 192 }
 193
 194 /* MX1 and MX3 has one interrupt *per* gpio port */
 195 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 196 {
 197         u32 irq_stat;
 198         struct mxc_gpio_port *port = irq_get_handler_data(irq);
 199
 200         irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
 201
 202         mxc_gpio_irq_handler(port, irq_stat);
 203 }
 204
 205 /* MX2 has one interrupt *for all* gpio ports */
 206 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 207 {
 208         u32 irq_msk, irq_stat;
 209         struct mxc_gpio_port *port;
 210
 211         /* walk through all interrupt status registers */
 212         list_for_each_entry(port, &mxc_gpio_ports, node) {
 213                 irq_msk = readl(port->base + GPIO_IMR);
 214                 if (!irq_msk)
 215                         continue;
 216
 217                 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
 218                 if (irq_stat)
 219                         mxc_gpio_irq_handler(port, irq_stat);
 220         }
 221 }
 222
 223 /*
 224  * Set interrupt number "irq" in the GPIO as a wake-up source.
 225  * While system is running, all registered GPIO interrupts need to have
 226  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 227  * need to have wake-up enabled.
 228  * @param  irq          interrupt source number
 229  * @param  enable       enable as wake-up if equal to non-zero
 230  * @return       This function returns 0 on success.
 231  */
 232 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 233 {
 234         u32 gpio = irq_to_gpio(d->irq);
 235         u32 gpio_idx = gpio & 0x1F;
 236         struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
 237
 238         if (enable) {
 239                 if (port->irq_high && (gpio_idx >= 16))
 240                         enable_irq_wake(port->irq_high);
 241                 else
 242                         enable_irq_wake(port->irq);
 243         } else {
 244                 if (port->irq_high && (gpio_idx >= 16))
 245                         disable_irq_wake(port->irq_high);
 246                 else
 247                         disable_irq_wake(port->irq);
 248         }
 249
 250         return 0;
 251 }
 252
 253 static struct irq_chip gpio_irq_chip = {
 254         .name = "GPIO",
 255         .irq_ack = gpio_ack_irq,
 256         .irq_mask = gpio_mask_irq,
 257         .irq_unmask = gpio_unmask_irq,
 258         .irq_set_type = gpio_set_irq_type,
 259         .irq_set_wake = gpio_set_wake_irq,
 260 };
 261
 262 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
 263                                 int dir)
 264 {
 265         struct mxc_gpio_port *port =
 266                 container_of(chip, struct mxc_gpio_port, chip);
 267         u32 l;
 268         unsigned long flags;
 269
 270         spin_lock_irqsave(&port->lock, flags);
 271         l = readl(port->base + GPIO_GDIR);
 272         if (dir)
 273                 l |= 1 << offset;
 274         else
 275                 l &= ~(1 << offset);
 276         writel(l, port->base + GPIO_GDIR);
 277         spin_unlock_irqrestore(&port->lock, flags);
 278 }
 279
 280 static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 281 {
 282         struct mxc_gpio_port *port =
 283                 container_of(chip, struct mxc_gpio_port, chip);
 284         void __iomem *reg = port->base + GPIO_DR;
 285         u32 l;
 286         unsigned long flags;
 287
 288         spin_lock_irqsave(&port->lock, flags);
 289         l = (readl(reg) & (~(1 << offset))) | (!!value << offset);
 290         writel(l, reg);
 291         spin_unlock_irqrestore(&port->lock, flags);
 292 }
 293
 294 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
 295 {
 296         struct mxc_gpio_port *port =
 297                 container_of(chip, struct mxc_gpio_port, chip);
 298
 299         return (readl(port->base + GPIO_PSR) >> offset) & 1;
 300 }
 301
 302 static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 303 {
 304         _set_gpio_direction(chip, offset, 0);
 305         return 0;
 306 }
 307
 308 static int mxc_gpio_direction_output(struct gpio_chip *chip,
 309                                      unsigned offset, int value)
 310 {
 311         mxc_gpio_set(chip, offset, value);
 312         _set_gpio_direction(chip, offset, 1);
 313         return 0;
 314 }
 315
 316 /*
 317  * This lock class tells lockdep that GPIO irqs are in a different
 318  * category than their parents, so it won't report false recursion.
 319  */
 320 static struct lock_class_key gpio_lock_class;
 321
 322 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
 323 {
 324         struct mxc_gpio_port *port;
 325         struct resource *iores;
 326         int err, i;
 327
 328         port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
 329         if (!port)
 330                 return -ENOMEM;
 331
 332         port->virtual_irq_start = MXC_GPIO_IRQ_START + pdev->id * 32;
 333
 334         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 335         if (!iores) {
 336                 err = -ENODEV;
 337                 goto out_kfree;
 338         }
 339
 340         if (!request_mem_region(iores->start, resource_size(iores),
 341                                 pdev->name)) {
 342                 err = -EBUSY;
 343                 goto out_kfree;
 344         }
 345
 346         port->base = ioremap(iores->start, resource_size(iores));
 347         if (!port->base) {
 348                 err = -ENOMEM;
 349                 goto out_release_mem;
 350         }
 351
 352         port->irq_high = platform_get_irq(pdev, 1);
 353         port->irq = platform_get_irq(pdev, 0);
 354         if (port->irq < 0) {
 355                 err = -EINVAL;
 356                 goto out_iounmap;
 357         }
 358
 359         /* disable the interrupt and clear the status */
 360         writel(0, port->base + GPIO_IMR);
 361         writel(~0, port->base + GPIO_ISR);
 362
 363         for (i = port->virtual_irq_start;
 364                 i < port->virtual_irq_start + 32; i++) {
 365                 irq_set_lockdep_class(i, &gpio_lock_class);
 366                 irq_set_chip_and_handler(i, &gpio_irq_chip, handle_level_irq);
 367                 set_irq_flags(i, IRQF_VALID);
 368                 irq_set_chip_data(i, port);
 369         }
 370
 371         if (cpu_is_mx2()) {
 372                 /* setup one handler for all GPIO interrupts */
 373                 if (pdev->id == 0)
 374                         irq_set_chained_handler(port->irq,
 375                                                 mx2_gpio_irq_handler);
 376         } else {
 377                 /* setup one handler for each entry */
 378                 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
 379                 irq_set_handler_data(port->irq, port);
 380                 if (port->irq_high > 0) {
 381                         /* setup handler for GPIO 16 to 31 */
 382                         irq_set_chained_handler(port->irq_high,
 383                                                 mx3_gpio_irq_handler);
 384                         irq_set_handler_data(port->irq_high, port);
 385                 }
 386         }
 387
 388         /* register gpio chip */
 389         port->chip.direction_input = mxc_gpio_direction_input;
 390         port->chip.direction_output = mxc_gpio_direction_output;
 391         port->chip.get = mxc_gpio_get;
 392         port->chip.set = mxc_gpio_set;
 393         port->chip.base = pdev->id * 32;
 394         port->chip.ngpio = 32;
 395
 396         spin_lock_init(&port->lock);
 397
 398         err = gpiochip_add(&port->chip);
 399         if (err)
 400                 goto out_iounmap;
 401
 402         list_add_tail(&port->node, &mxc_gpio_ports);
 403
 404         return 0;
 405
 406 out_iounmap:
 407         iounmap(port->base);
 408 out_release_mem:
 409         release_mem_region(iores->start, resource_size(iores));
 410 out_kfree:
 411         kfree(port);
 412         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 413         return err;
 414 }
 415
 416 static struct platform_driver mxc_gpio_driver = {
 417         .driver         = {
 418                 .name   = "gpio-mxc",
 419                 .owner  = THIS_MODULE,
 420         },
 421         .probe          = mxc_gpio_probe,
 422 };
 423
 424 static int __init gpio_mxc_init(void)
 425 {
 426         return platform_driver_register(&mxc_gpio_driver);
 427 }
 428 postcore_initcall(gpio_mxc_init);
 429
 430 MODULE_AUTHOR("Freescale Semiconductor, "
 431               "Daniel Mack <danielncaiaq.de>, "
 432               "Juergen Beisert <kernel@pengutronix.de>");
 433 MODULE_DESCRIPTION("Freescale MXC GPIO");
 434 MODULE_LICENSE("GPL");