drivers/gpio/gpio-mxc.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/irq.h>
  26 #include <linux/gpio.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/slab.h>
  29 #include <linux/basic_mmio_gpio.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <asm-generic/bug.h>
  33 #include <asm/mach/irq.h>
  34
  35 enum mxc_gpio_hwtype {
  36         IMX1_GPIO,      /* runs on i.mx1 */
  37         IMX21_GPIO,     /* runs on i.mx21 and i.mx27 */
  38         IMX31_GPIO,     /* runs on all other i.mx */
  39 };
  40
  41 /* device type dependent stuff */
  42 struct mxc_gpio_hwdata {
  43         unsigned dr_reg;
  44         unsigned gdir_reg;
  45         unsigned psr_reg;
  46         unsigned icr1_reg;
  47         unsigned icr2_reg;
  48         unsigned imr_reg;
  49         unsigned isr_reg;
  50         unsigned low_level;
  51         unsigned high_level;
  52         unsigned rise_edge;
  53         unsigned fall_edge;
  54 };
  55
  56 struct mxc_gpio_port {
  57         struct list_head node;
  58         void __iomem *base;
  59         int irq;
  60         int irq_high;
  61         int virtual_irq_start;
  62         struct bgpio_chip bgc;
  63         u32 both_edges;
  64 };
  65
  66 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
  67         .dr_reg         = 0x1c,
  68         .gdir_reg       = 0x00,
  69         .psr_reg        = 0x24,
  70         .icr1_reg       = 0x28,
  71         .icr2_reg       = 0x2c,
  72         .imr_reg        = 0x30,
  73         .isr_reg        = 0x34,
  74         .low_level      = 0x03,
  75         .high_level     = 0x02,
  76         .rise_edge      = 0x00,
  77         .fall_edge      = 0x01,
  78 };
  79
  80 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
  81         .dr_reg         = 0x00,
  82         .gdir_reg       = 0x04,
  83         .psr_reg        = 0x08,
  84         .icr1_reg       = 0x0c,
  85         .icr2_reg       = 0x10,
  86         .imr_reg        = 0x14,
  87         .isr_reg        = 0x18,
  88         .low_level      = 0x00,
  89         .high_level     = 0x01,
  90         .rise_edge      = 0x02,
  91         .fall_edge      = 0x03,
  92 };
  93
  94 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
  95 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
  96
  97 #define GPIO_DR                 (mxc_gpio_hwdata->dr_reg)
  98 #define GPIO_GDIR               (mxc_gpio_hwdata->gdir_reg)
  99 #define GPIO_PSR                (mxc_gpio_hwdata->psr_reg)
 100 #define GPIO_ICR1               (mxc_gpio_hwdata->icr1_reg)
 101 #define GPIO_ICR2               (mxc_gpio_hwdata->icr2_reg)
 102 #define GPIO_IMR                (mxc_gpio_hwdata->imr_reg)
 103 #define GPIO_ISR                (mxc_gpio_hwdata->isr_reg)
 104
 105 #define GPIO_INT_LOW_LEV        (mxc_gpio_hwdata->low_level)
 106 #define GPIO_INT_HIGH_LEV       (mxc_gpio_hwdata->high_level)
 107 #define GPIO_INT_RISE_EDGE      (mxc_gpio_hwdata->rise_edge)
 108 #define GPIO_INT_FALL_EDGE      (mxc_gpio_hwdata->fall_edge)
 109 #define GPIO_INT_NONE           0x4
 110
 111 static struct platform_device_id mxc_gpio_devtype[] = {
 112         {
 113                 .name = "imx1-gpio",
 114                 .driver_data = IMX1_GPIO,
 115         }, {
 116                 .name = "imx21-gpio",
 117                 .driver_data = IMX21_GPIO,
 118         }, {
 119                 .name = "imx31-gpio",
 120                 .driver_data = IMX31_GPIO,
 121         }, {
 122                 /* sentinel */
 123         }
 124 };
 125
 126 static const struct of_device_id mxc_gpio_dt_ids[] = {
 127         { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
 128         { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
 129         { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
 130         { /* sentinel */ }
 131 };
 132
 133 /*
 134  * MX2 has one interrupt *for all* gpio ports. The list is used
 135  * to save the references to all ports, so that mx2_gpio_irq_handler
 136  * can walk through all interrupt status registers.
 137  */
 138 static LIST_HEAD(mxc_gpio_ports);
 139
 140 /* Note: This driver assumes 32 GPIOs are handled in one register */
 141
 142 static int gpio_set_irq_type(struct irq_data *d, u32 type)
 143 {
 144         u32 gpio = irq_to_gpio(d->irq);
 145         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 146         struct mxc_gpio_port *port = gc->private;
 147         u32 bit, val;
 148         int edge;
 149         void __iomem *reg = port->base;
 150
 151         port->both_edges &= ~(1 << (gpio & 31));
 152         switch (type) {
 153         case IRQ_TYPE_EDGE_RISING:
 154                 edge = GPIO_INT_RISE_EDGE;
 155                 break;
 156         case IRQ_TYPE_EDGE_FALLING:
 157                 edge = GPIO_INT_FALL_EDGE;
 158                 break;
 159         case IRQ_TYPE_EDGE_BOTH:
 160                 val = gpio_get_value(gpio);
 161                 if (val) {
 162                         edge = GPIO_INT_LOW_LEV;
 163                         pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
 164                 } else {
 165                         edge = GPIO_INT_HIGH_LEV;
 166                         pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
 167                 }
 168                 port->both_edges |= 1 << (gpio & 31);
 169                 break;
 170         case IRQ_TYPE_LEVEL_LOW:
 171                 edge = GPIO_INT_LOW_LEV;
 172                 break;
 173         case IRQ_TYPE_LEVEL_HIGH:
 174                 edge = GPIO_INT_HIGH_LEV;
 175                 break;
 176         default:
 177                 return -EINVAL;
 178         }
 179
 180         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 181         bit = gpio & 0xf;
 182         val = readl(reg) & ~(0x3 << (bit << 1));
 183         writel(val | (edge << (bit << 1)), reg);
 184         writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
 185
 186         return 0;
 187 }
 188
 189 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 190 {
 191         void __iomem *reg = port->base;
 192         u32 bit, val;
 193         int edge;
 194
 195         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 196         bit = gpio & 0xf;
 197         val = readl(reg);
 198         edge = (val >> (bit << 1)) & 3;
 199         val &= ~(0x3 << (bit << 1));
 200         if (edge == GPIO_INT_HIGH_LEV) {
 201                 edge = GPIO_INT_LOW_LEV;
 202                 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
 203         } else if (edge == GPIO_INT_LOW_LEV) {
 204                 edge = GPIO_INT_HIGH_LEV;
 205                 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
 206         } else {
 207                 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
 208                        gpio, edge);
 209                 return;
 210         }
 211         writel(val | (edge << (bit << 1)), reg);
 212 }
 213
 214 /* handle 32 interrupts in one status register */
 215 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 216 {
 217         u32 gpio_irq_no_base = port->virtual_irq_start;
 218
 219         while (irq_stat != 0) {
 220                 int irqoffset = fls(irq_stat) - 1;
 221
 222                 if (port->both_edges & (1 << irqoffset))
 223                         mxc_flip_edge(port, irqoffset);
 224
 225                 generic_handle_irq(gpio_irq_no_base + irqoffset);
 226
 227                 irq_stat &= ~(1 << irqoffset);
 228         }
 229 }
 230
 231 /* MX1 and MX3 has one interrupt *per* gpio port */
 232 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 233 {
 234         u32 irq_stat;
 235         struct mxc_gpio_port *port = irq_get_handler_data(irq);
 236         struct irq_chip *chip = irq_get_chip(irq);
 237
 238         chained_irq_enter(chip, desc);
 239
 240         irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
 241
 242         mxc_gpio_irq_handler(port, irq_stat);
 243
 244         chained_irq_exit(chip, desc);
 245 }
 246
 247 /* MX2 has one interrupt *for all* gpio ports */
 248 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 249 {
 250         u32 irq_msk, irq_stat;
 251         struct mxc_gpio_port *port;
 252
 253         /* walk through all interrupt status registers */
 254         list_for_each_entry(port, &mxc_gpio_ports, node) {
 255                 irq_msk = readl(port->base + GPIO_IMR);
 256                 if (!irq_msk)
 257                         continue;
 258
 259                 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
 260                 if (irq_stat)
 261                         mxc_gpio_irq_handler(port, irq_stat);
 262         }
 263 }
 264
 265 /*
 266  * Set interrupt number "irq" in the GPIO as a wake-up source.
 267  * While system is running, all registered GPIO interrupts need to have
 268  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 269  * need to have wake-up enabled.
 270  * @param  irq          interrupt source number
 271  * @param  enable       enable as wake-up if equal to non-zero
 272  * @return       This function returns 0 on success.
 273  */
 274 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 275 {
 276         u32 gpio = irq_to_gpio(d->irq);
 277         u32 gpio_idx = gpio & 0x1F;
 278         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 279         struct mxc_gpio_port *port = gc->private;
 280
 281         if (enable) {
 282                 if (port->irq_high && (gpio_idx >= 16))
 283                         enable_irq_wake(port->irq_high);
 284                 else
 285                         enable_irq_wake(port->irq);
 286         } else {
 287                 if (port->irq_high && (gpio_idx >= 16))
 288                         disable_irq_wake(port->irq_high);
 289                 else
 290                         disable_irq_wake(port->irq);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
 297 {
 298         struct irq_chip_generic *gc;
 299         struct irq_chip_type *ct;
 300
 301         gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
 302                                     port->base, handle_level_irq);
 303         gc->private = port;
 304
 305         ct = gc->chip_types;
 306         ct->chip.irq_ack = irq_gc_ack_set_bit;
 307         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 308         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 309         ct->chip.irq_set_type = gpio_set_irq_type;
 310         ct->chip.irq_set_wake = gpio_set_wake_irq;
 311         ct->regs.ack = GPIO_ISR;
 312         ct->regs.mask = GPIO_IMR;
 313
 314         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
 315                                IRQ_NOREQUEST, 0);
 316 }
 317
 318 static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
 319 {
 320         const struct of_device_id *of_id =
 321                         of_match_device(mxc_gpio_dt_ids, &pdev->dev);
 322         enum mxc_gpio_hwtype hwtype;
 323
 324         if (of_id)
 325                 pdev->id_entry = of_id->data;
 326         hwtype = pdev->id_entry->driver_data;
 327
 328         if (mxc_gpio_hwtype) {
 329                 /*
 330                  * The driver works with a reasonable presupposition,
 331                  * that is all gpio ports must be the same type when
 332                  * running on one soc.
 333                  */
 334                 BUG_ON(mxc_gpio_hwtype != hwtype);
 335                 return;
 336         }
 337
 338         if (hwtype == IMX31_GPIO)
 339                 mxc_gpio_hwdata = &imx31_gpio_hwdata;
 340         else
 341                 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
 342
 343         mxc_gpio_hwtype = hwtype;
 344 }
 345
 346 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
 347 {
 348         struct device_node *np = pdev->dev.of_node;
 349         struct mxc_gpio_port *port;
 350         struct resource *iores;
 351         int err;
 352
 353         mxc_gpio_get_hw(pdev);
 354
 355         port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
 356         if (!port)
 357                 return -ENOMEM;
 358
 359         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 360         if (!iores) {
 361                 err = -ENODEV;
 362                 goto out_kfree;
 363         }
 364
 365         if (!request_mem_region(iores->start, resource_size(iores),
 366                                 pdev->name)) {
 367                 err = -EBUSY;
 368                 goto out_kfree;
 369         }
 370
 371         port->base = ioremap(iores->start, resource_size(iores));
 372         if (!port->base) {
 373                 err = -ENOMEM;
 374                 goto out_release_mem;
 375         }
 376
 377         port->irq_high = platform_get_irq(pdev, 1);
 378         port->irq = platform_get_irq(pdev, 0);
 379         if (port->irq < 0) {
 380                 err = -EINVAL;
 381                 goto out_iounmap;
 382         }
 383
 384         /* disable the interrupt and clear the status */
 385         writel(0, port->base + GPIO_IMR);
 386         writel(~0, port->base + GPIO_ISR);
 387
 388         if (mxc_gpio_hwtype == IMX21_GPIO) {
 389                 /* setup one handler for all GPIO interrupts */
 390                 if (pdev->id == 0)
 391                         irq_set_chained_handler(port->irq,
 392                                                 mx2_gpio_irq_handler);
 393         } else {
 394                 /* setup one handler for each entry */
 395                 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
 396                 irq_set_handler_data(port->irq, port);
 397                 if (port->irq_high > 0) {
 398                         /* setup handler for GPIO 16 to 31 */
 399                         irq_set_chained_handler(port->irq_high,
 400                                                 mx3_gpio_irq_handler);
 401                         irq_set_handler_data(port->irq_high, port);
 402                 }
 403         }
 404
 405         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 406                          port->base + GPIO_PSR,
 407                          port->base + GPIO_DR, NULL,
 408                          port->base + GPIO_GDIR, NULL, false);
 409         if (err)
 410                 goto out_iounmap;
 411
 412         port->bgc.gc.base = pdev->id * 32;
 413         port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
 414         port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
 415
 416         err = gpiochip_add(&port->bgc.gc);
 417         if (err)
 418                 goto out_bgpio_remove;
 419
 420         /*
 421          * In dt case, we use gpio number range dynamically
 422          * allocated by gpio core.
 423          */
 424         port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
 425                                                              pdev->id * 32);
 426
 427         /* gpio-mxc can be a generic irq chip */
 428         mxc_gpio_init_gc(port);
 429
 430         list_add_tail(&port->node, &mxc_gpio_ports);
 431
 432         return 0;
 433
 434 out_bgpio_remove:
 435         bgpio_remove(&port->bgc);
 436 out_iounmap:
 437         iounmap(port->base);
 438 out_release_mem:
 439         release_mem_region(iores->start, resource_size(iores));
 440 out_kfree:
 441         kfree(port);
 442         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 443         return err;
 444 }
 445
 446 static struct platform_driver mxc_gpio_driver = {
 447         .driver         = {
 448                 .name   = "gpio-mxc",
 449                 .owner  = THIS_MODULE,
 450                 .of_match_table = mxc_gpio_dt_ids,
 451         },
 452         .probe          = mxc_gpio_probe,
 453         .id_table       = mxc_gpio_devtype,
 454 };
 455
 456 static int __init gpio_mxc_init(void)
 457 {
 458         return platform_driver_register(&mxc_gpio_driver);
 459 }
 460 postcore_initcall(gpio_mxc_init);
 461
 462 MODULE_AUTHOR("Freescale Semiconductor, "
 463               "Daniel Mack <danielncaiaq.de>, "
 464               "Juergen Beisert <kernel@pengutronix.de>");
 465 MODULE_DESCRIPTION("Freescale MXC GPIO");
 466 MODULE_LICENSE("GPL");