drivers/gpio/gpio-mxc.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/irq.h>
  26 #include <linux/gpio.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/slab.h>
  29 #include <linux/basic_mmio_gpio.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <asm-generic/bug.h>
  33 #include <asm/mach/irq.h>
  34
  35 #define irq_to_gpio(irq)        ((irq) - MXC_GPIO_IRQ_START)
  36
  37 enum mxc_gpio_hwtype {
  38         IMX1_GPIO,      /* runs on i.mx1 */
  39         IMX21_GPIO,     /* runs on i.mx21 and i.mx27 */
  40         IMX31_GPIO,     /* runs on all other i.mx */
  41 };
  42
  43 /* device type dependent stuff */
  44 struct mxc_gpio_hwdata {
  45         unsigned dr_reg;
  46         unsigned gdir_reg;
  47         unsigned psr_reg;
  48         unsigned icr1_reg;
  49         unsigned icr2_reg;
  50         unsigned imr_reg;
  51         unsigned isr_reg;
  52         unsigned low_level;
  53         unsigned high_level;
  54         unsigned rise_edge;
  55         unsigned fall_edge;
  56 };
  57
  58 struct mxc_gpio_port {
  59         struct list_head node;
  60         void __iomem *base;
  61         int irq;
  62         int irq_high;
  63         int virtual_irq_start;
  64         struct bgpio_chip bgc;
  65         u32 both_edges;
  66 };
  67
  68 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
  69         .dr_reg         = 0x1c,
  70         .gdir_reg       = 0x00,
  71         .psr_reg        = 0x24,
  72         .icr1_reg       = 0x28,
  73         .icr2_reg       = 0x2c,
  74         .imr_reg        = 0x30,
  75         .isr_reg        = 0x34,
  76         .low_level      = 0x03,
  77         .high_level     = 0x02,
  78         .rise_edge      = 0x00,
  79         .fall_edge      = 0x01,
  80 };
  81
  82 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
  83         .dr_reg         = 0x00,
  84         .gdir_reg       = 0x04,
  85         .psr_reg        = 0x08,
  86         .icr1_reg       = 0x0c,
  87         .icr2_reg       = 0x10,
  88         .imr_reg        = 0x14,
  89         .isr_reg        = 0x18,
  90         .low_level      = 0x00,
  91         .high_level     = 0x01,
  92         .rise_edge      = 0x02,
  93         .fall_edge      = 0x03,
  94 };
  95
  96 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
  97 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
  98
  99 #define GPIO_DR                 (mxc_gpio_hwdata->dr_reg)
 100 #define GPIO_GDIR               (mxc_gpio_hwdata->gdir_reg)
 101 #define GPIO_PSR                (mxc_gpio_hwdata->psr_reg)
 102 #define GPIO_ICR1               (mxc_gpio_hwdata->icr1_reg)
 103 #define GPIO_ICR2               (mxc_gpio_hwdata->icr2_reg)
 104 #define GPIO_IMR                (mxc_gpio_hwdata->imr_reg)
 105 #define GPIO_ISR                (mxc_gpio_hwdata->isr_reg)
 106
 107 #define GPIO_INT_LOW_LEV        (mxc_gpio_hwdata->low_level)
 108 #define GPIO_INT_HIGH_LEV       (mxc_gpio_hwdata->high_level)
 109 #define GPIO_INT_RISE_EDGE      (mxc_gpio_hwdata->rise_edge)
 110 #define GPIO_INT_FALL_EDGE      (mxc_gpio_hwdata->fall_edge)
 111 #define GPIO_INT_NONE           0x4
 112
 113 static struct platform_device_id mxc_gpio_devtype[] = {
 114         {
 115                 .name = "imx1-gpio",
 116                 .driver_data = IMX1_GPIO,
 117         }, {
 118                 .name = "imx21-gpio",
 119                 .driver_data = IMX21_GPIO,
 120         }, {
 121                 .name = "imx31-gpio",
 122                 .driver_data = IMX31_GPIO,
 123         }, {
 124                 /* sentinel */
 125         }
 126 };
 127
 128 static const struct of_device_id mxc_gpio_dt_ids[] = {
 129         { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
 130         { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
 131         { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
 132         { /* sentinel */ }
 133 };
 134
 135 /*
 136  * MX2 has one interrupt *for all* gpio ports. The list is used
 137  * to save the references to all ports, so that mx2_gpio_irq_handler
 138  * can walk through all interrupt status registers.
 139  */
 140 static LIST_HEAD(mxc_gpio_ports);
 141
 142 /* Note: This driver assumes 32 GPIOs are handled in one register */
 143
 144 static int gpio_set_irq_type(struct irq_data *d, u32 type)
 145 {
 146         u32 gpio = irq_to_gpio(d->irq);
 147         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 148         struct mxc_gpio_port *port = gc->private;
 149         u32 bit, val;
 150         int edge;
 151         void __iomem *reg = port->base;
 152
 153         port->both_edges &= ~(1 << (gpio & 31));
 154         switch (type) {
 155         case IRQ_TYPE_EDGE_RISING:
 156                 edge = GPIO_INT_RISE_EDGE;
 157                 break;
 158         case IRQ_TYPE_EDGE_FALLING:
 159                 edge = GPIO_INT_FALL_EDGE;
 160                 break;
 161         case IRQ_TYPE_EDGE_BOTH:
 162                 val = gpio_get_value(gpio);
 163                 if (val) {
 164                         edge = GPIO_INT_LOW_LEV;
 165                         pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
 166                 } else {
 167                         edge = GPIO_INT_HIGH_LEV;
 168                         pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
 169                 }
 170                 port->both_edges |= 1 << (gpio & 31);
 171                 break;
 172         case IRQ_TYPE_LEVEL_LOW:
 173                 edge = GPIO_INT_LOW_LEV;
 174                 break;
 175         case IRQ_TYPE_LEVEL_HIGH:
 176                 edge = GPIO_INT_HIGH_LEV;
 177                 break;
 178         default:
 179                 return -EINVAL;
 180         }
 181
 182         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 183         bit = gpio & 0xf;
 184         val = readl(reg) & ~(0x3 << (bit << 1));
 185         writel(val | (edge << (bit << 1)), reg);
 186         writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
 187
 188         return 0;
 189 }
 190
 191 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 192 {
 193         void __iomem *reg = port->base;
 194         u32 bit, val;
 195         int edge;
 196
 197         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 198         bit = gpio & 0xf;
 199         val = readl(reg);
 200         edge = (val >> (bit << 1)) & 3;
 201         val &= ~(0x3 << (bit << 1));
 202         if (edge == GPIO_INT_HIGH_LEV) {
 203                 edge = GPIO_INT_LOW_LEV;
 204                 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
 205         } else if (edge == GPIO_INT_LOW_LEV) {
 206                 edge = GPIO_INT_HIGH_LEV;
 207                 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
 208         } else {
 209                 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
 210                        gpio, edge);
 211                 return;
 212         }
 213         writel(val | (edge << (bit << 1)), reg);
 214 }
 215
 216 /* handle 32 interrupts in one status register */
 217 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 218 {
 219         u32 gpio_irq_no_base = port->virtual_irq_start;
 220
 221         while (irq_stat != 0) {
 222                 int irqoffset = fls(irq_stat) - 1;
 223
 224                 if (port->both_edges & (1 << irqoffset))
 225                         mxc_flip_edge(port, irqoffset);
 226
 227                 generic_handle_irq(gpio_irq_no_base + irqoffset);
 228
 229                 irq_stat &= ~(1 << irqoffset);
 230         }
 231 }
 232
 233 /* MX1 and MX3 has one interrupt *per* gpio port */
 234 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 235 {
 236         u32 irq_stat;
 237         struct mxc_gpio_port *port = irq_get_handler_data(irq);
 238         struct irq_chip *chip = irq_get_chip(irq);
 239
 240         chained_irq_enter(chip, desc);
 241
 242         irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
 243
 244         mxc_gpio_irq_handler(port, irq_stat);
 245
 246         chained_irq_exit(chip, desc);
 247 }
 248
 249 /* MX2 has one interrupt *for all* gpio ports */
 250 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 251 {
 252         u32 irq_msk, irq_stat;
 253         struct mxc_gpio_port *port;
 254
 255         /* walk through all interrupt status registers */
 256         list_for_each_entry(port, &mxc_gpio_ports, node) {
 257                 irq_msk = readl(port->base + GPIO_IMR);
 258                 if (!irq_msk)
 259                         continue;
 260
 261                 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
 262                 if (irq_stat)
 263                         mxc_gpio_irq_handler(port, irq_stat);
 264         }
 265 }
 266
 267 /*
 268  * Set interrupt number "irq" in the GPIO as a wake-up source.
 269  * While system is running, all registered GPIO interrupts need to have
 270  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 271  * need to have wake-up enabled.
 272  * @param  irq          interrupt source number
 273  * @param  enable       enable as wake-up if equal to non-zero
 274  * @return       This function returns 0 on success.
 275  */
 276 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 277 {
 278         u32 gpio = irq_to_gpio(d->irq);
 279         u32 gpio_idx = gpio & 0x1F;
 280         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 281         struct mxc_gpio_port *port = gc->private;
 282
 283         if (enable) {
 284                 if (port->irq_high && (gpio_idx >= 16))
 285                         enable_irq_wake(port->irq_high);
 286                 else
 287                         enable_irq_wake(port->irq);
 288         } else {
 289                 if (port->irq_high && (gpio_idx >= 16))
 290                         disable_irq_wake(port->irq_high);
 291                 else
 292                         disable_irq_wake(port->irq);
 293         }
 294
 295         return 0;
 296 }
 297
 298 static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
 299 {
 300         struct irq_chip_generic *gc;
 301         struct irq_chip_type *ct;
 302
 303         gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
 304                                     port->base, handle_level_irq);
 305         gc->private = port;
 306
 307         ct = gc->chip_types;
 308         ct->chip.irq_ack = irq_gc_ack_set_bit;
 309         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 310         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 311         ct->chip.irq_set_type = gpio_set_irq_type;
 312         ct->chip.irq_set_wake = gpio_set_wake_irq;
 313         ct->regs.ack = GPIO_ISR;
 314         ct->regs.mask = GPIO_IMR;
 315
 316         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
 317                                IRQ_NOREQUEST, 0);
 318 }
 319
 320 static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
 321 {
 322         const struct of_device_id *of_id =
 323                         of_match_device(mxc_gpio_dt_ids, &pdev->dev);
 324         enum mxc_gpio_hwtype hwtype;
 325
 326         if (of_id)
 327                 pdev->id_entry = of_id->data;
 328         hwtype = pdev->id_entry->driver_data;
 329
 330         if (mxc_gpio_hwtype) {
 331                 /*
 332                  * The driver works with a reasonable presupposition,
 333                  * that is all gpio ports must be the same type when
 334                  * running on one soc.
 335                  */
 336                 BUG_ON(mxc_gpio_hwtype != hwtype);
 337                 return;
 338         }
 339
 340         if (hwtype == IMX31_GPIO)
 341                 mxc_gpio_hwdata = &imx31_gpio_hwdata;
 342         else
 343                 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
 344
 345         mxc_gpio_hwtype = hwtype;
 346 }
 347
 348 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 349 {
 350         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 351         struct mxc_gpio_port *port =
 352                 container_of(bgc, struct mxc_gpio_port, bgc);
 353
 354         return port->virtual_irq_start + offset;
 355 }
 356
 357 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
 358 {
 359         struct device_node *np = pdev->dev.of_node;
 360         struct mxc_gpio_port *port;
 361         struct resource *iores;
 362         int err;
 363
 364         mxc_gpio_get_hw(pdev);
 365
 366         port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
 367         if (!port)
 368                 return -ENOMEM;
 369
 370         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 371         if (!iores) {
 372                 err = -ENODEV;
 373                 goto out_kfree;
 374         }
 375
 376         if (!request_mem_region(iores->start, resource_size(iores),
 377                                 pdev->name)) {
 378                 err = -EBUSY;
 379                 goto out_kfree;
 380         }
 381
 382         port->base = ioremap(iores->start, resource_size(iores));
 383         if (!port->base) {
 384                 err = -ENOMEM;
 385                 goto out_release_mem;
 386         }
 387
 388         port->irq_high = platform_get_irq(pdev, 1);
 389         port->irq = platform_get_irq(pdev, 0);
 390         if (port->irq < 0) {
 391                 err = -EINVAL;
 392                 goto out_iounmap;
 393         }
 394
 395         /* disable the interrupt and clear the status */
 396         writel(0, port->base + GPIO_IMR);
 397         writel(~0, port->base + GPIO_ISR);
 398
 399         if (mxc_gpio_hwtype == IMX21_GPIO) {
 400                 /* setup one handler for all GPIO interrupts */
 401                 if (pdev->id == 0)
 402                         irq_set_chained_handler(port->irq,
 403                                                 mx2_gpio_irq_handler);
 404         } else {
 405                 /* setup one handler for each entry */
 406                 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
 407                 irq_set_handler_data(port->irq, port);
 408                 if (port->irq_high > 0) {
 409                         /* setup handler for GPIO 16 to 31 */
 410                         irq_set_chained_handler(port->irq_high,
 411                                                 mx3_gpio_irq_handler);
 412                         irq_set_handler_data(port->irq_high, port);
 413                 }
 414         }
 415
 416         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 417                          port->base + GPIO_PSR,
 418                          port->base + GPIO_DR, NULL,
 419                          port->base + GPIO_GDIR, NULL, false);
 420         if (err)
 421                 goto out_iounmap;
 422
 423         port->bgc.gc.to_irq = mxc_gpio_to_irq;
 424         port->bgc.gc.base = pdev->id * 32;
 425         port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
 426         port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
 427
 428         err = gpiochip_add(&port->bgc.gc);
 429         if (err)
 430                 goto out_bgpio_remove;
 431
 432         /*
 433          * In dt case, we use gpio number range dynamically
 434          * allocated by gpio core.
 435          */
 436         port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
 437                                                              pdev->id * 32);
 438
 439         /* gpio-mxc can be a generic irq chip */
 440         mxc_gpio_init_gc(port);
 441
 442         list_add_tail(&port->node, &mxc_gpio_ports);
 443
 444         return 0;
 445
 446 out_bgpio_remove:
 447         bgpio_remove(&port->bgc);
 448 out_iounmap:
 449         iounmap(port->base);
 450 out_release_mem:
 451         release_mem_region(iores->start, resource_size(iores));
 452 out_kfree:
 453         kfree(port);
 454         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 455         return err;
 456 }
 457
 458 static struct platform_driver mxc_gpio_driver = {
 459         .driver         = {
 460                 .name   = "gpio-mxc",
 461                 .owner  = THIS_MODULE,
 462                 .of_match_table = mxc_gpio_dt_ids,
 463         },
 464         .probe          = mxc_gpio_probe,
 465         .id_table       = mxc_gpio_devtype,
 466 };
 467
 468 static int __init gpio_mxc_init(void)
 469 {
 470         return platform_driver_register(&mxc_gpio_driver);
 471 }
 472 postcore_initcall(gpio_mxc_init);
 473
 474 MODULE_AUTHOR("Freescale Semiconductor, "
 475               "Daniel Mack <danielncaiaq.de>, "
 476               "Juergen Beisert <kernel@pengutronix.de>");
 477 MODULE_DESCRIPTION("Freescale MXC GPIO");
 478 MODULE_LICENSE("GPL");