drivers/gpio/gpio-mxs.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/gpio.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/slab.h>
  33 #include <linux/basic_mmio_gpio.h>
  34 #include <linux/module.h>
  35
  36 #define MXS_SET         0x4
  37 #define MXS_CLR         0x8
  38
  39 #define PINCTRL_DOUT(p)         ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
  40 #define PINCTRL_DIN(p)          ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
  41 #define PINCTRL_DOE(p)          ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
  42 #define PINCTRL_PIN2IRQ(p)      ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
  43 #define PINCTRL_IRQEN(p)        ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
  44 #define PINCTRL_IRQLEV(p)       ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
  45 #define PINCTRL_IRQPOL(p)       ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
  46 #define PINCTRL_IRQSTAT(p)      ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
  47
  48 #define GPIO_INT_FALL_EDGE      0x0
  49 #define GPIO_INT_LOW_LEV        0x1
  50 #define GPIO_INT_RISE_EDGE      0x2
  51 #define GPIO_INT_HIGH_LEV       0x3
  52 #define GPIO_INT_LEV_MASK       (1 << 0)
  53 #define GPIO_INT_POL_MASK       (1 << 1)
  54
  55 #define irq_to_gpio(irq)        ((irq) - MXS_GPIO_IRQ_START)
  56
  57 enum mxs_gpio_id {
  58         IMX23_GPIO,
  59         IMX28_GPIO,
  60 };
  61
  62 struct mxs_gpio_port {
  63         void __iomem *base;
  64         int id;
  65         int irq;
  66         int virtual_irq_start;
  67         struct bgpio_chip bgc;
  68         enum mxs_gpio_id devid;
  69 };
  70
  71 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
  72 {
  73         return port->devid == IMX23_GPIO;
  74 }
  75
  76 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
  77 {
  78         return port->devid == IMX28_GPIO;
  79 }
  80
  81 /* Note: This driver assumes 32 GPIOs are handled in one register */
  82
  83 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  84 {
  85         u32 gpio = irq_to_gpio(d->irq);
  86         u32 pin_mask = 1 << (gpio & 31);
  87         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  88         struct mxs_gpio_port *port = gc->private;
  89         void __iomem *pin_addr;
  90         int edge;
  91
  92         switch (type) {
  93         case IRQ_TYPE_EDGE_RISING:
  94                 edge = GPIO_INT_RISE_EDGE;
  95                 break;
  96         case IRQ_TYPE_EDGE_FALLING:
  97                 edge = GPIO_INT_FALL_EDGE;
  98                 break;
  99         case IRQ_TYPE_LEVEL_LOW:
 100                 edge = GPIO_INT_LOW_LEV;
 101                 break;
 102         case IRQ_TYPE_LEVEL_HIGH:
 103                 edge = GPIO_INT_HIGH_LEV;
 104                 break;
 105         default:
 106                 return -EINVAL;
 107         }
 108
 109         /* set level or edge */
 110         pin_addr = port->base + PINCTRL_IRQLEV(port);
 111         if (edge & GPIO_INT_LEV_MASK)
 112                 writel(pin_mask, pin_addr + MXS_SET);
 113         else
 114                 writel(pin_mask, pin_addr + MXS_CLR);
 115
 116         /* set polarity */
 117         pin_addr = port->base + PINCTRL_IRQPOL(port);
 118         if (edge & GPIO_INT_POL_MASK)
 119                 writel(pin_mask, pin_addr + MXS_SET);
 120         else
 121                 writel(pin_mask, pin_addr + MXS_CLR);
 122
 123         writel(1 << (gpio & 0x1f),
 124                port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 125
 126         return 0;
 127 }
 128
 129 /* MXS has one interrupt *per* gpio port */
 130 static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 131 {
 132         u32 irq_stat;
 133         struct mxs_gpio_port *port = irq_get_handler_data(irq);
 134         u32 gpio_irq_no_base = port->virtual_irq_start;
 135
 136         desc->irq_data.chip->irq_ack(&desc->irq_data);
 137
 138         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
 139                         readl(port->base + PINCTRL_IRQEN(port));
 140
 141         while (irq_stat != 0) {
 142                 int irqoffset = fls(irq_stat) - 1;
 143                 generic_handle_irq(gpio_irq_no_base + irqoffset);
 144                 irq_stat &= ~(1 << irqoffset);
 145         }
 146 }
 147
 148 /*
 149  * Set interrupt number "irq" in the GPIO as a wake-up source.
 150  * While system is running, all registered GPIO interrupts need to have
 151  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 152  * need to have wake-up enabled.
 153  * @param  irq          interrupt source number
 154  * @param  enable       enable as wake-up if equal to non-zero
 155  * @return       This function returns 0 on success.
 156  */
 157 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 158 {
 159         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 160         struct mxs_gpio_port *port = gc->private;
 161
 162         if (enable)
 163                 enable_irq_wake(port->irq);
 164         else
 165                 disable_irq_wake(port->irq);
 166
 167         return 0;
 168 }
 169
 170 static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
 171 {
 172         struct irq_chip_generic *gc;
 173         struct irq_chip_type *ct;
 174
 175         gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
 176                                     port->base, handle_level_irq);
 177         gc->private = port;
 178
 179         ct = gc->chip_types;
 180         ct->chip.irq_ack = irq_gc_ack_set_bit;
 181         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 182         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 183         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 184         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 185         ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
 186         ct->regs.mask = PINCTRL_IRQEN(port);
 187
 188         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 189 }
 190
 191 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 192 {
 193         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 194         struct mxs_gpio_port *port =
 195                 container_of(bgc, struct mxs_gpio_port, bgc);
 196
 197         return port->virtual_irq_start + offset;
 198 }
 199
 200 static struct platform_device_id mxs_gpio_ids[] = {
 201         {
 202                 .name = "imx23-gpio",
 203                 .driver_data = IMX23_GPIO,
 204         }, {
 205                 .name = "imx28-gpio",
 206                 .driver_data = IMX28_GPIO,
 207         }, {
 208                 /* sentinel */
 209         }
 210 };
 211 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
 212
 213 static const struct of_device_id mxs_gpio_dt_ids[] = {
 214         { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
 215         { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
 216         { /* sentinel */ }
 217 };
 218 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
 219
 220 static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 221 {
 222         const struct of_device_id *of_id =
 223                         of_match_device(mxs_gpio_dt_ids, &pdev->dev);
 224         struct device_node *np = pdev->dev.of_node;
 225         struct device_node *parent;
 226         static void __iomem *base;
 227         struct mxs_gpio_port *port;
 228         struct resource *iores = NULL;
 229         int err;
 230
 231         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 232         if (!port)
 233                 return -ENOMEM;
 234
 235         if (np) {
 236                 port->id = of_alias_get_id(np, "gpio");
 237                 if (port->id < 0)
 238                         return port->id;
 239                 port->devid = (enum mxs_gpio_id) of_id->data;
 240         } else {
 241                 port->id = pdev->id;
 242                 port->devid = pdev->id_entry->driver_data;
 243         }
 244         port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
 245
 246         port->irq = platform_get_irq(pdev, 0);
 247         if (port->irq < 0)
 248                 return port->irq;
 249
 250         /*
 251          * map memory region only once, as all the gpio ports
 252          * share the same one
 253          */
 254         if (!base) {
 255                 if (np) {
 256                         parent = of_get_parent(np);
 257                         base = of_iomap(parent, 0);
 258                         of_node_put(parent);
 259                 } else {
 260                         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 261                         base = devm_request_and_ioremap(&pdev->dev, iores);
 262                 }
 263                 if (!base)
 264                         return -EADDRNOTAVAIL;
 265         }
 266         port->base = base;
 267
 268         /*
 269          * select the pin interrupt functionality but initially
 270          * disable the interrupts
 271          */
 272         writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
 273         writel(0, port->base + PINCTRL_IRQEN(port));
 274
 275         /* clear address has to be used to clear IRQSTAT bits */
 276         writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 277
 278         /* gpio-mxs can be a generic irq chip */
 279         mxs_gpio_init_gc(port);
 280
 281         /* setup one handler for each entry */
 282         irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
 283         irq_set_handler_data(port->irq, port);
 284
 285         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 286                          port->base + PINCTRL_DIN(port),
 287                          port->base + PINCTRL_DOUT(port), NULL,
 288                          port->base + PINCTRL_DOE(port), NULL, 0);
 289         if (err)
 290                 return err;
 291
 292         port->bgc.gc.to_irq = mxs_gpio_to_irq;
 293         port->bgc.gc.base = port->id * 32;
 294
 295         err = gpiochip_add(&port->bgc.gc);
 296         if (err) {
 297                 bgpio_remove(&port->bgc);
 298                 return err;
 299         }
 300
 301         return 0;
 302 }
 303
 304 static struct platform_driver mxs_gpio_driver = {
 305         .driver         = {
 306                 .name   = "gpio-mxs",
 307                 .owner  = THIS_MODULE,
 308                 .of_match_table = mxs_gpio_dt_ids,
 309         },
 310         .probe          = mxs_gpio_probe,
 311         .id_table       = mxs_gpio_ids,
 312 };
 313
 314 static int __init mxs_gpio_init(void)
 315 {
 316         return platform_driver_register(&mxs_gpio_driver);
 317 }
 318 postcore_initcall(mxs_gpio_init);
 319
 320 MODULE_AUTHOR("Freescale Semiconductor, "
 321               "Daniel Mack <danielncaiaq.de>, "
 322               "Juergen Beisert <kernel@pengutronix.de>");
 323 MODULE_DESCRIPTION("Freescale MXS GPIO");
 324 MODULE_LICENSE("GPL");