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Merge branches 'regmap-core', 'regmap-mmio' and 'regmap-naming' into regmap-stride
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/irqdomain.h>
28
29 #include <mach/hardware.h>
30 #include <asm/irq.h>
31 #include <mach/irqs.h>
32 #include <asm/gpio.h>
33 #include <asm/mach/irq.h>
34
35 #define OFF_MODE 1
36
37 static LIST_HEAD(omap_gpio_list);
38
39 struct gpio_regs {
40 u32 irqenable1;
41 u32 irqenable2;
42 u32 wake_en;
43 u32 ctrl;
44 u32 oe;
45 u32 leveldetect0;
46 u32 leveldetect1;
47 u32 risingdetect;
48 u32 fallingdetect;
49 u32 dataout;
50 u32 debounce;
51 u32 debounce_en;
52 };
53
54 struct gpio_bank {
55 struct list_head node;
56 void __iomem *base;
57 u16 irq;
58 int irq_base;
59 struct irq_domain *domain;
60 u32 suspend_wakeup;
61 u32 saved_wakeup;
62 u32 non_wakeup_gpios;
63 u32 enabled_non_wakeup_gpios;
64 struct gpio_regs context;
65 u32 saved_datain;
66 u32 saved_fallingdetect;
67 u32 saved_risingdetect;
68 u32 level_mask;
69 u32 toggle_mask;
70 spinlock_t lock;
71 struct gpio_chip chip;
72 struct clk *dbck;
73 u32 mod_usage;
74 u32 dbck_enable_mask;
75 bool dbck_enabled;
76 struct device *dev;
77 bool is_mpuio;
78 bool dbck_flag;
79 bool loses_context;
80 int stride;
81 u32 width;
82 int context_loss_count;
83 int power_mode;
84 bool workaround_enabled;
85
86 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
87 int (*get_context_loss_count)(struct device *dev);
88
89 struct omap_gpio_reg_offs *regs;
90 };
91
92 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
93 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
94 #define GPIO_MOD_CTRL_BIT BIT(0)
95
96 static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
97 {
98 return gpio_irq - bank->irq_base + bank->chip.base;
99 }
100
101 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
102 {
103 void __iomem *reg = bank->base;
104 u32 l;
105
106 reg += bank->regs->direction;
107 l = __raw_readl(reg);
108 if (is_input)
109 l |= 1 << gpio;
110 else
111 l &= ~(1 << gpio);
112 __raw_writel(l, reg);
113 bank->context.oe = l;
114 }
115
116
117 /* set data out value using dedicate set/clear register */
118 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
119 {
120 void __iomem *reg = bank->base;
121 u32 l = GPIO_BIT(bank, gpio);
122
123 if (enable) {
124 reg += bank->regs->set_dataout;
125 bank->context.dataout |= l;
126 } else {
127 reg += bank->regs->clr_dataout;
128 bank->context.dataout &= ~l;
129 }
130
131 __raw_writel(l, reg);
132 }
133
134 /* set data out value using mask register */
135 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
136 {
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = GPIO_BIT(bank, gpio);
139 u32 l;
140
141 l = __raw_readl(reg);
142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
146 __raw_writel(l, reg);
147 bank->context.dataout = l;
148 }
149
150 static int _get_gpio_datain(struct gpio_bank *bank, int offset)
151 {
152 void __iomem *reg = bank->base + bank->regs->datain;
153
154 return (__raw_readl(reg) & (1 << offset)) != 0;
155 }
156
157 static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
158 {
159 void __iomem *reg = bank->base + bank->regs->dataout;
160
161 return (__raw_readl(reg) & (1 << offset)) != 0;
162 }
163
164 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165 {
166 int l = __raw_readl(base + reg);
167
168 if (set)
169 l |= mask;
170 else
171 l &= ~mask;
172
173 __raw_writel(l, base + reg);
174 }
175
176 static inline void _gpio_dbck_enable(struct gpio_bank *bank)
177 {
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
181 }
182 }
183
184 static inline void _gpio_dbck_disable(struct gpio_bank *bank)
185 {
186 if (bank->dbck_enable_mask && bank->dbck_enabled) {
187 clk_disable(bank->dbck);
188 bank->dbck_enabled = false;
189 }
190 }
191
192 /**
193 * _set_gpio_debounce - low level gpio debounce time
194 * @bank: the gpio bank we're acting upon
195 * @gpio: the gpio number on this @gpio
196 * @debounce: debounce time to use
197 *
198 * OMAP's debounce time is in 31us steps so we need
199 * to convert and round up to the closest unit.
200 */
201 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
202 unsigned debounce)
203 {
204 void __iomem *reg;
205 u32 val;
206 u32 l;
207
208 if (!bank->dbck_flag)
209 return;
210
211 if (debounce < 32)
212 debounce = 0x01;
213 else if (debounce > 7936)
214 debounce = 0xff;
215 else
216 debounce = (debounce / 0x1f) - 1;
217
218 l = GPIO_BIT(bank, gpio);
219
220 clk_enable(bank->dbck);
221 reg = bank->base + bank->regs->debounce;
222 __raw_writel(debounce, reg);
223
224 reg = bank->base + bank->regs->debounce_en;
225 val = __raw_readl(reg);
226
227 if (debounce)
228 val |= l;
229 else
230 val &= ~l;
231 bank->dbck_enable_mask = val;
232
233 __raw_writel(val, reg);
234 clk_disable(bank->dbck);
235 /*
236 * Enable debounce clock per module.
237 * This call is mandatory because in omap_gpio_request() when
238 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
239 * runtime callbck fails to turn on dbck because dbck_enable_mask
240 * used within _gpio_dbck_enable() is still not initialized at
241 * that point. Therefore we have to enable dbck here.
242 */
243 _gpio_dbck_enable(bank);
244 if (bank->dbck_enable_mask) {
245 bank->context.debounce = debounce;
246 bank->context.debounce_en = val;
247 }
248 }
249
250 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
251 unsigned trigger)
252 {
253 void __iomem *base = bank->base;
254 u32 gpio_bit = 1 << gpio;
255
256 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
257 trigger & IRQ_TYPE_LEVEL_LOW);
258 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
259 trigger & IRQ_TYPE_LEVEL_HIGH);
260 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
261 trigger & IRQ_TYPE_EDGE_RISING);
262 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
263 trigger & IRQ_TYPE_EDGE_FALLING);
264
265 bank->context.leveldetect0 =
266 __raw_readl(bank->base + bank->regs->leveldetect0);
267 bank->context.leveldetect1 =
268 __raw_readl(bank->base + bank->regs->leveldetect1);
269 bank->context.risingdetect =
270 __raw_readl(bank->base + bank->regs->risingdetect);
271 bank->context.fallingdetect =
272 __raw_readl(bank->base + bank->regs->fallingdetect);
273
274 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
275 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
276 bank->context.wake_en =
277 __raw_readl(bank->base + bank->regs->wkup_en);
278 }
279
280 /* This part needs to be executed always for OMAP{34xx, 44xx} */
281 if (!bank->regs->irqctrl) {
282 /* On omap24xx proceed only when valid GPIO bit is set */
283 if (bank->non_wakeup_gpios) {
284 if (!(bank->non_wakeup_gpios & gpio_bit))
285 goto exit;
286 }
287
288 /*
289 * Log the edge gpio and manually trigger the IRQ
290 * after resume if the input level changes
291 * to avoid irq lost during PER RET/OFF mode
292 * Applies for omap2 non-wakeup gpio and all omap3 gpios
293 */
294 if (trigger & IRQ_TYPE_EDGE_BOTH)
295 bank->enabled_non_wakeup_gpios |= gpio_bit;
296 else
297 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
298 }
299
300 exit:
301 bank->level_mask =
302 __raw_readl(bank->base + bank->regs->leveldetect0) |
303 __raw_readl(bank->base + bank->regs->leveldetect1);
304 }
305
306 #ifdef CONFIG_ARCH_OMAP1
307 /*
308 * This only applies to chips that can't do both rising and falling edge
309 * detection at once. For all other chips, this function is a noop.
310 */
311 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
312 {
313 void __iomem *reg = bank->base;
314 u32 l = 0;
315
316 if (!bank->regs->irqctrl)
317 return;
318
319 reg += bank->regs->irqctrl;
320
321 l = __raw_readl(reg);
322 if ((l >> gpio) & 1)
323 l &= ~(1 << gpio);
324 else
325 l |= 1 << gpio;
326
327 __raw_writel(l, reg);
328 }
329 #else
330 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
331 #endif
332
333 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
334 unsigned trigger)
335 {
336 void __iomem *reg = bank->base;
337 void __iomem *base = bank->base;
338 u32 l = 0;
339
340 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
341 set_gpio_trigger(bank, gpio, trigger);
342 } else if (bank->regs->irqctrl) {
343 reg += bank->regs->irqctrl;
344
345 l = __raw_readl(reg);
346 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
347 bank->toggle_mask |= 1 << gpio;
348 if (trigger & IRQ_TYPE_EDGE_RISING)
349 l |= 1 << gpio;
350 else if (trigger & IRQ_TYPE_EDGE_FALLING)
351 l &= ~(1 << gpio);
352 else
353 return -EINVAL;
354
355 __raw_writel(l, reg);
356 } else if (bank->regs->edgectrl1) {
357 if (gpio & 0x08)
358 reg += bank->regs->edgectrl2;
359 else
360 reg += bank->regs->edgectrl1;
361
362 gpio &= 0x07;
363 l = __raw_readl(reg);
364 l &= ~(3 << (gpio << 1));
365 if (trigger & IRQ_TYPE_EDGE_RISING)
366 l |= 2 << (gpio << 1);
367 if (trigger & IRQ_TYPE_EDGE_FALLING)
368 l |= 1 << (gpio << 1);
369
370 /* Enable wake-up during idle for dynamic tick */
371 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
372 bank->context.wake_en =
373 __raw_readl(bank->base + bank->regs->wkup_en);
374 __raw_writel(l, reg);
375 }
376 return 0;
377 }
378
379 static int gpio_irq_type(struct irq_data *d, unsigned type)
380 {
381 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
382 unsigned gpio;
383 int retval;
384 unsigned long flags;
385
386 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
387 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
388 else
389 gpio = irq_to_gpio(bank, d->irq);
390
391 if (type & ~IRQ_TYPE_SENSE_MASK)
392 return -EINVAL;
393
394 if (!bank->regs->leveldetect0 &&
395 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
396 return -EINVAL;
397
398 spin_lock_irqsave(&bank->lock, flags);
399 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
400 spin_unlock_irqrestore(&bank->lock, flags);
401
402 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
403 __irq_set_handler_locked(d->irq, handle_level_irq);
404 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
405 __irq_set_handler_locked(d->irq, handle_edge_irq);
406
407 return retval;
408 }
409
410 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
411 {
412 void __iomem *reg = bank->base;
413
414 reg += bank->regs->irqstatus;
415 __raw_writel(gpio_mask, reg);
416
417 /* Workaround for clearing DSP GPIO interrupts to allow retention */
418 if (bank->regs->irqstatus2) {
419 reg = bank->base + bank->regs->irqstatus2;
420 __raw_writel(gpio_mask, reg);
421 }
422
423 /* Flush posted write for the irq status to avoid spurious interrupts */
424 __raw_readl(reg);
425 }
426
427 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
428 {
429 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
430 }
431
432 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
433 {
434 void __iomem *reg = bank->base;
435 u32 l;
436 u32 mask = (1 << bank->width) - 1;
437
438 reg += bank->regs->irqenable;
439 l = __raw_readl(reg);
440 if (bank->regs->irqenable_inv)
441 l = ~l;
442 l &= mask;
443 return l;
444 }
445
446 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
447 {
448 void __iomem *reg = bank->base;
449 u32 l;
450
451 if (bank->regs->set_irqenable) {
452 reg += bank->regs->set_irqenable;
453 l = gpio_mask;
454 bank->context.irqenable1 |= gpio_mask;
455 } else {
456 reg += bank->regs->irqenable;
457 l = __raw_readl(reg);
458 if (bank->regs->irqenable_inv)
459 l &= ~gpio_mask;
460 else
461 l |= gpio_mask;
462 bank->context.irqenable1 = l;
463 }
464
465 __raw_writel(l, reg);
466 }
467
468 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
469 {
470 void __iomem *reg = bank->base;
471 u32 l;
472
473 if (bank->regs->clr_irqenable) {
474 reg += bank->regs->clr_irqenable;
475 l = gpio_mask;
476 bank->context.irqenable1 &= ~gpio_mask;
477 } else {
478 reg += bank->regs->irqenable;
479 l = __raw_readl(reg);
480 if (bank->regs->irqenable_inv)
481 l |= gpio_mask;
482 else
483 l &= ~gpio_mask;
484 bank->context.irqenable1 = l;
485 }
486
487 __raw_writel(l, reg);
488 }
489
490 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
491 {
492 if (enable)
493 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
494 else
495 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
496 }
497
498 /*
499 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
500 * 1510 does not seem to have a wake-up register. If JTAG is connected
501 * to the target, system will wake up always on GPIO events. While
502 * system is running all registered GPIO interrupts need to have wake-up
503 * enabled. When system is suspended, only selected GPIO interrupts need
504 * to have wake-up enabled.
505 */
506 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
507 {
508 u32 gpio_bit = GPIO_BIT(bank, gpio);
509 unsigned long flags;
510
511 if (bank->non_wakeup_gpios & gpio_bit) {
512 dev_err(bank->dev,
513 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
514 return -EINVAL;
515 }
516
517 spin_lock_irqsave(&bank->lock, flags);
518 if (enable)
519 bank->suspend_wakeup |= gpio_bit;
520 else
521 bank->suspend_wakeup &= ~gpio_bit;
522
523 __raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en);
524 spin_unlock_irqrestore(&bank->lock, flags);
525
526 return 0;
527 }
528
529 static void _reset_gpio(struct gpio_bank *bank, int gpio)
530 {
531 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
532 _set_gpio_irqenable(bank, gpio, 0);
533 _clear_gpio_irqstatus(bank, gpio);
534 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
535 }
536
537 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
538 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
539 {
540 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
541 unsigned int gpio = irq_to_gpio(bank, d->irq);
542
543 return _set_gpio_wakeup(bank, gpio, enable);
544 }
545
546 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
547 {
548 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
549 unsigned long flags;
550
551 /*
552 * If this is the first gpio_request for the bank,
553 * enable the bank module.
554 */
555 if (!bank->mod_usage)
556 pm_runtime_get_sync(bank->dev);
557
558 spin_lock_irqsave(&bank->lock, flags);
559 /* Set trigger to none. You need to enable the desired trigger with
560 * request_irq() or set_irq_type().
561 */
562 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
563
564 if (bank->regs->pinctrl) {
565 void __iomem *reg = bank->base + bank->regs->pinctrl;
566
567 /* Claim the pin for MPU */
568 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
569 }
570
571 if (bank->regs->ctrl && !bank->mod_usage) {
572 void __iomem *reg = bank->base + bank->regs->ctrl;
573 u32 ctrl;
574
575 ctrl = __raw_readl(reg);
576 /* Module is enabled, clocks are not gated */
577 ctrl &= ~GPIO_MOD_CTRL_BIT;
578 __raw_writel(ctrl, reg);
579 bank->context.ctrl = ctrl;
580 }
581
582 bank->mod_usage |= 1 << offset;
583
584 spin_unlock_irqrestore(&bank->lock, flags);
585
586 return 0;
587 }
588
589 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
590 {
591 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
592 void __iomem *base = bank->base;
593 unsigned long flags;
594
595 spin_lock_irqsave(&bank->lock, flags);
596
597 if (bank->regs->wkup_en) {
598 /* Disable wake-up during idle for dynamic tick */
599 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
600 bank->context.wake_en =
601 __raw_readl(bank->base + bank->regs->wkup_en);
602 }
603
604 bank->mod_usage &= ~(1 << offset);
605
606 if (bank->regs->ctrl && !bank->mod_usage) {
607 void __iomem *reg = bank->base + bank->regs->ctrl;
608 u32 ctrl;
609
610 ctrl = __raw_readl(reg);
611 /* Module is disabled, clocks are gated */
612 ctrl |= GPIO_MOD_CTRL_BIT;
613 __raw_writel(ctrl, reg);
614 bank->context.ctrl = ctrl;
615 }
616
617 _reset_gpio(bank, bank->chip.base + offset);
618 spin_unlock_irqrestore(&bank->lock, flags);
619
620 /*
621 * If this is the last gpio to be freed in the bank,
622 * disable the bank module.
623 */
624 if (!bank->mod_usage)
625 pm_runtime_put(bank->dev);
626 }
627
628 /*
629 * We need to unmask the GPIO bank interrupt as soon as possible to
630 * avoid missing GPIO interrupts for other lines in the bank.
631 * Then we need to mask-read-clear-unmask the triggered GPIO lines
632 * in the bank to avoid missing nested interrupts for a GPIO line.
633 * If we wait to unmask individual GPIO lines in the bank after the
634 * line's interrupt handler has been run, we may miss some nested
635 * interrupts.
636 */
637 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
638 {
639 void __iomem *isr_reg = NULL;
640 u32 isr;
641 unsigned int gpio_irq, gpio_index;
642 struct gpio_bank *bank;
643 u32 retrigger = 0;
644 int unmasked = 0;
645 struct irq_chip *chip = irq_desc_get_chip(desc);
646
647 chained_irq_enter(chip, desc);
648
649 bank = irq_get_handler_data(irq);
650 isr_reg = bank->base + bank->regs->irqstatus;
651 pm_runtime_get_sync(bank->dev);
652
653 if (WARN_ON(!isr_reg))
654 goto exit;
655
656 while(1) {
657 u32 isr_saved, level_mask = 0;
658 u32 enabled;
659
660 enabled = _get_gpio_irqbank_mask(bank);
661 isr_saved = isr = __raw_readl(isr_reg) & enabled;
662
663 if (bank->level_mask)
664 level_mask = bank->level_mask & enabled;
665
666 /* clear edge sensitive interrupts before handler(s) are
667 called so that we don't miss any interrupt occurred while
668 executing them */
669 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
670 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
671 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
672
673 /* if there is only edge sensitive GPIO pin interrupts
674 configured, we could unmask GPIO bank interrupt immediately */
675 if (!level_mask && !unmasked) {
676 unmasked = 1;
677 chained_irq_exit(chip, desc);
678 }
679
680 isr |= retrigger;
681 retrigger = 0;
682 if (!isr)
683 break;
684
685 gpio_irq = bank->irq_base;
686 for (; isr != 0; isr >>= 1, gpio_irq++) {
687 int gpio = irq_to_gpio(bank, gpio_irq);
688
689 if (!(isr & 1))
690 continue;
691
692 gpio_index = GPIO_INDEX(bank, gpio);
693
694 /*
695 * Some chips can't respond to both rising and falling
696 * at the same time. If this irq was requested with
697 * both flags, we need to flip the ICR data for the IRQ
698 * to respond to the IRQ for the opposite direction.
699 * This will be indicated in the bank toggle_mask.
700 */
701 if (bank->toggle_mask & (1 << gpio_index))
702 _toggle_gpio_edge_triggering(bank, gpio_index);
703
704 generic_handle_irq(gpio_irq);
705 }
706 }
707 /* if bank has any level sensitive GPIO pin interrupt
708 configured, we must unmask the bank interrupt only after
709 handler(s) are executed in order to avoid spurious bank
710 interrupt */
711 exit:
712 if (!unmasked)
713 chained_irq_exit(chip, desc);
714 pm_runtime_put(bank->dev);
715 }
716
717 static void gpio_irq_shutdown(struct irq_data *d)
718 {
719 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
720 unsigned int gpio = irq_to_gpio(bank, d->irq);
721 unsigned long flags;
722
723 spin_lock_irqsave(&bank->lock, flags);
724 _reset_gpio(bank, gpio);
725 spin_unlock_irqrestore(&bank->lock, flags);
726 }
727
728 static void gpio_ack_irq(struct irq_data *d)
729 {
730 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
731 unsigned int gpio = irq_to_gpio(bank, d->irq);
732
733 _clear_gpio_irqstatus(bank, gpio);
734 }
735
736 static void gpio_mask_irq(struct irq_data *d)
737 {
738 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
739 unsigned int gpio = irq_to_gpio(bank, d->irq);
740 unsigned long flags;
741
742 spin_lock_irqsave(&bank->lock, flags);
743 _set_gpio_irqenable(bank, gpio, 0);
744 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
745 spin_unlock_irqrestore(&bank->lock, flags);
746 }
747
748 static void gpio_unmask_irq(struct irq_data *d)
749 {
750 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
751 unsigned int gpio = irq_to_gpio(bank, d->irq);
752 unsigned int irq_mask = GPIO_BIT(bank, gpio);
753 u32 trigger = irqd_get_trigger_type(d);
754 unsigned long flags;
755
756 spin_lock_irqsave(&bank->lock, flags);
757 if (trigger)
758 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
759
760 /* For level-triggered GPIOs, the clearing must be done after
761 * the HW source is cleared, thus after the handler has run */
762 if (bank->level_mask & irq_mask) {
763 _set_gpio_irqenable(bank, gpio, 0);
764 _clear_gpio_irqstatus(bank, gpio);
765 }
766
767 _set_gpio_irqenable(bank, gpio, 1);
768 spin_unlock_irqrestore(&bank->lock, flags);
769 }
770
771 static struct irq_chip gpio_irq_chip = {
772 .name = "GPIO",
773 .irq_shutdown = gpio_irq_shutdown,
774 .irq_ack = gpio_ack_irq,
775 .irq_mask = gpio_mask_irq,
776 .irq_unmask = gpio_unmask_irq,
777 .irq_set_type = gpio_irq_type,
778 .irq_set_wake = gpio_wake_enable,
779 };
780
781 /*---------------------------------------------------------------------*/
782
783 static int omap_mpuio_suspend_noirq(struct device *dev)
784 {
785 struct platform_device *pdev = to_platform_device(dev);
786 struct gpio_bank *bank = platform_get_drvdata(pdev);
787 void __iomem *mask_reg = bank->base +
788 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
789 unsigned long flags;
790
791 spin_lock_irqsave(&bank->lock, flags);
792 bank->saved_wakeup = __raw_readl(mask_reg);
793 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
794 spin_unlock_irqrestore(&bank->lock, flags);
795
796 return 0;
797 }
798
799 static int omap_mpuio_resume_noirq(struct device *dev)
800 {
801 struct platform_device *pdev = to_platform_device(dev);
802 struct gpio_bank *bank = platform_get_drvdata(pdev);
803 void __iomem *mask_reg = bank->base +
804 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
805 unsigned long flags;
806
807 spin_lock_irqsave(&bank->lock, flags);
808 __raw_writel(bank->saved_wakeup, mask_reg);
809 spin_unlock_irqrestore(&bank->lock, flags);
810
811 return 0;
812 }
813
814 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
815 .suspend_noirq = omap_mpuio_suspend_noirq,
816 .resume_noirq = omap_mpuio_resume_noirq,
817 };
818
819 /* use platform_driver for this. */
820 static struct platform_driver omap_mpuio_driver = {
821 .driver = {
822 .name = "mpuio",
823 .pm = &omap_mpuio_dev_pm_ops,
824 },
825 };
826
827 static struct platform_device omap_mpuio_device = {
828 .name = "mpuio",
829 .id = -1,
830 .dev = {
831 .driver = &omap_mpuio_driver.driver,
832 }
833 /* could list the /proc/iomem resources */
834 };
835
836 static inline void mpuio_init(struct gpio_bank *bank)
837 {
838 platform_set_drvdata(&omap_mpuio_device, bank);
839
840 if (platform_driver_register(&omap_mpuio_driver) == 0)
841 (void) platform_device_register(&omap_mpuio_device);
842 }
843
844 /*---------------------------------------------------------------------*/
845
846 static int gpio_input(struct gpio_chip *chip, unsigned offset)
847 {
848 struct gpio_bank *bank;
849 unsigned long flags;
850
851 bank = container_of(chip, struct gpio_bank, chip);
852 spin_lock_irqsave(&bank->lock, flags);
853 _set_gpio_direction(bank, offset, 1);
854 spin_unlock_irqrestore(&bank->lock, flags);
855 return 0;
856 }
857
858 static int gpio_is_input(struct gpio_bank *bank, int mask)
859 {
860 void __iomem *reg = bank->base + bank->regs->direction;
861
862 return __raw_readl(reg) & mask;
863 }
864
865 static int gpio_get(struct gpio_chip *chip, unsigned offset)
866 {
867 struct gpio_bank *bank;
868 u32 mask;
869
870 bank = container_of(chip, struct gpio_bank, chip);
871 mask = (1 << offset);
872
873 if (gpio_is_input(bank, mask))
874 return _get_gpio_datain(bank, offset);
875 else
876 return _get_gpio_dataout(bank, offset);
877 }
878
879 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
880 {
881 struct gpio_bank *bank;
882 unsigned long flags;
883
884 bank = container_of(chip, struct gpio_bank, chip);
885 spin_lock_irqsave(&bank->lock, flags);
886 bank->set_dataout(bank, offset, value);
887 _set_gpio_direction(bank, offset, 0);
888 spin_unlock_irqrestore(&bank->lock, flags);
889 return 0;
890 }
891
892 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
893 unsigned debounce)
894 {
895 struct gpio_bank *bank;
896 unsigned long flags;
897
898 bank = container_of(chip, struct gpio_bank, chip);
899
900 if (!bank->dbck) {
901 bank->dbck = clk_get(bank->dev, "dbclk");
902 if (IS_ERR(bank->dbck))
903 dev_err(bank->dev, "Could not get gpio dbck\n");
904 }
905
906 spin_lock_irqsave(&bank->lock, flags);
907 _set_gpio_debounce(bank, offset, debounce);
908 spin_unlock_irqrestore(&bank->lock, flags);
909
910 return 0;
911 }
912
913 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
914 {
915 struct gpio_bank *bank;
916 unsigned long flags;
917
918 bank = container_of(chip, struct gpio_bank, chip);
919 spin_lock_irqsave(&bank->lock, flags);
920 bank->set_dataout(bank, offset, value);
921 spin_unlock_irqrestore(&bank->lock, flags);
922 }
923
924 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
925 {
926 struct gpio_bank *bank;
927
928 bank = container_of(chip, struct gpio_bank, chip);
929 return bank->irq_base + offset;
930 }
931
932 /*---------------------------------------------------------------------*/
933
934 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
935 {
936 static bool called;
937 u32 rev;
938
939 if (called || bank->regs->revision == USHRT_MAX)
940 return;
941
942 rev = __raw_readw(bank->base + bank->regs->revision);
943 pr_info("OMAP GPIO hardware version %d.%d\n",
944 (rev >> 4) & 0x0f, rev & 0x0f);
945
946 called = true;
947 }
948
949 /* This lock class tells lockdep that GPIO irqs are in a different
950 * category than their parents, so it won't report false recursion.
951 */
952 static struct lock_class_key gpio_lock_class;
953
954 static void omap_gpio_mod_init(struct gpio_bank *bank)
955 {
956 void __iomem *base = bank->base;
957 u32 l = 0xffffffff;
958
959 if (bank->width == 16)
960 l = 0xffff;
961
962 if (bank->is_mpuio) {
963 __raw_writel(l, bank->base + bank->regs->irqenable);
964 return;
965 }
966
967 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
968 _gpio_rmw(base, bank->regs->irqstatus, l,
969 bank->regs->irqenable_inv == false);
970 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
971 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
972 if (bank->regs->debounce_en)
973 _gpio_rmw(base, bank->regs->debounce_en, 0, 1);
974
975 /* Save OE default value (0xffffffff) in the context */
976 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
977 /* Initialize interface clk ungated, module enabled */
978 if (bank->regs->ctrl)
979 _gpio_rmw(base, bank->regs->ctrl, 0, 1);
980 }
981
982 static __devinit void
983 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
984 unsigned int num)
985 {
986 struct irq_chip_generic *gc;
987 struct irq_chip_type *ct;
988
989 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
990 handle_simple_irq);
991 if (!gc) {
992 dev_err(bank->dev, "Memory alloc failed for gc\n");
993 return;
994 }
995
996 ct = gc->chip_types;
997
998 /* NOTE: No ack required, reading IRQ status clears it. */
999 ct->chip.irq_mask = irq_gc_mask_set_bit;
1000 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1001 ct->chip.irq_set_type = gpio_irq_type;
1002
1003 if (bank->regs->wkup_en)
1004 ct->chip.irq_set_wake = gpio_wake_enable,
1005
1006 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1007 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1008 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1009 }
1010
1011 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1012 {
1013 int j;
1014 static int gpio;
1015
1016 /*
1017 * REVISIT eventually switch from OMAP-specific gpio structs
1018 * over to the generic ones
1019 */
1020 bank->chip.request = omap_gpio_request;
1021 bank->chip.free = omap_gpio_free;
1022 bank->chip.direction_input = gpio_input;
1023 bank->chip.get = gpio_get;
1024 bank->chip.direction_output = gpio_output;
1025 bank->chip.set_debounce = gpio_debounce;
1026 bank->chip.set = gpio_set;
1027 bank->chip.to_irq = gpio_2irq;
1028 if (bank->is_mpuio) {
1029 bank->chip.label = "mpuio";
1030 if (bank->regs->wkup_en)
1031 bank->chip.dev = &omap_mpuio_device.dev;
1032 bank->chip.base = OMAP_MPUIO(0);
1033 } else {
1034 bank->chip.label = "gpio";
1035 bank->chip.base = gpio;
1036 gpio += bank->width;
1037 }
1038 bank->chip.ngpio = bank->width;
1039
1040 gpiochip_add(&bank->chip);
1041
1042 for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1043 irq_set_lockdep_class(j, &gpio_lock_class);
1044 irq_set_chip_data(j, bank);
1045 if (bank->is_mpuio) {
1046 omap_mpuio_alloc_gc(bank, j, bank->width);
1047 } else {
1048 irq_set_chip(j, &gpio_irq_chip);
1049 irq_set_handler(j, handle_simple_irq);
1050 set_irq_flags(j, IRQF_VALID);
1051 }
1052 }
1053 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1054 irq_set_handler_data(bank->irq, bank);
1055 }
1056
1057 static const struct of_device_id omap_gpio_match[];
1058
1059 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1060 {
1061 struct device *dev = &pdev->dev;
1062 struct device_node *node = dev->of_node;
1063 const struct of_device_id *match;
1064 struct omap_gpio_platform_data *pdata;
1065 struct resource *res;
1066 struct gpio_bank *bank;
1067 int ret = 0;
1068
1069 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1070
1071 pdata = match ? match->data : dev->platform_data;
1072 if (!pdata)
1073 return -EINVAL;
1074
1075 bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
1076 if (!bank) {
1077 dev_err(dev, "Memory alloc failed\n");
1078 return -ENOMEM;
1079 }
1080
1081 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1082 if (unlikely(!res)) {
1083 dev_err(dev, "Invalid IRQ resource\n");
1084 return -ENODEV;
1085 }
1086
1087 bank->irq = res->start;
1088 bank->dev = dev;
1089 bank->dbck_flag = pdata->dbck_flag;
1090 bank->stride = pdata->bank_stride;
1091 bank->width = pdata->bank_width;
1092 bank->is_mpuio = pdata->is_mpuio;
1093 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1094 bank->loses_context = pdata->loses_context;
1095 bank->get_context_loss_count = pdata->get_context_loss_count;
1096 bank->regs = pdata->regs;
1097 #ifdef CONFIG_OF_GPIO
1098 bank->chip.of_node = of_node_get(node);
1099 #endif
1100
1101 bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1102 if (bank->irq_base < 0) {
1103 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1104 return -ENODEV;
1105 }
1106
1107 bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1108 0, &irq_domain_simple_ops, NULL);
1109
1110 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1111 bank->set_dataout = _set_gpio_dataout_reg;
1112 else
1113 bank->set_dataout = _set_gpio_dataout_mask;
1114
1115 spin_lock_init(&bank->lock);
1116
1117 /* Static mapping, never released */
1118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1119 if (unlikely(!res)) {
1120 dev_err(dev, "Invalid mem resource\n");
1121 return -ENODEV;
1122 }
1123
1124 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1125 pdev->name)) {
1126 dev_err(dev, "Region already claimed\n");
1127 return -EBUSY;
1128 }
1129
1130 bank->base = devm_ioremap(dev, res->start, resource_size(res));
1131 if (!bank->base) {
1132 dev_err(dev, "Could not ioremap\n");
1133 return -ENOMEM;
1134 }
1135
1136 platform_set_drvdata(pdev, bank);
1137
1138 pm_runtime_enable(bank->dev);
1139 pm_runtime_irq_safe(bank->dev);
1140 pm_runtime_get_sync(bank->dev);
1141
1142 if (bank->is_mpuio)
1143 mpuio_init(bank);
1144
1145 omap_gpio_mod_init(bank);
1146 omap_gpio_chip_init(bank);
1147 omap_gpio_show_rev(bank);
1148
1149 pm_runtime_put(bank->dev);
1150
1151 list_add_tail(&bank->node, &omap_gpio_list);
1152
1153 return ret;
1154 }
1155
1156 #ifdef CONFIG_ARCH_OMAP2PLUS
1157
1158 #if defined(CONFIG_PM_SLEEP)
1159 static int omap_gpio_suspend(struct device *dev)
1160 {
1161 struct platform_device *pdev = to_platform_device(dev);
1162 struct gpio_bank *bank = platform_get_drvdata(pdev);
1163 void __iomem *base = bank->base;
1164 void __iomem *wakeup_enable;
1165 unsigned long flags;
1166
1167 if (!bank->mod_usage || !bank->loses_context)
1168 return 0;
1169
1170 if (!bank->regs->wkup_en || !bank->suspend_wakeup)
1171 return 0;
1172
1173 wakeup_enable = bank->base + bank->regs->wkup_en;
1174
1175 spin_lock_irqsave(&bank->lock, flags);
1176 bank->saved_wakeup = __raw_readl(wakeup_enable);
1177 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1178 _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
1179 spin_unlock_irqrestore(&bank->lock, flags);
1180
1181 return 0;
1182 }
1183
1184 static int omap_gpio_resume(struct device *dev)
1185 {
1186 struct platform_device *pdev = to_platform_device(dev);
1187 struct gpio_bank *bank = platform_get_drvdata(pdev);
1188 void __iomem *base = bank->base;
1189 unsigned long flags;
1190
1191 if (!bank->mod_usage || !bank->loses_context)
1192 return 0;
1193
1194 if (!bank->regs->wkup_en || !bank->saved_wakeup)
1195 return 0;
1196
1197 spin_lock_irqsave(&bank->lock, flags);
1198 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1199 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
1200 spin_unlock_irqrestore(&bank->lock, flags);
1201
1202 return 0;
1203 }
1204 #endif /* CONFIG_PM_SLEEP */
1205
1206 #if defined(CONFIG_PM_RUNTIME)
1207 static void omap_gpio_restore_context(struct gpio_bank *bank);
1208
1209 static int omap_gpio_runtime_suspend(struct device *dev)
1210 {
1211 struct platform_device *pdev = to_platform_device(dev);
1212 struct gpio_bank *bank = platform_get_drvdata(pdev);
1213 u32 l1 = 0, l2 = 0;
1214 unsigned long flags;
1215 u32 wake_low, wake_hi;
1216
1217 spin_lock_irqsave(&bank->lock, flags);
1218
1219 /*
1220 * Only edges can generate a wakeup event to the PRCM.
1221 *
1222 * Therefore, ensure any wake-up capable GPIOs have
1223 * edge-detection enabled before going idle to ensure a wakeup
1224 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1225 * NDA TRM 25.5.3.1)
1226 *
1227 * The normal values will be restored upon ->runtime_resume()
1228 * by writing back the values saved in bank->context.
1229 */
1230 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1231 if (wake_low)
1232 __raw_writel(wake_low | bank->context.fallingdetect,
1233 bank->base + bank->regs->fallingdetect);
1234 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1235 if (wake_hi)
1236 __raw_writel(wake_hi | bank->context.risingdetect,
1237 bank->base + bank->regs->risingdetect);
1238
1239 if (bank->power_mode != OFF_MODE) {
1240 bank->power_mode = 0;
1241 goto update_gpio_context_count;
1242 }
1243 /*
1244 * If going to OFF, remove triggering for all
1245 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1246 * generated. See OMAP2420 Errata item 1.101.
1247 */
1248 bank->saved_datain = __raw_readl(bank->base +
1249 bank->regs->datain);
1250 l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
1251 l2 = __raw_readl(bank->base + bank->regs->risingdetect);
1252
1253 bank->saved_fallingdetect = l1;
1254 bank->saved_risingdetect = l2;
1255 l1 &= ~bank->enabled_non_wakeup_gpios;
1256 l2 &= ~bank->enabled_non_wakeup_gpios;
1257
1258 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1259 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1260
1261 bank->workaround_enabled = true;
1262
1263 update_gpio_context_count:
1264 if (bank->get_context_loss_count)
1265 bank->context_loss_count =
1266 bank->get_context_loss_count(bank->dev);
1267
1268 _gpio_dbck_disable(bank);
1269 spin_unlock_irqrestore(&bank->lock, flags);
1270
1271 return 0;
1272 }
1273
1274 static int omap_gpio_runtime_resume(struct device *dev)
1275 {
1276 struct platform_device *pdev = to_platform_device(dev);
1277 struct gpio_bank *bank = platform_get_drvdata(pdev);
1278 int context_lost_cnt_after;
1279 u32 l = 0, gen, gen0, gen1;
1280 unsigned long flags;
1281
1282 spin_lock_irqsave(&bank->lock, flags);
1283 _gpio_dbck_enable(bank);
1284
1285 /*
1286 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1287 * GPIOs were set to edge trigger also in order to be able to
1288 * generate a PRCM wakeup. Here we restore the
1289 * pre-runtime_suspend() values for edge triggering.
1290 */
1291 __raw_writel(bank->context.fallingdetect,
1292 bank->base + bank->regs->fallingdetect);
1293 __raw_writel(bank->context.risingdetect,
1294 bank->base + bank->regs->risingdetect);
1295
1296 if (!bank->workaround_enabled) {
1297 spin_unlock_irqrestore(&bank->lock, flags);
1298 return 0;
1299 }
1300
1301 if (bank->get_context_loss_count) {
1302 context_lost_cnt_after =
1303 bank->get_context_loss_count(bank->dev);
1304 if (context_lost_cnt_after != bank->context_loss_count ||
1305 !context_lost_cnt_after) {
1306 omap_gpio_restore_context(bank);
1307 } else {
1308 spin_unlock_irqrestore(&bank->lock, flags);
1309 return 0;
1310 }
1311 }
1312
1313 __raw_writel(bank->saved_fallingdetect,
1314 bank->base + bank->regs->fallingdetect);
1315 __raw_writel(bank->saved_risingdetect,
1316 bank->base + bank->regs->risingdetect);
1317 l = __raw_readl(bank->base + bank->regs->datain);
1318
1319 /*
1320 * Check if any of the non-wakeup interrupt GPIOs have changed
1321 * state. If so, generate an IRQ by software. This is
1322 * horribly racy, but it's the best we can do to work around
1323 * this silicon bug.
1324 */
1325 l ^= bank->saved_datain;
1326 l &= bank->enabled_non_wakeup_gpios;
1327
1328 /*
1329 * No need to generate IRQs for the rising edge for gpio IRQs
1330 * configured with falling edge only; and vice versa.
1331 */
1332 gen0 = l & bank->saved_fallingdetect;
1333 gen0 &= bank->saved_datain;
1334
1335 gen1 = l & bank->saved_risingdetect;
1336 gen1 &= ~(bank->saved_datain);
1337
1338 /* FIXME: Consider GPIO IRQs with level detections properly! */
1339 gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect));
1340 /* Consider all GPIO IRQs needed to be updated */
1341 gen |= gen0 | gen1;
1342
1343 if (gen) {
1344 u32 old0, old1;
1345
1346 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1347 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1348
1349 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1350 __raw_writel(old0 | gen, bank->base +
1351 bank->regs->leveldetect0);
1352 __raw_writel(old1 | gen, bank->base +
1353 bank->regs->leveldetect1);
1354 }
1355
1356 if (cpu_is_omap44xx()) {
1357 __raw_writel(old0 | l, bank->base +
1358 bank->regs->leveldetect0);
1359 __raw_writel(old1 | l, bank->base +
1360 bank->regs->leveldetect1);
1361 }
1362 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1363 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1364 }
1365
1366 bank->workaround_enabled = false;
1367 spin_unlock_irqrestore(&bank->lock, flags);
1368
1369 return 0;
1370 }
1371 #endif /* CONFIG_PM_RUNTIME */
1372
1373 void omap2_gpio_prepare_for_idle(int pwr_mode)
1374 {
1375 struct gpio_bank *bank;
1376
1377 list_for_each_entry(bank, &omap_gpio_list, node) {
1378 if (!bank->mod_usage || !bank->loses_context)
1379 continue;
1380
1381 bank->power_mode = pwr_mode;
1382
1383 pm_runtime_put_sync_suspend(bank->dev);
1384 }
1385 }
1386
1387 void omap2_gpio_resume_after_idle(void)
1388 {
1389 struct gpio_bank *bank;
1390
1391 list_for_each_entry(bank, &omap_gpio_list, node) {
1392 if (!bank->mod_usage || !bank->loses_context)
1393 continue;
1394
1395 pm_runtime_get_sync(bank->dev);
1396 }
1397 }
1398
1399 #if defined(CONFIG_PM_RUNTIME)
1400 static void omap_gpio_restore_context(struct gpio_bank *bank)
1401 {
1402 __raw_writel(bank->context.wake_en,
1403 bank->base + bank->regs->wkup_en);
1404 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1405 __raw_writel(bank->context.leveldetect0,
1406 bank->base + bank->regs->leveldetect0);
1407 __raw_writel(bank->context.leveldetect1,
1408 bank->base + bank->regs->leveldetect1);
1409 __raw_writel(bank->context.risingdetect,
1410 bank->base + bank->regs->risingdetect);
1411 __raw_writel(bank->context.fallingdetect,
1412 bank->base + bank->regs->fallingdetect);
1413 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1414 __raw_writel(bank->context.dataout,
1415 bank->base + bank->regs->set_dataout);
1416 else
1417 __raw_writel(bank->context.dataout,
1418 bank->base + bank->regs->dataout);
1419 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1420
1421 if (bank->dbck_enable_mask) {
1422 __raw_writel(bank->context.debounce, bank->base +
1423 bank->regs->debounce);
1424 __raw_writel(bank->context.debounce_en,
1425 bank->base + bank->regs->debounce_en);
1426 }
1427
1428 __raw_writel(bank->context.irqenable1,
1429 bank->base + bank->regs->irqenable);
1430 __raw_writel(bank->context.irqenable2,
1431 bank->base + bank->regs->irqenable2);
1432 }
1433 #endif /* CONFIG_PM_RUNTIME */
1434 #else
1435 #define omap_gpio_suspend NULL
1436 #define omap_gpio_resume NULL
1437 #define omap_gpio_runtime_suspend NULL
1438 #define omap_gpio_runtime_resume NULL
1439 #endif
1440
1441 static const struct dev_pm_ops gpio_pm_ops = {
1442 SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1443 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1444 NULL)
1445 };
1446
1447 #if defined(CONFIG_OF)
1448 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1449 .revision = OMAP24XX_GPIO_REVISION,
1450 .direction = OMAP24XX_GPIO_OE,
1451 .datain = OMAP24XX_GPIO_DATAIN,
1452 .dataout = OMAP24XX_GPIO_DATAOUT,
1453 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1454 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1455 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1456 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1457 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1458 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1459 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1460 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1461 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1462 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1463 .ctrl = OMAP24XX_GPIO_CTRL,
1464 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1465 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1466 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1467 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1468 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1469 };
1470
1471 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1472 .revision = OMAP4_GPIO_REVISION,
1473 .direction = OMAP4_GPIO_OE,
1474 .datain = OMAP4_GPIO_DATAIN,
1475 .dataout = OMAP4_GPIO_DATAOUT,
1476 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1477 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1478 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1479 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1480 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1481 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1482 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1483 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1484 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1485 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1486 .ctrl = OMAP4_GPIO_CTRL,
1487 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1488 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1489 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1490 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1491 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1492 };
1493
1494 static struct omap_gpio_platform_data omap2_pdata = {
1495 .regs = &omap2_gpio_regs,
1496 .bank_width = 32,
1497 .dbck_flag = false,
1498 };
1499
1500 static struct omap_gpio_platform_data omap3_pdata = {
1501 .regs = &omap2_gpio_regs,
1502 .bank_width = 32,
1503 .dbck_flag = true,
1504 };
1505
1506 static struct omap_gpio_platform_data omap4_pdata = {
1507 .regs = &omap4_gpio_regs,
1508 .bank_width = 32,
1509 .dbck_flag = true,
1510 };
1511
1512 static const struct of_device_id omap_gpio_match[] = {
1513 {
1514 .compatible = "ti,omap4-gpio",
1515 .data = &omap4_pdata,
1516 },
1517 {
1518 .compatible = "ti,omap3-gpio",
1519 .data = &omap3_pdata,
1520 },
1521 {
1522 .compatible = "ti,omap2-gpio",
1523 .data = &omap2_pdata,
1524 },
1525 { },
1526 };
1527 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1528 #endif
1529
1530 static struct platform_driver omap_gpio_driver = {
1531 .probe = omap_gpio_probe,
1532 .driver = {
1533 .name = "omap_gpio",
1534 .pm = &gpio_pm_ops,
1535 .of_match_table = of_match_ptr(omap_gpio_match),
1536 },
1537 };
1538
1539 /*
1540 * gpio driver register needs to be done before
1541 * machine_init functions access gpio APIs.
1542 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1543 */
1544 static int __init omap_gpio_drv_reg(void)
1545 {
1546 return platform_driver_register(&omap_gpio_driver);
1547 }
1548 postcore_initcall(omap_gpio_drv_reg);
Linux kernel - Deliverables
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