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[deliverable/linux.git] / drivers / gpio / gpio-omap.c
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25
26 #include <mach/hardware.h>
27 #include <asm/irq.h>
28 #include <mach/irqs.h>
29 #include <asm/gpio.h>
30 #include <asm/mach/irq.h>
31
32 static LIST_HEAD(omap_gpio_list);
33
34 struct gpio_regs {
35 u32 irqenable1;
36 u32 irqenable2;
37 u32 wake_en;
38 u32 ctrl;
39 u32 oe;
40 u32 leveldetect0;
41 u32 leveldetect1;
42 u32 risingdetect;
43 u32 fallingdetect;
44 u32 dataout;
45 };
46
47 struct gpio_bank {
48 struct list_head node;
49 unsigned long pbase;
50 void __iomem *base;
51 u16 irq;
52 u16 virtual_irq_start;
53 u32 suspend_wakeup;
54 u32 saved_wakeup;
55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
58 u32 saved_datain;
59 u32 saved_fallingdetect;
60 u32 saved_risingdetect;
61 u32 level_mask;
62 u32 toggle_mask;
63 spinlock_t lock;
64 struct gpio_chip chip;
65 struct clk *dbck;
66 u32 mod_usage;
67 u32 dbck_enable_mask;
68 struct device *dev;
69 bool is_mpuio;
70 bool dbck_flag;
71 bool loses_context;
72 int stride;
73 u32 width;
74 int context_loss_count;
75 u16 id;
76
77 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
78 int (*get_context_loss_count)(struct device *dev);
79
80 struct omap_gpio_reg_offs *regs;
81 };
82
83 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
84 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
85 #define GPIO_MOD_CTRL_BIT BIT(0)
86
87 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
88 {
89 void __iomem *reg = bank->base;
90 u32 l;
91
92 reg += bank->regs->direction;
93 l = __raw_readl(reg);
94 if (is_input)
95 l |= 1 << gpio;
96 else
97 l &= ~(1 << gpio);
98 __raw_writel(l, reg);
99 }
100
101
102 /* set data out value using dedicate set/clear register */
103 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
104 {
105 void __iomem *reg = bank->base;
106 u32 l = GPIO_BIT(bank, gpio);
107
108 if (enable)
109 reg += bank->regs->set_dataout;
110 else
111 reg += bank->regs->clr_dataout;
112
113 __raw_writel(l, reg);
114 }
115
116 /* set data out value using mask register */
117 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
118 {
119 void __iomem *reg = bank->base + bank->regs->dataout;
120 u32 gpio_bit = GPIO_BIT(bank, gpio);
121 u32 l;
122
123 l = __raw_readl(reg);
124 if (enable)
125 l |= gpio_bit;
126 else
127 l &= ~gpio_bit;
128 __raw_writel(l, reg);
129 }
130
131 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
132 {
133 void __iomem *reg = bank->base + bank->regs->datain;
134
135 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
136 }
137
138 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
139 {
140 void __iomem *reg = bank->base + bank->regs->dataout;
141
142 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
143 }
144
145 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
146 {
147 int l = __raw_readl(base + reg);
148
149 if (set)
150 l |= mask;
151 else
152 l &= ~mask;
153
154 __raw_writel(l, base + reg);
155 }
156
157 /**
158 * _set_gpio_debounce - low level gpio debounce time
159 * @bank: the gpio bank we're acting upon
160 * @gpio: the gpio number on this @gpio
161 * @debounce: debounce time to use
162 *
163 * OMAP's debounce time is in 31us steps so we need
164 * to convert and round up to the closest unit.
165 */
166 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
167 unsigned debounce)
168 {
169 void __iomem *reg;
170 u32 val;
171 u32 l;
172
173 if (!bank->dbck_flag)
174 return;
175
176 if (debounce < 32)
177 debounce = 0x01;
178 else if (debounce > 7936)
179 debounce = 0xff;
180 else
181 debounce = (debounce / 0x1f) - 1;
182
183 l = GPIO_BIT(bank, gpio);
184
185 reg = bank->base + bank->regs->debounce;
186 __raw_writel(debounce, reg);
187
188 reg = bank->base + bank->regs->debounce_en;
189 val = __raw_readl(reg);
190
191 if (debounce) {
192 val |= l;
193 clk_enable(bank->dbck);
194 } else {
195 val &= ~l;
196 clk_disable(bank->dbck);
197 }
198 bank->dbck_enable_mask = val;
199
200 __raw_writel(val, reg);
201 }
202
203 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
204 int trigger)
205 {
206 void __iomem *base = bank->base;
207 u32 gpio_bit = 1 << gpio;
208
209 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
210 trigger & IRQ_TYPE_LEVEL_LOW);
211 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
212 trigger & IRQ_TYPE_LEVEL_HIGH);
213 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
214 trigger & IRQ_TYPE_EDGE_RISING);
215 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
216 trigger & IRQ_TYPE_EDGE_FALLING);
217
218 if (likely(!(bank->non_wakeup_gpios & gpio_bit)))
219 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
220
221 /* This part needs to be executed always for OMAP{34xx, 44xx} */
222 if (!bank->regs->irqctrl) {
223 /* On omap24xx proceed only when valid GPIO bit is set */
224 if (bank->non_wakeup_gpios) {
225 if (!(bank->non_wakeup_gpios & gpio_bit))
226 goto exit;
227 }
228
229 /*
230 * Log the edge gpio and manually trigger the IRQ
231 * after resume if the input level changes
232 * to avoid irq lost during PER RET/OFF mode
233 * Applies for omap2 non-wakeup gpio and all omap3 gpios
234 */
235 if (trigger & IRQ_TYPE_EDGE_BOTH)
236 bank->enabled_non_wakeup_gpios |= gpio_bit;
237 else
238 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
239 }
240
241 exit:
242 bank->level_mask =
243 __raw_readl(bank->base + bank->regs->leveldetect0) |
244 __raw_readl(bank->base + bank->regs->leveldetect1);
245 }
246
247 #ifdef CONFIG_ARCH_OMAP1
248 /*
249 * This only applies to chips that can't do both rising and falling edge
250 * detection at once. For all other chips, this function is a noop.
251 */
252 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
253 {
254 void __iomem *reg = bank->base;
255 u32 l = 0;
256
257 if (!bank->regs->irqctrl)
258 return;
259
260 reg += bank->regs->irqctrl;
261
262 l = __raw_readl(reg);
263 if ((l >> gpio) & 1)
264 l &= ~(1 << gpio);
265 else
266 l |= 1 << gpio;
267
268 __raw_writel(l, reg);
269 }
270 #else
271 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
272 #endif
273
274 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
275 {
276 void __iomem *reg = bank->base;
277 void __iomem *base = bank->base;
278 u32 l = 0;
279
280 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
281 set_gpio_trigger(bank, gpio, trigger);
282 } else if (bank->regs->irqctrl) {
283 reg += bank->regs->irqctrl;
284
285 l = __raw_readl(reg);
286 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
287 bank->toggle_mask |= 1 << gpio;
288 if (trigger & IRQ_TYPE_EDGE_RISING)
289 l |= 1 << gpio;
290 else if (trigger & IRQ_TYPE_EDGE_FALLING)
291 l &= ~(1 << gpio);
292 else
293 return -EINVAL;
294
295 __raw_writel(l, reg);
296 } else if (bank->regs->edgectrl1) {
297 if (gpio & 0x08)
298 reg += bank->regs->edgectrl2;
299 else
300 reg += bank->regs->edgectrl1;
301
302 gpio &= 0x07;
303 l = __raw_readl(reg);
304 l &= ~(3 << (gpio << 1));
305 if (trigger & IRQ_TYPE_EDGE_RISING)
306 l |= 2 << (gpio << 1);
307 if (trigger & IRQ_TYPE_EDGE_FALLING)
308 l |= 1 << (gpio << 1);
309
310 /* Enable wake-up during idle for dynamic tick */
311 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
312 __raw_writel(l, reg);
313 }
314 return 0;
315 }
316
317 static int gpio_irq_type(struct irq_data *d, unsigned type)
318 {
319 struct gpio_bank *bank;
320 unsigned gpio;
321 int retval;
322 unsigned long flags;
323
324 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
325 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
326 else
327 gpio = d->irq - IH_GPIO_BASE;
328
329 if (type & ~IRQ_TYPE_SENSE_MASK)
330 return -EINVAL;
331
332 bank = irq_data_get_irq_chip_data(d);
333
334 if (!bank->regs->leveldetect0 &&
335 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
336 return -EINVAL;
337
338 spin_lock_irqsave(&bank->lock, flags);
339 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
340 spin_unlock_irqrestore(&bank->lock, flags);
341
342 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
343 __irq_set_handler_locked(d->irq, handle_level_irq);
344 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
345 __irq_set_handler_locked(d->irq, handle_edge_irq);
346
347 return retval;
348 }
349
350 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
351 {
352 void __iomem *reg = bank->base;
353
354 reg += bank->regs->irqstatus;
355 __raw_writel(gpio_mask, reg);
356
357 /* Workaround for clearing DSP GPIO interrupts to allow retention */
358 if (bank->regs->irqstatus2) {
359 reg = bank->base + bank->regs->irqstatus2;
360 __raw_writel(gpio_mask, reg);
361 }
362
363 /* Flush posted write for the irq status to avoid spurious interrupts */
364 __raw_readl(reg);
365 }
366
367 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
368 {
369 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
370 }
371
372 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
373 {
374 void __iomem *reg = bank->base;
375 u32 l;
376 u32 mask = (1 << bank->width) - 1;
377
378 reg += bank->regs->irqenable;
379 l = __raw_readl(reg);
380 if (bank->regs->irqenable_inv)
381 l = ~l;
382 l &= mask;
383 return l;
384 }
385
386 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
387 {
388 void __iomem *reg = bank->base;
389 u32 l;
390
391 if (bank->regs->set_irqenable) {
392 reg += bank->regs->set_irqenable;
393 l = gpio_mask;
394 } else {
395 reg += bank->regs->irqenable;
396 l = __raw_readl(reg);
397 if (bank->regs->irqenable_inv)
398 l &= ~gpio_mask;
399 else
400 l |= gpio_mask;
401 }
402
403 __raw_writel(l, reg);
404 }
405
406 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
407 {
408 void __iomem *reg = bank->base;
409 u32 l;
410
411 if (bank->regs->clr_irqenable) {
412 reg += bank->regs->clr_irqenable;
413 l = gpio_mask;
414 } else {
415 reg += bank->regs->irqenable;
416 l = __raw_readl(reg);
417 if (bank->regs->irqenable_inv)
418 l |= gpio_mask;
419 else
420 l &= ~gpio_mask;
421 }
422
423 __raw_writel(l, reg);
424 }
425
426 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
427 {
428 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
429 }
430
431 /*
432 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
433 * 1510 does not seem to have a wake-up register. If JTAG is connected
434 * to the target, system will wake up always on GPIO events. While
435 * system is running all registered GPIO interrupts need to have wake-up
436 * enabled. When system is suspended, only selected GPIO interrupts need
437 * to have wake-up enabled.
438 */
439 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
440 {
441 u32 gpio_bit = GPIO_BIT(bank, gpio);
442 unsigned long flags;
443
444 if (bank->non_wakeup_gpios & gpio_bit) {
445 dev_err(bank->dev,
446 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
447 return -EINVAL;
448 }
449
450 spin_lock_irqsave(&bank->lock, flags);
451 if (enable)
452 bank->suspend_wakeup |= gpio_bit;
453 else
454 bank->suspend_wakeup &= ~gpio_bit;
455
456 spin_unlock_irqrestore(&bank->lock, flags);
457
458 return 0;
459 }
460
461 static void _reset_gpio(struct gpio_bank *bank, int gpio)
462 {
463 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
464 _set_gpio_irqenable(bank, gpio, 0);
465 _clear_gpio_irqstatus(bank, gpio);
466 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
467 }
468
469 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
470 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
471 {
472 unsigned int gpio = d->irq - IH_GPIO_BASE;
473 struct gpio_bank *bank;
474 int retval;
475
476 bank = irq_data_get_irq_chip_data(d);
477 retval = _set_gpio_wakeup(bank, gpio, enable);
478
479 return retval;
480 }
481
482 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
483 {
484 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
485 unsigned long flags;
486
487 /*
488 * If this is the first gpio_request for the bank,
489 * enable the bank module.
490 */
491 if (!bank->mod_usage)
492 pm_runtime_get_sync(bank->dev);
493
494 spin_lock_irqsave(&bank->lock, flags);
495 /* Set trigger to none. You need to enable the desired trigger with
496 * request_irq() or set_irq_type().
497 */
498 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
499
500 if (bank->regs->pinctrl) {
501 void __iomem *reg = bank->base + bank->regs->pinctrl;
502
503 /* Claim the pin for MPU */
504 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
505 }
506
507 if (bank->regs->ctrl && !bank->mod_usage) {
508 void __iomem *reg = bank->base + bank->regs->ctrl;
509 u32 ctrl;
510
511 ctrl = __raw_readl(reg);
512 /* Module is enabled, clocks are not gated */
513 ctrl &= ~GPIO_MOD_CTRL_BIT;
514 __raw_writel(ctrl, reg);
515 }
516
517 bank->mod_usage |= 1 << offset;
518
519 spin_unlock_irqrestore(&bank->lock, flags);
520
521 return 0;
522 }
523
524 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
525 {
526 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
527 void __iomem *base = bank->base;
528 unsigned long flags;
529
530 spin_lock_irqsave(&bank->lock, flags);
531
532 if (bank->regs->wkup_en)
533 /* Disable wake-up during idle for dynamic tick */
534 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
535
536 bank->mod_usage &= ~(1 << offset);
537
538 if (bank->regs->ctrl && !bank->mod_usage) {
539 void __iomem *reg = bank->base + bank->regs->ctrl;
540 u32 ctrl;
541
542 ctrl = __raw_readl(reg);
543 /* Module is disabled, clocks are gated */
544 ctrl |= GPIO_MOD_CTRL_BIT;
545 __raw_writel(ctrl, reg);
546 }
547
548 _reset_gpio(bank, bank->chip.base + offset);
549 spin_unlock_irqrestore(&bank->lock, flags);
550
551 /*
552 * If this is the last gpio to be freed in the bank,
553 * disable the bank module.
554 */
555 if (!bank->mod_usage)
556 pm_runtime_put(bank->dev);
557 }
558
559 /*
560 * We need to unmask the GPIO bank interrupt as soon as possible to
561 * avoid missing GPIO interrupts for other lines in the bank.
562 * Then we need to mask-read-clear-unmask the triggered GPIO lines
563 * in the bank to avoid missing nested interrupts for a GPIO line.
564 * If we wait to unmask individual GPIO lines in the bank after the
565 * line's interrupt handler has been run, we may miss some nested
566 * interrupts.
567 */
568 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
569 {
570 void __iomem *isr_reg = NULL;
571 u32 isr;
572 unsigned int gpio_irq, gpio_index;
573 struct gpio_bank *bank;
574 u32 retrigger = 0;
575 int unmasked = 0;
576 struct irq_chip *chip = irq_desc_get_chip(desc);
577
578 chained_irq_enter(chip, desc);
579
580 bank = irq_get_handler_data(irq);
581 isr_reg = bank->base + bank->regs->irqstatus;
582 pm_runtime_get_sync(bank->dev);
583
584 if (WARN_ON(!isr_reg))
585 goto exit;
586
587 while(1) {
588 u32 isr_saved, level_mask = 0;
589 u32 enabled;
590
591 enabled = _get_gpio_irqbank_mask(bank);
592 isr_saved = isr = __raw_readl(isr_reg) & enabled;
593
594 if (bank->level_mask)
595 level_mask = bank->level_mask & enabled;
596
597 /* clear edge sensitive interrupts before handler(s) are
598 called so that we don't miss any interrupt occurred while
599 executing them */
600 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
601 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
602 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
603
604 /* if there is only edge sensitive GPIO pin interrupts
605 configured, we could unmask GPIO bank interrupt immediately */
606 if (!level_mask && !unmasked) {
607 unmasked = 1;
608 chained_irq_exit(chip, desc);
609 }
610
611 isr |= retrigger;
612 retrigger = 0;
613 if (!isr)
614 break;
615
616 gpio_irq = bank->virtual_irq_start;
617 for (; isr != 0; isr >>= 1, gpio_irq++) {
618 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
619
620 if (!(isr & 1))
621 continue;
622
623 /*
624 * Some chips can't respond to both rising and falling
625 * at the same time. If this irq was requested with
626 * both flags, we need to flip the ICR data for the IRQ
627 * to respond to the IRQ for the opposite direction.
628 * This will be indicated in the bank toggle_mask.
629 */
630 if (bank->toggle_mask & (1 << gpio_index))
631 _toggle_gpio_edge_triggering(bank, gpio_index);
632
633 generic_handle_irq(gpio_irq);
634 }
635 }
636 /* if bank has any level sensitive GPIO pin interrupt
637 configured, we must unmask the bank interrupt only after
638 handler(s) are executed in order to avoid spurious bank
639 interrupt */
640 exit:
641 if (!unmasked)
642 chained_irq_exit(chip, desc);
643 pm_runtime_put(bank->dev);
644 }
645
646 static void gpio_irq_shutdown(struct irq_data *d)
647 {
648 unsigned int gpio = d->irq - IH_GPIO_BASE;
649 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
650 unsigned long flags;
651
652 spin_lock_irqsave(&bank->lock, flags);
653 _reset_gpio(bank, gpio);
654 spin_unlock_irqrestore(&bank->lock, flags);
655 }
656
657 static void gpio_ack_irq(struct irq_data *d)
658 {
659 unsigned int gpio = d->irq - IH_GPIO_BASE;
660 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
661
662 _clear_gpio_irqstatus(bank, gpio);
663 }
664
665 static void gpio_mask_irq(struct irq_data *d)
666 {
667 unsigned int gpio = d->irq - IH_GPIO_BASE;
668 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
669 unsigned long flags;
670
671 spin_lock_irqsave(&bank->lock, flags);
672 _set_gpio_irqenable(bank, gpio, 0);
673 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
674 spin_unlock_irqrestore(&bank->lock, flags);
675 }
676
677 static void gpio_unmask_irq(struct irq_data *d)
678 {
679 unsigned int gpio = d->irq - IH_GPIO_BASE;
680 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
681 unsigned int irq_mask = GPIO_BIT(bank, gpio);
682 u32 trigger = irqd_get_trigger_type(d);
683 unsigned long flags;
684
685 spin_lock_irqsave(&bank->lock, flags);
686 if (trigger)
687 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
688
689 /* For level-triggered GPIOs, the clearing must be done after
690 * the HW source is cleared, thus after the handler has run */
691 if (bank->level_mask & irq_mask) {
692 _set_gpio_irqenable(bank, gpio, 0);
693 _clear_gpio_irqstatus(bank, gpio);
694 }
695
696 _set_gpio_irqenable(bank, gpio, 1);
697 spin_unlock_irqrestore(&bank->lock, flags);
698 }
699
700 static struct irq_chip gpio_irq_chip = {
701 .name = "GPIO",
702 .irq_shutdown = gpio_irq_shutdown,
703 .irq_ack = gpio_ack_irq,
704 .irq_mask = gpio_mask_irq,
705 .irq_unmask = gpio_unmask_irq,
706 .irq_set_type = gpio_irq_type,
707 .irq_set_wake = gpio_wake_enable,
708 };
709
710 /*---------------------------------------------------------------------*/
711
712 static int omap_mpuio_suspend_noirq(struct device *dev)
713 {
714 struct platform_device *pdev = to_platform_device(dev);
715 struct gpio_bank *bank = platform_get_drvdata(pdev);
716 void __iomem *mask_reg = bank->base +
717 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
718 unsigned long flags;
719
720 spin_lock_irqsave(&bank->lock, flags);
721 bank->saved_wakeup = __raw_readl(mask_reg);
722 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
723 spin_unlock_irqrestore(&bank->lock, flags);
724
725 return 0;
726 }
727
728 static int omap_mpuio_resume_noirq(struct device *dev)
729 {
730 struct platform_device *pdev = to_platform_device(dev);
731 struct gpio_bank *bank = platform_get_drvdata(pdev);
732 void __iomem *mask_reg = bank->base +
733 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
734 unsigned long flags;
735
736 spin_lock_irqsave(&bank->lock, flags);
737 __raw_writel(bank->saved_wakeup, mask_reg);
738 spin_unlock_irqrestore(&bank->lock, flags);
739
740 return 0;
741 }
742
743 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
744 .suspend_noirq = omap_mpuio_suspend_noirq,
745 .resume_noirq = omap_mpuio_resume_noirq,
746 };
747
748 /* use platform_driver for this. */
749 static struct platform_driver omap_mpuio_driver = {
750 .driver = {
751 .name = "mpuio",
752 .pm = &omap_mpuio_dev_pm_ops,
753 },
754 };
755
756 static struct platform_device omap_mpuio_device = {
757 .name = "mpuio",
758 .id = -1,
759 .dev = {
760 .driver = &omap_mpuio_driver.driver,
761 }
762 /* could list the /proc/iomem resources */
763 };
764
765 static inline void mpuio_init(struct gpio_bank *bank)
766 {
767 platform_set_drvdata(&omap_mpuio_device, bank);
768
769 if (platform_driver_register(&omap_mpuio_driver) == 0)
770 (void) platform_device_register(&omap_mpuio_device);
771 }
772
773 /*---------------------------------------------------------------------*/
774
775 static int gpio_input(struct gpio_chip *chip, unsigned offset)
776 {
777 struct gpio_bank *bank;
778 unsigned long flags;
779
780 bank = container_of(chip, struct gpio_bank, chip);
781 spin_lock_irqsave(&bank->lock, flags);
782 _set_gpio_direction(bank, offset, 1);
783 spin_unlock_irqrestore(&bank->lock, flags);
784 return 0;
785 }
786
787 static int gpio_is_input(struct gpio_bank *bank, int mask)
788 {
789 void __iomem *reg = bank->base + bank->regs->direction;
790
791 return __raw_readl(reg) & mask;
792 }
793
794 static int gpio_get(struct gpio_chip *chip, unsigned offset)
795 {
796 struct gpio_bank *bank;
797 void __iomem *reg;
798 int gpio;
799 u32 mask;
800
801 gpio = chip->base + offset;
802 bank = container_of(chip, struct gpio_bank, chip);
803 reg = bank->base;
804 mask = GPIO_BIT(bank, gpio);
805
806 if (gpio_is_input(bank, mask))
807 return _get_gpio_datain(bank, gpio);
808 else
809 return _get_gpio_dataout(bank, gpio);
810 }
811
812 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
813 {
814 struct gpio_bank *bank;
815 unsigned long flags;
816
817 bank = container_of(chip, struct gpio_bank, chip);
818 spin_lock_irqsave(&bank->lock, flags);
819 bank->set_dataout(bank, offset, value);
820 _set_gpio_direction(bank, offset, 0);
821 spin_unlock_irqrestore(&bank->lock, flags);
822 return 0;
823 }
824
825 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
826 unsigned debounce)
827 {
828 struct gpio_bank *bank;
829 unsigned long flags;
830
831 bank = container_of(chip, struct gpio_bank, chip);
832
833 if (!bank->dbck) {
834 bank->dbck = clk_get(bank->dev, "dbclk");
835 if (IS_ERR(bank->dbck))
836 dev_err(bank->dev, "Could not get gpio dbck\n");
837 }
838
839 spin_lock_irqsave(&bank->lock, flags);
840 _set_gpio_debounce(bank, offset, debounce);
841 spin_unlock_irqrestore(&bank->lock, flags);
842
843 return 0;
844 }
845
846 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
847 {
848 struct gpio_bank *bank;
849 unsigned long flags;
850
851 bank = container_of(chip, struct gpio_bank, chip);
852 spin_lock_irqsave(&bank->lock, flags);
853 bank->set_dataout(bank, offset, value);
854 spin_unlock_irqrestore(&bank->lock, flags);
855 }
856
857 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
858 {
859 struct gpio_bank *bank;
860
861 bank = container_of(chip, struct gpio_bank, chip);
862 return bank->virtual_irq_start + offset;
863 }
864
865 /*---------------------------------------------------------------------*/
866
867 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
868 {
869 static bool called;
870 u32 rev;
871
872 if (called || bank->regs->revision == USHRT_MAX)
873 return;
874
875 rev = __raw_readw(bank->base + bank->regs->revision);
876 pr_info("OMAP GPIO hardware version %d.%d\n",
877 (rev >> 4) & 0x0f, rev & 0x0f);
878
879 called = true;
880 }
881
882 /* This lock class tells lockdep that GPIO irqs are in a different
883 * category than their parents, so it won't report false recursion.
884 */
885 static struct lock_class_key gpio_lock_class;
886
887 static void omap_gpio_mod_init(struct gpio_bank *bank)
888 {
889 void __iomem *base = bank->base;
890 u32 l = 0xffffffff;
891
892 if (bank->width == 16)
893 l = 0xffff;
894
895 if (bank->is_mpuio) {
896 __raw_writel(l, bank->base + bank->regs->irqenable);
897 return;
898 }
899
900 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
901 _gpio_rmw(base, bank->regs->irqstatus, l,
902 bank->regs->irqenable_inv == false);
903 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
904 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
905 if (bank->regs->debounce_en)
906 _gpio_rmw(base, bank->regs->debounce_en, 0, 1);
907
908 /* Initialize interface clk ungated, module enabled */
909 if (bank->regs->ctrl)
910 _gpio_rmw(base, bank->regs->ctrl, 0, 1);
911 }
912
913 static __init void
914 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
915 unsigned int num)
916 {
917 struct irq_chip_generic *gc;
918 struct irq_chip_type *ct;
919
920 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
921 handle_simple_irq);
922 if (!gc) {
923 dev_err(bank->dev, "Memory alloc failed for gc\n");
924 return;
925 }
926
927 ct = gc->chip_types;
928
929 /* NOTE: No ack required, reading IRQ status clears it. */
930 ct->chip.irq_mask = irq_gc_mask_set_bit;
931 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
932 ct->chip.irq_set_type = gpio_irq_type;
933
934 if (bank->regs->wkup_en)
935 ct->chip.irq_set_wake = gpio_wake_enable,
936
937 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
938 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
939 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
940 }
941
942 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
943 {
944 int j;
945 static int gpio;
946
947 /*
948 * REVISIT eventually switch from OMAP-specific gpio structs
949 * over to the generic ones
950 */
951 bank->chip.request = omap_gpio_request;
952 bank->chip.free = omap_gpio_free;
953 bank->chip.direction_input = gpio_input;
954 bank->chip.get = gpio_get;
955 bank->chip.direction_output = gpio_output;
956 bank->chip.set_debounce = gpio_debounce;
957 bank->chip.set = gpio_set;
958 bank->chip.to_irq = gpio_2irq;
959 if (bank->is_mpuio) {
960 bank->chip.label = "mpuio";
961 if (bank->regs->wkup_en)
962 bank->chip.dev = &omap_mpuio_device.dev;
963 bank->chip.base = OMAP_MPUIO(0);
964 } else {
965 bank->chip.label = "gpio";
966 bank->chip.base = gpio;
967 gpio += bank->width;
968 }
969 bank->chip.ngpio = bank->width;
970
971 gpiochip_add(&bank->chip);
972
973 for (j = bank->virtual_irq_start;
974 j < bank->virtual_irq_start + bank->width; j++) {
975 irq_set_lockdep_class(j, &gpio_lock_class);
976 irq_set_chip_data(j, bank);
977 if (bank->is_mpuio) {
978 omap_mpuio_alloc_gc(bank, j, bank->width);
979 } else {
980 irq_set_chip(j, &gpio_irq_chip);
981 irq_set_handler(j, handle_simple_irq);
982 set_irq_flags(j, IRQF_VALID);
983 }
984 }
985 irq_set_chained_handler(bank->irq, gpio_irq_handler);
986 irq_set_handler_data(bank->irq, bank);
987 }
988
989 static int __devinit omap_gpio_probe(struct platform_device *pdev)
990 {
991 struct omap_gpio_platform_data *pdata;
992 struct resource *res;
993 struct gpio_bank *bank;
994 int ret = 0;
995
996 if (!pdev->dev.platform_data) {
997 ret = -EINVAL;
998 goto err_exit;
999 }
1000
1001 bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
1002 if (!bank) {
1003 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1004 ret = -ENOMEM;
1005 goto err_exit;
1006 }
1007
1008 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1009 if (unlikely(!res)) {
1010 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
1011 pdev->id);
1012 ret = -ENODEV;
1013 goto err_free;
1014 }
1015
1016 bank->irq = res->start;
1017 bank->id = pdev->id;
1018
1019 pdata = pdev->dev.platform_data;
1020 bank->virtual_irq_start = pdata->virtual_irq_start;
1021 bank->dev = &pdev->dev;
1022 bank->dbck_flag = pdata->dbck_flag;
1023 bank->stride = pdata->bank_stride;
1024 bank->width = pdata->bank_width;
1025 bank->is_mpuio = pdata->is_mpuio;
1026 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1027 bank->loses_context = pdata->loses_context;
1028 bank->get_context_loss_count = pdata->get_context_loss_count;
1029 bank->regs = pdata->regs;
1030
1031 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1032 bank->set_dataout = _set_gpio_dataout_reg;
1033 else
1034 bank->set_dataout = _set_gpio_dataout_mask;
1035
1036 spin_lock_init(&bank->lock);
1037
1038 /* Static mapping, never released */
1039 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1040 if (unlikely(!res)) {
1041 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
1042 pdev->id);
1043 ret = -ENODEV;
1044 goto err_free;
1045 }
1046
1047 bank->base = ioremap(res->start, resource_size(res));
1048 if (!bank->base) {
1049 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
1050 pdev->id);
1051 ret = -ENOMEM;
1052 goto err_free;
1053 }
1054
1055 pm_runtime_enable(bank->dev);
1056 pm_runtime_irq_safe(bank->dev);
1057 pm_runtime_get_sync(bank->dev);
1058
1059 if (bank->is_mpuio)
1060 mpuio_init(bank);
1061
1062 omap_gpio_mod_init(bank);
1063 omap_gpio_chip_init(bank);
1064 omap_gpio_show_rev(bank);
1065
1066 pm_runtime_put(bank->dev);
1067
1068 list_add_tail(&bank->node, &omap_gpio_list);
1069
1070 return ret;
1071
1072 err_free:
1073 kfree(bank);
1074 err_exit:
1075 return ret;
1076 }
1077
1078 #ifdef CONFIG_ARCH_OMAP2PLUS
1079
1080 #if defined(CONFIG_PM_SLEEP)
1081 static int omap_gpio_suspend(struct device *dev)
1082 {
1083 struct gpio_bank *bank;
1084
1085 list_for_each_entry(bank, &omap_gpio_list, node) {
1086 void __iomem *base = bank->base;
1087 void __iomem *wake_status;
1088 unsigned long flags;
1089
1090 if (!bank->regs->wkup_en)
1091 return 0;
1092
1093 wake_status = bank->base + bank->regs->wkup_en;
1094
1095 spin_lock_irqsave(&bank->lock, flags);
1096 bank->saved_wakeup = __raw_readl(wake_status);
1097 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1098 _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
1099 spin_unlock_irqrestore(&bank->lock, flags);
1100 }
1101
1102 return 0;
1103 }
1104
1105 static int omap_gpio_resume(struct device *dev)
1106 {
1107 struct gpio_bank *bank;
1108
1109 list_for_each_entry(bank, &omap_gpio_list, node) {
1110 void __iomem *base = bank->base;
1111 unsigned long flags;
1112
1113 if (!bank->regs->wkup_en)
1114 return 0;
1115
1116 spin_lock_irqsave(&bank->lock, flags);
1117 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1118 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
1119 spin_unlock_irqrestore(&bank->lock, flags);
1120 }
1121
1122 return 0;
1123 }
1124 #endif /* CONFIG_PM_SLEEP */
1125
1126 static void omap_gpio_save_context(struct gpio_bank *bank);
1127 static void omap_gpio_restore_context(struct gpio_bank *bank);
1128
1129 void omap2_gpio_prepare_for_idle(int off_mode)
1130 {
1131 struct gpio_bank *bank;
1132
1133 list_for_each_entry(bank, &omap_gpio_list, node) {
1134 u32 l1 = 0, l2 = 0;
1135 int j;
1136
1137 if (!bank->loses_context)
1138 continue;
1139
1140 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1141 clk_disable(bank->dbck);
1142
1143 if (!off_mode)
1144 continue;
1145
1146 /* If going to OFF, remove triggering for all
1147 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1148 * generated. See OMAP2420 Errata item 1.101. */
1149 if (!(bank->enabled_non_wakeup_gpios))
1150 goto save_gpio_context;
1151
1152 bank->saved_datain = __raw_readl(bank->base +
1153 bank->regs->datain);
1154 l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
1155 l2 = __raw_readl(bank->base + bank->regs->risingdetect);
1156
1157 bank->saved_fallingdetect = l1;
1158 bank->saved_risingdetect = l2;
1159 l1 &= ~bank->enabled_non_wakeup_gpios;
1160 l2 &= ~bank->enabled_non_wakeup_gpios;
1161
1162 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1163 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1164
1165 save_gpio_context:
1166
1167 if (bank->get_context_loss_count)
1168 bank->context_loss_count =
1169 bank->get_context_loss_count(bank->dev);
1170
1171 omap_gpio_save_context(bank);
1172
1173 if (!pm_runtime_suspended(bank->dev))
1174 pm_runtime_put(bank->dev);
1175 }
1176 }
1177
1178 void omap2_gpio_resume_after_idle(void)
1179 {
1180 struct gpio_bank *bank;
1181
1182 list_for_each_entry(bank, &omap_gpio_list, node) {
1183 int context_lost_cnt_after;
1184 u32 l = 0, gen, gen0, gen1;
1185 int j;
1186
1187 if (!bank->loses_context)
1188 continue;
1189
1190 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1191 clk_enable(bank->dbck);
1192
1193 if (pm_runtime_suspended(bank->dev))
1194 pm_runtime_get_sync(bank->dev);
1195
1196 if (bank->get_context_loss_count) {
1197 context_lost_cnt_after =
1198 bank->get_context_loss_count(bank->dev);
1199 if (context_lost_cnt_after != bank->context_loss_count
1200 || !context_lost_cnt_after)
1201 omap_gpio_restore_context(bank);
1202 }
1203
1204 if (!(bank->enabled_non_wakeup_gpios))
1205 continue;
1206
1207 __raw_writel(bank->saved_fallingdetect,
1208 bank->base + bank->regs->fallingdetect);
1209 __raw_writel(bank->saved_risingdetect,
1210 bank->base + bank->regs->risingdetect);
1211 l = __raw_readl(bank->base + bank->regs->datain);
1212
1213 /* Check if any of the non-wakeup interrupt GPIOs have changed
1214 * state. If so, generate an IRQ by software. This is
1215 * horribly racy, but it's the best we can do to work around
1216 * this silicon bug. */
1217 l ^= bank->saved_datain;
1218 l &= bank->enabled_non_wakeup_gpios;
1219
1220 /*
1221 * No need to generate IRQs for the rising edge for gpio IRQs
1222 * configured with falling edge only; and vice versa.
1223 */
1224 gen0 = l & bank->saved_fallingdetect;
1225 gen0 &= bank->saved_datain;
1226
1227 gen1 = l & bank->saved_risingdetect;
1228 gen1 &= ~(bank->saved_datain);
1229
1230 /* FIXME: Consider GPIO IRQs with level detections properly! */
1231 gen = l & (~(bank->saved_fallingdetect) &
1232 ~(bank->saved_risingdetect));
1233 /* Consider all GPIO IRQs needed to be updated */
1234 gen |= gen0 | gen1;
1235
1236 if (gen) {
1237 u32 old0, old1;
1238
1239 old0 = __raw_readl(bank->base +
1240 bank->regs->leveldetect0);
1241 old1 = __raw_readl(bank->base +
1242 bank->regs->leveldetect1);
1243
1244 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1245 old0 |= gen;
1246 old1 |= gen;
1247 }
1248
1249 if (cpu_is_omap44xx()) {
1250 old0 |= l;
1251 old1 |= l;
1252 }
1253 __raw_writel(old0, bank->base +
1254 bank->regs->leveldetect0);
1255 __raw_writel(old1, bank->base +
1256 bank->regs->leveldetect1);
1257 }
1258 }
1259 }
1260
1261 static void omap_gpio_save_context(struct gpio_bank *bank)
1262 {
1263 bank->context.irqenable1 =
1264 __raw_readl(bank->base + bank->regs->irqenable);
1265 bank->context.irqenable2 =
1266 __raw_readl(bank->base + bank->regs->irqenable2);
1267 bank->context.wake_en =
1268 __raw_readl(bank->base + bank->regs->wkup_en);
1269 bank->context.ctrl = __raw_readl(bank->base + bank->regs->ctrl);
1270 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
1271 bank->context.leveldetect0 =
1272 __raw_readl(bank->base + bank->regs->leveldetect0);
1273 bank->context.leveldetect1 =
1274 __raw_readl(bank->base + bank->regs->leveldetect1);
1275 bank->context.risingdetect =
1276 __raw_readl(bank->base + bank->regs->risingdetect);
1277 bank->context.fallingdetect =
1278 __raw_readl(bank->base + bank->regs->fallingdetect);
1279 bank->context.dataout = __raw_readl(bank->base + bank->regs->dataout);
1280 }
1281
1282 static void omap_gpio_restore_context(struct gpio_bank *bank)
1283 {
1284 __raw_writel(bank->context.irqenable1,
1285 bank->base + bank->regs->irqenable);
1286 __raw_writel(bank->context.irqenable2,
1287 bank->base + bank->regs->irqenable2);
1288 __raw_writel(bank->context.wake_en,
1289 bank->base + bank->regs->wkup_en);
1290 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1291 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1292 __raw_writel(bank->context.leveldetect0,
1293 bank->base + bank->regs->leveldetect0);
1294 __raw_writel(bank->context.leveldetect1,
1295 bank->base + bank->regs->leveldetect1);
1296 __raw_writel(bank->context.risingdetect,
1297 bank->base + bank->regs->risingdetect);
1298 __raw_writel(bank->context.fallingdetect,
1299 bank->base + bank->regs->fallingdetect);
1300 __raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
1301 }
1302 #else
1303 #define omap_gpio_suspend NULL
1304 #define omap_gpio_resume NULL
1305 #endif
1306
1307 static const struct dev_pm_ops gpio_pm_ops = {
1308 SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1309 };
1310
1311 static struct platform_driver omap_gpio_driver = {
1312 .probe = omap_gpio_probe,
1313 .driver = {
1314 .name = "omap_gpio",
1315 .pm = &gpio_pm_ops,
1316 },
1317 };
1318
1319 /*
1320 * gpio driver register needs to be done before
1321 * machine_init functions access gpio APIs.
1322 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1323 */
1324 static int __init omap_gpio_drv_reg(void)
1325 {
1326 return platform_driver_register(&omap_gpio_driver);
1327 }
1328 postcore_initcall(omap_gpio_drv_reg);
Linux kernel - Deliverables
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