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gpio/omap: remove saved_wakeup field from struct gpio_bank
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/irqdomain.h>
28
29 #include <mach/hardware.h>
30 #include <asm/irq.h>
31 #include <mach/irqs.h>
32 #include <asm/gpio.h>
33 #include <asm/mach/irq.h>
34
35 #define OFF_MODE 1
36
37 static LIST_HEAD(omap_gpio_list);
38
39 struct gpio_regs {
40 u32 irqenable1;
41 u32 irqenable2;
42 u32 wake_en;
43 u32 ctrl;
44 u32 oe;
45 u32 leveldetect0;
46 u32 leveldetect1;
47 u32 risingdetect;
48 u32 fallingdetect;
49 u32 dataout;
50 u32 debounce;
51 u32 debounce_en;
52 };
53
54 struct gpio_bank {
55 struct list_head node;
56 void __iomem *base;
57 u16 irq;
58 int irq_base;
59 struct irq_domain *domain;
60 u32 non_wakeup_gpios;
61 u32 enabled_non_wakeup_gpios;
62 struct gpio_regs context;
63 u32 saved_datain;
64 u32 level_mask;
65 u32 toggle_mask;
66 spinlock_t lock;
67 struct gpio_chip chip;
68 struct clk *dbck;
69 u32 mod_usage;
70 u32 dbck_enable_mask;
71 bool dbck_enabled;
72 struct device *dev;
73 bool is_mpuio;
74 bool dbck_flag;
75 bool loses_context;
76 int stride;
77 u32 width;
78 int context_loss_count;
79 int power_mode;
80 bool workaround_enabled;
81
82 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
83 int (*get_context_loss_count)(struct device *dev);
84
85 struct omap_gpio_reg_offs *regs;
86 };
87
88 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
89 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
90 #define GPIO_MOD_CTRL_BIT BIT(0)
91
92 static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
93 {
94 return gpio_irq - bank->irq_base + bank->chip.base;
95 }
96
97 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
98 {
99 void __iomem *reg = bank->base;
100 u32 l;
101
102 reg += bank->regs->direction;
103 l = __raw_readl(reg);
104 if (is_input)
105 l |= 1 << gpio;
106 else
107 l &= ~(1 << gpio);
108 __raw_writel(l, reg);
109 bank->context.oe = l;
110 }
111
112
113 /* set data out value using dedicate set/clear register */
114 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
115 {
116 void __iomem *reg = bank->base;
117 u32 l = GPIO_BIT(bank, gpio);
118
119 if (enable) {
120 reg += bank->regs->set_dataout;
121 bank->context.dataout |= l;
122 } else {
123 reg += bank->regs->clr_dataout;
124 bank->context.dataout &= ~l;
125 }
126
127 __raw_writel(l, reg);
128 }
129
130 /* set data out value using mask register */
131 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
132 {
133 void __iomem *reg = bank->base + bank->regs->dataout;
134 u32 gpio_bit = GPIO_BIT(bank, gpio);
135 u32 l;
136
137 l = __raw_readl(reg);
138 if (enable)
139 l |= gpio_bit;
140 else
141 l &= ~gpio_bit;
142 __raw_writel(l, reg);
143 bank->context.dataout = l;
144 }
145
146 static int _get_gpio_datain(struct gpio_bank *bank, int offset)
147 {
148 void __iomem *reg = bank->base + bank->regs->datain;
149
150 return (__raw_readl(reg) & (1 << offset)) != 0;
151 }
152
153 static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
154 {
155 void __iomem *reg = bank->base + bank->regs->dataout;
156
157 return (__raw_readl(reg) & (1 << offset)) != 0;
158 }
159
160 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
161 {
162 int l = __raw_readl(base + reg);
163
164 if (set)
165 l |= mask;
166 else
167 l &= ~mask;
168
169 __raw_writel(l, base + reg);
170 }
171
172 static inline void _gpio_dbck_enable(struct gpio_bank *bank)
173 {
174 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
175 clk_enable(bank->dbck);
176 bank->dbck_enabled = true;
177 }
178 }
179
180 static inline void _gpio_dbck_disable(struct gpio_bank *bank)
181 {
182 if (bank->dbck_enable_mask && bank->dbck_enabled) {
183 clk_disable(bank->dbck);
184 bank->dbck_enabled = false;
185 }
186 }
187
188 /**
189 * _set_gpio_debounce - low level gpio debounce time
190 * @bank: the gpio bank we're acting upon
191 * @gpio: the gpio number on this @gpio
192 * @debounce: debounce time to use
193 *
194 * OMAP's debounce time is in 31us steps so we need
195 * to convert and round up to the closest unit.
196 */
197 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
198 unsigned debounce)
199 {
200 void __iomem *reg;
201 u32 val;
202 u32 l;
203
204 if (!bank->dbck_flag)
205 return;
206
207 if (debounce < 32)
208 debounce = 0x01;
209 else if (debounce > 7936)
210 debounce = 0xff;
211 else
212 debounce = (debounce / 0x1f) - 1;
213
214 l = GPIO_BIT(bank, gpio);
215
216 clk_enable(bank->dbck);
217 reg = bank->base + bank->regs->debounce;
218 __raw_writel(debounce, reg);
219
220 reg = bank->base + bank->regs->debounce_en;
221 val = __raw_readl(reg);
222
223 if (debounce)
224 val |= l;
225 else
226 val &= ~l;
227 bank->dbck_enable_mask = val;
228
229 __raw_writel(val, reg);
230 clk_disable(bank->dbck);
231 /*
232 * Enable debounce clock per module.
233 * This call is mandatory because in omap_gpio_request() when
234 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
235 * runtime callbck fails to turn on dbck because dbck_enable_mask
236 * used within _gpio_dbck_enable() is still not initialized at
237 * that point. Therefore we have to enable dbck here.
238 */
239 _gpio_dbck_enable(bank);
240 if (bank->dbck_enable_mask) {
241 bank->context.debounce = debounce;
242 bank->context.debounce_en = val;
243 }
244 }
245
246 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
247 unsigned trigger)
248 {
249 void __iomem *base = bank->base;
250 u32 gpio_bit = 1 << gpio;
251
252 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
253 trigger & IRQ_TYPE_LEVEL_LOW);
254 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
255 trigger & IRQ_TYPE_LEVEL_HIGH);
256 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
257 trigger & IRQ_TYPE_EDGE_RISING);
258 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
259 trigger & IRQ_TYPE_EDGE_FALLING);
260
261 bank->context.leveldetect0 =
262 __raw_readl(bank->base + bank->regs->leveldetect0);
263 bank->context.leveldetect1 =
264 __raw_readl(bank->base + bank->regs->leveldetect1);
265 bank->context.risingdetect =
266 __raw_readl(bank->base + bank->regs->risingdetect);
267 bank->context.fallingdetect =
268 __raw_readl(bank->base + bank->regs->fallingdetect);
269
270 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
271 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
272 bank->context.wake_en =
273 __raw_readl(bank->base + bank->regs->wkup_en);
274 }
275
276 /* This part needs to be executed always for OMAP{34xx, 44xx} */
277 if (!bank->regs->irqctrl) {
278 /* On omap24xx proceed only when valid GPIO bit is set */
279 if (bank->non_wakeup_gpios) {
280 if (!(bank->non_wakeup_gpios & gpio_bit))
281 goto exit;
282 }
283
284 /*
285 * Log the edge gpio and manually trigger the IRQ
286 * after resume if the input level changes
287 * to avoid irq lost during PER RET/OFF mode
288 * Applies for omap2 non-wakeup gpio and all omap3 gpios
289 */
290 if (trigger & IRQ_TYPE_EDGE_BOTH)
291 bank->enabled_non_wakeup_gpios |= gpio_bit;
292 else
293 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
294 }
295
296 exit:
297 bank->level_mask =
298 __raw_readl(bank->base + bank->regs->leveldetect0) |
299 __raw_readl(bank->base + bank->regs->leveldetect1);
300 }
301
302 #ifdef CONFIG_ARCH_OMAP1
303 /*
304 * This only applies to chips that can't do both rising and falling edge
305 * detection at once. For all other chips, this function is a noop.
306 */
307 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
308 {
309 void __iomem *reg = bank->base;
310 u32 l = 0;
311
312 if (!bank->regs->irqctrl)
313 return;
314
315 reg += bank->regs->irqctrl;
316
317 l = __raw_readl(reg);
318 if ((l >> gpio) & 1)
319 l &= ~(1 << gpio);
320 else
321 l |= 1 << gpio;
322
323 __raw_writel(l, reg);
324 }
325 #else
326 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
327 #endif
328
329 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
330 unsigned trigger)
331 {
332 void __iomem *reg = bank->base;
333 void __iomem *base = bank->base;
334 u32 l = 0;
335
336 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
337 set_gpio_trigger(bank, gpio, trigger);
338 } else if (bank->regs->irqctrl) {
339 reg += bank->regs->irqctrl;
340
341 l = __raw_readl(reg);
342 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
343 bank->toggle_mask |= 1 << gpio;
344 if (trigger & IRQ_TYPE_EDGE_RISING)
345 l |= 1 << gpio;
346 else if (trigger & IRQ_TYPE_EDGE_FALLING)
347 l &= ~(1 << gpio);
348 else
349 return -EINVAL;
350
351 __raw_writel(l, reg);
352 } else if (bank->regs->edgectrl1) {
353 if (gpio & 0x08)
354 reg += bank->regs->edgectrl2;
355 else
356 reg += bank->regs->edgectrl1;
357
358 gpio &= 0x07;
359 l = __raw_readl(reg);
360 l &= ~(3 << (gpio << 1));
361 if (trigger & IRQ_TYPE_EDGE_RISING)
362 l |= 2 << (gpio << 1);
363 if (trigger & IRQ_TYPE_EDGE_FALLING)
364 l |= 1 << (gpio << 1);
365
366 /* Enable wake-up during idle for dynamic tick */
367 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
368 bank->context.wake_en =
369 __raw_readl(bank->base + bank->regs->wkup_en);
370 __raw_writel(l, reg);
371 }
372 return 0;
373 }
374
375 static int gpio_irq_type(struct irq_data *d, unsigned type)
376 {
377 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
378 unsigned gpio;
379 int retval;
380 unsigned long flags;
381
382 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
383 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
384 else
385 gpio = irq_to_gpio(bank, d->irq);
386
387 if (type & ~IRQ_TYPE_SENSE_MASK)
388 return -EINVAL;
389
390 if (!bank->regs->leveldetect0 &&
391 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
392 return -EINVAL;
393
394 spin_lock_irqsave(&bank->lock, flags);
395 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
396 spin_unlock_irqrestore(&bank->lock, flags);
397
398 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
399 __irq_set_handler_locked(d->irq, handle_level_irq);
400 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
401 __irq_set_handler_locked(d->irq, handle_edge_irq);
402
403 return retval;
404 }
405
406 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
407 {
408 void __iomem *reg = bank->base;
409
410 reg += bank->regs->irqstatus;
411 __raw_writel(gpio_mask, reg);
412
413 /* Workaround for clearing DSP GPIO interrupts to allow retention */
414 if (bank->regs->irqstatus2) {
415 reg = bank->base + bank->regs->irqstatus2;
416 __raw_writel(gpio_mask, reg);
417 }
418
419 /* Flush posted write for the irq status to avoid spurious interrupts */
420 __raw_readl(reg);
421 }
422
423 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
424 {
425 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
426 }
427
428 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
429 {
430 void __iomem *reg = bank->base;
431 u32 l;
432 u32 mask = (1 << bank->width) - 1;
433
434 reg += bank->regs->irqenable;
435 l = __raw_readl(reg);
436 if (bank->regs->irqenable_inv)
437 l = ~l;
438 l &= mask;
439 return l;
440 }
441
442 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
443 {
444 void __iomem *reg = bank->base;
445 u32 l;
446
447 if (bank->regs->set_irqenable) {
448 reg += bank->regs->set_irqenable;
449 l = gpio_mask;
450 bank->context.irqenable1 |= gpio_mask;
451 } else {
452 reg += bank->regs->irqenable;
453 l = __raw_readl(reg);
454 if (bank->regs->irqenable_inv)
455 l &= ~gpio_mask;
456 else
457 l |= gpio_mask;
458 bank->context.irqenable1 = l;
459 }
460
461 __raw_writel(l, reg);
462 }
463
464 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
465 {
466 void __iomem *reg = bank->base;
467 u32 l;
468
469 if (bank->regs->clr_irqenable) {
470 reg += bank->regs->clr_irqenable;
471 l = gpio_mask;
472 bank->context.irqenable1 &= ~gpio_mask;
473 } else {
474 reg += bank->regs->irqenable;
475 l = __raw_readl(reg);
476 if (bank->regs->irqenable_inv)
477 l |= gpio_mask;
478 else
479 l &= ~gpio_mask;
480 bank->context.irqenable1 = l;
481 }
482
483 __raw_writel(l, reg);
484 }
485
486 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
487 {
488 if (enable)
489 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
490 else
491 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
492 }
493
494 /*
495 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
496 * 1510 does not seem to have a wake-up register. If JTAG is connected
497 * to the target, system will wake up always on GPIO events. While
498 * system is running all registered GPIO interrupts need to have wake-up
499 * enabled. When system is suspended, only selected GPIO interrupts need
500 * to have wake-up enabled.
501 */
502 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
503 {
504 u32 gpio_bit = GPIO_BIT(bank, gpio);
505 unsigned long flags;
506
507 if (bank->non_wakeup_gpios & gpio_bit) {
508 dev_err(bank->dev,
509 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
510 return -EINVAL;
511 }
512
513 spin_lock_irqsave(&bank->lock, flags);
514 if (enable)
515 bank->context.wake_en |= gpio_bit;
516 else
517 bank->context.wake_en &= ~gpio_bit;
518
519 __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
520 spin_unlock_irqrestore(&bank->lock, flags);
521
522 return 0;
523 }
524
525 static void _reset_gpio(struct gpio_bank *bank, int gpio)
526 {
527 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
528 _set_gpio_irqenable(bank, gpio, 0);
529 _clear_gpio_irqstatus(bank, gpio);
530 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
531 }
532
533 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
534 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
535 {
536 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
537 unsigned int gpio = irq_to_gpio(bank, d->irq);
538
539 return _set_gpio_wakeup(bank, gpio, enable);
540 }
541
542 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
543 {
544 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
545 unsigned long flags;
546
547 /*
548 * If this is the first gpio_request for the bank,
549 * enable the bank module.
550 */
551 if (!bank->mod_usage)
552 pm_runtime_get_sync(bank->dev);
553
554 spin_lock_irqsave(&bank->lock, flags);
555 /* Set trigger to none. You need to enable the desired trigger with
556 * request_irq() or set_irq_type().
557 */
558 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
559
560 if (bank->regs->pinctrl) {
561 void __iomem *reg = bank->base + bank->regs->pinctrl;
562
563 /* Claim the pin for MPU */
564 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
565 }
566
567 if (bank->regs->ctrl && !bank->mod_usage) {
568 void __iomem *reg = bank->base + bank->regs->ctrl;
569 u32 ctrl;
570
571 ctrl = __raw_readl(reg);
572 /* Module is enabled, clocks are not gated */
573 ctrl &= ~GPIO_MOD_CTRL_BIT;
574 __raw_writel(ctrl, reg);
575 bank->context.ctrl = ctrl;
576 }
577
578 bank->mod_usage |= 1 << offset;
579
580 spin_unlock_irqrestore(&bank->lock, flags);
581
582 return 0;
583 }
584
585 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
586 {
587 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
588 void __iomem *base = bank->base;
589 unsigned long flags;
590
591 spin_lock_irqsave(&bank->lock, flags);
592
593 if (bank->regs->wkup_en) {
594 /* Disable wake-up during idle for dynamic tick */
595 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
596 bank->context.wake_en =
597 __raw_readl(bank->base + bank->regs->wkup_en);
598 }
599
600 bank->mod_usage &= ~(1 << offset);
601
602 if (bank->regs->ctrl && !bank->mod_usage) {
603 void __iomem *reg = bank->base + bank->regs->ctrl;
604 u32 ctrl;
605
606 ctrl = __raw_readl(reg);
607 /* Module is disabled, clocks are gated */
608 ctrl |= GPIO_MOD_CTRL_BIT;
609 __raw_writel(ctrl, reg);
610 bank->context.ctrl = ctrl;
611 }
612
613 _reset_gpio(bank, bank->chip.base + offset);
614 spin_unlock_irqrestore(&bank->lock, flags);
615
616 /*
617 * If this is the last gpio to be freed in the bank,
618 * disable the bank module.
619 */
620 if (!bank->mod_usage)
621 pm_runtime_put(bank->dev);
622 }
623
624 /*
625 * We need to unmask the GPIO bank interrupt as soon as possible to
626 * avoid missing GPIO interrupts for other lines in the bank.
627 * Then we need to mask-read-clear-unmask the triggered GPIO lines
628 * in the bank to avoid missing nested interrupts for a GPIO line.
629 * If we wait to unmask individual GPIO lines in the bank after the
630 * line's interrupt handler has been run, we may miss some nested
631 * interrupts.
632 */
633 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
634 {
635 void __iomem *isr_reg = NULL;
636 u32 isr;
637 unsigned int gpio_irq, gpio_index;
638 struct gpio_bank *bank;
639 u32 retrigger = 0;
640 int unmasked = 0;
641 struct irq_chip *chip = irq_desc_get_chip(desc);
642
643 chained_irq_enter(chip, desc);
644
645 bank = irq_get_handler_data(irq);
646 isr_reg = bank->base + bank->regs->irqstatus;
647 pm_runtime_get_sync(bank->dev);
648
649 if (WARN_ON(!isr_reg))
650 goto exit;
651
652 while(1) {
653 u32 isr_saved, level_mask = 0;
654 u32 enabled;
655
656 enabled = _get_gpio_irqbank_mask(bank);
657 isr_saved = isr = __raw_readl(isr_reg) & enabled;
658
659 if (bank->level_mask)
660 level_mask = bank->level_mask & enabled;
661
662 /* clear edge sensitive interrupts before handler(s) are
663 called so that we don't miss any interrupt occurred while
664 executing them */
665 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
666 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
667 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
668
669 /* if there is only edge sensitive GPIO pin interrupts
670 configured, we could unmask GPIO bank interrupt immediately */
671 if (!level_mask && !unmasked) {
672 unmasked = 1;
673 chained_irq_exit(chip, desc);
674 }
675
676 isr |= retrigger;
677 retrigger = 0;
678 if (!isr)
679 break;
680
681 gpio_irq = bank->irq_base;
682 for (; isr != 0; isr >>= 1, gpio_irq++) {
683 int gpio = irq_to_gpio(bank, gpio_irq);
684
685 if (!(isr & 1))
686 continue;
687
688 gpio_index = GPIO_INDEX(bank, gpio);
689
690 /*
691 * Some chips can't respond to both rising and falling
692 * at the same time. If this irq was requested with
693 * both flags, we need to flip the ICR data for the IRQ
694 * to respond to the IRQ for the opposite direction.
695 * This will be indicated in the bank toggle_mask.
696 */
697 if (bank->toggle_mask & (1 << gpio_index))
698 _toggle_gpio_edge_triggering(bank, gpio_index);
699
700 generic_handle_irq(gpio_irq);
701 }
702 }
703 /* if bank has any level sensitive GPIO pin interrupt
704 configured, we must unmask the bank interrupt only after
705 handler(s) are executed in order to avoid spurious bank
706 interrupt */
707 exit:
708 if (!unmasked)
709 chained_irq_exit(chip, desc);
710 pm_runtime_put(bank->dev);
711 }
712
713 static void gpio_irq_shutdown(struct irq_data *d)
714 {
715 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
716 unsigned int gpio = irq_to_gpio(bank, d->irq);
717 unsigned long flags;
718
719 spin_lock_irqsave(&bank->lock, flags);
720 _reset_gpio(bank, gpio);
721 spin_unlock_irqrestore(&bank->lock, flags);
722 }
723
724 static void gpio_ack_irq(struct irq_data *d)
725 {
726 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
727 unsigned int gpio = irq_to_gpio(bank, d->irq);
728
729 _clear_gpio_irqstatus(bank, gpio);
730 }
731
732 static void gpio_mask_irq(struct irq_data *d)
733 {
734 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
735 unsigned int gpio = irq_to_gpio(bank, d->irq);
736 unsigned long flags;
737
738 spin_lock_irqsave(&bank->lock, flags);
739 _set_gpio_irqenable(bank, gpio, 0);
740 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
741 spin_unlock_irqrestore(&bank->lock, flags);
742 }
743
744 static void gpio_unmask_irq(struct irq_data *d)
745 {
746 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
747 unsigned int gpio = irq_to_gpio(bank, d->irq);
748 unsigned int irq_mask = GPIO_BIT(bank, gpio);
749 u32 trigger = irqd_get_trigger_type(d);
750 unsigned long flags;
751
752 spin_lock_irqsave(&bank->lock, flags);
753 if (trigger)
754 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
755
756 /* For level-triggered GPIOs, the clearing must be done after
757 * the HW source is cleared, thus after the handler has run */
758 if (bank->level_mask & irq_mask) {
759 _set_gpio_irqenable(bank, gpio, 0);
760 _clear_gpio_irqstatus(bank, gpio);
761 }
762
763 _set_gpio_irqenable(bank, gpio, 1);
764 spin_unlock_irqrestore(&bank->lock, flags);
765 }
766
767 static struct irq_chip gpio_irq_chip = {
768 .name = "GPIO",
769 .irq_shutdown = gpio_irq_shutdown,
770 .irq_ack = gpio_ack_irq,
771 .irq_mask = gpio_mask_irq,
772 .irq_unmask = gpio_unmask_irq,
773 .irq_set_type = gpio_irq_type,
774 .irq_set_wake = gpio_wake_enable,
775 };
776
777 /*---------------------------------------------------------------------*/
778
779 static int omap_mpuio_suspend_noirq(struct device *dev)
780 {
781 struct platform_device *pdev = to_platform_device(dev);
782 struct gpio_bank *bank = platform_get_drvdata(pdev);
783 void __iomem *mask_reg = bank->base +
784 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
785 unsigned long flags;
786
787 spin_lock_irqsave(&bank->lock, flags);
788 __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
789 spin_unlock_irqrestore(&bank->lock, flags);
790
791 return 0;
792 }
793
794 static int omap_mpuio_resume_noirq(struct device *dev)
795 {
796 struct platform_device *pdev = to_platform_device(dev);
797 struct gpio_bank *bank = platform_get_drvdata(pdev);
798 void __iomem *mask_reg = bank->base +
799 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
800 unsigned long flags;
801
802 spin_lock_irqsave(&bank->lock, flags);
803 __raw_writel(bank->context.wake_en, mask_reg);
804 spin_unlock_irqrestore(&bank->lock, flags);
805
806 return 0;
807 }
808
809 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
810 .suspend_noirq = omap_mpuio_suspend_noirq,
811 .resume_noirq = omap_mpuio_resume_noirq,
812 };
813
814 /* use platform_driver for this. */
815 static struct platform_driver omap_mpuio_driver = {
816 .driver = {
817 .name = "mpuio",
818 .pm = &omap_mpuio_dev_pm_ops,
819 },
820 };
821
822 static struct platform_device omap_mpuio_device = {
823 .name = "mpuio",
824 .id = -1,
825 .dev = {
826 .driver = &omap_mpuio_driver.driver,
827 }
828 /* could list the /proc/iomem resources */
829 };
830
831 static inline void mpuio_init(struct gpio_bank *bank)
832 {
833 platform_set_drvdata(&omap_mpuio_device, bank);
834
835 if (platform_driver_register(&omap_mpuio_driver) == 0)
836 (void) platform_device_register(&omap_mpuio_device);
837 }
838
839 /*---------------------------------------------------------------------*/
840
841 static int gpio_input(struct gpio_chip *chip, unsigned offset)
842 {
843 struct gpio_bank *bank;
844 unsigned long flags;
845
846 bank = container_of(chip, struct gpio_bank, chip);
847 spin_lock_irqsave(&bank->lock, flags);
848 _set_gpio_direction(bank, offset, 1);
849 spin_unlock_irqrestore(&bank->lock, flags);
850 return 0;
851 }
852
853 static int gpio_is_input(struct gpio_bank *bank, int mask)
854 {
855 void __iomem *reg = bank->base + bank->regs->direction;
856
857 return __raw_readl(reg) & mask;
858 }
859
860 static int gpio_get(struct gpio_chip *chip, unsigned offset)
861 {
862 struct gpio_bank *bank;
863 u32 mask;
864
865 bank = container_of(chip, struct gpio_bank, chip);
866 mask = (1 << offset);
867
868 if (gpio_is_input(bank, mask))
869 return _get_gpio_datain(bank, offset);
870 else
871 return _get_gpio_dataout(bank, offset);
872 }
873
874 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
875 {
876 struct gpio_bank *bank;
877 unsigned long flags;
878
879 bank = container_of(chip, struct gpio_bank, chip);
880 spin_lock_irqsave(&bank->lock, flags);
881 bank->set_dataout(bank, offset, value);
882 _set_gpio_direction(bank, offset, 0);
883 spin_unlock_irqrestore(&bank->lock, flags);
884 return 0;
885 }
886
887 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
888 unsigned debounce)
889 {
890 struct gpio_bank *bank;
891 unsigned long flags;
892
893 bank = container_of(chip, struct gpio_bank, chip);
894
895 if (!bank->dbck) {
896 bank->dbck = clk_get(bank->dev, "dbclk");
897 if (IS_ERR(bank->dbck))
898 dev_err(bank->dev, "Could not get gpio dbck\n");
899 }
900
901 spin_lock_irqsave(&bank->lock, flags);
902 _set_gpio_debounce(bank, offset, debounce);
903 spin_unlock_irqrestore(&bank->lock, flags);
904
905 return 0;
906 }
907
908 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
909 {
910 struct gpio_bank *bank;
911 unsigned long flags;
912
913 bank = container_of(chip, struct gpio_bank, chip);
914 spin_lock_irqsave(&bank->lock, flags);
915 bank->set_dataout(bank, offset, value);
916 spin_unlock_irqrestore(&bank->lock, flags);
917 }
918
919 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
920 {
921 struct gpio_bank *bank;
922
923 bank = container_of(chip, struct gpio_bank, chip);
924 return bank->irq_base + offset;
925 }
926
927 /*---------------------------------------------------------------------*/
928
929 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
930 {
931 static bool called;
932 u32 rev;
933
934 if (called || bank->regs->revision == USHRT_MAX)
935 return;
936
937 rev = __raw_readw(bank->base + bank->regs->revision);
938 pr_info("OMAP GPIO hardware version %d.%d\n",
939 (rev >> 4) & 0x0f, rev & 0x0f);
940
941 called = true;
942 }
943
944 /* This lock class tells lockdep that GPIO irqs are in a different
945 * category than their parents, so it won't report false recursion.
946 */
947 static struct lock_class_key gpio_lock_class;
948
949 static void omap_gpio_mod_init(struct gpio_bank *bank)
950 {
951 void __iomem *base = bank->base;
952 u32 l = 0xffffffff;
953
954 if (bank->width == 16)
955 l = 0xffff;
956
957 if (bank->is_mpuio) {
958 __raw_writel(l, bank->base + bank->regs->irqenable);
959 return;
960 }
961
962 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
963 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
964 if (bank->regs->debounce_en)
965 __raw_writel(0, base + bank->regs->debounce_en);
966
967 /* Save OE default value (0xffffffff) in the context */
968 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
969 /* Initialize interface clk ungated, module enabled */
970 if (bank->regs->ctrl)
971 __raw_writel(0, base + bank->regs->ctrl);
972 }
973
974 static __devinit void
975 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
976 unsigned int num)
977 {
978 struct irq_chip_generic *gc;
979 struct irq_chip_type *ct;
980
981 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
982 handle_simple_irq);
983 if (!gc) {
984 dev_err(bank->dev, "Memory alloc failed for gc\n");
985 return;
986 }
987
988 ct = gc->chip_types;
989
990 /* NOTE: No ack required, reading IRQ status clears it. */
991 ct->chip.irq_mask = irq_gc_mask_set_bit;
992 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
993 ct->chip.irq_set_type = gpio_irq_type;
994
995 if (bank->regs->wkup_en)
996 ct->chip.irq_set_wake = gpio_wake_enable,
997
998 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
999 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1000 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1001 }
1002
1003 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1004 {
1005 int j;
1006 static int gpio;
1007
1008 /*
1009 * REVISIT eventually switch from OMAP-specific gpio structs
1010 * over to the generic ones
1011 */
1012 bank->chip.request = omap_gpio_request;
1013 bank->chip.free = omap_gpio_free;
1014 bank->chip.direction_input = gpio_input;
1015 bank->chip.get = gpio_get;
1016 bank->chip.direction_output = gpio_output;
1017 bank->chip.set_debounce = gpio_debounce;
1018 bank->chip.set = gpio_set;
1019 bank->chip.to_irq = gpio_2irq;
1020 if (bank->is_mpuio) {
1021 bank->chip.label = "mpuio";
1022 if (bank->regs->wkup_en)
1023 bank->chip.dev = &omap_mpuio_device.dev;
1024 bank->chip.base = OMAP_MPUIO(0);
1025 } else {
1026 bank->chip.label = "gpio";
1027 bank->chip.base = gpio;
1028 gpio += bank->width;
1029 }
1030 bank->chip.ngpio = bank->width;
1031
1032 gpiochip_add(&bank->chip);
1033
1034 for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1035 irq_set_lockdep_class(j, &gpio_lock_class);
1036 irq_set_chip_data(j, bank);
1037 if (bank->is_mpuio) {
1038 omap_mpuio_alloc_gc(bank, j, bank->width);
1039 } else {
1040 irq_set_chip(j, &gpio_irq_chip);
1041 irq_set_handler(j, handle_simple_irq);
1042 set_irq_flags(j, IRQF_VALID);
1043 }
1044 }
1045 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1046 irq_set_handler_data(bank->irq, bank);
1047 }
1048
1049 static const struct of_device_id omap_gpio_match[];
1050
1051 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1052 {
1053 struct device *dev = &pdev->dev;
1054 struct device_node *node = dev->of_node;
1055 const struct of_device_id *match;
1056 struct omap_gpio_platform_data *pdata;
1057 struct resource *res;
1058 struct gpio_bank *bank;
1059 int ret = 0;
1060
1061 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1062
1063 pdata = match ? match->data : dev->platform_data;
1064 if (!pdata)
1065 return -EINVAL;
1066
1067 bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
1068 if (!bank) {
1069 dev_err(dev, "Memory alloc failed\n");
1070 return -ENOMEM;
1071 }
1072
1073 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1074 if (unlikely(!res)) {
1075 dev_err(dev, "Invalid IRQ resource\n");
1076 return -ENODEV;
1077 }
1078
1079 bank->irq = res->start;
1080 bank->dev = dev;
1081 bank->dbck_flag = pdata->dbck_flag;
1082 bank->stride = pdata->bank_stride;
1083 bank->width = pdata->bank_width;
1084 bank->is_mpuio = pdata->is_mpuio;
1085 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1086 bank->loses_context = pdata->loses_context;
1087 bank->get_context_loss_count = pdata->get_context_loss_count;
1088 bank->regs = pdata->regs;
1089 #ifdef CONFIG_OF_GPIO
1090 bank->chip.of_node = of_node_get(node);
1091 #endif
1092
1093 bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1094 if (bank->irq_base < 0) {
1095 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1096 return -ENODEV;
1097 }
1098
1099 bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1100 0, &irq_domain_simple_ops, NULL);
1101
1102 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1103 bank->set_dataout = _set_gpio_dataout_reg;
1104 else
1105 bank->set_dataout = _set_gpio_dataout_mask;
1106
1107 spin_lock_init(&bank->lock);
1108
1109 /* Static mapping, never released */
1110 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1111 if (unlikely(!res)) {
1112 dev_err(dev, "Invalid mem resource\n");
1113 return -ENODEV;
1114 }
1115
1116 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1117 pdev->name)) {
1118 dev_err(dev, "Region already claimed\n");
1119 return -EBUSY;
1120 }
1121
1122 bank->base = devm_ioremap(dev, res->start, resource_size(res));
1123 if (!bank->base) {
1124 dev_err(dev, "Could not ioremap\n");
1125 return -ENOMEM;
1126 }
1127
1128 platform_set_drvdata(pdev, bank);
1129
1130 pm_runtime_enable(bank->dev);
1131 pm_runtime_irq_safe(bank->dev);
1132 pm_runtime_get_sync(bank->dev);
1133
1134 if (bank->is_mpuio)
1135 mpuio_init(bank);
1136
1137 omap_gpio_mod_init(bank);
1138 omap_gpio_chip_init(bank);
1139 omap_gpio_show_rev(bank);
1140
1141 pm_runtime_put(bank->dev);
1142
1143 list_add_tail(&bank->node, &omap_gpio_list);
1144
1145 return ret;
1146 }
1147
1148 #ifdef CONFIG_ARCH_OMAP2PLUS
1149
1150 #if defined(CONFIG_PM_SLEEP)
1151 static int omap_gpio_suspend(struct device *dev)
1152 {
1153 struct platform_device *pdev = to_platform_device(dev);
1154 struct gpio_bank *bank = platform_get_drvdata(pdev);
1155 void __iomem *base = bank->base;
1156 unsigned long flags;
1157
1158 if (!bank->mod_usage || !bank->loses_context)
1159 return 0;
1160
1161 if (!bank->regs->wkup_en || !bank->context.wake_en)
1162 return 0;
1163
1164 spin_lock_irqsave(&bank->lock, flags);
1165 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1166 _gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
1167 spin_unlock_irqrestore(&bank->lock, flags);
1168
1169 return 0;
1170 }
1171
1172 static int omap_gpio_resume(struct device *dev)
1173 {
1174 struct platform_device *pdev = to_platform_device(dev);
1175 struct gpio_bank *bank = platform_get_drvdata(pdev);
1176 void __iomem *base = bank->base;
1177 unsigned long flags;
1178
1179 if (!bank->mod_usage || !bank->loses_context)
1180 return 0;
1181
1182 if (!bank->regs->wkup_en || !bank->context.wake_en)
1183 return 0;
1184
1185 spin_lock_irqsave(&bank->lock, flags);
1186 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1187 _gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
1188 spin_unlock_irqrestore(&bank->lock, flags);
1189
1190 return 0;
1191 }
1192 #endif /* CONFIG_PM_SLEEP */
1193
1194 #if defined(CONFIG_PM_RUNTIME)
1195 static void omap_gpio_restore_context(struct gpio_bank *bank);
1196
1197 static int omap_gpio_runtime_suspend(struct device *dev)
1198 {
1199 struct platform_device *pdev = to_platform_device(dev);
1200 struct gpio_bank *bank = platform_get_drvdata(pdev);
1201 u32 l1 = 0, l2 = 0;
1202 unsigned long flags;
1203 u32 wake_low, wake_hi;
1204
1205 spin_lock_irqsave(&bank->lock, flags);
1206
1207 /*
1208 * Only edges can generate a wakeup event to the PRCM.
1209 *
1210 * Therefore, ensure any wake-up capable GPIOs have
1211 * edge-detection enabled before going idle to ensure a wakeup
1212 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1213 * NDA TRM 25.5.3.1)
1214 *
1215 * The normal values will be restored upon ->runtime_resume()
1216 * by writing back the values saved in bank->context.
1217 */
1218 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1219 if (wake_low)
1220 __raw_writel(wake_low | bank->context.fallingdetect,
1221 bank->base + bank->regs->fallingdetect);
1222 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1223 if (wake_hi)
1224 __raw_writel(wake_hi | bank->context.risingdetect,
1225 bank->base + bank->regs->risingdetect);
1226
1227 if (bank->power_mode != OFF_MODE) {
1228 bank->power_mode = 0;
1229 goto update_gpio_context_count;
1230 }
1231 /*
1232 * If going to OFF, remove triggering for all
1233 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1234 * generated. See OMAP2420 Errata item 1.101.
1235 */
1236 bank->saved_datain = __raw_readl(bank->base +
1237 bank->regs->datain);
1238 l1 = bank->context.fallingdetect;
1239 l2 = bank->context.risingdetect;
1240
1241 l1 &= ~bank->enabled_non_wakeup_gpios;
1242 l2 &= ~bank->enabled_non_wakeup_gpios;
1243
1244 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1245 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1246
1247 bank->workaround_enabled = true;
1248
1249 update_gpio_context_count:
1250 if (bank->get_context_loss_count)
1251 bank->context_loss_count =
1252 bank->get_context_loss_count(bank->dev);
1253
1254 _gpio_dbck_disable(bank);
1255 spin_unlock_irqrestore(&bank->lock, flags);
1256
1257 return 0;
1258 }
1259
1260 static int omap_gpio_runtime_resume(struct device *dev)
1261 {
1262 struct platform_device *pdev = to_platform_device(dev);
1263 struct gpio_bank *bank = platform_get_drvdata(pdev);
1264 int context_lost_cnt_after;
1265 u32 l = 0, gen, gen0, gen1;
1266 unsigned long flags;
1267
1268 spin_lock_irqsave(&bank->lock, flags);
1269 _gpio_dbck_enable(bank);
1270
1271 /*
1272 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1273 * GPIOs were set to edge trigger also in order to be able to
1274 * generate a PRCM wakeup. Here we restore the
1275 * pre-runtime_suspend() values for edge triggering.
1276 */
1277 __raw_writel(bank->context.fallingdetect,
1278 bank->base + bank->regs->fallingdetect);
1279 __raw_writel(bank->context.risingdetect,
1280 bank->base + bank->regs->risingdetect);
1281
1282 if (!bank->workaround_enabled) {
1283 spin_unlock_irqrestore(&bank->lock, flags);
1284 return 0;
1285 }
1286
1287 if (bank->get_context_loss_count) {
1288 context_lost_cnt_after =
1289 bank->get_context_loss_count(bank->dev);
1290 if (context_lost_cnt_after != bank->context_loss_count ||
1291 !context_lost_cnt_after) {
1292 omap_gpio_restore_context(bank);
1293 } else {
1294 spin_unlock_irqrestore(&bank->lock, flags);
1295 return 0;
1296 }
1297 }
1298
1299 __raw_writel(bank->context.fallingdetect,
1300 bank->base + bank->regs->fallingdetect);
1301 __raw_writel(bank->context.risingdetect,
1302 bank->base + bank->regs->risingdetect);
1303 l = __raw_readl(bank->base + bank->regs->datain);
1304
1305 /*
1306 * Check if any of the non-wakeup interrupt GPIOs have changed
1307 * state. If so, generate an IRQ by software. This is
1308 * horribly racy, but it's the best we can do to work around
1309 * this silicon bug.
1310 */
1311 l ^= bank->saved_datain;
1312 l &= bank->enabled_non_wakeup_gpios;
1313
1314 /*
1315 * No need to generate IRQs for the rising edge for gpio IRQs
1316 * configured with falling edge only; and vice versa.
1317 */
1318 gen0 = l & bank->context.fallingdetect;
1319 gen0 &= bank->saved_datain;
1320
1321 gen1 = l & bank->context.risingdetect;
1322 gen1 &= ~(bank->saved_datain);
1323
1324 /* FIXME: Consider GPIO IRQs with level detections properly! */
1325 gen = l & (~(bank->context.fallingdetect) &
1326 ~(bank->context.risingdetect));
1327 /* Consider all GPIO IRQs needed to be updated */
1328 gen |= gen0 | gen1;
1329
1330 if (gen) {
1331 u32 old0, old1;
1332
1333 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1334 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1335
1336 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1337 __raw_writel(old0 | gen, bank->base +
1338 bank->regs->leveldetect0);
1339 __raw_writel(old1 | gen, bank->base +
1340 bank->regs->leveldetect1);
1341 }
1342
1343 if (cpu_is_omap44xx()) {
1344 __raw_writel(old0 | l, bank->base +
1345 bank->regs->leveldetect0);
1346 __raw_writel(old1 | l, bank->base +
1347 bank->regs->leveldetect1);
1348 }
1349 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1350 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1351 }
1352
1353 bank->workaround_enabled = false;
1354 spin_unlock_irqrestore(&bank->lock, flags);
1355
1356 return 0;
1357 }
1358 #endif /* CONFIG_PM_RUNTIME */
1359
1360 void omap2_gpio_prepare_for_idle(int pwr_mode)
1361 {
1362 struct gpio_bank *bank;
1363
1364 list_for_each_entry(bank, &omap_gpio_list, node) {
1365 if (!bank->mod_usage || !bank->loses_context)
1366 continue;
1367
1368 bank->power_mode = pwr_mode;
1369
1370 pm_runtime_put_sync_suspend(bank->dev);
1371 }
1372 }
1373
1374 void omap2_gpio_resume_after_idle(void)
1375 {
1376 struct gpio_bank *bank;
1377
1378 list_for_each_entry(bank, &omap_gpio_list, node) {
1379 if (!bank->mod_usage || !bank->loses_context)
1380 continue;
1381
1382 pm_runtime_get_sync(bank->dev);
1383 }
1384 }
1385
1386 #if defined(CONFIG_PM_RUNTIME)
1387 static void omap_gpio_restore_context(struct gpio_bank *bank)
1388 {
1389 __raw_writel(bank->context.wake_en,
1390 bank->base + bank->regs->wkup_en);
1391 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1392 __raw_writel(bank->context.leveldetect0,
1393 bank->base + bank->regs->leveldetect0);
1394 __raw_writel(bank->context.leveldetect1,
1395 bank->base + bank->regs->leveldetect1);
1396 __raw_writel(bank->context.risingdetect,
1397 bank->base + bank->regs->risingdetect);
1398 __raw_writel(bank->context.fallingdetect,
1399 bank->base + bank->regs->fallingdetect);
1400 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1401 __raw_writel(bank->context.dataout,
1402 bank->base + bank->regs->set_dataout);
1403 else
1404 __raw_writel(bank->context.dataout,
1405 bank->base + bank->regs->dataout);
1406 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1407
1408 if (bank->dbck_enable_mask) {
1409 __raw_writel(bank->context.debounce, bank->base +
1410 bank->regs->debounce);
1411 __raw_writel(bank->context.debounce_en,
1412 bank->base + bank->regs->debounce_en);
1413 }
1414
1415 __raw_writel(bank->context.irqenable1,
1416 bank->base + bank->regs->irqenable);
1417 __raw_writel(bank->context.irqenable2,
1418 bank->base + bank->regs->irqenable2);
1419 }
1420 #endif /* CONFIG_PM_RUNTIME */
1421 #else
1422 #define omap_gpio_suspend NULL
1423 #define omap_gpio_resume NULL
1424 #define omap_gpio_runtime_suspend NULL
1425 #define omap_gpio_runtime_resume NULL
1426 #endif
1427
1428 static const struct dev_pm_ops gpio_pm_ops = {
1429 SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1430 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1431 NULL)
1432 };
1433
1434 #if defined(CONFIG_OF)
1435 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1436 .revision = OMAP24XX_GPIO_REVISION,
1437 .direction = OMAP24XX_GPIO_OE,
1438 .datain = OMAP24XX_GPIO_DATAIN,
1439 .dataout = OMAP24XX_GPIO_DATAOUT,
1440 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1441 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1442 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1443 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1444 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1445 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1446 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1447 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1448 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1449 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1450 .ctrl = OMAP24XX_GPIO_CTRL,
1451 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1452 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1453 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1454 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1455 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1456 };
1457
1458 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1459 .revision = OMAP4_GPIO_REVISION,
1460 .direction = OMAP4_GPIO_OE,
1461 .datain = OMAP4_GPIO_DATAIN,
1462 .dataout = OMAP4_GPIO_DATAOUT,
1463 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1464 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1465 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1466 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1467 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1468 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1469 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1470 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1471 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1472 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1473 .ctrl = OMAP4_GPIO_CTRL,
1474 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1475 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1476 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1477 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1478 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1479 };
1480
1481 static struct omap_gpio_platform_data omap2_pdata = {
1482 .regs = &omap2_gpio_regs,
1483 .bank_width = 32,
1484 .dbck_flag = false,
1485 };
1486
1487 static struct omap_gpio_platform_data omap3_pdata = {
1488 .regs = &omap2_gpio_regs,
1489 .bank_width = 32,
1490 .dbck_flag = true,
1491 };
1492
1493 static struct omap_gpio_platform_data omap4_pdata = {
1494 .regs = &omap4_gpio_regs,
1495 .bank_width = 32,
1496 .dbck_flag = true,
1497 };
1498
1499 static const struct of_device_id omap_gpio_match[] = {
1500 {
1501 .compatible = "ti,omap4-gpio",
1502 .data = &omap4_pdata,
1503 },
1504 {
1505 .compatible = "ti,omap3-gpio",
1506 .data = &omap3_pdata,
1507 },
1508 {
1509 .compatible = "ti,omap2-gpio",
1510 .data = &omap2_pdata,
1511 },
1512 { },
1513 };
1514 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1515 #endif
1516
1517 static struct platform_driver omap_gpio_driver = {
1518 .probe = omap_gpio_probe,
1519 .driver = {
1520 .name = "omap_gpio",
1521 .pm = &gpio_pm_ops,
1522 .of_match_table = of_match_ptr(omap_gpio_match),
1523 },
1524 };
1525
1526 /*
1527 * gpio driver register needs to be done before
1528 * machine_init functions access gpio APIs.
1529 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1530 */
1531 static int __init omap_gpio_drv_reg(void)
1532 {
1533 return platform_driver_register(&omap_gpio_driver);
1534 }
1535 postcore_initcall(omap_gpio_drv_reg);
Linux kernel - Deliverables
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