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[deliverable/linux.git] / drivers / gpio / gpio-omap.c
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/irqchip/chained_irq.h>
28 #include <linux/gpio.h>
29 #include <linux/platform_data/gpio-omap.h>
30
31 #define OFF_MODE 1
32
33 static LIST_HEAD(omap_gpio_list);
34
35 struct gpio_regs {
36 u32 irqenable1;
37 u32 irqenable2;
38 u32 wake_en;
39 u32 ctrl;
40 u32 oe;
41 u32 leveldetect0;
42 u32 leveldetect1;
43 u32 risingdetect;
44 u32 fallingdetect;
45 u32 dataout;
46 u32 debounce;
47 u32 debounce_en;
48 };
49
50 struct gpio_bank {
51 struct list_head node;
52 void __iomem *base;
53 u16 irq;
54 u32 non_wakeup_gpios;
55 u32 enabled_non_wakeup_gpios;
56 struct gpio_regs context;
57 u32 saved_datain;
58 u32 level_mask;
59 u32 toggle_mask;
60 spinlock_t lock;
61 struct gpio_chip chip;
62 struct clk *dbck;
63 u32 mod_usage;
64 u32 irq_usage;
65 u32 dbck_enable_mask;
66 bool dbck_enabled;
67 struct device *dev;
68 bool is_mpuio;
69 bool dbck_flag;
70 bool loses_context;
71 bool context_valid;
72 int stride;
73 u32 width;
74 int context_loss_count;
75 int power_mode;
76 bool workaround_enabled;
77
78 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
79 int (*get_context_loss_count)(struct device *dev);
80
81 struct omap_gpio_reg_offs *regs;
82 };
83
84 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
85 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
86 #define GPIO_MOD_CTRL_BIT BIT(0)
87
88 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
89 #define LINE_USED(line, offset) (line & (1 << offset))
90
91 static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
92 {
93 return bank->chip.base + gpio_irq;
94 }
95
96 static inline struct gpio_bank *_irq_data_get_bank(struct irq_data *d)
97 {
98 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
99 return container_of(chip, struct gpio_bank, chip);
100 }
101
102 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
103 {
104 void __iomem *reg = bank->base;
105 u32 l;
106
107 reg += bank->regs->direction;
108 l = readl_relaxed(reg);
109 if (is_input)
110 l |= 1 << gpio;
111 else
112 l &= ~(1 << gpio);
113 writel_relaxed(l, reg);
114 bank->context.oe = l;
115 }
116
117
118 /* set data out value using dedicate set/clear register */
119 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
120 {
121 void __iomem *reg = bank->base;
122 u32 l = GPIO_BIT(bank, gpio);
123
124 if (enable) {
125 reg += bank->regs->set_dataout;
126 bank->context.dataout |= l;
127 } else {
128 reg += bank->regs->clr_dataout;
129 bank->context.dataout &= ~l;
130 }
131
132 writel_relaxed(l, reg);
133 }
134
135 /* set data out value using mask register */
136 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
137 {
138 void __iomem *reg = bank->base + bank->regs->dataout;
139 u32 gpio_bit = GPIO_BIT(bank, gpio);
140 u32 l;
141
142 l = readl_relaxed(reg);
143 if (enable)
144 l |= gpio_bit;
145 else
146 l &= ~gpio_bit;
147 writel_relaxed(l, reg);
148 bank->context.dataout = l;
149 }
150
151 static int _get_gpio_datain(struct gpio_bank *bank, int offset)
152 {
153 void __iomem *reg = bank->base + bank->regs->datain;
154
155 return (readl_relaxed(reg) & (1 << offset)) != 0;
156 }
157
158 static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
159 {
160 void __iomem *reg = bank->base + bank->regs->dataout;
161
162 return (readl_relaxed(reg) & (1 << offset)) != 0;
163 }
164
165 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
166 {
167 int l = readl_relaxed(base + reg);
168
169 if (set)
170 l |= mask;
171 else
172 l &= ~mask;
173
174 writel_relaxed(l, base + reg);
175 }
176
177 static inline void _gpio_dbck_enable(struct gpio_bank *bank)
178 {
179 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
180 clk_enable(bank->dbck);
181 bank->dbck_enabled = true;
182
183 writel_relaxed(bank->dbck_enable_mask,
184 bank->base + bank->regs->debounce_en);
185 }
186 }
187
188 static inline void _gpio_dbck_disable(struct gpio_bank *bank)
189 {
190 if (bank->dbck_enable_mask && bank->dbck_enabled) {
191 /*
192 * Disable debounce before cutting it's clock. If debounce is
193 * enabled but the clock is not, GPIO module seems to be unable
194 * to detect events and generate interrupts at least on OMAP3.
195 */
196 writel_relaxed(0, bank->base + bank->regs->debounce_en);
197
198 clk_disable(bank->dbck);
199 bank->dbck_enabled = false;
200 }
201 }
202
203 /**
204 * _set_gpio_debounce - low level gpio debounce time
205 * @bank: the gpio bank we're acting upon
206 * @gpio: the gpio number on this @gpio
207 * @debounce: debounce time to use
208 *
209 * OMAP's debounce time is in 31us steps so we need
210 * to convert and round up to the closest unit.
211 */
212 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
213 unsigned debounce)
214 {
215 void __iomem *reg;
216 u32 val;
217 u32 l;
218
219 if (!bank->dbck_flag)
220 return;
221
222 if (debounce < 32)
223 debounce = 0x01;
224 else if (debounce > 7936)
225 debounce = 0xff;
226 else
227 debounce = (debounce / 0x1f) - 1;
228
229 l = GPIO_BIT(bank, gpio);
230
231 clk_enable(bank->dbck);
232 reg = bank->base + bank->regs->debounce;
233 writel_relaxed(debounce, reg);
234
235 reg = bank->base + bank->regs->debounce_en;
236 val = readl_relaxed(reg);
237
238 if (debounce)
239 val |= l;
240 else
241 val &= ~l;
242 bank->dbck_enable_mask = val;
243
244 writel_relaxed(val, reg);
245 clk_disable(bank->dbck);
246 /*
247 * Enable debounce clock per module.
248 * This call is mandatory because in omap_gpio_request() when
249 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
250 * runtime callbck fails to turn on dbck because dbck_enable_mask
251 * used within _gpio_dbck_enable() is still not initialized at
252 * that point. Therefore we have to enable dbck here.
253 */
254 _gpio_dbck_enable(bank);
255 if (bank->dbck_enable_mask) {
256 bank->context.debounce = debounce;
257 bank->context.debounce_en = val;
258 }
259 }
260
261 /**
262 * _clear_gpio_debounce - clear debounce settings for a gpio
263 * @bank: the gpio bank we're acting upon
264 * @gpio: the gpio number on this @gpio
265 *
266 * If a gpio is using debounce, then clear the debounce enable bit and if
267 * this is the only gpio in this bank using debounce, then clear the debounce
268 * time too. The debounce clock will also be disabled when calling this function
269 * if this is the only gpio in the bank using debounce.
270 */
271 static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
272 {
273 u32 gpio_bit = GPIO_BIT(bank, gpio);
274
275 if (!bank->dbck_flag)
276 return;
277
278 if (!(bank->dbck_enable_mask & gpio_bit))
279 return;
280
281 bank->dbck_enable_mask &= ~gpio_bit;
282 bank->context.debounce_en &= ~gpio_bit;
283 writel_relaxed(bank->context.debounce_en,
284 bank->base + bank->regs->debounce_en);
285
286 if (!bank->dbck_enable_mask) {
287 bank->context.debounce = 0;
288 writel_relaxed(bank->context.debounce, bank->base +
289 bank->regs->debounce);
290 clk_disable(bank->dbck);
291 bank->dbck_enabled = false;
292 }
293 }
294
295 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
296 unsigned trigger)
297 {
298 void __iomem *base = bank->base;
299 u32 gpio_bit = 1 << gpio;
300
301 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
302 trigger & IRQ_TYPE_LEVEL_LOW);
303 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
304 trigger & IRQ_TYPE_LEVEL_HIGH);
305 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
306 trigger & IRQ_TYPE_EDGE_RISING);
307 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
308 trigger & IRQ_TYPE_EDGE_FALLING);
309
310 bank->context.leveldetect0 =
311 readl_relaxed(bank->base + bank->regs->leveldetect0);
312 bank->context.leveldetect1 =
313 readl_relaxed(bank->base + bank->regs->leveldetect1);
314 bank->context.risingdetect =
315 readl_relaxed(bank->base + bank->regs->risingdetect);
316 bank->context.fallingdetect =
317 readl_relaxed(bank->base + bank->regs->fallingdetect);
318
319 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
320 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
321 bank->context.wake_en =
322 readl_relaxed(bank->base + bank->regs->wkup_en);
323 }
324
325 /* This part needs to be executed always for OMAP{34xx, 44xx} */
326 if (!bank->regs->irqctrl) {
327 /* On omap24xx proceed only when valid GPIO bit is set */
328 if (bank->non_wakeup_gpios) {
329 if (!(bank->non_wakeup_gpios & gpio_bit))
330 goto exit;
331 }
332
333 /*
334 * Log the edge gpio and manually trigger the IRQ
335 * after resume if the input level changes
336 * to avoid irq lost during PER RET/OFF mode
337 * Applies for omap2 non-wakeup gpio and all omap3 gpios
338 */
339 if (trigger & IRQ_TYPE_EDGE_BOTH)
340 bank->enabled_non_wakeup_gpios |= gpio_bit;
341 else
342 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
343 }
344
345 exit:
346 bank->level_mask =
347 readl_relaxed(bank->base + bank->regs->leveldetect0) |
348 readl_relaxed(bank->base + bank->regs->leveldetect1);
349 }
350
351 #ifdef CONFIG_ARCH_OMAP1
352 /*
353 * This only applies to chips that can't do both rising and falling edge
354 * detection at once. For all other chips, this function is a noop.
355 */
356 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
357 {
358 void __iomem *reg = bank->base;
359 u32 l = 0;
360
361 if (!bank->regs->irqctrl)
362 return;
363
364 reg += bank->regs->irqctrl;
365
366 l = readl_relaxed(reg);
367 if ((l >> gpio) & 1)
368 l &= ~(1 << gpio);
369 else
370 l |= 1 << gpio;
371
372 writel_relaxed(l, reg);
373 }
374 #else
375 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
376 #endif
377
378 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
379 unsigned trigger)
380 {
381 void __iomem *reg = bank->base;
382 void __iomem *base = bank->base;
383 u32 l = 0;
384
385 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
386 set_gpio_trigger(bank, gpio, trigger);
387 } else if (bank->regs->irqctrl) {
388 reg += bank->regs->irqctrl;
389
390 l = readl_relaxed(reg);
391 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
392 bank->toggle_mask |= 1 << gpio;
393 if (trigger & IRQ_TYPE_EDGE_RISING)
394 l |= 1 << gpio;
395 else if (trigger & IRQ_TYPE_EDGE_FALLING)
396 l &= ~(1 << gpio);
397 else
398 return -EINVAL;
399
400 writel_relaxed(l, reg);
401 } else if (bank->regs->edgectrl1) {
402 if (gpio & 0x08)
403 reg += bank->regs->edgectrl2;
404 else
405 reg += bank->regs->edgectrl1;
406
407 gpio &= 0x07;
408 l = readl_relaxed(reg);
409 l &= ~(3 << (gpio << 1));
410 if (trigger & IRQ_TYPE_EDGE_RISING)
411 l |= 2 << (gpio << 1);
412 if (trigger & IRQ_TYPE_EDGE_FALLING)
413 l |= 1 << (gpio << 1);
414
415 /* Enable wake-up during idle for dynamic tick */
416 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
417 bank->context.wake_en =
418 readl_relaxed(bank->base + bank->regs->wkup_en);
419 writel_relaxed(l, reg);
420 }
421 return 0;
422 }
423
424 static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset)
425 {
426 if (bank->regs->pinctrl) {
427 void __iomem *reg = bank->base + bank->regs->pinctrl;
428
429 /* Claim the pin for MPU */
430 writel_relaxed(readl_relaxed(reg) | (1 << offset), reg);
431 }
432
433 if (bank->regs->ctrl && !BANK_USED(bank)) {
434 void __iomem *reg = bank->base + bank->regs->ctrl;
435 u32 ctrl;
436
437 ctrl = readl_relaxed(reg);
438 /* Module is enabled, clocks are not gated */
439 ctrl &= ~GPIO_MOD_CTRL_BIT;
440 writel_relaxed(ctrl, reg);
441 bank->context.ctrl = ctrl;
442 }
443 }
444
445 static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset)
446 {
447 void __iomem *base = bank->base;
448
449 if (bank->regs->wkup_en &&
450 !LINE_USED(bank->mod_usage, offset) &&
451 !LINE_USED(bank->irq_usage, offset)) {
452 /* Disable wake-up during idle for dynamic tick */
453 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
454 bank->context.wake_en =
455 readl_relaxed(bank->base + bank->regs->wkup_en);
456 }
457
458 if (bank->regs->ctrl && !BANK_USED(bank)) {
459 void __iomem *reg = bank->base + bank->regs->ctrl;
460 u32 ctrl;
461
462 ctrl = readl_relaxed(reg);
463 /* Module is disabled, clocks are gated */
464 ctrl |= GPIO_MOD_CTRL_BIT;
465 writel_relaxed(ctrl, reg);
466 bank->context.ctrl = ctrl;
467 }
468 }
469
470 static int gpio_is_input(struct gpio_bank *bank, int mask)
471 {
472 void __iomem *reg = bank->base + bank->regs->direction;
473
474 return readl_relaxed(reg) & mask;
475 }
476
477 static int gpio_irq_type(struct irq_data *d, unsigned type)
478 {
479 struct gpio_bank *bank = _irq_data_get_bank(d);
480 unsigned gpio = 0;
481 int retval;
482 unsigned long flags;
483 unsigned offset;
484
485 if (!BANK_USED(bank))
486 pm_runtime_get_sync(bank->dev);
487
488 #ifdef CONFIG_ARCH_OMAP1
489 if (d->irq > IH_MPUIO_BASE)
490 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
491 #endif
492
493 if (!gpio)
494 gpio = irq_to_gpio(bank, d->hwirq);
495
496 if (type & ~IRQ_TYPE_SENSE_MASK)
497 return -EINVAL;
498
499 if (!bank->regs->leveldetect0 &&
500 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
501 return -EINVAL;
502
503 spin_lock_irqsave(&bank->lock, flags);
504 offset = GPIO_INDEX(bank, gpio);
505 retval = _set_gpio_triggering(bank, offset, type);
506 if (!LINE_USED(bank->mod_usage, offset)) {
507 _enable_gpio_module(bank, offset);
508 _set_gpio_direction(bank, offset, 1);
509 } else if (!gpio_is_input(bank, 1 << offset)) {
510 spin_unlock_irqrestore(&bank->lock, flags);
511 return -EINVAL;
512 }
513
514 bank->irq_usage |= 1 << GPIO_INDEX(bank, gpio);
515 spin_unlock_irqrestore(&bank->lock, flags);
516
517 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
518 __irq_set_handler_locked(d->irq, handle_level_irq);
519 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
520 __irq_set_handler_locked(d->irq, handle_edge_irq);
521
522 return retval;
523 }
524
525 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
526 {
527 void __iomem *reg = bank->base;
528
529 reg += bank->regs->irqstatus;
530 writel_relaxed(gpio_mask, reg);
531
532 /* Workaround for clearing DSP GPIO interrupts to allow retention */
533 if (bank->regs->irqstatus2) {
534 reg = bank->base + bank->regs->irqstatus2;
535 writel_relaxed(gpio_mask, reg);
536 }
537
538 /* Flush posted write for the irq status to avoid spurious interrupts */
539 readl_relaxed(reg);
540 }
541
542 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
543 {
544 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
545 }
546
547 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
548 {
549 void __iomem *reg = bank->base;
550 u32 l;
551 u32 mask = (1 << bank->width) - 1;
552
553 reg += bank->regs->irqenable;
554 l = readl_relaxed(reg);
555 if (bank->regs->irqenable_inv)
556 l = ~l;
557 l &= mask;
558 return l;
559 }
560
561 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
562 {
563 void __iomem *reg = bank->base;
564 u32 l;
565
566 if (bank->regs->set_irqenable) {
567 reg += bank->regs->set_irqenable;
568 l = gpio_mask;
569 bank->context.irqenable1 |= gpio_mask;
570 } else {
571 reg += bank->regs->irqenable;
572 l = readl_relaxed(reg);
573 if (bank->regs->irqenable_inv)
574 l &= ~gpio_mask;
575 else
576 l |= gpio_mask;
577 bank->context.irqenable1 = l;
578 }
579
580 writel_relaxed(l, reg);
581 }
582
583 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
584 {
585 void __iomem *reg = bank->base;
586 u32 l;
587
588 if (bank->regs->clr_irqenable) {
589 reg += bank->regs->clr_irqenable;
590 l = gpio_mask;
591 bank->context.irqenable1 &= ~gpio_mask;
592 } else {
593 reg += bank->regs->irqenable;
594 l = readl_relaxed(reg);
595 if (bank->regs->irqenable_inv)
596 l |= gpio_mask;
597 else
598 l &= ~gpio_mask;
599 bank->context.irqenable1 = l;
600 }
601
602 writel_relaxed(l, reg);
603 }
604
605 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
606 {
607 if (enable)
608 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
609 else
610 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
611 }
612
613 /*
614 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
615 * 1510 does not seem to have a wake-up register. If JTAG is connected
616 * to the target, system will wake up always on GPIO events. While
617 * system is running all registered GPIO interrupts need to have wake-up
618 * enabled. When system is suspended, only selected GPIO interrupts need
619 * to have wake-up enabled.
620 */
621 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
622 {
623 u32 gpio_bit = GPIO_BIT(bank, gpio);
624 unsigned long flags;
625
626 if (bank->non_wakeup_gpios & gpio_bit) {
627 dev_err(bank->dev,
628 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
629 return -EINVAL;
630 }
631
632 spin_lock_irqsave(&bank->lock, flags);
633 if (enable)
634 bank->context.wake_en |= gpio_bit;
635 else
636 bank->context.wake_en &= ~gpio_bit;
637
638 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
639 spin_unlock_irqrestore(&bank->lock, flags);
640
641 return 0;
642 }
643
644 static void _reset_gpio(struct gpio_bank *bank, int gpio)
645 {
646 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
647 _set_gpio_irqenable(bank, gpio, 0);
648 _clear_gpio_irqstatus(bank, gpio);
649 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
650 _clear_gpio_debounce(bank, gpio);
651 }
652
653 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
654 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
655 {
656 struct gpio_bank *bank = _irq_data_get_bank(d);
657 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
658
659 return _set_gpio_wakeup(bank, gpio, enable);
660 }
661
662 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
663 {
664 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
665 unsigned long flags;
666
667 /*
668 * If this is the first gpio_request for the bank,
669 * enable the bank module.
670 */
671 if (!BANK_USED(bank))
672 pm_runtime_get_sync(bank->dev);
673
674 spin_lock_irqsave(&bank->lock, flags);
675 /* Set trigger to none. You need to enable the desired trigger with
676 * request_irq() or set_irq_type(). Only do this if the IRQ line has
677 * not already been requested.
678 */
679 if (!LINE_USED(bank->irq_usage, offset)) {
680 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
681 _enable_gpio_module(bank, offset);
682 }
683 bank->mod_usage |= 1 << offset;
684 spin_unlock_irqrestore(&bank->lock, flags);
685
686 return 0;
687 }
688
689 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
690 {
691 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
692 unsigned long flags;
693
694 spin_lock_irqsave(&bank->lock, flags);
695 bank->mod_usage &= ~(1 << offset);
696 _disable_gpio_module(bank, offset);
697 _reset_gpio(bank, bank->chip.base + offset);
698 spin_unlock_irqrestore(&bank->lock, flags);
699
700 /*
701 * If this is the last gpio to be freed in the bank,
702 * disable the bank module.
703 */
704 if (!BANK_USED(bank))
705 pm_runtime_put(bank->dev);
706 }
707
708 /*
709 * We need to unmask the GPIO bank interrupt as soon as possible to
710 * avoid missing GPIO interrupts for other lines in the bank.
711 * Then we need to mask-read-clear-unmask the triggered GPIO lines
712 * in the bank to avoid missing nested interrupts for a GPIO line.
713 * If we wait to unmask individual GPIO lines in the bank after the
714 * line's interrupt handler has been run, we may miss some nested
715 * interrupts.
716 */
717 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
718 {
719 void __iomem *isr_reg = NULL;
720 u32 isr;
721 unsigned int bit;
722 struct gpio_bank *bank;
723 int unmasked = 0;
724 struct irq_chip *irqchip = irq_desc_get_chip(desc);
725 struct gpio_chip *chip = irq_get_handler_data(irq);
726
727 chained_irq_enter(irqchip, desc);
728
729 bank = container_of(chip, struct gpio_bank, chip);
730 isr_reg = bank->base + bank->regs->irqstatus;
731 pm_runtime_get_sync(bank->dev);
732
733 if (WARN_ON(!isr_reg))
734 goto exit;
735
736 while (1) {
737 u32 isr_saved, level_mask = 0;
738 u32 enabled;
739
740 enabled = _get_gpio_irqbank_mask(bank);
741 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
742
743 if (bank->level_mask)
744 level_mask = bank->level_mask & enabled;
745
746 /* clear edge sensitive interrupts before handler(s) are
747 called so that we don't miss any interrupt occurred while
748 executing them */
749 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
750 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
751 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
752
753 /* if there is only edge sensitive GPIO pin interrupts
754 configured, we could unmask GPIO bank interrupt immediately */
755 if (!level_mask && !unmasked) {
756 unmasked = 1;
757 chained_irq_exit(irqchip, desc);
758 }
759
760 if (!isr)
761 break;
762
763 while (isr) {
764 bit = __ffs(isr);
765 isr &= ~(1 << bit);
766
767 /*
768 * Some chips can't respond to both rising and falling
769 * at the same time. If this irq was requested with
770 * both flags, we need to flip the ICR data for the IRQ
771 * to respond to the IRQ for the opposite direction.
772 * This will be indicated in the bank toggle_mask.
773 */
774 if (bank->toggle_mask & (1 << bit))
775 _toggle_gpio_edge_triggering(bank, bit);
776
777 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
778 bit));
779 }
780 }
781 /* if bank has any level sensitive GPIO pin interrupt
782 configured, we must unmask the bank interrupt only after
783 handler(s) are executed in order to avoid spurious bank
784 interrupt */
785 exit:
786 if (!unmasked)
787 chained_irq_exit(irqchip, desc);
788 pm_runtime_put(bank->dev);
789 }
790
791 static void gpio_irq_shutdown(struct irq_data *d)
792 {
793 struct gpio_bank *bank = _irq_data_get_bank(d);
794 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
795 unsigned long flags;
796 unsigned offset = GPIO_INDEX(bank, gpio);
797
798 spin_lock_irqsave(&bank->lock, flags);
799 gpio_unlock_as_irq(&bank->chip, offset);
800 bank->irq_usage &= ~(1 << offset);
801 _disable_gpio_module(bank, offset);
802 _reset_gpio(bank, gpio);
803 spin_unlock_irqrestore(&bank->lock, flags);
804
805 /*
806 * If this is the last IRQ to be freed in the bank,
807 * disable the bank module.
808 */
809 if (!BANK_USED(bank))
810 pm_runtime_put(bank->dev);
811 }
812
813 static void gpio_ack_irq(struct irq_data *d)
814 {
815 struct gpio_bank *bank = _irq_data_get_bank(d);
816 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
817
818 _clear_gpio_irqstatus(bank, gpio);
819 }
820
821 static void gpio_mask_irq(struct irq_data *d)
822 {
823 struct gpio_bank *bank = _irq_data_get_bank(d);
824 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
825 unsigned long flags;
826
827 spin_lock_irqsave(&bank->lock, flags);
828 _set_gpio_irqenable(bank, gpio, 0);
829 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
830 spin_unlock_irqrestore(&bank->lock, flags);
831 }
832
833 static void gpio_unmask_irq(struct irq_data *d)
834 {
835 struct gpio_bank *bank = _irq_data_get_bank(d);
836 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
837 unsigned int irq_mask = GPIO_BIT(bank, gpio);
838 u32 trigger = irqd_get_trigger_type(d);
839 unsigned long flags;
840
841 spin_lock_irqsave(&bank->lock, flags);
842 if (trigger)
843 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
844
845 /* For level-triggered GPIOs, the clearing must be done after
846 * the HW source is cleared, thus after the handler has run */
847 if (bank->level_mask & irq_mask) {
848 _set_gpio_irqenable(bank, gpio, 0);
849 _clear_gpio_irqstatus(bank, gpio);
850 }
851
852 _set_gpio_irqenable(bank, gpio, 1);
853 spin_unlock_irqrestore(&bank->lock, flags);
854 }
855
856 static struct irq_chip gpio_irq_chip = {
857 .name = "GPIO",
858 .irq_shutdown = gpio_irq_shutdown,
859 .irq_ack = gpio_ack_irq,
860 .irq_mask = gpio_mask_irq,
861 .irq_unmask = gpio_unmask_irq,
862 .irq_set_type = gpio_irq_type,
863 .irq_set_wake = gpio_wake_enable,
864 };
865
866 /*---------------------------------------------------------------------*/
867
868 static int omap_mpuio_suspend_noirq(struct device *dev)
869 {
870 struct platform_device *pdev = to_platform_device(dev);
871 struct gpio_bank *bank = platform_get_drvdata(pdev);
872 void __iomem *mask_reg = bank->base +
873 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
874 unsigned long flags;
875
876 spin_lock_irqsave(&bank->lock, flags);
877 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
878 spin_unlock_irqrestore(&bank->lock, flags);
879
880 return 0;
881 }
882
883 static int omap_mpuio_resume_noirq(struct device *dev)
884 {
885 struct platform_device *pdev = to_platform_device(dev);
886 struct gpio_bank *bank = platform_get_drvdata(pdev);
887 void __iomem *mask_reg = bank->base +
888 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
889 unsigned long flags;
890
891 spin_lock_irqsave(&bank->lock, flags);
892 writel_relaxed(bank->context.wake_en, mask_reg);
893 spin_unlock_irqrestore(&bank->lock, flags);
894
895 return 0;
896 }
897
898 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
899 .suspend_noirq = omap_mpuio_suspend_noirq,
900 .resume_noirq = omap_mpuio_resume_noirq,
901 };
902
903 /* use platform_driver for this. */
904 static struct platform_driver omap_mpuio_driver = {
905 .driver = {
906 .name = "mpuio",
907 .pm = &omap_mpuio_dev_pm_ops,
908 },
909 };
910
911 static struct platform_device omap_mpuio_device = {
912 .name = "mpuio",
913 .id = -1,
914 .dev = {
915 .driver = &omap_mpuio_driver.driver,
916 }
917 /* could list the /proc/iomem resources */
918 };
919
920 static inline void mpuio_init(struct gpio_bank *bank)
921 {
922 platform_set_drvdata(&omap_mpuio_device, bank);
923
924 if (platform_driver_register(&omap_mpuio_driver) == 0)
925 (void) platform_device_register(&omap_mpuio_device);
926 }
927
928 /*---------------------------------------------------------------------*/
929
930 static int gpio_input(struct gpio_chip *chip, unsigned offset)
931 {
932 struct gpio_bank *bank;
933 unsigned long flags;
934
935 bank = container_of(chip, struct gpio_bank, chip);
936 spin_lock_irqsave(&bank->lock, flags);
937 _set_gpio_direction(bank, offset, 1);
938 spin_unlock_irqrestore(&bank->lock, flags);
939 return 0;
940 }
941
942 static int gpio_get(struct gpio_chip *chip, unsigned offset)
943 {
944 struct gpio_bank *bank;
945 u32 mask;
946
947 bank = container_of(chip, struct gpio_bank, chip);
948 mask = (1 << offset);
949
950 if (gpio_is_input(bank, mask))
951 return _get_gpio_datain(bank, offset);
952 else
953 return _get_gpio_dataout(bank, offset);
954 }
955
956 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
957 {
958 struct gpio_bank *bank;
959 unsigned long flags;
960
961 bank = container_of(chip, struct gpio_bank, chip);
962 spin_lock_irqsave(&bank->lock, flags);
963 bank->set_dataout(bank, offset, value);
964 _set_gpio_direction(bank, offset, 0);
965 spin_unlock_irqrestore(&bank->lock, flags);
966 return 0;
967 }
968
969 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
970 unsigned debounce)
971 {
972 struct gpio_bank *bank;
973 unsigned long flags;
974
975 bank = container_of(chip, struct gpio_bank, chip);
976
977 spin_lock_irqsave(&bank->lock, flags);
978 _set_gpio_debounce(bank, offset, debounce);
979 spin_unlock_irqrestore(&bank->lock, flags);
980
981 return 0;
982 }
983
984 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
985 {
986 struct gpio_bank *bank;
987 unsigned long flags;
988
989 bank = container_of(chip, struct gpio_bank, chip);
990 spin_lock_irqsave(&bank->lock, flags);
991 bank->set_dataout(bank, offset, value);
992 spin_unlock_irqrestore(&bank->lock, flags);
993 }
994
995 /*---------------------------------------------------------------------*/
996
997 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
998 {
999 static bool called;
1000 u32 rev;
1001
1002 if (called || bank->regs->revision == USHRT_MAX)
1003 return;
1004
1005 rev = readw_relaxed(bank->base + bank->regs->revision);
1006 pr_info("OMAP GPIO hardware version %d.%d\n",
1007 (rev >> 4) & 0x0f, rev & 0x0f);
1008
1009 called = true;
1010 }
1011
1012 /* This lock class tells lockdep that GPIO irqs are in a different
1013 * category than their parents, so it won't report false recursion.
1014 */
1015 static struct lock_class_key gpio_lock_class;
1016
1017 static void omap_gpio_mod_init(struct gpio_bank *bank)
1018 {
1019 void __iomem *base = bank->base;
1020 u32 l = 0xffffffff;
1021
1022 if (bank->width == 16)
1023 l = 0xffff;
1024
1025 if (bank->is_mpuio) {
1026 writel_relaxed(l, bank->base + bank->regs->irqenable);
1027 return;
1028 }
1029
1030 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
1031 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
1032 if (bank->regs->debounce_en)
1033 writel_relaxed(0, base + bank->regs->debounce_en);
1034
1035 /* Save OE default value (0xffffffff) in the context */
1036 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1037 /* Initialize interface clk ungated, module enabled */
1038 if (bank->regs->ctrl)
1039 writel_relaxed(0, base + bank->regs->ctrl);
1040
1041 bank->dbck = clk_get(bank->dev, "dbclk");
1042 if (IS_ERR(bank->dbck))
1043 dev_err(bank->dev, "Could not get gpio dbck\n");
1044 }
1045
1046 static void
1047 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1048 unsigned int num)
1049 {
1050 struct irq_chip_generic *gc;
1051 struct irq_chip_type *ct;
1052
1053 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1054 handle_simple_irq);
1055 if (!gc) {
1056 dev_err(bank->dev, "Memory alloc failed for gc\n");
1057 return;
1058 }
1059
1060 ct = gc->chip_types;
1061
1062 /* NOTE: No ack required, reading IRQ status clears it. */
1063 ct->chip.irq_mask = irq_gc_mask_set_bit;
1064 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1065 ct->chip.irq_set_type = gpio_irq_type;
1066
1067 if (bank->regs->wkup_en)
1068 ct->chip.irq_set_wake = gpio_wake_enable;
1069
1070 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1071 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1072 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1073 }
1074
1075 static int omap_gpio_chip_init(struct gpio_bank *bank)
1076 {
1077 int j;
1078 static int gpio;
1079 int irq_base = 0;
1080 int ret;
1081
1082 /*
1083 * REVISIT eventually switch from OMAP-specific gpio structs
1084 * over to the generic ones
1085 */
1086 bank->chip.request = omap_gpio_request;
1087 bank->chip.free = omap_gpio_free;
1088 bank->chip.direction_input = gpio_input;
1089 bank->chip.get = gpio_get;
1090 bank->chip.direction_output = gpio_output;
1091 bank->chip.set_debounce = gpio_debounce;
1092 bank->chip.set = gpio_set;
1093 if (bank->is_mpuio) {
1094 bank->chip.label = "mpuio";
1095 if (bank->regs->wkup_en)
1096 bank->chip.dev = &omap_mpuio_device.dev;
1097 bank->chip.base = OMAP_MPUIO(0);
1098 } else {
1099 bank->chip.label = "gpio";
1100 bank->chip.base = gpio;
1101 gpio += bank->width;
1102 }
1103 bank->chip.ngpio = bank->width;
1104
1105 ret = gpiochip_add(&bank->chip);
1106 if (ret) {
1107 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1108 return ret;
1109 }
1110
1111 #ifdef CONFIG_ARCH_OMAP1
1112 /*
1113 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1114 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1115 */
1116 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1117 if (irq_base < 0) {
1118 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1119 return -ENODEV;
1120 }
1121 #endif
1122
1123 ret = gpiochip_irqchip_add(&bank->chip, &gpio_irq_chip,
1124 irq_base, gpio_irq_handler,
1125 IRQ_TYPE_NONE);
1126
1127 if (ret) {
1128 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1129 ret = gpiochip_remove(&bank->chip);
1130 return -ENODEV;
1131 }
1132
1133 gpiochip_set_chained_irqchip(&bank->chip, &gpio_irq_chip,
1134 bank->irq, gpio_irq_handler);
1135
1136 for (j = 0; j < bank->width; j++) {
1137 int irq = irq_find_mapping(bank->chip.irqdomain, j);
1138 irq_set_lockdep_class(irq, &gpio_lock_class);
1139 if (bank->is_mpuio) {
1140 omap_mpuio_alloc_gc(bank, irq, bank->width);
1141 irq_set_chip_and_handler(irq, NULL, NULL);
1142 set_irq_flags(irq, 0);
1143 }
1144 }
1145
1146 return 0;
1147 }
1148
1149 static const struct of_device_id omap_gpio_match[];
1150
1151 static int omap_gpio_probe(struct platform_device *pdev)
1152 {
1153 struct device *dev = &pdev->dev;
1154 struct device_node *node = dev->of_node;
1155 const struct of_device_id *match;
1156 const struct omap_gpio_platform_data *pdata;
1157 struct resource *res;
1158 struct gpio_bank *bank;
1159 int ret;
1160
1161 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1162
1163 pdata = match ? match->data : dev_get_platdata(dev);
1164 if (!pdata)
1165 return -EINVAL;
1166
1167 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1168 if (!bank) {
1169 dev_err(dev, "Memory alloc failed\n");
1170 return -ENOMEM;
1171 }
1172
1173 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1174 if (unlikely(!res)) {
1175 dev_err(dev, "Invalid IRQ resource\n");
1176 return -ENODEV;
1177 }
1178
1179 bank->irq = res->start;
1180 bank->dev = dev;
1181 bank->chip.dev = dev;
1182 bank->dbck_flag = pdata->dbck_flag;
1183 bank->stride = pdata->bank_stride;
1184 bank->width = pdata->bank_width;
1185 bank->is_mpuio = pdata->is_mpuio;
1186 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1187 bank->regs = pdata->regs;
1188 #ifdef CONFIG_OF_GPIO
1189 bank->chip.of_node = of_node_get(node);
1190 #endif
1191 if (node) {
1192 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1193 bank->loses_context = true;
1194 } else {
1195 bank->loses_context = pdata->loses_context;
1196
1197 if (bank->loses_context)
1198 bank->get_context_loss_count =
1199 pdata->get_context_loss_count;
1200 }
1201
1202 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1203 bank->set_dataout = _set_gpio_dataout_reg;
1204 else
1205 bank->set_dataout = _set_gpio_dataout_mask;
1206
1207 spin_lock_init(&bank->lock);
1208
1209 /* Static mapping, never released */
1210 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1211 bank->base = devm_ioremap_resource(dev, res);
1212 if (IS_ERR(bank->base)) {
1213 irq_domain_remove(bank->chip.irqdomain);
1214 return PTR_ERR(bank->base);
1215 }
1216
1217 platform_set_drvdata(pdev, bank);
1218
1219 pm_runtime_enable(bank->dev);
1220 pm_runtime_irq_safe(bank->dev);
1221 pm_runtime_get_sync(bank->dev);
1222
1223 if (bank->is_mpuio)
1224 mpuio_init(bank);
1225
1226 omap_gpio_mod_init(bank);
1227
1228 ret = omap_gpio_chip_init(bank);
1229 if (ret)
1230 return ret;
1231
1232 omap_gpio_show_rev(bank);
1233
1234 pm_runtime_put(bank->dev);
1235
1236 list_add_tail(&bank->node, &omap_gpio_list);
1237
1238 return 0;
1239 }
1240
1241 #ifdef CONFIG_ARCH_OMAP2PLUS
1242
1243 #if defined(CONFIG_PM_RUNTIME)
1244 static void omap_gpio_restore_context(struct gpio_bank *bank);
1245
1246 static int omap_gpio_runtime_suspend(struct device *dev)
1247 {
1248 struct platform_device *pdev = to_platform_device(dev);
1249 struct gpio_bank *bank = platform_get_drvdata(pdev);
1250 u32 l1 = 0, l2 = 0;
1251 unsigned long flags;
1252 u32 wake_low, wake_hi;
1253
1254 spin_lock_irqsave(&bank->lock, flags);
1255
1256 /*
1257 * Only edges can generate a wakeup event to the PRCM.
1258 *
1259 * Therefore, ensure any wake-up capable GPIOs have
1260 * edge-detection enabled before going idle to ensure a wakeup
1261 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1262 * NDA TRM 25.5.3.1)
1263 *
1264 * The normal values will be restored upon ->runtime_resume()
1265 * by writing back the values saved in bank->context.
1266 */
1267 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1268 if (wake_low)
1269 writel_relaxed(wake_low | bank->context.fallingdetect,
1270 bank->base + bank->regs->fallingdetect);
1271 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1272 if (wake_hi)
1273 writel_relaxed(wake_hi | bank->context.risingdetect,
1274 bank->base + bank->regs->risingdetect);
1275
1276 if (!bank->enabled_non_wakeup_gpios)
1277 goto update_gpio_context_count;
1278
1279 if (bank->power_mode != OFF_MODE) {
1280 bank->power_mode = 0;
1281 goto update_gpio_context_count;
1282 }
1283 /*
1284 * If going to OFF, remove triggering for all
1285 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1286 * generated. See OMAP2420 Errata item 1.101.
1287 */
1288 bank->saved_datain = readl_relaxed(bank->base +
1289 bank->regs->datain);
1290 l1 = bank->context.fallingdetect;
1291 l2 = bank->context.risingdetect;
1292
1293 l1 &= ~bank->enabled_non_wakeup_gpios;
1294 l2 &= ~bank->enabled_non_wakeup_gpios;
1295
1296 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1297 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1298
1299 bank->workaround_enabled = true;
1300
1301 update_gpio_context_count:
1302 if (bank->get_context_loss_count)
1303 bank->context_loss_count =
1304 bank->get_context_loss_count(bank->dev);
1305
1306 _gpio_dbck_disable(bank);
1307 spin_unlock_irqrestore(&bank->lock, flags);
1308
1309 return 0;
1310 }
1311
1312 static void omap_gpio_init_context(struct gpio_bank *p);
1313
1314 static int omap_gpio_runtime_resume(struct device *dev)
1315 {
1316 struct platform_device *pdev = to_platform_device(dev);
1317 struct gpio_bank *bank = platform_get_drvdata(pdev);
1318 u32 l = 0, gen, gen0, gen1;
1319 unsigned long flags;
1320 int c;
1321
1322 spin_lock_irqsave(&bank->lock, flags);
1323
1324 /*
1325 * On the first resume during the probe, the context has not
1326 * been initialised and so initialise it now. Also initialise
1327 * the context loss count.
1328 */
1329 if (bank->loses_context && !bank->context_valid) {
1330 omap_gpio_init_context(bank);
1331
1332 if (bank->get_context_loss_count)
1333 bank->context_loss_count =
1334 bank->get_context_loss_count(bank->dev);
1335 }
1336
1337 _gpio_dbck_enable(bank);
1338
1339 /*
1340 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1341 * GPIOs were set to edge trigger also in order to be able to
1342 * generate a PRCM wakeup. Here we restore the
1343 * pre-runtime_suspend() values for edge triggering.
1344 */
1345 writel_relaxed(bank->context.fallingdetect,
1346 bank->base + bank->regs->fallingdetect);
1347 writel_relaxed(bank->context.risingdetect,
1348 bank->base + bank->regs->risingdetect);
1349
1350 if (bank->loses_context) {
1351 if (!bank->get_context_loss_count) {
1352 omap_gpio_restore_context(bank);
1353 } else {
1354 c = bank->get_context_loss_count(bank->dev);
1355 if (c != bank->context_loss_count) {
1356 omap_gpio_restore_context(bank);
1357 } else {
1358 spin_unlock_irqrestore(&bank->lock, flags);
1359 return 0;
1360 }
1361 }
1362 }
1363
1364 if (!bank->workaround_enabled) {
1365 spin_unlock_irqrestore(&bank->lock, flags);
1366 return 0;
1367 }
1368
1369 l = readl_relaxed(bank->base + bank->regs->datain);
1370
1371 /*
1372 * Check if any of the non-wakeup interrupt GPIOs have changed
1373 * state. If so, generate an IRQ by software. This is
1374 * horribly racy, but it's the best we can do to work around
1375 * this silicon bug.
1376 */
1377 l ^= bank->saved_datain;
1378 l &= bank->enabled_non_wakeup_gpios;
1379
1380 /*
1381 * No need to generate IRQs for the rising edge for gpio IRQs
1382 * configured with falling edge only; and vice versa.
1383 */
1384 gen0 = l & bank->context.fallingdetect;
1385 gen0 &= bank->saved_datain;
1386
1387 gen1 = l & bank->context.risingdetect;
1388 gen1 &= ~(bank->saved_datain);
1389
1390 /* FIXME: Consider GPIO IRQs with level detections properly! */
1391 gen = l & (~(bank->context.fallingdetect) &
1392 ~(bank->context.risingdetect));
1393 /* Consider all GPIO IRQs needed to be updated */
1394 gen |= gen0 | gen1;
1395
1396 if (gen) {
1397 u32 old0, old1;
1398
1399 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1400 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1401
1402 if (!bank->regs->irqstatus_raw0) {
1403 writel_relaxed(old0 | gen, bank->base +
1404 bank->regs->leveldetect0);
1405 writel_relaxed(old1 | gen, bank->base +
1406 bank->regs->leveldetect1);
1407 }
1408
1409 if (bank->regs->irqstatus_raw0) {
1410 writel_relaxed(old0 | l, bank->base +
1411 bank->regs->leveldetect0);
1412 writel_relaxed(old1 | l, bank->base +
1413 bank->regs->leveldetect1);
1414 }
1415 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1416 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1417 }
1418
1419 bank->workaround_enabled = false;
1420 spin_unlock_irqrestore(&bank->lock, flags);
1421
1422 return 0;
1423 }
1424 #endif /* CONFIG_PM_RUNTIME */
1425
1426 void omap2_gpio_prepare_for_idle(int pwr_mode)
1427 {
1428 struct gpio_bank *bank;
1429
1430 list_for_each_entry(bank, &omap_gpio_list, node) {
1431 if (!BANK_USED(bank) || !bank->loses_context)
1432 continue;
1433
1434 bank->power_mode = pwr_mode;
1435
1436 pm_runtime_put_sync_suspend(bank->dev);
1437 }
1438 }
1439
1440 void omap2_gpio_resume_after_idle(void)
1441 {
1442 struct gpio_bank *bank;
1443
1444 list_for_each_entry(bank, &omap_gpio_list, node) {
1445 if (!BANK_USED(bank) || !bank->loses_context)
1446 continue;
1447
1448 pm_runtime_get_sync(bank->dev);
1449 }
1450 }
1451
1452 #if defined(CONFIG_PM_RUNTIME)
1453 static void omap_gpio_init_context(struct gpio_bank *p)
1454 {
1455 struct omap_gpio_reg_offs *regs = p->regs;
1456 void __iomem *base = p->base;
1457
1458 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1459 p->context.oe = readl_relaxed(base + regs->direction);
1460 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1461 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1462 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1463 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1464 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1465 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1466 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1467
1468 if (regs->set_dataout && p->regs->clr_dataout)
1469 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1470 else
1471 p->context.dataout = readl_relaxed(base + regs->dataout);
1472
1473 p->context_valid = true;
1474 }
1475
1476 static void omap_gpio_restore_context(struct gpio_bank *bank)
1477 {
1478 writel_relaxed(bank->context.wake_en,
1479 bank->base + bank->regs->wkup_en);
1480 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1481 writel_relaxed(bank->context.leveldetect0,
1482 bank->base + bank->regs->leveldetect0);
1483 writel_relaxed(bank->context.leveldetect1,
1484 bank->base + bank->regs->leveldetect1);
1485 writel_relaxed(bank->context.risingdetect,
1486 bank->base + bank->regs->risingdetect);
1487 writel_relaxed(bank->context.fallingdetect,
1488 bank->base + bank->regs->fallingdetect);
1489 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1490 writel_relaxed(bank->context.dataout,
1491 bank->base + bank->regs->set_dataout);
1492 else
1493 writel_relaxed(bank->context.dataout,
1494 bank->base + bank->regs->dataout);
1495 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1496
1497 if (bank->dbck_enable_mask) {
1498 writel_relaxed(bank->context.debounce, bank->base +
1499 bank->regs->debounce);
1500 writel_relaxed(bank->context.debounce_en,
1501 bank->base + bank->regs->debounce_en);
1502 }
1503
1504 writel_relaxed(bank->context.irqenable1,
1505 bank->base + bank->regs->irqenable);
1506 writel_relaxed(bank->context.irqenable2,
1507 bank->base + bank->regs->irqenable2);
1508 }
1509 #endif /* CONFIG_PM_RUNTIME */
1510 #else
1511 #define omap_gpio_runtime_suspend NULL
1512 #define omap_gpio_runtime_resume NULL
1513 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1514 #endif
1515
1516 static const struct dev_pm_ops gpio_pm_ops = {
1517 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1518 NULL)
1519 };
1520
1521 #if defined(CONFIG_OF)
1522 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1523 .revision = OMAP24XX_GPIO_REVISION,
1524 .direction = OMAP24XX_GPIO_OE,
1525 .datain = OMAP24XX_GPIO_DATAIN,
1526 .dataout = OMAP24XX_GPIO_DATAOUT,
1527 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1528 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1529 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1530 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1531 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1532 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1533 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1534 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1535 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1536 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1537 .ctrl = OMAP24XX_GPIO_CTRL,
1538 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1539 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1540 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1541 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1542 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1543 };
1544
1545 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1546 .revision = OMAP4_GPIO_REVISION,
1547 .direction = OMAP4_GPIO_OE,
1548 .datain = OMAP4_GPIO_DATAIN,
1549 .dataout = OMAP4_GPIO_DATAOUT,
1550 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1551 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1552 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1553 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1554 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1555 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1556 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1557 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1558 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1559 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1560 .ctrl = OMAP4_GPIO_CTRL,
1561 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1562 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1563 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1564 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1565 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1566 };
1567
1568 static const struct omap_gpio_platform_data omap2_pdata = {
1569 .regs = &omap2_gpio_regs,
1570 .bank_width = 32,
1571 .dbck_flag = false,
1572 };
1573
1574 static const struct omap_gpio_platform_data omap3_pdata = {
1575 .regs = &omap2_gpio_regs,
1576 .bank_width = 32,
1577 .dbck_flag = true,
1578 };
1579
1580 static const struct omap_gpio_platform_data omap4_pdata = {
1581 .regs = &omap4_gpio_regs,
1582 .bank_width = 32,
1583 .dbck_flag = true,
1584 };
1585
1586 static const struct of_device_id omap_gpio_match[] = {
1587 {
1588 .compatible = "ti,omap4-gpio",
1589 .data = &omap4_pdata,
1590 },
1591 {
1592 .compatible = "ti,omap3-gpio",
1593 .data = &omap3_pdata,
1594 },
1595 {
1596 .compatible = "ti,omap2-gpio",
1597 .data = &omap2_pdata,
1598 },
1599 { },
1600 };
1601 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1602 #endif
1603
1604 static struct platform_driver omap_gpio_driver = {
1605 .probe = omap_gpio_probe,
1606 .driver = {
1607 .name = "omap_gpio",
1608 .pm = &gpio_pm_ops,
1609 .of_match_table = of_match_ptr(omap_gpio_match),
1610 },
1611 };
1612
1613 /*
1614 * gpio driver register needs to be done before
1615 * machine_init functions access gpio APIs.
1616 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1617 */
1618 static int __init omap_gpio_drv_reg(void)
1619 {
1620 return platform_driver_register(&omap_gpio_driver);
1621 }
1622 postcore_initcall(omap_gpio_drv_reg);
Linux kernel - Deliverables
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