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gpio/omap: remove bank->method & METHOD_* macros
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <asm/gpio.h>
29 #include <asm/mach/irq.h>
30
31 static LIST_HEAD(omap_gpio_list);
32
33 struct gpio_regs {
34 u32 irqenable1;
35 u32 irqenable2;
36 u32 wake_en;
37 u32 ctrl;
38 u32 oe;
39 u32 leveldetect0;
40 u32 leveldetect1;
41 u32 risingdetect;
42 u32 fallingdetect;
43 u32 dataout;
44 };
45
46 struct gpio_bank {
47 struct list_head node;
48 unsigned long pbase;
49 void __iomem *base;
50 u16 irq;
51 u16 virtual_irq_start;
52 u32 suspend_wakeup;
53 u32 saved_wakeup;
54 u32 non_wakeup_gpios;
55 u32 enabled_non_wakeup_gpios;
56 struct gpio_regs context;
57 u32 saved_datain;
58 u32 saved_fallingdetect;
59 u32 saved_risingdetect;
60 u32 level_mask;
61 u32 toggle_mask;
62 spinlock_t lock;
63 struct gpio_chip chip;
64 struct clk *dbck;
65 u32 mod_usage;
66 u32 dbck_enable_mask;
67 struct device *dev;
68 bool is_mpuio;
69 bool dbck_flag;
70 bool loses_context;
71 int stride;
72 u32 width;
73 int context_loss_count;
74 u16 id;
75
76 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
77 int (*get_context_loss_count)(struct device *dev);
78
79 struct omap_gpio_reg_offs *regs;
80 };
81
82 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
83 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
84 #define GPIO_MOD_CTRL_BIT BIT(0)
85
86 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
87 {
88 void __iomem *reg = bank->base;
89 u32 l;
90
91 reg += bank->regs->direction;
92 l = __raw_readl(reg);
93 if (is_input)
94 l |= 1 << gpio;
95 else
96 l &= ~(1 << gpio);
97 __raw_writel(l, reg);
98 }
99
100
101 /* set data out value using dedicate set/clear register */
102 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
103 {
104 void __iomem *reg = bank->base;
105 u32 l = GPIO_BIT(bank, gpio);
106
107 if (enable)
108 reg += bank->regs->set_dataout;
109 else
110 reg += bank->regs->clr_dataout;
111
112 __raw_writel(l, reg);
113 }
114
115 /* set data out value using mask register */
116 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
117 {
118 void __iomem *reg = bank->base + bank->regs->dataout;
119 u32 gpio_bit = GPIO_BIT(bank, gpio);
120 u32 l;
121
122 l = __raw_readl(reg);
123 if (enable)
124 l |= gpio_bit;
125 else
126 l &= ~gpio_bit;
127 __raw_writel(l, reg);
128 }
129
130 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
131 {
132 void __iomem *reg = bank->base + bank->regs->datain;
133
134 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
135 }
136
137 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
138 {
139 void __iomem *reg = bank->base + bank->regs->dataout;
140
141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
142 }
143
144 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
145 {
146 int l = __raw_readl(base + reg);
147
148 if (set)
149 l |= mask;
150 else
151 l &= ~mask;
152
153 __raw_writel(l, base + reg);
154 }
155
156 /**
157 * _set_gpio_debounce - low level gpio debounce time
158 * @bank: the gpio bank we're acting upon
159 * @gpio: the gpio number on this @gpio
160 * @debounce: debounce time to use
161 *
162 * OMAP's debounce time is in 31us steps so we need
163 * to convert and round up to the closest unit.
164 */
165 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
166 unsigned debounce)
167 {
168 void __iomem *reg;
169 u32 val;
170 u32 l;
171
172 if (!bank->dbck_flag)
173 return;
174
175 if (debounce < 32)
176 debounce = 0x01;
177 else if (debounce > 7936)
178 debounce = 0xff;
179 else
180 debounce = (debounce / 0x1f) - 1;
181
182 l = GPIO_BIT(bank, gpio);
183
184 reg = bank->base + bank->regs->debounce;
185 __raw_writel(debounce, reg);
186
187 reg = bank->base + bank->regs->debounce_en;
188 val = __raw_readl(reg);
189
190 if (debounce) {
191 val |= l;
192 clk_enable(bank->dbck);
193 } else {
194 val &= ~l;
195 clk_disable(bank->dbck);
196 }
197 bank->dbck_enable_mask = val;
198
199 __raw_writel(val, reg);
200 }
201
202 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
203 int trigger)
204 {
205 void __iomem *base = bank->base;
206 u32 gpio_bit = 1 << gpio;
207
208 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
209 trigger & IRQ_TYPE_LEVEL_LOW);
210 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
211 trigger & IRQ_TYPE_LEVEL_HIGH);
212 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
213 trigger & IRQ_TYPE_EDGE_RISING);
214 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
215 trigger & IRQ_TYPE_EDGE_FALLING);
216
217 if (likely(!(bank->non_wakeup_gpios & gpio_bit)))
218 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
219
220 /* This part needs to be executed always for OMAP{34xx, 44xx} */
221 if (!bank->regs->irqctrl) {
222 /* On omap24xx proceed only when valid GPIO bit is set */
223 if (bank->non_wakeup_gpios) {
224 if (!(bank->non_wakeup_gpios & gpio_bit))
225 goto exit;
226 }
227
228 /*
229 * Log the edge gpio and manually trigger the IRQ
230 * after resume if the input level changes
231 * to avoid irq lost during PER RET/OFF mode
232 * Applies for omap2 non-wakeup gpio and all omap3 gpios
233 */
234 if (trigger & IRQ_TYPE_EDGE_BOTH)
235 bank->enabled_non_wakeup_gpios |= gpio_bit;
236 else
237 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
238 }
239
240 exit:
241 bank->level_mask =
242 __raw_readl(bank->base + bank->regs->leveldetect0) |
243 __raw_readl(bank->base + bank->regs->leveldetect1);
244 }
245
246 #ifdef CONFIG_ARCH_OMAP1
247 /*
248 * This only applies to chips that can't do both rising and falling edge
249 * detection at once. For all other chips, this function is a noop.
250 */
251 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
252 {
253 void __iomem *reg = bank->base;
254 u32 l = 0;
255
256 if (!bank->regs->irqctrl)
257 return;
258
259 reg += bank->regs->irqctrl;
260
261 l = __raw_readl(reg);
262 if ((l >> gpio) & 1)
263 l &= ~(1 << gpio);
264 else
265 l |= 1 << gpio;
266
267 __raw_writel(l, reg);
268 }
269 #else
270 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
271 #endif
272
273 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
274 {
275 void __iomem *reg = bank->base;
276 void __iomem *base = bank->base;
277 u32 l = 0;
278
279 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
280 set_gpio_trigger(bank, gpio, trigger);
281 } else if (bank->regs->irqctrl) {
282 reg += bank->regs->irqctrl;
283
284 l = __raw_readl(reg);
285 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
286 bank->toggle_mask |= 1 << gpio;
287 if (trigger & IRQ_TYPE_EDGE_RISING)
288 l |= 1 << gpio;
289 else if (trigger & IRQ_TYPE_EDGE_FALLING)
290 l &= ~(1 << gpio);
291 else
292 return -EINVAL;
293
294 __raw_writel(l, reg);
295 } else if (bank->regs->edgectrl1) {
296 if (gpio & 0x08)
297 reg += bank->regs->edgectrl2;
298 else
299 reg += bank->regs->edgectrl1;
300
301 gpio &= 0x07;
302 l = __raw_readl(reg);
303 l &= ~(3 << (gpio << 1));
304 if (trigger & IRQ_TYPE_EDGE_RISING)
305 l |= 2 << (gpio << 1);
306 if (trigger & IRQ_TYPE_EDGE_FALLING)
307 l |= 1 << (gpio << 1);
308
309 /* Enable wake-up during idle for dynamic tick */
310 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
311 __raw_writel(l, reg);
312 }
313 return 0;
314 }
315
316 static int gpio_irq_type(struct irq_data *d, unsigned type)
317 {
318 struct gpio_bank *bank;
319 unsigned gpio;
320 int retval;
321 unsigned long flags;
322
323 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
324 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
325 else
326 gpio = d->irq - IH_GPIO_BASE;
327
328 if (type & ~IRQ_TYPE_SENSE_MASK)
329 return -EINVAL;
330
331 bank = irq_data_get_irq_chip_data(d);
332
333 if (!bank->regs->leveldetect0 &&
334 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
335 return -EINVAL;
336
337 spin_lock_irqsave(&bank->lock, flags);
338 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
339 spin_unlock_irqrestore(&bank->lock, flags);
340
341 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
342 __irq_set_handler_locked(d->irq, handle_level_irq);
343 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
344 __irq_set_handler_locked(d->irq, handle_edge_irq);
345
346 return retval;
347 }
348
349 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
350 {
351 void __iomem *reg = bank->base;
352
353 reg += bank->regs->irqstatus;
354 __raw_writel(gpio_mask, reg);
355
356 /* Workaround for clearing DSP GPIO interrupts to allow retention */
357 if (bank->regs->irqstatus2) {
358 reg = bank->base + bank->regs->irqstatus2;
359 __raw_writel(gpio_mask, reg);
360 }
361
362 /* Flush posted write for the irq status to avoid spurious interrupts */
363 __raw_readl(reg);
364 }
365
366 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
367 {
368 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
369 }
370
371 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
372 {
373 void __iomem *reg = bank->base;
374 u32 l;
375 u32 mask = (1 << bank->width) - 1;
376
377 reg += bank->regs->irqenable;
378 l = __raw_readl(reg);
379 if (bank->regs->irqenable_inv)
380 l = ~l;
381 l &= mask;
382 return l;
383 }
384
385 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
386 {
387 void __iomem *reg = bank->base;
388 u32 l;
389
390 if (bank->regs->set_irqenable) {
391 reg += bank->regs->set_irqenable;
392 l = gpio_mask;
393 } else {
394 reg += bank->regs->irqenable;
395 l = __raw_readl(reg);
396 if (bank->regs->irqenable_inv)
397 l &= ~gpio_mask;
398 else
399 l |= gpio_mask;
400 }
401
402 __raw_writel(l, reg);
403 }
404
405 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
406 {
407 void __iomem *reg = bank->base;
408 u32 l;
409
410 if (bank->regs->clr_irqenable) {
411 reg += bank->regs->clr_irqenable;
412 l = gpio_mask;
413 } else {
414 reg += bank->regs->irqenable;
415 l = __raw_readl(reg);
416 if (bank->regs->irqenable_inv)
417 l |= gpio_mask;
418 else
419 l &= ~gpio_mask;
420 }
421
422 __raw_writel(l, reg);
423 }
424
425 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
426 {
427 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
428 }
429
430 /*
431 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
432 * 1510 does not seem to have a wake-up register. If JTAG is connected
433 * to the target, system will wake up always on GPIO events. While
434 * system is running all registered GPIO interrupts need to have wake-up
435 * enabled. When system is suspended, only selected GPIO interrupts need
436 * to have wake-up enabled.
437 */
438 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
439 {
440 u32 gpio_bit = GPIO_BIT(bank, gpio);
441 unsigned long flags;
442
443 if (bank->non_wakeup_gpios & gpio_bit) {
444 dev_err(bank->dev,
445 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
446 return -EINVAL;
447 }
448
449 spin_lock_irqsave(&bank->lock, flags);
450 if (enable)
451 bank->suspend_wakeup |= gpio_bit;
452 else
453 bank->suspend_wakeup &= ~gpio_bit;
454
455 spin_unlock_irqrestore(&bank->lock, flags);
456
457 return 0;
458 }
459
460 static void _reset_gpio(struct gpio_bank *bank, int gpio)
461 {
462 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
463 _set_gpio_irqenable(bank, gpio, 0);
464 _clear_gpio_irqstatus(bank, gpio);
465 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
466 }
467
468 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
469 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
470 {
471 unsigned int gpio = d->irq - IH_GPIO_BASE;
472 struct gpio_bank *bank;
473 int retval;
474
475 bank = irq_data_get_irq_chip_data(d);
476 retval = _set_gpio_wakeup(bank, gpio, enable);
477
478 return retval;
479 }
480
481 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
482 {
483 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
484 unsigned long flags;
485
486 spin_lock_irqsave(&bank->lock, flags);
487
488 /* Set trigger to none. You need to enable the desired trigger with
489 * request_irq() or set_irq_type().
490 */
491 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
492
493 if (bank->regs->pinctrl) {
494 void __iomem *reg = bank->base + bank->regs->pinctrl;
495
496 /* Claim the pin for MPU */
497 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
498 }
499
500 if (bank->regs->ctrl && !bank->mod_usage) {
501 void __iomem *reg = bank->base + bank->regs->ctrl;
502 u32 ctrl;
503
504 ctrl = __raw_readl(reg);
505 /* Module is enabled, clocks are not gated */
506 ctrl &= ~GPIO_MOD_CTRL_BIT;
507 __raw_writel(ctrl, reg);
508 }
509
510 bank->mod_usage |= 1 << offset;
511
512 spin_unlock_irqrestore(&bank->lock, flags);
513
514 return 0;
515 }
516
517 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
518 {
519 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
520 void __iomem *base = bank->base;
521 unsigned long flags;
522
523 spin_lock_irqsave(&bank->lock, flags);
524
525 if (bank->regs->wkup_en)
526 /* Disable wake-up during idle for dynamic tick */
527 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
528
529 bank->mod_usage &= ~(1 << offset);
530
531 if (bank->regs->ctrl && !bank->mod_usage) {
532 void __iomem *reg = bank->base + bank->regs->ctrl;
533 u32 ctrl;
534
535 ctrl = __raw_readl(reg);
536 /* Module is disabled, clocks are gated */
537 ctrl |= GPIO_MOD_CTRL_BIT;
538 __raw_writel(ctrl, reg);
539 }
540
541 _reset_gpio(bank, bank->chip.base + offset);
542 spin_unlock_irqrestore(&bank->lock, flags);
543 }
544
545 /*
546 * We need to unmask the GPIO bank interrupt as soon as possible to
547 * avoid missing GPIO interrupts for other lines in the bank.
548 * Then we need to mask-read-clear-unmask the triggered GPIO lines
549 * in the bank to avoid missing nested interrupts for a GPIO line.
550 * If we wait to unmask individual GPIO lines in the bank after the
551 * line's interrupt handler has been run, we may miss some nested
552 * interrupts.
553 */
554 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
555 {
556 void __iomem *isr_reg = NULL;
557 u32 isr;
558 unsigned int gpio_irq, gpio_index;
559 struct gpio_bank *bank;
560 u32 retrigger = 0;
561 int unmasked = 0;
562 struct irq_chip *chip = irq_desc_get_chip(desc);
563
564 chained_irq_enter(chip, desc);
565
566 bank = irq_get_handler_data(irq);
567 isr_reg = bank->base + bank->regs->irqstatus;
568
569 if (WARN_ON(!isr_reg))
570 goto exit;
571
572 while(1) {
573 u32 isr_saved, level_mask = 0;
574 u32 enabled;
575
576 enabled = _get_gpio_irqbank_mask(bank);
577 isr_saved = isr = __raw_readl(isr_reg) & enabled;
578
579 if (bank->level_mask)
580 level_mask = bank->level_mask & enabled;
581
582 /* clear edge sensitive interrupts before handler(s) are
583 called so that we don't miss any interrupt occurred while
584 executing them */
585 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
586 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
587 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
588
589 /* if there is only edge sensitive GPIO pin interrupts
590 configured, we could unmask GPIO bank interrupt immediately */
591 if (!level_mask && !unmasked) {
592 unmasked = 1;
593 chained_irq_exit(chip, desc);
594 }
595
596 isr |= retrigger;
597 retrigger = 0;
598 if (!isr)
599 break;
600
601 gpio_irq = bank->virtual_irq_start;
602 for (; isr != 0; isr >>= 1, gpio_irq++) {
603 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
604
605 if (!(isr & 1))
606 continue;
607
608 /*
609 * Some chips can't respond to both rising and falling
610 * at the same time. If this irq was requested with
611 * both flags, we need to flip the ICR data for the IRQ
612 * to respond to the IRQ for the opposite direction.
613 * This will be indicated in the bank toggle_mask.
614 */
615 if (bank->toggle_mask & (1 << gpio_index))
616 _toggle_gpio_edge_triggering(bank, gpio_index);
617
618 generic_handle_irq(gpio_irq);
619 }
620 }
621 /* if bank has any level sensitive GPIO pin interrupt
622 configured, we must unmask the bank interrupt only after
623 handler(s) are executed in order to avoid spurious bank
624 interrupt */
625 exit:
626 if (!unmasked)
627 chained_irq_exit(chip, desc);
628 }
629
630 static void gpio_irq_shutdown(struct irq_data *d)
631 {
632 unsigned int gpio = d->irq - IH_GPIO_BASE;
633 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
634 unsigned long flags;
635
636 spin_lock_irqsave(&bank->lock, flags);
637 _reset_gpio(bank, gpio);
638 spin_unlock_irqrestore(&bank->lock, flags);
639 }
640
641 static void gpio_ack_irq(struct irq_data *d)
642 {
643 unsigned int gpio = d->irq - IH_GPIO_BASE;
644 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
645
646 _clear_gpio_irqstatus(bank, gpio);
647 }
648
649 static void gpio_mask_irq(struct irq_data *d)
650 {
651 unsigned int gpio = d->irq - IH_GPIO_BASE;
652 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
653 unsigned long flags;
654
655 spin_lock_irqsave(&bank->lock, flags);
656 _set_gpio_irqenable(bank, gpio, 0);
657 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
658 spin_unlock_irqrestore(&bank->lock, flags);
659 }
660
661 static void gpio_unmask_irq(struct irq_data *d)
662 {
663 unsigned int gpio = d->irq - IH_GPIO_BASE;
664 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
665 unsigned int irq_mask = GPIO_BIT(bank, gpio);
666 u32 trigger = irqd_get_trigger_type(d);
667 unsigned long flags;
668
669 spin_lock_irqsave(&bank->lock, flags);
670 if (trigger)
671 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
672
673 /* For level-triggered GPIOs, the clearing must be done after
674 * the HW source is cleared, thus after the handler has run */
675 if (bank->level_mask & irq_mask) {
676 _set_gpio_irqenable(bank, gpio, 0);
677 _clear_gpio_irqstatus(bank, gpio);
678 }
679
680 _set_gpio_irqenable(bank, gpio, 1);
681 spin_unlock_irqrestore(&bank->lock, flags);
682 }
683
684 static struct irq_chip gpio_irq_chip = {
685 .name = "GPIO",
686 .irq_shutdown = gpio_irq_shutdown,
687 .irq_ack = gpio_ack_irq,
688 .irq_mask = gpio_mask_irq,
689 .irq_unmask = gpio_unmask_irq,
690 .irq_set_type = gpio_irq_type,
691 .irq_set_wake = gpio_wake_enable,
692 };
693
694 /*---------------------------------------------------------------------*/
695
696 static int omap_mpuio_suspend_noirq(struct device *dev)
697 {
698 struct platform_device *pdev = to_platform_device(dev);
699 struct gpio_bank *bank = platform_get_drvdata(pdev);
700 void __iomem *mask_reg = bank->base +
701 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
702 unsigned long flags;
703
704 spin_lock_irqsave(&bank->lock, flags);
705 bank->saved_wakeup = __raw_readl(mask_reg);
706 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
707 spin_unlock_irqrestore(&bank->lock, flags);
708
709 return 0;
710 }
711
712 static int omap_mpuio_resume_noirq(struct device *dev)
713 {
714 struct platform_device *pdev = to_platform_device(dev);
715 struct gpio_bank *bank = platform_get_drvdata(pdev);
716 void __iomem *mask_reg = bank->base +
717 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
718 unsigned long flags;
719
720 spin_lock_irqsave(&bank->lock, flags);
721 __raw_writel(bank->saved_wakeup, mask_reg);
722 spin_unlock_irqrestore(&bank->lock, flags);
723
724 return 0;
725 }
726
727 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
728 .suspend_noirq = omap_mpuio_suspend_noirq,
729 .resume_noirq = omap_mpuio_resume_noirq,
730 };
731
732 /* use platform_driver for this. */
733 static struct platform_driver omap_mpuio_driver = {
734 .driver = {
735 .name = "mpuio",
736 .pm = &omap_mpuio_dev_pm_ops,
737 },
738 };
739
740 static struct platform_device omap_mpuio_device = {
741 .name = "mpuio",
742 .id = -1,
743 .dev = {
744 .driver = &omap_mpuio_driver.driver,
745 }
746 /* could list the /proc/iomem resources */
747 };
748
749 static inline void mpuio_init(struct gpio_bank *bank)
750 {
751 platform_set_drvdata(&omap_mpuio_device, bank);
752
753 if (platform_driver_register(&omap_mpuio_driver) == 0)
754 (void) platform_device_register(&omap_mpuio_device);
755 }
756
757 /*---------------------------------------------------------------------*/
758
759 static int gpio_input(struct gpio_chip *chip, unsigned offset)
760 {
761 struct gpio_bank *bank;
762 unsigned long flags;
763
764 bank = container_of(chip, struct gpio_bank, chip);
765 spin_lock_irqsave(&bank->lock, flags);
766 _set_gpio_direction(bank, offset, 1);
767 spin_unlock_irqrestore(&bank->lock, flags);
768 return 0;
769 }
770
771 static int gpio_is_input(struct gpio_bank *bank, int mask)
772 {
773 void __iomem *reg = bank->base + bank->regs->direction;
774
775 return __raw_readl(reg) & mask;
776 }
777
778 static int gpio_get(struct gpio_chip *chip, unsigned offset)
779 {
780 struct gpio_bank *bank;
781 void __iomem *reg;
782 int gpio;
783 u32 mask;
784
785 gpio = chip->base + offset;
786 bank = container_of(chip, struct gpio_bank, chip);
787 reg = bank->base;
788 mask = GPIO_BIT(bank, gpio);
789
790 if (gpio_is_input(bank, mask))
791 return _get_gpio_datain(bank, gpio);
792 else
793 return _get_gpio_dataout(bank, gpio);
794 }
795
796 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
797 {
798 struct gpio_bank *bank;
799 unsigned long flags;
800
801 bank = container_of(chip, struct gpio_bank, chip);
802 spin_lock_irqsave(&bank->lock, flags);
803 bank->set_dataout(bank, offset, value);
804 _set_gpio_direction(bank, offset, 0);
805 spin_unlock_irqrestore(&bank->lock, flags);
806 return 0;
807 }
808
809 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
810 unsigned debounce)
811 {
812 struct gpio_bank *bank;
813 unsigned long flags;
814
815 bank = container_of(chip, struct gpio_bank, chip);
816
817 if (!bank->dbck) {
818 bank->dbck = clk_get(bank->dev, "dbclk");
819 if (IS_ERR(bank->dbck))
820 dev_err(bank->dev, "Could not get gpio dbck\n");
821 }
822
823 spin_lock_irqsave(&bank->lock, flags);
824 _set_gpio_debounce(bank, offset, debounce);
825 spin_unlock_irqrestore(&bank->lock, flags);
826
827 return 0;
828 }
829
830 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
831 {
832 struct gpio_bank *bank;
833 unsigned long flags;
834
835 bank = container_of(chip, struct gpio_bank, chip);
836 spin_lock_irqsave(&bank->lock, flags);
837 bank->set_dataout(bank, offset, value);
838 spin_unlock_irqrestore(&bank->lock, flags);
839 }
840
841 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
842 {
843 struct gpio_bank *bank;
844
845 bank = container_of(chip, struct gpio_bank, chip);
846 return bank->virtual_irq_start + offset;
847 }
848
849 /*---------------------------------------------------------------------*/
850
851 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
852 {
853 static bool called;
854 u32 rev;
855
856 if (called || bank->regs->revision == USHRT_MAX)
857 return;
858
859 rev = __raw_readw(bank->base + bank->regs->revision);
860 pr_info("OMAP GPIO hardware version %d.%d\n",
861 (rev >> 4) & 0x0f, rev & 0x0f);
862
863 called = true;
864 }
865
866 /* This lock class tells lockdep that GPIO irqs are in a different
867 * category than their parents, so it won't report false recursion.
868 */
869 static struct lock_class_key gpio_lock_class;
870
871 static void omap_gpio_mod_init(struct gpio_bank *bank)
872 {
873 void __iomem *base = bank->base;
874 u32 l = 0xffffffff;
875
876 if (bank->width == 16)
877 l = 0xffff;
878
879 if (bank->is_mpuio) {
880 __raw_writel(l, bank->base + bank->regs->irqenable);
881 return;
882 }
883
884 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
885 _gpio_rmw(base, bank->regs->irqstatus, l,
886 bank->regs->irqenable_inv == false);
887 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
888 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
889 if (bank->regs->debounce_en)
890 _gpio_rmw(base, bank->regs->debounce_en, 0, 1);
891
892 /* Initialize interface clk ungated, module enabled */
893 if (bank->regs->ctrl)
894 _gpio_rmw(base, bank->regs->ctrl, 0, 1);
895 }
896
897 static __init void
898 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
899 unsigned int num)
900 {
901 struct irq_chip_generic *gc;
902 struct irq_chip_type *ct;
903
904 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
905 handle_simple_irq);
906 if (!gc) {
907 dev_err(bank->dev, "Memory alloc failed for gc\n");
908 return;
909 }
910
911 ct = gc->chip_types;
912
913 /* NOTE: No ack required, reading IRQ status clears it. */
914 ct->chip.irq_mask = irq_gc_mask_set_bit;
915 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
916 ct->chip.irq_set_type = gpio_irq_type;
917
918 if (bank->regs->wkup_en)
919 ct->chip.irq_set_wake = gpio_wake_enable,
920
921 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
922 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
923 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
924 }
925
926 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
927 {
928 int j;
929 static int gpio;
930
931 /*
932 * REVISIT eventually switch from OMAP-specific gpio structs
933 * over to the generic ones
934 */
935 bank->chip.request = omap_gpio_request;
936 bank->chip.free = omap_gpio_free;
937 bank->chip.direction_input = gpio_input;
938 bank->chip.get = gpio_get;
939 bank->chip.direction_output = gpio_output;
940 bank->chip.set_debounce = gpio_debounce;
941 bank->chip.set = gpio_set;
942 bank->chip.to_irq = gpio_2irq;
943 if (bank->is_mpuio) {
944 bank->chip.label = "mpuio";
945 if (bank->regs->wkup_en)
946 bank->chip.dev = &omap_mpuio_device.dev;
947 bank->chip.base = OMAP_MPUIO(0);
948 } else {
949 bank->chip.label = "gpio";
950 bank->chip.base = gpio;
951 gpio += bank->width;
952 }
953 bank->chip.ngpio = bank->width;
954
955 gpiochip_add(&bank->chip);
956
957 for (j = bank->virtual_irq_start;
958 j < bank->virtual_irq_start + bank->width; j++) {
959 irq_set_lockdep_class(j, &gpio_lock_class);
960 irq_set_chip_data(j, bank);
961 if (bank->is_mpuio) {
962 omap_mpuio_alloc_gc(bank, j, bank->width);
963 } else {
964 irq_set_chip(j, &gpio_irq_chip);
965 irq_set_handler(j, handle_simple_irq);
966 set_irq_flags(j, IRQF_VALID);
967 }
968 }
969 irq_set_chained_handler(bank->irq, gpio_irq_handler);
970 irq_set_handler_data(bank->irq, bank);
971 }
972
973 static int __devinit omap_gpio_probe(struct platform_device *pdev)
974 {
975 struct omap_gpio_platform_data *pdata;
976 struct resource *res;
977 struct gpio_bank *bank;
978 int ret = 0;
979
980 if (!pdev->dev.platform_data) {
981 ret = -EINVAL;
982 goto err_exit;
983 }
984
985 bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
986 if (!bank) {
987 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
988 ret = -ENOMEM;
989 goto err_exit;
990 }
991
992 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
993 if (unlikely(!res)) {
994 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
995 pdev->id);
996 ret = -ENODEV;
997 goto err_free;
998 }
999
1000 bank->irq = res->start;
1001 bank->id = pdev->id;
1002
1003 pdata = pdev->dev.platform_data;
1004 bank->virtual_irq_start = pdata->virtual_irq_start;
1005 bank->dev = &pdev->dev;
1006 bank->dbck_flag = pdata->dbck_flag;
1007 bank->stride = pdata->bank_stride;
1008 bank->width = pdata->bank_width;
1009 bank->is_mpuio = pdata->is_mpuio;
1010 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1011 bank->loses_context = pdata->loses_context;
1012 bank->get_context_loss_count = pdata->get_context_loss_count;
1013 bank->regs = pdata->regs;
1014
1015 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1016 bank->set_dataout = _set_gpio_dataout_reg;
1017 else
1018 bank->set_dataout = _set_gpio_dataout_mask;
1019
1020 spin_lock_init(&bank->lock);
1021
1022 /* Static mapping, never released */
1023 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1024 if (unlikely(!res)) {
1025 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
1026 pdev->id);
1027 ret = -ENODEV;
1028 goto err_free;
1029 }
1030
1031 bank->base = ioremap(res->start, resource_size(res));
1032 if (!bank->base) {
1033 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
1034 pdev->id);
1035 ret = -ENOMEM;
1036 goto err_free;
1037 }
1038
1039 pm_runtime_enable(bank->dev);
1040 pm_runtime_get_sync(bank->dev);
1041
1042 if (bank->is_mpuio)
1043 mpuio_init(bank);
1044
1045 omap_gpio_mod_init(bank);
1046 omap_gpio_chip_init(bank);
1047 omap_gpio_show_rev(bank);
1048
1049 list_add_tail(&bank->node, &omap_gpio_list);
1050
1051 return ret;
1052
1053 err_free:
1054 kfree(bank);
1055 err_exit:
1056 return ret;
1057 }
1058
1059 static int omap_gpio_suspend(void)
1060 {
1061 struct gpio_bank *bank;
1062
1063 list_for_each_entry(bank, &omap_gpio_list, node) {
1064 void __iomem *base = bank->base;
1065 void __iomem *wake_status;
1066 unsigned long flags;
1067
1068 if (!bank->regs->wkup_en)
1069 return 0;
1070
1071 wake_status = bank->base + bank->regs->wkup_en;
1072
1073 spin_lock_irqsave(&bank->lock, flags);
1074 bank->saved_wakeup = __raw_readl(wake_status);
1075 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1076 _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
1077 spin_unlock_irqrestore(&bank->lock, flags);
1078 }
1079
1080 return 0;
1081 }
1082
1083 static void omap_gpio_resume(void)
1084 {
1085 struct gpio_bank *bank;
1086
1087 list_for_each_entry(bank, &omap_gpio_list, node) {
1088 void __iomem *base = bank->base;
1089 unsigned long flags;
1090
1091 if (!bank->regs->wkup_en)
1092 return;
1093
1094 spin_lock_irqsave(&bank->lock, flags);
1095 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1096 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
1097 spin_unlock_irqrestore(&bank->lock, flags);
1098 }
1099 }
1100
1101 static struct syscore_ops omap_gpio_syscore_ops = {
1102 .suspend = omap_gpio_suspend,
1103 .resume = omap_gpio_resume,
1104 };
1105
1106 #ifdef CONFIG_ARCH_OMAP2PLUS
1107
1108 static void omap_gpio_save_context(struct gpio_bank *bank);
1109 static void omap_gpio_restore_context(struct gpio_bank *bank);
1110
1111 void omap2_gpio_prepare_for_idle(int off_mode)
1112 {
1113 struct gpio_bank *bank;
1114
1115 list_for_each_entry(bank, &omap_gpio_list, node) {
1116 u32 l1 = 0, l2 = 0;
1117 int j;
1118
1119 if (!bank->loses_context)
1120 continue;
1121
1122 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1123 clk_disable(bank->dbck);
1124
1125 if (!off_mode)
1126 continue;
1127
1128 /* If going to OFF, remove triggering for all
1129 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1130 * generated. See OMAP2420 Errata item 1.101. */
1131 if (!(bank->enabled_non_wakeup_gpios))
1132 goto save_gpio_context;
1133
1134 bank->saved_datain = __raw_readl(bank->base +
1135 bank->regs->datain);
1136 l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
1137 l2 = __raw_readl(bank->base + bank->regs->risingdetect);
1138
1139 bank->saved_fallingdetect = l1;
1140 bank->saved_risingdetect = l2;
1141 l1 &= ~bank->enabled_non_wakeup_gpios;
1142 l2 &= ~bank->enabled_non_wakeup_gpios;
1143
1144 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1145 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1146
1147 save_gpio_context:
1148 if (bank->get_context_loss_count)
1149 bank->context_loss_count =
1150 bank->get_context_loss_count(bank->dev);
1151
1152 omap_gpio_save_context(bank);
1153 }
1154 }
1155
1156 void omap2_gpio_resume_after_idle(void)
1157 {
1158 struct gpio_bank *bank;
1159
1160 list_for_each_entry(bank, &omap_gpio_list, node) {
1161 int context_lost_cnt_after;
1162 u32 l = 0, gen, gen0, gen1;
1163 int j;
1164
1165 if (!bank->loses_context)
1166 continue;
1167
1168 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1169 clk_enable(bank->dbck);
1170
1171 if (bank->get_context_loss_count) {
1172 context_lost_cnt_after =
1173 bank->get_context_loss_count(bank->dev);
1174 if (context_lost_cnt_after != bank->context_loss_count
1175 || !context_lost_cnt_after)
1176 omap_gpio_restore_context(bank);
1177 }
1178
1179 if (!(bank->enabled_non_wakeup_gpios))
1180 continue;
1181
1182 __raw_writel(bank->saved_fallingdetect,
1183 bank->base + bank->regs->fallingdetect);
1184 __raw_writel(bank->saved_risingdetect,
1185 bank->base + bank->regs->risingdetect);
1186 l = __raw_readl(bank->base + bank->regs->datain);
1187
1188 /* Check if any of the non-wakeup interrupt GPIOs have changed
1189 * state. If so, generate an IRQ by software. This is
1190 * horribly racy, but it's the best we can do to work around
1191 * this silicon bug. */
1192 l ^= bank->saved_datain;
1193 l &= bank->enabled_non_wakeup_gpios;
1194
1195 /*
1196 * No need to generate IRQs for the rising edge for gpio IRQs
1197 * configured with falling edge only; and vice versa.
1198 */
1199 gen0 = l & bank->saved_fallingdetect;
1200 gen0 &= bank->saved_datain;
1201
1202 gen1 = l & bank->saved_risingdetect;
1203 gen1 &= ~(bank->saved_datain);
1204
1205 /* FIXME: Consider GPIO IRQs with level detections properly! */
1206 gen = l & (~(bank->saved_fallingdetect) &
1207 ~(bank->saved_risingdetect));
1208 /* Consider all GPIO IRQs needed to be updated */
1209 gen |= gen0 | gen1;
1210
1211 if (gen) {
1212 u32 old0, old1;
1213
1214 old0 = __raw_readl(bank->base +
1215 bank->regs->leveldetect0);
1216 old1 = __raw_readl(bank->base +
1217 bank->regs->leveldetect1);
1218
1219 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1220 old0 |= gen;
1221 old1 |= gen;
1222 }
1223
1224 if (cpu_is_omap44xx()) {
1225 old0 |= l;
1226 old1 |= l;
1227 }
1228 __raw_writel(old0, bank->base +
1229 bank->regs->leveldetect0);
1230 __raw_writel(old1, bank->base +
1231 bank->regs->leveldetect1);
1232 }
1233 }
1234 }
1235
1236 static void omap_gpio_save_context(struct gpio_bank *bank)
1237 {
1238 bank->context.irqenable1 =
1239 __raw_readl(bank->base + bank->regs->irqenable);
1240 bank->context.irqenable2 =
1241 __raw_readl(bank->base + bank->regs->irqenable2);
1242 bank->context.wake_en =
1243 __raw_readl(bank->base + bank->regs->wkup_en);
1244 bank->context.ctrl = __raw_readl(bank->base + bank->regs->ctrl);
1245 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
1246 bank->context.leveldetect0 =
1247 __raw_readl(bank->base + bank->regs->leveldetect0);
1248 bank->context.leveldetect1 =
1249 __raw_readl(bank->base + bank->regs->leveldetect1);
1250 bank->context.risingdetect =
1251 __raw_readl(bank->base + bank->regs->risingdetect);
1252 bank->context.fallingdetect =
1253 __raw_readl(bank->base + bank->regs->fallingdetect);
1254 bank->context.dataout = __raw_readl(bank->base + bank->regs->dataout);
1255 }
1256
1257 static void omap_gpio_restore_context(struct gpio_bank *bank)
1258 {
1259 __raw_writel(bank->context.irqenable1,
1260 bank->base + bank->regs->irqenable);
1261 __raw_writel(bank->context.irqenable2,
1262 bank->base + bank->regs->irqenable2);
1263 __raw_writel(bank->context.wake_en,
1264 bank->base + bank->regs->wkup_en);
1265 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1266 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1267 __raw_writel(bank->context.leveldetect0,
1268 bank->base + bank->regs->leveldetect0);
1269 __raw_writel(bank->context.leveldetect1,
1270 bank->base + bank->regs->leveldetect1);
1271 __raw_writel(bank->context.risingdetect,
1272 bank->base + bank->regs->risingdetect);
1273 __raw_writel(bank->context.fallingdetect,
1274 bank->base + bank->regs->fallingdetect);
1275 __raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
1276 }
1277 #endif
1278
1279 static struct platform_driver omap_gpio_driver = {
1280 .probe = omap_gpio_probe,
1281 .driver = {
1282 .name = "omap_gpio",
1283 },
1284 };
1285
1286 /*
1287 * gpio driver register needs to be done before
1288 * machine_init functions access gpio APIs.
1289 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1290 */
1291 static int __init omap_gpio_drv_reg(void)
1292 {
1293 return platform_driver_register(&omap_gpio_driver);
1294 }
1295 postcore_initcall(omap_gpio_drv_reg);
1296
1297 static int __init omap_gpio_sysinit(void)
1298 {
1299
1300 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1301 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1302 register_syscore_ops(&omap_gpio_syscore_ops);
1303 #endif
1304
1305 return 0;
1306 }
1307
1308 arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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