2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
35 u16 virtual_irq_start
;
37 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
42 u32 enabled_non_wakeup_gpios
;
45 u32 saved_fallingdetect
;
46 u32 saved_risingdetect
;
50 struct gpio_chip chip
;
59 #ifdef CONFIG_ARCH_OMAP3
60 struct omap3_gpio_regs
{
73 static struct omap3_gpio_regs gpio_context
[OMAP34XX_NR_GPIOS
];
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
80 static struct gpio_bank
*gpio_bank
;
82 static int bank_width
;
84 /* TODO: Analyze removing gpio_bank_count usage from driver code */
87 static inline struct gpio_bank
*get_gpio_bank(int gpio
)
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio
))
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio
))
97 return &gpio_bank
[1 + (gpio
>> 4)];
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio
))
101 return &gpio_bank
[0];
102 return &gpio_bank
[1 + (gpio
>> 5)];
104 if (cpu_is_omap24xx())
105 return &gpio_bank
[gpio
>> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank
[gpio
>> 5];
112 static inline int get_gpio_index(int gpio
)
114 if (cpu_is_omap7xx())
116 if (cpu_is_omap24xx())
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
123 static inline int gpio_valid(int gpio
)
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio
)) {
128 if (gpio
>= OMAP_MAX_GPIO_LINES
+ 16)
132 if (cpu_is_omap15xx() && gpio
< 16)
134 if ((cpu_is_omap16xx()) && gpio
< 64)
136 if (cpu_is_omap7xx() && gpio
< 192)
138 if (cpu_is_omap2420() && gpio
< 128)
140 if (cpu_is_omap2430() && gpio
< 160)
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio
< 192)
147 static int check_gpio(int gpio
)
149 if (unlikely(gpio_valid(gpio
) < 0)) {
150 printk(KERN_ERR
"omap-gpio: invalid GPIO %d\n", gpio
);
157 static void _set_gpio_direction(struct gpio_bank
*bank
, int gpio
, int is_input
)
159 void __iomem
*reg
= bank
->base
;
162 switch (bank
->method
) {
163 #ifdef CONFIG_ARCH_OMAP1
165 reg
+= OMAP_MPUIO_IO_CNTL
/ bank
->stride
;
168 #ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510
:
170 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
173 #ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610
:
175 reg
+= OMAP1610_GPIO_DIRECTION
;
178 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX
:
180 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
183 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX
:
185 reg
+= OMAP24XX_GPIO_OE
;
188 #if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX
:
190 reg
+= OMAP4_GPIO_OE
;
197 l
= __raw_readl(reg
);
202 __raw_writel(l
, reg
);
205 static void _set_gpio_dataout(struct gpio_bank
*bank
, int gpio
, int enable
)
207 void __iomem
*reg
= bank
->base
;
210 switch (bank
->method
) {
211 #ifdef CONFIG_ARCH_OMAP1
213 reg
+= OMAP_MPUIO_OUTPUT
/ bank
->stride
;
214 l
= __raw_readl(reg
);
221 #ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510
:
223 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
224 l
= __raw_readl(reg
);
231 #ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610
:
234 reg
+= OMAP1610_GPIO_SET_DATAOUT
;
236 reg
+= OMAP1610_GPIO_CLEAR_DATAOUT
;
240 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX
:
242 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
243 l
= __raw_readl(reg
);
250 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX
:
253 reg
+= OMAP24XX_GPIO_SETDATAOUT
;
255 reg
+= OMAP24XX_GPIO_CLEARDATAOUT
;
259 #ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX
:
262 reg
+= OMAP4_GPIO_SETDATAOUT
;
264 reg
+= OMAP4_GPIO_CLEARDATAOUT
;
272 __raw_writel(l
, reg
);
275 static int _get_gpio_datain(struct gpio_bank
*bank
, int gpio
)
279 if (check_gpio(gpio
) < 0)
282 switch (bank
->method
) {
283 #ifdef CONFIG_ARCH_OMAP1
285 reg
+= OMAP_MPUIO_INPUT_LATCH
/ bank
->stride
;
288 #ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510
:
290 reg
+= OMAP1510_GPIO_DATA_INPUT
;
293 #ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610
:
295 reg
+= OMAP1610_GPIO_DATAIN
;
298 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX
:
300 reg
+= OMAP7XX_GPIO_DATA_INPUT
;
303 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX
:
305 reg
+= OMAP24XX_GPIO_DATAIN
;
308 #ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX
:
310 reg
+= OMAP4_GPIO_DATAIN
;
316 return (__raw_readl(reg
)
317 & (1 << get_gpio_index(gpio
))) != 0;
320 static int _get_gpio_dataout(struct gpio_bank
*bank
, int gpio
)
324 if (check_gpio(gpio
) < 0)
328 switch (bank
->method
) {
329 #ifdef CONFIG_ARCH_OMAP1
331 reg
+= OMAP_MPUIO_OUTPUT
/ bank
->stride
;
334 #ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510
:
336 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
339 #ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610
:
341 reg
+= OMAP1610_GPIO_DATAOUT
;
344 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX
:
346 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
349 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX
:
351 reg
+= OMAP24XX_GPIO_DATAOUT
;
354 #ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX
:
356 reg
+= OMAP4_GPIO_DATAOUT
;
363 return (__raw_readl(reg
) & (1 << get_gpio_index(gpio
))) != 0;
366 #define MOD_REG_BIT(reg, bit_mask, set) \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
383 static void _set_gpio_debounce(struct gpio_bank
*bank
, unsigned gpio
,
386 void __iomem
*reg
= bank
->base
;
390 if (!bank
->dbck_flag
)
395 else if (debounce
> 7936)
398 debounce
= (debounce
/ 0x1f) - 1;
400 l
= 1 << get_gpio_index(gpio
);
402 if (bank
->method
== METHOD_GPIO_44XX
)
403 reg
+= OMAP4_GPIO_DEBOUNCINGTIME
;
405 reg
+= OMAP24XX_GPIO_DEBOUNCE_VAL
;
407 __raw_writel(debounce
, reg
);
410 if (bank
->method
== METHOD_GPIO_44XX
)
411 reg
+= OMAP4_GPIO_DEBOUNCENABLE
;
413 reg
+= OMAP24XX_GPIO_DEBOUNCE_EN
;
415 val
= __raw_readl(reg
);
419 clk_enable(bank
->dbck
);
422 clk_disable(bank
->dbck
);
424 bank
->dbck_enable_mask
= val
;
426 __raw_writel(val
, reg
);
429 #ifdef CONFIG_ARCH_OMAP2PLUS
430 static inline void set_24xx_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
433 void __iomem
*base
= bank
->base
;
434 u32 gpio_bit
= 1 << gpio
;
437 if (cpu_is_omap44xx()) {
438 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0
, gpio_bit
,
439 trigger
& IRQ_TYPE_LEVEL_LOW
);
440 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1
, gpio_bit
,
441 trigger
& IRQ_TYPE_LEVEL_HIGH
);
442 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT
, gpio_bit
,
443 trigger
& IRQ_TYPE_EDGE_RISING
);
444 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT
, gpio_bit
,
445 trigger
& IRQ_TYPE_EDGE_FALLING
);
447 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0
, gpio_bit
,
448 trigger
& IRQ_TYPE_LEVEL_LOW
);
449 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1
, gpio_bit
,
450 trigger
& IRQ_TYPE_LEVEL_HIGH
);
451 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT
, gpio_bit
,
452 trigger
& IRQ_TYPE_EDGE_RISING
);
453 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT
, gpio_bit
,
454 trigger
& IRQ_TYPE_EDGE_FALLING
);
456 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
457 if (cpu_is_omap44xx()) {
459 __raw_writel(1 << gpio
, bank
->base
+
460 OMAP4_GPIO_IRQWAKEN0
);
462 val
= __raw_readl(bank
->base
+
463 OMAP4_GPIO_IRQWAKEN0
);
464 __raw_writel(val
& (~(1 << gpio
)), bank
->base
+
465 OMAP4_GPIO_IRQWAKEN0
);
469 * GPIO wakeup request can only be generated on edge
472 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
473 __raw_writel(1 << gpio
, bank
->base
474 + OMAP24XX_GPIO_SETWKUENA
);
476 __raw_writel(1 << gpio
, bank
->base
477 + OMAP24XX_GPIO_CLEARWKUENA
);
480 /* This part needs to be executed always for OMAP34xx */
481 if (cpu_is_omap34xx() || (bank
->non_wakeup_gpios
& gpio_bit
)) {
483 * Log the edge gpio and manually trigger the IRQ
484 * after resume if the input level changes
485 * to avoid irq lost during PER RET/OFF mode
486 * Applies for omap2 non-wakeup gpio and all omap3 gpios
488 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
489 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
491 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
494 if (cpu_is_omap44xx()) {
496 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT0
) |
497 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT1
);
500 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
) |
501 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
506 #ifdef CONFIG_ARCH_OMAP1
508 * This only applies to chips that can't do both rising and falling edge
509 * detection at once. For all other chips, this function is a noop.
511 static void _toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
)
513 void __iomem
*reg
= bank
->base
;
516 switch (bank
->method
) {
518 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
/ bank
->stride
;
520 #ifdef CONFIG_ARCH_OMAP15XX
521 case METHOD_GPIO_1510
:
522 reg
+= OMAP1510_GPIO_INT_CONTROL
;
525 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
526 case METHOD_GPIO_7XX
:
527 reg
+= OMAP7XX_GPIO_INT_CONTROL
;
534 l
= __raw_readl(reg
);
540 __raw_writel(l
, reg
);
544 static int _set_gpio_triggering(struct gpio_bank
*bank
, int gpio
, int trigger
)
546 void __iomem
*reg
= bank
->base
;
549 switch (bank
->method
) {
550 #ifdef CONFIG_ARCH_OMAP1
552 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
/ bank
->stride
;
553 l
= __raw_readl(reg
);
554 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
555 bank
->toggle_mask
|= 1 << gpio
;
556 if (trigger
& IRQ_TYPE_EDGE_RISING
)
558 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
564 #ifdef CONFIG_ARCH_OMAP15XX
565 case METHOD_GPIO_1510
:
566 reg
+= OMAP1510_GPIO_INT_CONTROL
;
567 l
= __raw_readl(reg
);
568 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
569 bank
->toggle_mask
|= 1 << gpio
;
570 if (trigger
& IRQ_TYPE_EDGE_RISING
)
572 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
578 #ifdef CONFIG_ARCH_OMAP16XX
579 case METHOD_GPIO_1610
:
581 reg
+= OMAP1610_GPIO_EDGE_CTRL2
;
583 reg
+= OMAP1610_GPIO_EDGE_CTRL1
;
585 l
= __raw_readl(reg
);
586 l
&= ~(3 << (gpio
<< 1));
587 if (trigger
& IRQ_TYPE_EDGE_RISING
)
588 l
|= 2 << (gpio
<< 1);
589 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
590 l
|= 1 << (gpio
<< 1);
592 /* Enable wake-up during idle for dynamic tick */
593 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
);
595 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
);
598 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
599 case METHOD_GPIO_7XX
:
600 reg
+= OMAP7XX_GPIO_INT_CONTROL
;
601 l
= __raw_readl(reg
);
602 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
603 bank
->toggle_mask
|= 1 << gpio
;
604 if (trigger
& IRQ_TYPE_EDGE_RISING
)
606 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
612 #ifdef CONFIG_ARCH_OMAP2PLUS
613 case METHOD_GPIO_24XX
:
614 case METHOD_GPIO_44XX
:
615 set_24xx_gpio_triggering(bank
, gpio
, trigger
);
621 __raw_writel(l
, reg
);
627 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
629 struct gpio_bank
*bank
;
634 if (!cpu_class_is_omap2() && d
->irq
> IH_MPUIO_BASE
)
635 gpio
= OMAP_MPUIO(d
->irq
- IH_MPUIO_BASE
);
637 gpio
= d
->irq
- IH_GPIO_BASE
;
639 if (check_gpio(gpio
) < 0)
642 if (type
& ~IRQ_TYPE_SENSE_MASK
)
645 /* OMAP1 allows only only edge triggering */
646 if (!cpu_class_is_omap2()
647 && (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
650 bank
= irq_data_get_irq_chip_data(d
);
651 spin_lock_irqsave(&bank
->lock
, flags
);
652 retval
= _set_gpio_triggering(bank
, get_gpio_index(gpio
), type
);
653 spin_unlock_irqrestore(&bank
->lock
, flags
);
655 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
656 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
657 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
658 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
663 static void _clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
665 void __iomem
*reg
= bank
->base
;
667 switch (bank
->method
) {
668 #ifdef CONFIG_ARCH_OMAP1
670 /* MPUIO irqstatus is reset by reading the status register,
671 * so do nothing here */
674 #ifdef CONFIG_ARCH_OMAP15XX
675 case METHOD_GPIO_1510
:
676 reg
+= OMAP1510_GPIO_INT_STATUS
;
679 #ifdef CONFIG_ARCH_OMAP16XX
680 case METHOD_GPIO_1610
:
681 reg
+= OMAP1610_GPIO_IRQSTATUS1
;
684 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
685 case METHOD_GPIO_7XX
:
686 reg
+= OMAP7XX_GPIO_INT_STATUS
;
689 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
690 case METHOD_GPIO_24XX
:
691 reg
+= OMAP24XX_GPIO_IRQSTATUS1
;
694 #if defined(CONFIG_ARCH_OMAP4)
695 case METHOD_GPIO_44XX
:
696 reg
+= OMAP4_GPIO_IRQSTATUS0
;
703 __raw_writel(gpio_mask
, reg
);
705 /* Workaround for clearing DSP GPIO interrupts to allow retention */
706 if (cpu_is_omap24xx() || cpu_is_omap34xx())
707 reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS2
;
708 else if (cpu_is_omap44xx())
709 reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS1
;
711 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
712 __raw_writel(gpio_mask
, reg
);
714 /* Flush posted write for the irq status to avoid spurious interrupts */
719 static inline void _clear_gpio_irqstatus(struct gpio_bank
*bank
, int gpio
)
721 _clear_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
));
724 static u32
_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
726 void __iomem
*reg
= bank
->base
;
731 switch (bank
->method
) {
732 #ifdef CONFIG_ARCH_OMAP1
734 reg
+= OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
739 #ifdef CONFIG_ARCH_OMAP15XX
740 case METHOD_GPIO_1510
:
741 reg
+= OMAP1510_GPIO_INT_MASK
;
746 #ifdef CONFIG_ARCH_OMAP16XX
747 case METHOD_GPIO_1610
:
748 reg
+= OMAP1610_GPIO_IRQENABLE1
;
752 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
753 case METHOD_GPIO_7XX
:
754 reg
+= OMAP7XX_GPIO_INT_MASK
;
759 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
760 case METHOD_GPIO_24XX
:
761 reg
+= OMAP24XX_GPIO_IRQENABLE1
;
765 #if defined(CONFIG_ARCH_OMAP4)
766 case METHOD_GPIO_44XX
:
767 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
776 l
= __raw_readl(reg
);
783 static void _enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
, int enable
)
785 void __iomem
*reg
= bank
->base
;
788 switch (bank
->method
) {
789 #ifdef CONFIG_ARCH_OMAP1
791 reg
+= OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
792 l
= __raw_readl(reg
);
799 #ifdef CONFIG_ARCH_OMAP15XX
800 case METHOD_GPIO_1510
:
801 reg
+= OMAP1510_GPIO_INT_MASK
;
802 l
= __raw_readl(reg
);
809 #ifdef CONFIG_ARCH_OMAP16XX
810 case METHOD_GPIO_1610
:
812 reg
+= OMAP1610_GPIO_SET_IRQENABLE1
;
814 reg
+= OMAP1610_GPIO_CLEAR_IRQENABLE1
;
818 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
819 case METHOD_GPIO_7XX
:
820 reg
+= OMAP7XX_GPIO_INT_MASK
;
821 l
= __raw_readl(reg
);
828 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
829 case METHOD_GPIO_24XX
:
831 reg
+= OMAP24XX_GPIO_SETIRQENABLE1
;
833 reg
+= OMAP24XX_GPIO_CLEARIRQENABLE1
;
837 #ifdef CONFIG_ARCH_OMAP4
838 case METHOD_GPIO_44XX
:
840 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
842 reg
+= OMAP4_GPIO_IRQSTATUSCLR0
;
850 __raw_writel(l
, reg
);
853 static inline void _set_gpio_irqenable(struct gpio_bank
*bank
, int gpio
, int enable
)
855 _enable_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
), enable
);
859 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
860 * 1510 does not seem to have a wake-up register. If JTAG is connected
861 * to the target, system will wake up always on GPIO events. While
862 * system is running all registered GPIO interrupts need to have wake-up
863 * enabled. When system is suspended, only selected GPIO interrupts need
864 * to have wake-up enabled.
866 static int _set_gpio_wakeup(struct gpio_bank
*bank
, int gpio
, int enable
)
868 unsigned long uninitialized_var(flags
);
870 switch (bank
->method
) {
871 #ifdef CONFIG_ARCH_OMAP16XX
873 case METHOD_GPIO_1610
:
874 spin_lock_irqsave(&bank
->lock
, flags
);
876 bank
->suspend_wakeup
|= (1 << gpio
);
878 bank
->suspend_wakeup
&= ~(1 << gpio
);
879 spin_unlock_irqrestore(&bank
->lock
, flags
);
882 #ifdef CONFIG_ARCH_OMAP2PLUS
883 case METHOD_GPIO_24XX
:
884 case METHOD_GPIO_44XX
:
885 if (bank
->non_wakeup_gpios
& (1 << gpio
)) {
886 printk(KERN_ERR
"Unable to modify wakeup on "
887 "non-wakeup GPIO%d\n",
888 (bank
- gpio_bank
) * 32 + gpio
);
891 spin_lock_irqsave(&bank
->lock
, flags
);
893 bank
->suspend_wakeup
|= (1 << gpio
);
895 bank
->suspend_wakeup
&= ~(1 << gpio
);
896 spin_unlock_irqrestore(&bank
->lock
, flags
);
900 printk(KERN_ERR
"Can't enable GPIO wakeup for method %i\n",
906 static void _reset_gpio(struct gpio_bank
*bank
, int gpio
)
908 _set_gpio_direction(bank
, get_gpio_index(gpio
), 1);
909 _set_gpio_irqenable(bank
, gpio
, 0);
910 _clear_gpio_irqstatus(bank
, gpio
);
911 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
914 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
915 static int gpio_wake_enable(struct irq_data
*d
, unsigned int enable
)
917 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
918 struct gpio_bank
*bank
;
921 if (check_gpio(gpio
) < 0)
923 bank
= irq_data_get_irq_chip_data(d
);
924 retval
= _set_gpio_wakeup(bank
, get_gpio_index(gpio
), enable
);
929 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
931 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
934 spin_lock_irqsave(&bank
->lock
, flags
);
936 /* Set trigger to none. You need to enable the desired trigger with
937 * request_irq() or set_irq_type().
939 _set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
941 #ifdef CONFIG_ARCH_OMAP15XX
942 if (bank
->method
== METHOD_GPIO_1510
) {
945 /* Claim the pin for MPU */
946 reg
= bank
->base
+ OMAP1510_GPIO_PIN_CONTROL
;
947 __raw_writel(__raw_readl(reg
) | (1 << offset
), reg
);
950 if (!cpu_class_is_omap1()) {
951 if (!bank
->mod_usage
) {
952 void __iomem
*reg
= bank
->base
;
955 if (cpu_is_omap24xx() || cpu_is_omap34xx())
956 reg
+= OMAP24XX_GPIO_CTRL
;
957 else if (cpu_is_omap44xx())
958 reg
+= OMAP4_GPIO_CTRL
;
959 ctrl
= __raw_readl(reg
);
960 /* Module is enabled, clocks are not gated */
962 __raw_writel(ctrl
, reg
);
964 bank
->mod_usage
|= 1 << offset
;
966 spin_unlock_irqrestore(&bank
->lock
, flags
);
971 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
973 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
976 spin_lock_irqsave(&bank
->lock
, flags
);
977 #ifdef CONFIG_ARCH_OMAP16XX
978 if (bank
->method
== METHOD_GPIO_1610
) {
979 /* Disable wake-up during idle for dynamic tick */
980 void __iomem
*reg
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
981 __raw_writel(1 << offset
, reg
);
984 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
985 if (bank
->method
== METHOD_GPIO_24XX
) {
986 /* Disable wake-up during idle for dynamic tick */
987 void __iomem
*reg
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
988 __raw_writel(1 << offset
, reg
);
991 #ifdef CONFIG_ARCH_OMAP4
992 if (bank
->method
== METHOD_GPIO_44XX
) {
993 /* Disable wake-up during idle for dynamic tick */
994 void __iomem
*reg
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
995 __raw_writel(1 << offset
, reg
);
998 if (!cpu_class_is_omap1()) {
999 bank
->mod_usage
&= ~(1 << offset
);
1000 if (!bank
->mod_usage
) {
1001 void __iomem
*reg
= bank
->base
;
1004 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1005 reg
+= OMAP24XX_GPIO_CTRL
;
1006 else if (cpu_is_omap44xx())
1007 reg
+= OMAP4_GPIO_CTRL
;
1008 ctrl
= __raw_readl(reg
);
1009 /* Module is disabled, clocks are gated */
1011 __raw_writel(ctrl
, reg
);
1014 _reset_gpio(bank
, bank
->chip
.base
+ offset
);
1015 spin_unlock_irqrestore(&bank
->lock
, flags
);
1019 * We need to unmask the GPIO bank interrupt as soon as possible to
1020 * avoid missing GPIO interrupts for other lines in the bank.
1021 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1022 * in the bank to avoid missing nested interrupts for a GPIO line.
1023 * If we wait to unmask individual GPIO lines in the bank after the
1024 * line's interrupt handler has been run, we may miss some nested
1027 static void gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
1029 void __iomem
*isr_reg
= NULL
;
1031 unsigned int gpio_irq
, gpio_index
;
1032 struct gpio_bank
*bank
;
1035 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1037 chained_irq_enter(chip
, desc
);
1039 bank
= irq_get_handler_data(irq
);
1040 #ifdef CONFIG_ARCH_OMAP1
1041 if (bank
->method
== METHOD_MPUIO
)
1042 isr_reg
= bank
->base
+
1043 OMAP_MPUIO_GPIO_INT
/ bank
->stride
;
1045 #ifdef CONFIG_ARCH_OMAP15XX
1046 if (bank
->method
== METHOD_GPIO_1510
)
1047 isr_reg
= bank
->base
+ OMAP1510_GPIO_INT_STATUS
;
1049 #if defined(CONFIG_ARCH_OMAP16XX)
1050 if (bank
->method
== METHOD_GPIO_1610
)
1051 isr_reg
= bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
;
1053 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1054 if (bank
->method
== METHOD_GPIO_7XX
)
1055 isr_reg
= bank
->base
+ OMAP7XX_GPIO_INT_STATUS
;
1057 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1058 if (bank
->method
== METHOD_GPIO_24XX
)
1059 isr_reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
;
1061 #if defined(CONFIG_ARCH_OMAP4)
1062 if (bank
->method
== METHOD_GPIO_44XX
)
1063 isr_reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS0
;
1066 if (WARN_ON(!isr_reg
))
1070 u32 isr_saved
, level_mask
= 0;
1073 enabled
= _get_gpio_irqbank_mask(bank
);
1074 isr_saved
= isr
= __raw_readl(isr_reg
) & enabled
;
1076 if (cpu_is_omap15xx() && (bank
->method
== METHOD_MPUIO
))
1079 if (cpu_class_is_omap2()) {
1080 level_mask
= bank
->level_mask
& enabled
;
1083 /* clear edge sensitive interrupts before handler(s) are
1084 called so that we don't miss any interrupt occurred while
1086 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 0);
1087 _clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
1088 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 1);
1090 /* if there is only edge sensitive GPIO pin interrupts
1091 configured, we could unmask GPIO bank interrupt immediately */
1092 if (!level_mask
&& !unmasked
) {
1094 chained_irq_exit(chip
, desc
);
1102 gpio_irq
= bank
->virtual_irq_start
;
1103 for (; isr
!= 0; isr
>>= 1, gpio_irq
++) {
1104 gpio_index
= get_gpio_index(irq_to_gpio(gpio_irq
));
1109 #ifdef CONFIG_ARCH_OMAP1
1111 * Some chips can't respond to both rising and falling
1112 * at the same time. If this irq was requested with
1113 * both flags, we need to flip the ICR data for the IRQ
1114 * to respond to the IRQ for the opposite direction.
1115 * This will be indicated in the bank toggle_mask.
1117 if (bank
->toggle_mask
& (1 << gpio_index
))
1118 _toggle_gpio_edge_triggering(bank
, gpio_index
);
1121 generic_handle_irq(gpio_irq
);
1124 /* if bank has any level sensitive GPIO pin interrupt
1125 configured, we must unmask the bank interrupt only after
1126 handler(s) are executed in order to avoid spurious bank
1130 chained_irq_exit(chip
, desc
);
1133 static void gpio_irq_shutdown(struct irq_data
*d
)
1135 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
1136 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1138 _reset_gpio(bank
, gpio
);
1141 static void gpio_ack_irq(struct irq_data
*d
)
1143 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
1144 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1146 _clear_gpio_irqstatus(bank
, gpio
);
1149 static void gpio_mask_irq(struct irq_data
*d
)
1151 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
1152 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1154 _set_gpio_irqenable(bank
, gpio
, 0);
1155 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
1158 static void gpio_unmask_irq(struct irq_data
*d
)
1160 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
1161 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1162 unsigned int irq_mask
= 1 << get_gpio_index(gpio
);
1163 u32 trigger
= irqd_get_trigger_type(d
);
1166 _set_gpio_triggering(bank
, get_gpio_index(gpio
), trigger
);
1168 /* For level-triggered GPIOs, the clearing must be done after
1169 * the HW source is cleared, thus after the handler has run */
1170 if (bank
->level_mask
& irq_mask
) {
1171 _set_gpio_irqenable(bank
, gpio
, 0);
1172 _clear_gpio_irqstatus(bank
, gpio
);
1175 _set_gpio_irqenable(bank
, gpio
, 1);
1178 static struct irq_chip gpio_irq_chip
= {
1180 .irq_shutdown
= gpio_irq_shutdown
,
1181 .irq_ack
= gpio_ack_irq
,
1182 .irq_mask
= gpio_mask_irq
,
1183 .irq_unmask
= gpio_unmask_irq
,
1184 .irq_set_type
= gpio_irq_type
,
1185 .irq_set_wake
= gpio_wake_enable
,
1188 /*---------------------------------------------------------------------*/
1190 #ifdef CONFIG_ARCH_OMAP1
1192 /* MPUIO uses the always-on 32k clock */
1194 static void mpuio_ack_irq(struct irq_data
*d
)
1196 /* The ISR is reset automatically, so do nothing here. */
1199 static void mpuio_mask_irq(struct irq_data
*d
)
1201 unsigned int gpio
= OMAP_MPUIO(d
->irq
- IH_MPUIO_BASE
);
1202 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1204 _set_gpio_irqenable(bank
, gpio
, 0);
1207 static void mpuio_unmask_irq(struct irq_data
*d
)
1209 unsigned int gpio
= OMAP_MPUIO(d
->irq
- IH_MPUIO_BASE
);
1210 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1212 _set_gpio_irqenable(bank
, gpio
, 1);
1215 static struct irq_chip mpuio_irq_chip
= {
1217 .irq_ack
= mpuio_ack_irq
,
1218 .irq_mask
= mpuio_mask_irq
,
1219 .irq_unmask
= mpuio_unmask_irq
,
1220 .irq_set_type
= gpio_irq_type
,
1221 #ifdef CONFIG_ARCH_OMAP16XX
1222 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1223 .irq_set_wake
= gpio_wake_enable
,
1228 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1231 #ifdef CONFIG_ARCH_OMAP16XX
1233 #include <linux/platform_device.h>
1235 static int omap_mpuio_suspend_noirq(struct device
*dev
)
1237 struct platform_device
*pdev
= to_platform_device(dev
);
1238 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1239 void __iomem
*mask_reg
= bank
->base
+
1240 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
1241 unsigned long flags
;
1243 spin_lock_irqsave(&bank
->lock
, flags
);
1244 bank
->saved_wakeup
= __raw_readl(mask_reg
);
1245 __raw_writel(0xffff & ~bank
->suspend_wakeup
, mask_reg
);
1246 spin_unlock_irqrestore(&bank
->lock
, flags
);
1251 static int omap_mpuio_resume_noirq(struct device
*dev
)
1253 struct platform_device
*pdev
= to_platform_device(dev
);
1254 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1255 void __iomem
*mask_reg
= bank
->base
+
1256 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
1257 unsigned long flags
;
1259 spin_lock_irqsave(&bank
->lock
, flags
);
1260 __raw_writel(bank
->saved_wakeup
, mask_reg
);
1261 spin_unlock_irqrestore(&bank
->lock
, flags
);
1266 static const struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
1267 .suspend_noirq
= omap_mpuio_suspend_noirq
,
1268 .resume_noirq
= omap_mpuio_resume_noirq
,
1271 /* use platform_driver for this. */
1272 static struct platform_driver omap_mpuio_driver
= {
1275 .pm
= &omap_mpuio_dev_pm_ops
,
1279 static struct platform_device omap_mpuio_device
= {
1283 .driver
= &omap_mpuio_driver
.driver
,
1285 /* could list the /proc/iomem resources */
1288 static inline void mpuio_init(void)
1290 struct gpio_bank
*bank
= get_gpio_bank(OMAP_MPUIO(0));
1291 platform_set_drvdata(&omap_mpuio_device
, bank
);
1293 if (platform_driver_register(&omap_mpuio_driver
) == 0)
1294 (void) platform_device_register(&omap_mpuio_device
);
1298 static inline void mpuio_init(void) {}
1303 extern struct irq_chip mpuio_irq_chip
;
1305 #define bank_is_mpuio(bank) 0
1306 static inline void mpuio_init(void) {}
1310 /*---------------------------------------------------------------------*/
1312 /* REVISIT these are stupid implementations! replace by ones that
1313 * don't switch on METHOD_* and which mostly avoid spinlocks
1316 static int gpio_input(struct gpio_chip
*chip
, unsigned offset
)
1318 struct gpio_bank
*bank
;
1319 unsigned long flags
;
1321 bank
= container_of(chip
, struct gpio_bank
, chip
);
1322 spin_lock_irqsave(&bank
->lock
, flags
);
1323 _set_gpio_direction(bank
, offset
, 1);
1324 spin_unlock_irqrestore(&bank
->lock
, flags
);
1328 static int gpio_is_input(struct gpio_bank
*bank
, int mask
)
1330 void __iomem
*reg
= bank
->base
;
1332 switch (bank
->method
) {
1334 reg
+= OMAP_MPUIO_IO_CNTL
/ bank
->stride
;
1336 case METHOD_GPIO_1510
:
1337 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
1339 case METHOD_GPIO_1610
:
1340 reg
+= OMAP1610_GPIO_DIRECTION
;
1342 case METHOD_GPIO_7XX
:
1343 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
1345 case METHOD_GPIO_24XX
:
1346 reg
+= OMAP24XX_GPIO_OE
;
1348 case METHOD_GPIO_44XX
:
1349 reg
+= OMAP4_GPIO_OE
;
1352 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1355 return __raw_readl(reg
) & mask
;
1358 static int gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1360 struct gpio_bank
*bank
;
1365 gpio
= chip
->base
+ offset
;
1366 bank
= get_gpio_bank(gpio
);
1368 mask
= 1 << get_gpio_index(gpio
);
1370 if (gpio_is_input(bank
, mask
))
1371 return _get_gpio_datain(bank
, gpio
);
1373 return _get_gpio_dataout(bank
, gpio
);
1376 static int gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
1378 struct gpio_bank
*bank
;
1379 unsigned long flags
;
1381 bank
= container_of(chip
, struct gpio_bank
, chip
);
1382 spin_lock_irqsave(&bank
->lock
, flags
);
1383 _set_gpio_dataout(bank
, offset
, value
);
1384 _set_gpio_direction(bank
, offset
, 0);
1385 spin_unlock_irqrestore(&bank
->lock
, flags
);
1389 static int gpio_debounce(struct gpio_chip
*chip
, unsigned offset
,
1392 struct gpio_bank
*bank
;
1393 unsigned long flags
;
1395 bank
= container_of(chip
, struct gpio_bank
, chip
);
1398 bank
->dbck
= clk_get(bank
->dev
, "dbclk");
1399 if (IS_ERR(bank
->dbck
))
1400 dev_err(bank
->dev
, "Could not get gpio dbck\n");
1403 spin_lock_irqsave(&bank
->lock
, flags
);
1404 _set_gpio_debounce(bank
, offset
, debounce
);
1405 spin_unlock_irqrestore(&bank
->lock
, flags
);
1410 static void gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1412 struct gpio_bank
*bank
;
1413 unsigned long flags
;
1415 bank
= container_of(chip
, struct gpio_bank
, chip
);
1416 spin_lock_irqsave(&bank
->lock
, flags
);
1417 _set_gpio_dataout(bank
, offset
, value
);
1418 spin_unlock_irqrestore(&bank
->lock
, flags
);
1421 static int gpio_2irq(struct gpio_chip
*chip
, unsigned offset
)
1423 struct gpio_bank
*bank
;
1425 bank
= container_of(chip
, struct gpio_bank
, chip
);
1426 return bank
->virtual_irq_start
+ offset
;
1429 /*---------------------------------------------------------------------*/
1431 static void __init
omap_gpio_show_rev(struct gpio_bank
*bank
)
1435 if (cpu_is_omap16xx() && !(bank
->method
!= METHOD_MPUIO
))
1436 rev
= __raw_readw(bank
->base
+ OMAP1610_GPIO_REVISION
);
1437 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1438 rev
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_REVISION
);
1439 else if (cpu_is_omap44xx())
1440 rev
= __raw_readl(bank
->base
+ OMAP4_GPIO_REVISION
);
1444 printk(KERN_INFO
"OMAP GPIO hardware version %d.%d\n",
1445 (rev
>> 4) & 0x0f, rev
& 0x0f);
1448 /* This lock class tells lockdep that GPIO irqs are in a different
1449 * category than their parents, so it won't report false recursion.
1451 static struct lock_class_key gpio_lock_class
;
1453 static inline int init_gpio_info(struct platform_device
*pdev
)
1455 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1456 gpio_bank
= kzalloc(gpio_bank_count
* sizeof(struct gpio_bank
),
1459 dev_err(&pdev
->dev
, "Memory alloc failed for gpio_bank\n");
1465 /* TODO: Cleanup cpu_is_* checks */
1466 static void omap_gpio_mod_init(struct gpio_bank
*bank
, int id
)
1468 if (cpu_class_is_omap2()) {
1469 if (cpu_is_omap44xx()) {
1470 __raw_writel(0xffffffff, bank
->base
+
1471 OMAP4_GPIO_IRQSTATUSCLR0
);
1472 __raw_writel(0x00000000, bank
->base
+
1473 OMAP4_GPIO_DEBOUNCENABLE
);
1474 /* Initialize interface clk ungated, module enabled */
1475 __raw_writel(0, bank
->base
+ OMAP4_GPIO_CTRL
);
1476 } else if (cpu_is_omap34xx()) {
1477 __raw_writel(0x00000000, bank
->base
+
1478 OMAP24XX_GPIO_IRQENABLE1
);
1479 __raw_writel(0xffffffff, bank
->base
+
1480 OMAP24XX_GPIO_IRQSTATUS1
);
1481 __raw_writel(0x00000000, bank
->base
+
1482 OMAP24XX_GPIO_DEBOUNCE_EN
);
1484 /* Initialize interface clk ungated, module enabled */
1485 __raw_writel(0, bank
->base
+ OMAP24XX_GPIO_CTRL
);
1486 } else if (cpu_is_omap24xx()) {
1487 static const u32 non_wakeup_gpios
[] = {
1488 0xe203ffc0, 0x08700040
1490 if (id
< ARRAY_SIZE(non_wakeup_gpios
))
1491 bank
->non_wakeup_gpios
= non_wakeup_gpios
[id
];
1493 } else if (cpu_class_is_omap1()) {
1494 if (bank_is_mpuio(bank
))
1495 __raw_writew(0xffff, bank
->base
+
1496 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
);
1497 if (cpu_is_omap15xx() && bank
->method
== METHOD_GPIO_1510
) {
1498 __raw_writew(0xffff, bank
->base
1499 + OMAP1510_GPIO_INT_MASK
);
1500 __raw_writew(0x0000, bank
->base
1501 + OMAP1510_GPIO_INT_STATUS
);
1503 if (cpu_is_omap16xx() && bank
->method
== METHOD_GPIO_1610
) {
1504 __raw_writew(0x0000, bank
->base
1505 + OMAP1610_GPIO_IRQENABLE1
);
1506 __raw_writew(0xffff, bank
->base
1507 + OMAP1610_GPIO_IRQSTATUS1
);
1508 __raw_writew(0x0014, bank
->base
1509 + OMAP1610_GPIO_SYSCONFIG
);
1512 * Enable system clock for GPIO module.
1513 * The CAM_CLK_CTRL *is* really the right place.
1515 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL
) | 0x04,
1518 if (cpu_is_omap7xx() && bank
->method
== METHOD_GPIO_7XX
) {
1519 __raw_writel(0xffffffff, bank
->base
1520 + OMAP7XX_GPIO_INT_MASK
);
1521 __raw_writel(0x00000000, bank
->base
1522 + OMAP7XX_GPIO_INT_STATUS
);
1527 static void __init
omap_gpio_chip_init(struct gpio_bank
*bank
)
1532 bank
->mod_usage
= 0;
1534 * REVISIT eventually switch from OMAP-specific gpio structs
1535 * over to the generic ones
1537 bank
->chip
.request
= omap_gpio_request
;
1538 bank
->chip
.free
= omap_gpio_free
;
1539 bank
->chip
.direction_input
= gpio_input
;
1540 bank
->chip
.get
= gpio_get
;
1541 bank
->chip
.direction_output
= gpio_output
;
1542 bank
->chip
.set_debounce
= gpio_debounce
;
1543 bank
->chip
.set
= gpio_set
;
1544 bank
->chip
.to_irq
= gpio_2irq
;
1545 if (bank_is_mpuio(bank
)) {
1546 bank
->chip
.label
= "mpuio";
1547 #ifdef CONFIG_ARCH_OMAP16XX
1548 bank
->chip
.dev
= &omap_mpuio_device
.dev
;
1550 bank
->chip
.base
= OMAP_MPUIO(0);
1552 bank
->chip
.label
= "gpio";
1553 bank
->chip
.base
= gpio
;
1556 bank
->chip
.ngpio
= bank_width
;
1558 gpiochip_add(&bank
->chip
);
1560 for (j
= bank
->virtual_irq_start
;
1561 j
< bank
->virtual_irq_start
+ bank_width
; j
++) {
1562 irq_set_lockdep_class(j
, &gpio_lock_class
);
1563 irq_set_chip_data(j
, bank
);
1564 if (bank_is_mpuio(bank
))
1565 irq_set_chip(j
, &mpuio_irq_chip
);
1567 irq_set_chip(j
, &gpio_irq_chip
);
1568 irq_set_handler(j
, handle_simple_irq
);
1569 set_irq_flags(j
, IRQF_VALID
);
1571 irq_set_chained_handler(bank
->irq
, gpio_irq_handler
);
1572 irq_set_handler_data(bank
->irq
, bank
);
1575 static int __devinit
omap_gpio_probe(struct platform_device
*pdev
)
1577 static int gpio_init_done
;
1578 struct omap_gpio_platform_data
*pdata
;
1579 struct resource
*res
;
1581 struct gpio_bank
*bank
;
1583 if (!pdev
->dev
.platform_data
)
1586 pdata
= pdev
->dev
.platform_data
;
1588 if (!gpio_init_done
) {
1591 ret
= init_gpio_info(pdev
);
1597 bank
= &gpio_bank
[id
];
1599 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1600 if (unlikely(!res
)) {
1601 dev_err(&pdev
->dev
, "GPIO Bank %i Invalid IRQ resource\n", id
);
1605 bank
->irq
= res
->start
;
1606 bank
->virtual_irq_start
= pdata
->virtual_irq_start
;
1607 bank
->method
= pdata
->bank_type
;
1608 bank
->dev
= &pdev
->dev
;
1609 bank
->dbck_flag
= pdata
->dbck_flag
;
1610 bank
->stride
= pdata
->bank_stride
;
1611 bank_width
= pdata
->bank_width
;
1613 spin_lock_init(&bank
->lock
);
1615 /* Static mapping, never released */
1616 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1617 if (unlikely(!res
)) {
1618 dev_err(&pdev
->dev
, "GPIO Bank %i Invalid mem resource\n", id
);
1622 bank
->base
= ioremap(res
->start
, resource_size(res
));
1624 dev_err(&pdev
->dev
, "Could not ioremap gpio bank%i\n", id
);
1628 pm_runtime_enable(bank
->dev
);
1629 pm_runtime_get_sync(bank
->dev
);
1631 omap_gpio_mod_init(bank
, id
);
1632 omap_gpio_chip_init(bank
);
1633 omap_gpio_show_rev(bank
);
1635 if (!gpio_init_done
)
1641 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1642 static int omap_gpio_suspend(void)
1646 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1649 for (i
= 0; i
< gpio_bank_count
; i
++) {
1650 struct gpio_bank
*bank
= &gpio_bank
[i
];
1651 void __iomem
*wake_status
;
1652 void __iomem
*wake_clear
;
1653 void __iomem
*wake_set
;
1654 unsigned long flags
;
1656 switch (bank
->method
) {
1657 #ifdef CONFIG_ARCH_OMAP16XX
1658 case METHOD_GPIO_1610
:
1659 wake_status
= bank
->base
+ OMAP1610_GPIO_WAKEUPENABLE
;
1660 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1661 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1664 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1665 case METHOD_GPIO_24XX
:
1666 wake_status
= bank
->base
+ OMAP24XX_GPIO_WAKE_EN
;
1667 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1668 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1671 #ifdef CONFIG_ARCH_OMAP4
1672 case METHOD_GPIO_44XX
:
1673 wake_status
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1674 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1675 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1682 spin_lock_irqsave(&bank
->lock
, flags
);
1683 bank
->saved_wakeup
= __raw_readl(wake_status
);
1684 __raw_writel(0xffffffff, wake_clear
);
1685 __raw_writel(bank
->suspend_wakeup
, wake_set
);
1686 spin_unlock_irqrestore(&bank
->lock
, flags
);
1692 static void omap_gpio_resume(void)
1696 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1699 for (i
= 0; i
< gpio_bank_count
; i
++) {
1700 struct gpio_bank
*bank
= &gpio_bank
[i
];
1701 void __iomem
*wake_clear
;
1702 void __iomem
*wake_set
;
1703 unsigned long flags
;
1705 switch (bank
->method
) {
1706 #ifdef CONFIG_ARCH_OMAP16XX
1707 case METHOD_GPIO_1610
:
1708 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1709 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1712 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1713 case METHOD_GPIO_24XX
:
1714 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1715 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1718 #ifdef CONFIG_ARCH_OMAP4
1719 case METHOD_GPIO_44XX
:
1720 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1721 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1728 spin_lock_irqsave(&bank
->lock
, flags
);
1729 __raw_writel(0xffffffff, wake_clear
);
1730 __raw_writel(bank
->saved_wakeup
, wake_set
);
1731 spin_unlock_irqrestore(&bank
->lock
, flags
);
1735 static struct syscore_ops omap_gpio_syscore_ops
= {
1736 .suspend
= omap_gpio_suspend
,
1737 .resume
= omap_gpio_resume
,
1742 #ifdef CONFIG_ARCH_OMAP2PLUS
1744 static int workaround_enabled
;
1746 void omap2_gpio_prepare_for_idle(int off_mode
)
1751 if (cpu_is_omap34xx())
1754 for (i
= min
; i
< gpio_bank_count
; i
++) {
1755 struct gpio_bank
*bank
= &gpio_bank
[i
];
1759 for (j
= 0; j
< hweight_long(bank
->dbck_enable_mask
); j
++)
1760 clk_disable(bank
->dbck
);
1765 /* If going to OFF, remove triggering for all
1766 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1767 * generated. See OMAP2420 Errata item 1.101. */
1768 if (!(bank
->enabled_non_wakeup_gpios
))
1771 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1772 bank
->saved_datain
= __raw_readl(bank
->base
+
1773 OMAP24XX_GPIO_DATAIN
);
1774 l1
= __raw_readl(bank
->base
+
1775 OMAP24XX_GPIO_FALLINGDETECT
);
1776 l2
= __raw_readl(bank
->base
+
1777 OMAP24XX_GPIO_RISINGDETECT
);
1780 if (cpu_is_omap44xx()) {
1781 bank
->saved_datain
= __raw_readl(bank
->base
+
1783 l1
= __raw_readl(bank
->base
+
1784 OMAP4_GPIO_FALLINGDETECT
);
1785 l2
= __raw_readl(bank
->base
+
1786 OMAP4_GPIO_RISINGDETECT
);
1789 bank
->saved_fallingdetect
= l1
;
1790 bank
->saved_risingdetect
= l2
;
1791 l1
&= ~bank
->enabled_non_wakeup_gpios
;
1792 l2
&= ~bank
->enabled_non_wakeup_gpios
;
1794 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1795 __raw_writel(l1
, bank
->base
+
1796 OMAP24XX_GPIO_FALLINGDETECT
);
1797 __raw_writel(l2
, bank
->base
+
1798 OMAP24XX_GPIO_RISINGDETECT
);
1801 if (cpu_is_omap44xx()) {
1802 __raw_writel(l1
, bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
1803 __raw_writel(l2
, bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
1809 workaround_enabled
= 0;
1812 workaround_enabled
= 1;
1815 void omap2_gpio_resume_after_idle(void)
1820 if (cpu_is_omap34xx())
1822 for (i
= min
; i
< gpio_bank_count
; i
++) {
1823 struct gpio_bank
*bank
= &gpio_bank
[i
];
1824 u32 l
= 0, gen
, gen0
, gen1
;
1827 for (j
= 0; j
< hweight_long(bank
->dbck_enable_mask
); j
++)
1828 clk_enable(bank
->dbck
);
1830 if (!workaround_enabled
)
1833 if (!(bank
->enabled_non_wakeup_gpios
))
1836 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1837 __raw_writel(bank
->saved_fallingdetect
,
1838 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1839 __raw_writel(bank
->saved_risingdetect
,
1840 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1841 l
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
1844 if (cpu_is_omap44xx()) {
1845 __raw_writel(bank
->saved_fallingdetect
,
1846 bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
1847 __raw_writel(bank
->saved_risingdetect
,
1848 bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
1849 l
= __raw_readl(bank
->base
+ OMAP4_GPIO_DATAIN
);
1852 /* Check if any of the non-wakeup interrupt GPIOs have changed
1853 * state. If so, generate an IRQ by software. This is
1854 * horribly racy, but it's the best we can do to work around
1855 * this silicon bug. */
1856 l
^= bank
->saved_datain
;
1857 l
&= bank
->enabled_non_wakeup_gpios
;
1860 * No need to generate IRQs for the rising edge for gpio IRQs
1861 * configured with falling edge only; and vice versa.
1863 gen0
= l
& bank
->saved_fallingdetect
;
1864 gen0
&= bank
->saved_datain
;
1866 gen1
= l
& bank
->saved_risingdetect
;
1867 gen1
&= ~(bank
->saved_datain
);
1869 /* FIXME: Consider GPIO IRQs with level detections properly! */
1870 gen
= l
& (~(bank
->saved_fallingdetect
) &
1871 ~(bank
->saved_risingdetect
));
1872 /* Consider all GPIO IRQs needed to be updated */
1878 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1879 old0
= __raw_readl(bank
->base
+
1880 OMAP24XX_GPIO_LEVELDETECT0
);
1881 old1
= __raw_readl(bank
->base
+
1882 OMAP24XX_GPIO_LEVELDETECT1
);
1883 __raw_writel(old0
| gen
, bank
->base
+
1884 OMAP24XX_GPIO_LEVELDETECT0
);
1885 __raw_writel(old1
| gen
, bank
->base
+
1886 OMAP24XX_GPIO_LEVELDETECT1
);
1887 __raw_writel(old0
, bank
->base
+
1888 OMAP24XX_GPIO_LEVELDETECT0
);
1889 __raw_writel(old1
, bank
->base
+
1890 OMAP24XX_GPIO_LEVELDETECT1
);
1893 if (cpu_is_omap44xx()) {
1894 old0
= __raw_readl(bank
->base
+
1895 OMAP4_GPIO_LEVELDETECT0
);
1896 old1
= __raw_readl(bank
->base
+
1897 OMAP4_GPIO_LEVELDETECT1
);
1898 __raw_writel(old0
| l
, bank
->base
+
1899 OMAP4_GPIO_LEVELDETECT0
);
1900 __raw_writel(old1
| l
, bank
->base
+
1901 OMAP4_GPIO_LEVELDETECT1
);
1902 __raw_writel(old0
, bank
->base
+
1903 OMAP4_GPIO_LEVELDETECT0
);
1904 __raw_writel(old1
, bank
->base
+
1905 OMAP4_GPIO_LEVELDETECT1
);
1914 #ifdef CONFIG_ARCH_OMAP3
1915 /* save the registers of bank 2-6 */
1916 void omap_gpio_save_context(void)
1920 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1921 for (i
= 1; i
< gpio_bank_count
; i
++) {
1922 struct gpio_bank
*bank
= &gpio_bank
[i
];
1923 gpio_context
[i
].irqenable1
=
1924 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
1925 gpio_context
[i
].irqenable2
=
1926 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
1927 gpio_context
[i
].wake_en
=
1928 __raw_readl(bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
1929 gpio_context
[i
].ctrl
=
1930 __raw_readl(bank
->base
+ OMAP24XX_GPIO_CTRL
);
1931 gpio_context
[i
].oe
=
1932 __raw_readl(bank
->base
+ OMAP24XX_GPIO_OE
);
1933 gpio_context
[i
].leveldetect0
=
1934 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1935 gpio_context
[i
].leveldetect1
=
1936 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1937 gpio_context
[i
].risingdetect
=
1938 __raw_readl(bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1939 gpio_context
[i
].fallingdetect
=
1940 __raw_readl(bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1941 gpio_context
[i
].dataout
=
1942 __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
1946 /* restore the required registers of bank 2-6 */
1947 void omap_gpio_restore_context(void)
1951 for (i
= 1; i
< gpio_bank_count
; i
++) {
1952 struct gpio_bank
*bank
= &gpio_bank
[i
];
1953 __raw_writel(gpio_context
[i
].irqenable1
,
1954 bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
1955 __raw_writel(gpio_context
[i
].irqenable2
,
1956 bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
1957 __raw_writel(gpio_context
[i
].wake_en
,
1958 bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
1959 __raw_writel(gpio_context
[i
].ctrl
,
1960 bank
->base
+ OMAP24XX_GPIO_CTRL
);
1961 __raw_writel(gpio_context
[i
].oe
,
1962 bank
->base
+ OMAP24XX_GPIO_OE
);
1963 __raw_writel(gpio_context
[i
].leveldetect0
,
1964 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1965 __raw_writel(gpio_context
[i
].leveldetect1
,
1966 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1967 __raw_writel(gpio_context
[i
].risingdetect
,
1968 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1969 __raw_writel(gpio_context
[i
].fallingdetect
,
1970 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1971 __raw_writel(gpio_context
[i
].dataout
,
1972 bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
1977 static struct platform_driver omap_gpio_driver
= {
1978 .probe
= omap_gpio_probe
,
1980 .name
= "omap_gpio",
1985 * gpio driver register needs to be done before
1986 * machine_init functions access gpio APIs.
1987 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1989 static int __init
omap_gpio_drv_reg(void)
1991 return platform_driver_register(&omap_gpio_driver
);
1993 postcore_initcall(omap_gpio_drv_reg
);
1995 static int __init
omap_gpio_sysinit(void)
1999 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2000 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2001 register_syscore_ops(&omap_gpio_syscore_ops
);
2007 arch_initcall(omap_gpio_sysinit
);