2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
35 u16 virtual_irq_start
;
37 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
42 u32 enabled_non_wakeup_gpios
;
45 u32 saved_fallingdetect
;
46 u32 saved_risingdetect
;
50 struct gpio_chip chip
;
59 #ifdef CONFIG_ARCH_OMAP3
60 struct omap3_gpio_regs
{
73 static struct omap3_gpio_regs gpio_context
[OMAP34XX_NR_GPIOS
];
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
80 static struct gpio_bank
*gpio_bank
;
82 static int bank_width
;
84 /* TODO: Analyze removing gpio_bank_count usage from driver code */
87 static inline struct gpio_bank
*get_gpio_bank(int gpio
)
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio
))
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio
))
97 return &gpio_bank
[1 + (gpio
>> 4)];
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio
))
101 return &gpio_bank
[0];
102 return &gpio_bank
[1 + (gpio
>> 5)];
104 if (cpu_is_omap24xx())
105 return &gpio_bank
[gpio
>> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank
[gpio
>> 5];
112 static inline int get_gpio_index(int gpio
)
114 if (cpu_is_omap7xx())
116 if (cpu_is_omap24xx())
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
123 static inline int gpio_valid(int gpio
)
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio
)) {
128 if (gpio
>= OMAP_MAX_GPIO_LINES
+ 16)
132 if (cpu_is_omap15xx() && gpio
< 16)
134 if ((cpu_is_omap16xx()) && gpio
< 64)
136 if (cpu_is_omap7xx() && gpio
< 192)
138 if (cpu_is_omap2420() && gpio
< 128)
140 if (cpu_is_omap2430() && gpio
< 160)
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio
< 192)
147 static int check_gpio(int gpio
)
149 if (unlikely(gpio_valid(gpio
) < 0)) {
150 printk(KERN_ERR
"omap-gpio: invalid GPIO %d\n", gpio
);
157 static void _set_gpio_direction(struct gpio_bank
*bank
, int gpio
, int is_input
)
159 void __iomem
*reg
= bank
->base
;
162 switch (bank
->method
) {
163 #ifdef CONFIG_ARCH_OMAP1
165 reg
+= OMAP_MPUIO_IO_CNTL
/ bank
->stride
;
168 #ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510
:
170 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
173 #ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610
:
175 reg
+= OMAP1610_GPIO_DIRECTION
;
178 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX
:
180 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
183 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX
:
185 reg
+= OMAP24XX_GPIO_OE
;
188 #if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX
:
190 reg
+= OMAP4_GPIO_OE
;
197 l
= __raw_readl(reg
);
202 __raw_writel(l
, reg
);
205 static void _set_gpio_dataout(struct gpio_bank
*bank
, int gpio
, int enable
)
207 void __iomem
*reg
= bank
->base
;
210 switch (bank
->method
) {
211 #ifdef CONFIG_ARCH_OMAP1
213 reg
+= OMAP_MPUIO_OUTPUT
/ bank
->stride
;
214 l
= __raw_readl(reg
);
221 #ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510
:
223 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
224 l
= __raw_readl(reg
);
231 #ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610
:
234 reg
+= OMAP1610_GPIO_SET_DATAOUT
;
236 reg
+= OMAP1610_GPIO_CLEAR_DATAOUT
;
240 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX
:
242 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
243 l
= __raw_readl(reg
);
250 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX
:
253 reg
+= OMAP24XX_GPIO_SETDATAOUT
;
255 reg
+= OMAP24XX_GPIO_CLEARDATAOUT
;
259 #ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX
:
262 reg
+= OMAP4_GPIO_SETDATAOUT
;
264 reg
+= OMAP4_GPIO_CLEARDATAOUT
;
272 __raw_writel(l
, reg
);
275 static int _get_gpio_datain(struct gpio_bank
*bank
, int gpio
)
279 if (check_gpio(gpio
) < 0)
282 switch (bank
->method
) {
283 #ifdef CONFIG_ARCH_OMAP1
285 reg
+= OMAP_MPUIO_INPUT_LATCH
/ bank
->stride
;
288 #ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510
:
290 reg
+= OMAP1510_GPIO_DATA_INPUT
;
293 #ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610
:
295 reg
+= OMAP1610_GPIO_DATAIN
;
298 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX
:
300 reg
+= OMAP7XX_GPIO_DATA_INPUT
;
303 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX
:
305 reg
+= OMAP24XX_GPIO_DATAIN
;
308 #ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX
:
310 reg
+= OMAP4_GPIO_DATAIN
;
316 return (__raw_readl(reg
)
317 & (1 << get_gpio_index(gpio
))) != 0;
320 static int _get_gpio_dataout(struct gpio_bank
*bank
, int gpio
)
324 if (check_gpio(gpio
) < 0)
328 switch (bank
->method
) {
329 #ifdef CONFIG_ARCH_OMAP1
331 reg
+= OMAP_MPUIO_OUTPUT
/ bank
->stride
;
334 #ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510
:
336 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
339 #ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610
:
341 reg
+= OMAP1610_GPIO_DATAOUT
;
344 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX
:
346 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
349 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX
:
351 reg
+= OMAP24XX_GPIO_DATAOUT
;
354 #ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX
:
356 reg
+= OMAP4_GPIO_DATAOUT
;
363 return (__raw_readl(reg
) & (1 << get_gpio_index(gpio
))) != 0;
366 #define MOD_REG_BIT(reg, bit_mask, set) \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
383 static void _set_gpio_debounce(struct gpio_bank
*bank
, unsigned gpio
,
386 void __iomem
*reg
= bank
->base
;
390 if (!bank
->dbck_flag
)
395 else if (debounce
> 7936)
398 debounce
= (debounce
/ 0x1f) - 1;
400 l
= 1 << get_gpio_index(gpio
);
402 if (bank
->method
== METHOD_GPIO_44XX
)
403 reg
+= OMAP4_GPIO_DEBOUNCINGTIME
;
405 reg
+= OMAP24XX_GPIO_DEBOUNCE_VAL
;
407 __raw_writel(debounce
, reg
);
410 if (bank
->method
== METHOD_GPIO_44XX
)
411 reg
+= OMAP4_GPIO_DEBOUNCENABLE
;
413 reg
+= OMAP24XX_GPIO_DEBOUNCE_EN
;
415 val
= __raw_readl(reg
);
419 clk_enable(bank
->dbck
);
422 clk_disable(bank
->dbck
);
424 bank
->dbck_enable_mask
= val
;
426 __raw_writel(val
, reg
);
429 #ifdef CONFIG_ARCH_OMAP2PLUS
430 static inline void set_24xx_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
433 void __iomem
*base
= bank
->base
;
434 u32 gpio_bit
= 1 << gpio
;
436 if (cpu_is_omap44xx()) {
437 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0
, gpio_bit
,
438 trigger
& IRQ_TYPE_LEVEL_LOW
);
439 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1
, gpio_bit
,
440 trigger
& IRQ_TYPE_LEVEL_HIGH
);
441 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT
, gpio_bit
,
442 trigger
& IRQ_TYPE_EDGE_RISING
);
443 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT
, gpio_bit
,
444 trigger
& IRQ_TYPE_EDGE_FALLING
);
446 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0
, gpio_bit
,
447 trigger
& IRQ_TYPE_LEVEL_LOW
);
448 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1
, gpio_bit
,
449 trigger
& IRQ_TYPE_LEVEL_HIGH
);
450 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT
, gpio_bit
,
451 trigger
& IRQ_TYPE_EDGE_RISING
);
452 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT
, gpio_bit
,
453 trigger
& IRQ_TYPE_EDGE_FALLING
);
455 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
456 if (cpu_is_omap44xx()) {
457 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0
, gpio_bit
,
461 * GPIO wakeup request can only be generated on edge
464 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
465 __raw_writel(1 << gpio
, bank
->base
466 + OMAP24XX_GPIO_SETWKUENA
);
468 __raw_writel(1 << gpio
, bank
->base
469 + OMAP24XX_GPIO_CLEARWKUENA
);
472 /* This part needs to be executed always for OMAP34xx */
473 if (cpu_is_omap34xx() || (bank
->non_wakeup_gpios
& gpio_bit
)) {
475 * Log the edge gpio and manually trigger the IRQ
476 * after resume if the input level changes
477 * to avoid irq lost during PER RET/OFF mode
478 * Applies for omap2 non-wakeup gpio and all omap3 gpios
480 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
481 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
483 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
486 if (cpu_is_omap44xx()) {
488 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT0
) |
489 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT1
);
492 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
) |
493 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
498 #ifdef CONFIG_ARCH_OMAP1
500 * This only applies to chips that can't do both rising and falling edge
501 * detection at once. For all other chips, this function is a noop.
503 static void _toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
)
505 void __iomem
*reg
= bank
->base
;
508 switch (bank
->method
) {
510 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
/ bank
->stride
;
512 #ifdef CONFIG_ARCH_OMAP15XX
513 case METHOD_GPIO_1510
:
514 reg
+= OMAP1510_GPIO_INT_CONTROL
;
517 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
518 case METHOD_GPIO_7XX
:
519 reg
+= OMAP7XX_GPIO_INT_CONTROL
;
526 l
= __raw_readl(reg
);
532 __raw_writel(l
, reg
);
536 static int _set_gpio_triggering(struct gpio_bank
*bank
, int gpio
, int trigger
)
538 void __iomem
*reg
= bank
->base
;
541 switch (bank
->method
) {
542 #ifdef CONFIG_ARCH_OMAP1
544 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
/ bank
->stride
;
545 l
= __raw_readl(reg
);
546 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
547 bank
->toggle_mask
|= 1 << gpio
;
548 if (trigger
& IRQ_TYPE_EDGE_RISING
)
550 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
556 #ifdef CONFIG_ARCH_OMAP15XX
557 case METHOD_GPIO_1510
:
558 reg
+= OMAP1510_GPIO_INT_CONTROL
;
559 l
= __raw_readl(reg
);
560 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
561 bank
->toggle_mask
|= 1 << gpio
;
562 if (trigger
& IRQ_TYPE_EDGE_RISING
)
564 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
570 #ifdef CONFIG_ARCH_OMAP16XX
571 case METHOD_GPIO_1610
:
573 reg
+= OMAP1610_GPIO_EDGE_CTRL2
;
575 reg
+= OMAP1610_GPIO_EDGE_CTRL1
;
577 l
= __raw_readl(reg
);
578 l
&= ~(3 << (gpio
<< 1));
579 if (trigger
& IRQ_TYPE_EDGE_RISING
)
580 l
|= 2 << (gpio
<< 1);
581 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
582 l
|= 1 << (gpio
<< 1);
584 /* Enable wake-up during idle for dynamic tick */
585 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
);
587 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
);
590 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
591 case METHOD_GPIO_7XX
:
592 reg
+= OMAP7XX_GPIO_INT_CONTROL
;
593 l
= __raw_readl(reg
);
594 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
595 bank
->toggle_mask
|= 1 << gpio
;
596 if (trigger
& IRQ_TYPE_EDGE_RISING
)
598 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
604 #ifdef CONFIG_ARCH_OMAP2PLUS
605 case METHOD_GPIO_24XX
:
606 case METHOD_GPIO_44XX
:
607 set_24xx_gpio_triggering(bank
, gpio
, trigger
);
613 __raw_writel(l
, reg
);
619 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
621 struct gpio_bank
*bank
;
626 if (!cpu_class_is_omap2() && d
->irq
> IH_MPUIO_BASE
)
627 gpio
= OMAP_MPUIO(d
->irq
- IH_MPUIO_BASE
);
629 gpio
= d
->irq
- IH_GPIO_BASE
;
631 if (check_gpio(gpio
) < 0)
634 if (type
& ~IRQ_TYPE_SENSE_MASK
)
637 /* OMAP1 allows only only edge triggering */
638 if (!cpu_class_is_omap2()
639 && (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
642 bank
= irq_data_get_irq_chip_data(d
);
643 spin_lock_irqsave(&bank
->lock
, flags
);
644 retval
= _set_gpio_triggering(bank
, get_gpio_index(gpio
), type
);
645 spin_unlock_irqrestore(&bank
->lock
, flags
);
647 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
648 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
649 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
650 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
655 static void _clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
657 void __iomem
*reg
= bank
->base
;
659 switch (bank
->method
) {
660 #ifdef CONFIG_ARCH_OMAP1
662 /* MPUIO irqstatus is reset by reading the status register,
663 * so do nothing here */
666 #ifdef CONFIG_ARCH_OMAP15XX
667 case METHOD_GPIO_1510
:
668 reg
+= OMAP1510_GPIO_INT_STATUS
;
671 #ifdef CONFIG_ARCH_OMAP16XX
672 case METHOD_GPIO_1610
:
673 reg
+= OMAP1610_GPIO_IRQSTATUS1
;
676 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
677 case METHOD_GPIO_7XX
:
678 reg
+= OMAP7XX_GPIO_INT_STATUS
;
681 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
682 case METHOD_GPIO_24XX
:
683 reg
+= OMAP24XX_GPIO_IRQSTATUS1
;
686 #if defined(CONFIG_ARCH_OMAP4)
687 case METHOD_GPIO_44XX
:
688 reg
+= OMAP4_GPIO_IRQSTATUS0
;
695 __raw_writel(gpio_mask
, reg
);
697 /* Workaround for clearing DSP GPIO interrupts to allow retention */
698 if (cpu_is_omap24xx() || cpu_is_omap34xx())
699 reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS2
;
700 else if (cpu_is_omap44xx())
701 reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS1
;
703 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
704 __raw_writel(gpio_mask
, reg
);
706 /* Flush posted write for the irq status to avoid spurious interrupts */
711 static inline void _clear_gpio_irqstatus(struct gpio_bank
*bank
, int gpio
)
713 _clear_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
));
716 static u32
_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
718 void __iomem
*reg
= bank
->base
;
723 switch (bank
->method
) {
724 #ifdef CONFIG_ARCH_OMAP1
726 reg
+= OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
731 #ifdef CONFIG_ARCH_OMAP15XX
732 case METHOD_GPIO_1510
:
733 reg
+= OMAP1510_GPIO_INT_MASK
;
738 #ifdef CONFIG_ARCH_OMAP16XX
739 case METHOD_GPIO_1610
:
740 reg
+= OMAP1610_GPIO_IRQENABLE1
;
744 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
745 case METHOD_GPIO_7XX
:
746 reg
+= OMAP7XX_GPIO_INT_MASK
;
751 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
752 case METHOD_GPIO_24XX
:
753 reg
+= OMAP24XX_GPIO_IRQENABLE1
;
757 #if defined(CONFIG_ARCH_OMAP4)
758 case METHOD_GPIO_44XX
:
759 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
768 l
= __raw_readl(reg
);
775 static void _enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
, int enable
)
777 void __iomem
*reg
= bank
->base
;
780 switch (bank
->method
) {
781 #ifdef CONFIG_ARCH_OMAP1
783 reg
+= OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
784 l
= __raw_readl(reg
);
791 #ifdef CONFIG_ARCH_OMAP15XX
792 case METHOD_GPIO_1510
:
793 reg
+= OMAP1510_GPIO_INT_MASK
;
794 l
= __raw_readl(reg
);
801 #ifdef CONFIG_ARCH_OMAP16XX
802 case METHOD_GPIO_1610
:
804 reg
+= OMAP1610_GPIO_SET_IRQENABLE1
;
806 reg
+= OMAP1610_GPIO_CLEAR_IRQENABLE1
;
810 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
811 case METHOD_GPIO_7XX
:
812 reg
+= OMAP7XX_GPIO_INT_MASK
;
813 l
= __raw_readl(reg
);
820 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
821 case METHOD_GPIO_24XX
:
823 reg
+= OMAP24XX_GPIO_SETIRQENABLE1
;
825 reg
+= OMAP24XX_GPIO_CLEARIRQENABLE1
;
829 #ifdef CONFIG_ARCH_OMAP4
830 case METHOD_GPIO_44XX
:
832 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
834 reg
+= OMAP4_GPIO_IRQSTATUSCLR0
;
842 __raw_writel(l
, reg
);
845 static inline void _set_gpio_irqenable(struct gpio_bank
*bank
, int gpio
, int enable
)
847 _enable_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
), enable
);
851 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
852 * 1510 does not seem to have a wake-up register. If JTAG is connected
853 * to the target, system will wake up always on GPIO events. While
854 * system is running all registered GPIO interrupts need to have wake-up
855 * enabled. When system is suspended, only selected GPIO interrupts need
856 * to have wake-up enabled.
858 static int _set_gpio_wakeup(struct gpio_bank
*bank
, int gpio
, int enable
)
860 unsigned long uninitialized_var(flags
);
862 switch (bank
->method
) {
863 #ifdef CONFIG_ARCH_OMAP16XX
865 case METHOD_GPIO_1610
:
866 spin_lock_irqsave(&bank
->lock
, flags
);
868 bank
->suspend_wakeup
|= (1 << gpio
);
870 bank
->suspend_wakeup
&= ~(1 << gpio
);
871 spin_unlock_irqrestore(&bank
->lock
, flags
);
874 #ifdef CONFIG_ARCH_OMAP2PLUS
875 case METHOD_GPIO_24XX
:
876 case METHOD_GPIO_44XX
:
877 if (bank
->non_wakeup_gpios
& (1 << gpio
)) {
878 printk(KERN_ERR
"Unable to modify wakeup on "
879 "non-wakeup GPIO%d\n",
880 (bank
- gpio_bank
) * 32 + gpio
);
883 spin_lock_irqsave(&bank
->lock
, flags
);
885 bank
->suspend_wakeup
|= (1 << gpio
);
887 bank
->suspend_wakeup
&= ~(1 << gpio
);
888 spin_unlock_irqrestore(&bank
->lock
, flags
);
892 printk(KERN_ERR
"Can't enable GPIO wakeup for method %i\n",
898 static void _reset_gpio(struct gpio_bank
*bank
, int gpio
)
900 _set_gpio_direction(bank
, get_gpio_index(gpio
), 1);
901 _set_gpio_irqenable(bank
, gpio
, 0);
902 _clear_gpio_irqstatus(bank
, gpio
);
903 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
906 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
907 static int gpio_wake_enable(struct irq_data
*d
, unsigned int enable
)
909 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
910 struct gpio_bank
*bank
;
913 if (check_gpio(gpio
) < 0)
915 bank
= irq_data_get_irq_chip_data(d
);
916 retval
= _set_gpio_wakeup(bank
, get_gpio_index(gpio
), enable
);
921 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
923 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
926 spin_lock_irqsave(&bank
->lock
, flags
);
928 /* Set trigger to none. You need to enable the desired trigger with
929 * request_irq() or set_irq_type().
931 _set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
933 #ifdef CONFIG_ARCH_OMAP15XX
934 if (bank
->method
== METHOD_GPIO_1510
) {
937 /* Claim the pin for MPU */
938 reg
= bank
->base
+ OMAP1510_GPIO_PIN_CONTROL
;
939 __raw_writel(__raw_readl(reg
) | (1 << offset
), reg
);
942 if (!cpu_class_is_omap1()) {
943 if (!bank
->mod_usage
) {
944 void __iomem
*reg
= bank
->base
;
947 if (cpu_is_omap24xx() || cpu_is_omap34xx())
948 reg
+= OMAP24XX_GPIO_CTRL
;
949 else if (cpu_is_omap44xx())
950 reg
+= OMAP4_GPIO_CTRL
;
951 ctrl
= __raw_readl(reg
);
952 /* Module is enabled, clocks are not gated */
954 __raw_writel(ctrl
, reg
);
956 bank
->mod_usage
|= 1 << offset
;
958 spin_unlock_irqrestore(&bank
->lock
, flags
);
963 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
965 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
968 spin_lock_irqsave(&bank
->lock
, flags
);
969 #ifdef CONFIG_ARCH_OMAP16XX
970 if (bank
->method
== METHOD_GPIO_1610
) {
971 /* Disable wake-up during idle for dynamic tick */
972 void __iomem
*reg
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
973 __raw_writel(1 << offset
, reg
);
976 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
977 if (bank
->method
== METHOD_GPIO_24XX
) {
978 /* Disable wake-up during idle for dynamic tick */
979 void __iomem
*reg
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
980 __raw_writel(1 << offset
, reg
);
983 #ifdef CONFIG_ARCH_OMAP4
984 if (bank
->method
== METHOD_GPIO_44XX
) {
985 /* Disable wake-up during idle for dynamic tick */
986 void __iomem
*reg
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
987 __raw_writel(1 << offset
, reg
);
990 if (!cpu_class_is_omap1()) {
991 bank
->mod_usage
&= ~(1 << offset
);
992 if (!bank
->mod_usage
) {
993 void __iomem
*reg
= bank
->base
;
996 if (cpu_is_omap24xx() || cpu_is_omap34xx())
997 reg
+= OMAP24XX_GPIO_CTRL
;
998 else if (cpu_is_omap44xx())
999 reg
+= OMAP4_GPIO_CTRL
;
1000 ctrl
= __raw_readl(reg
);
1001 /* Module is disabled, clocks are gated */
1003 __raw_writel(ctrl
, reg
);
1006 _reset_gpio(bank
, bank
->chip
.base
+ offset
);
1007 spin_unlock_irqrestore(&bank
->lock
, flags
);
1011 * We need to unmask the GPIO bank interrupt as soon as possible to
1012 * avoid missing GPIO interrupts for other lines in the bank.
1013 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1014 * in the bank to avoid missing nested interrupts for a GPIO line.
1015 * If we wait to unmask individual GPIO lines in the bank after the
1016 * line's interrupt handler has been run, we may miss some nested
1019 static void gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
1021 void __iomem
*isr_reg
= NULL
;
1023 unsigned int gpio_irq
, gpio_index
;
1024 struct gpio_bank
*bank
;
1027 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1029 chained_irq_enter(chip
, desc
);
1031 bank
= irq_get_handler_data(irq
);
1032 #ifdef CONFIG_ARCH_OMAP1
1033 if (bank
->method
== METHOD_MPUIO
)
1034 isr_reg
= bank
->base
+
1035 OMAP_MPUIO_GPIO_INT
/ bank
->stride
;
1037 #ifdef CONFIG_ARCH_OMAP15XX
1038 if (bank
->method
== METHOD_GPIO_1510
)
1039 isr_reg
= bank
->base
+ OMAP1510_GPIO_INT_STATUS
;
1041 #if defined(CONFIG_ARCH_OMAP16XX)
1042 if (bank
->method
== METHOD_GPIO_1610
)
1043 isr_reg
= bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
;
1045 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1046 if (bank
->method
== METHOD_GPIO_7XX
)
1047 isr_reg
= bank
->base
+ OMAP7XX_GPIO_INT_STATUS
;
1049 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1050 if (bank
->method
== METHOD_GPIO_24XX
)
1051 isr_reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
;
1053 #if defined(CONFIG_ARCH_OMAP4)
1054 if (bank
->method
== METHOD_GPIO_44XX
)
1055 isr_reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS0
;
1058 if (WARN_ON(!isr_reg
))
1062 u32 isr_saved
, level_mask
= 0;
1065 enabled
= _get_gpio_irqbank_mask(bank
);
1066 isr_saved
= isr
= __raw_readl(isr_reg
) & enabled
;
1068 if (cpu_is_omap15xx() && (bank
->method
== METHOD_MPUIO
))
1071 if (cpu_class_is_omap2()) {
1072 level_mask
= bank
->level_mask
& enabled
;
1075 /* clear edge sensitive interrupts before handler(s) are
1076 called so that we don't miss any interrupt occurred while
1078 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 0);
1079 _clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
1080 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 1);
1082 /* if there is only edge sensitive GPIO pin interrupts
1083 configured, we could unmask GPIO bank interrupt immediately */
1084 if (!level_mask
&& !unmasked
) {
1086 chained_irq_exit(chip
, desc
);
1094 gpio_irq
= bank
->virtual_irq_start
;
1095 for (; isr
!= 0; isr
>>= 1, gpio_irq
++) {
1096 gpio_index
= get_gpio_index(irq_to_gpio(gpio_irq
));
1101 #ifdef CONFIG_ARCH_OMAP1
1103 * Some chips can't respond to both rising and falling
1104 * at the same time. If this irq was requested with
1105 * both flags, we need to flip the ICR data for the IRQ
1106 * to respond to the IRQ for the opposite direction.
1107 * This will be indicated in the bank toggle_mask.
1109 if (bank
->toggle_mask
& (1 << gpio_index
))
1110 _toggle_gpio_edge_triggering(bank
, gpio_index
);
1113 generic_handle_irq(gpio_irq
);
1116 /* if bank has any level sensitive GPIO pin interrupt
1117 configured, we must unmask the bank interrupt only after
1118 handler(s) are executed in order to avoid spurious bank
1122 chained_irq_exit(chip
, desc
);
1125 static void gpio_irq_shutdown(struct irq_data
*d
)
1127 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
1128 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1129 unsigned long flags
;
1131 spin_lock_irqsave(&bank
->lock
, flags
);
1132 _reset_gpio(bank
, gpio
);
1133 spin_unlock_irqrestore(&bank
->lock
, flags
);
1136 static void gpio_ack_irq(struct irq_data
*d
)
1138 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
1139 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1141 _clear_gpio_irqstatus(bank
, gpio
);
1144 static void gpio_mask_irq(struct irq_data
*d
)
1146 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
1147 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1148 unsigned long flags
;
1150 spin_lock_irqsave(&bank
->lock
, flags
);
1151 _set_gpio_irqenable(bank
, gpio
, 0);
1152 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
1153 spin_unlock_irqrestore(&bank
->lock
, flags
);
1156 static void gpio_unmask_irq(struct irq_data
*d
)
1158 unsigned int gpio
= d
->irq
- IH_GPIO_BASE
;
1159 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1160 unsigned int irq_mask
= 1 << get_gpio_index(gpio
);
1161 u32 trigger
= irqd_get_trigger_type(d
);
1162 unsigned long flags
;
1164 spin_lock_irqsave(&bank
->lock
, flags
);
1166 _set_gpio_triggering(bank
, get_gpio_index(gpio
), trigger
);
1168 /* For level-triggered GPIOs, the clearing must be done after
1169 * the HW source is cleared, thus after the handler has run */
1170 if (bank
->level_mask
& irq_mask
) {
1171 _set_gpio_irqenable(bank
, gpio
, 0);
1172 _clear_gpio_irqstatus(bank
, gpio
);
1175 _set_gpio_irqenable(bank
, gpio
, 1);
1176 spin_unlock_irqrestore(&bank
->lock
, flags
);
1179 static struct irq_chip gpio_irq_chip
= {
1181 .irq_shutdown
= gpio_irq_shutdown
,
1182 .irq_ack
= gpio_ack_irq
,
1183 .irq_mask
= gpio_mask_irq
,
1184 .irq_unmask
= gpio_unmask_irq
,
1185 .irq_set_type
= gpio_irq_type
,
1186 .irq_set_wake
= gpio_wake_enable
,
1189 /*---------------------------------------------------------------------*/
1191 #ifdef CONFIG_ARCH_OMAP1
1193 /* MPUIO uses the always-on 32k clock */
1195 static void mpuio_ack_irq(struct irq_data
*d
)
1197 /* The ISR is reset automatically, so do nothing here. */
1200 static void mpuio_mask_irq(struct irq_data
*d
)
1202 unsigned int gpio
= OMAP_MPUIO(d
->irq
- IH_MPUIO_BASE
);
1203 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1205 _set_gpio_irqenable(bank
, gpio
, 0);
1208 static void mpuio_unmask_irq(struct irq_data
*d
)
1210 unsigned int gpio
= OMAP_MPUIO(d
->irq
- IH_MPUIO_BASE
);
1211 struct gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
1213 _set_gpio_irqenable(bank
, gpio
, 1);
1216 static struct irq_chip mpuio_irq_chip
= {
1218 .irq_ack
= mpuio_ack_irq
,
1219 .irq_mask
= mpuio_mask_irq
,
1220 .irq_unmask
= mpuio_unmask_irq
,
1221 .irq_set_type
= gpio_irq_type
,
1222 #ifdef CONFIG_ARCH_OMAP16XX
1223 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1224 .irq_set_wake
= gpio_wake_enable
,
1229 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1232 #ifdef CONFIG_ARCH_OMAP16XX
1234 #include <linux/platform_device.h>
1236 static int omap_mpuio_suspend_noirq(struct device
*dev
)
1238 struct platform_device
*pdev
= to_platform_device(dev
);
1239 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1240 void __iomem
*mask_reg
= bank
->base
+
1241 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
1242 unsigned long flags
;
1244 spin_lock_irqsave(&bank
->lock
, flags
);
1245 bank
->saved_wakeup
= __raw_readl(mask_reg
);
1246 __raw_writel(0xffff & ~bank
->suspend_wakeup
, mask_reg
);
1247 spin_unlock_irqrestore(&bank
->lock
, flags
);
1252 static int omap_mpuio_resume_noirq(struct device
*dev
)
1254 struct platform_device
*pdev
= to_platform_device(dev
);
1255 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1256 void __iomem
*mask_reg
= bank
->base
+
1257 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
1258 unsigned long flags
;
1260 spin_lock_irqsave(&bank
->lock
, flags
);
1261 __raw_writel(bank
->saved_wakeup
, mask_reg
);
1262 spin_unlock_irqrestore(&bank
->lock
, flags
);
1267 static const struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
1268 .suspend_noirq
= omap_mpuio_suspend_noirq
,
1269 .resume_noirq
= omap_mpuio_resume_noirq
,
1272 /* use platform_driver for this. */
1273 static struct platform_driver omap_mpuio_driver
= {
1276 .pm
= &omap_mpuio_dev_pm_ops
,
1280 static struct platform_device omap_mpuio_device
= {
1284 .driver
= &omap_mpuio_driver
.driver
,
1286 /* could list the /proc/iomem resources */
1289 static inline void mpuio_init(void)
1291 struct gpio_bank
*bank
= get_gpio_bank(OMAP_MPUIO(0));
1292 platform_set_drvdata(&omap_mpuio_device
, bank
);
1294 if (platform_driver_register(&omap_mpuio_driver
) == 0)
1295 (void) platform_device_register(&omap_mpuio_device
);
1299 static inline void mpuio_init(void) {}
1304 extern struct irq_chip mpuio_irq_chip
;
1306 #define bank_is_mpuio(bank) 0
1307 static inline void mpuio_init(void) {}
1311 /*---------------------------------------------------------------------*/
1313 /* REVISIT these are stupid implementations! replace by ones that
1314 * don't switch on METHOD_* and which mostly avoid spinlocks
1317 static int gpio_input(struct gpio_chip
*chip
, unsigned offset
)
1319 struct gpio_bank
*bank
;
1320 unsigned long flags
;
1322 bank
= container_of(chip
, struct gpio_bank
, chip
);
1323 spin_lock_irqsave(&bank
->lock
, flags
);
1324 _set_gpio_direction(bank
, offset
, 1);
1325 spin_unlock_irqrestore(&bank
->lock
, flags
);
1329 static int gpio_is_input(struct gpio_bank
*bank
, int mask
)
1331 void __iomem
*reg
= bank
->base
;
1333 switch (bank
->method
) {
1335 reg
+= OMAP_MPUIO_IO_CNTL
/ bank
->stride
;
1337 case METHOD_GPIO_1510
:
1338 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
1340 case METHOD_GPIO_1610
:
1341 reg
+= OMAP1610_GPIO_DIRECTION
;
1343 case METHOD_GPIO_7XX
:
1344 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
1346 case METHOD_GPIO_24XX
:
1347 reg
+= OMAP24XX_GPIO_OE
;
1349 case METHOD_GPIO_44XX
:
1350 reg
+= OMAP4_GPIO_OE
;
1353 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1356 return __raw_readl(reg
) & mask
;
1359 static int gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1361 struct gpio_bank
*bank
;
1366 gpio
= chip
->base
+ offset
;
1367 bank
= get_gpio_bank(gpio
);
1369 mask
= 1 << get_gpio_index(gpio
);
1371 if (gpio_is_input(bank
, mask
))
1372 return _get_gpio_datain(bank
, gpio
);
1374 return _get_gpio_dataout(bank
, gpio
);
1377 static int gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
1379 struct gpio_bank
*bank
;
1380 unsigned long flags
;
1382 bank
= container_of(chip
, struct gpio_bank
, chip
);
1383 spin_lock_irqsave(&bank
->lock
, flags
);
1384 _set_gpio_dataout(bank
, offset
, value
);
1385 _set_gpio_direction(bank
, offset
, 0);
1386 spin_unlock_irqrestore(&bank
->lock
, flags
);
1390 static int gpio_debounce(struct gpio_chip
*chip
, unsigned offset
,
1393 struct gpio_bank
*bank
;
1394 unsigned long flags
;
1396 bank
= container_of(chip
, struct gpio_bank
, chip
);
1399 bank
->dbck
= clk_get(bank
->dev
, "dbclk");
1400 if (IS_ERR(bank
->dbck
))
1401 dev_err(bank
->dev
, "Could not get gpio dbck\n");
1404 spin_lock_irqsave(&bank
->lock
, flags
);
1405 _set_gpio_debounce(bank
, offset
, debounce
);
1406 spin_unlock_irqrestore(&bank
->lock
, flags
);
1411 static void gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1413 struct gpio_bank
*bank
;
1414 unsigned long flags
;
1416 bank
= container_of(chip
, struct gpio_bank
, chip
);
1417 spin_lock_irqsave(&bank
->lock
, flags
);
1418 _set_gpio_dataout(bank
, offset
, value
);
1419 spin_unlock_irqrestore(&bank
->lock
, flags
);
1422 static int gpio_2irq(struct gpio_chip
*chip
, unsigned offset
)
1424 struct gpio_bank
*bank
;
1426 bank
= container_of(chip
, struct gpio_bank
, chip
);
1427 return bank
->virtual_irq_start
+ offset
;
1430 /*---------------------------------------------------------------------*/
1432 static void __init
omap_gpio_show_rev(struct gpio_bank
*bank
)
1436 if (cpu_is_omap16xx() && !(bank
->method
!= METHOD_MPUIO
))
1437 rev
= __raw_readw(bank
->base
+ OMAP1610_GPIO_REVISION
);
1438 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1439 rev
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_REVISION
);
1440 else if (cpu_is_omap44xx())
1441 rev
= __raw_readl(bank
->base
+ OMAP4_GPIO_REVISION
);
1445 printk(KERN_INFO
"OMAP GPIO hardware version %d.%d\n",
1446 (rev
>> 4) & 0x0f, rev
& 0x0f);
1449 /* This lock class tells lockdep that GPIO irqs are in a different
1450 * category than their parents, so it won't report false recursion.
1452 static struct lock_class_key gpio_lock_class
;
1454 static inline int init_gpio_info(struct platform_device
*pdev
)
1456 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1457 gpio_bank
= kzalloc(gpio_bank_count
* sizeof(struct gpio_bank
),
1460 dev_err(&pdev
->dev
, "Memory alloc failed for gpio_bank\n");
1466 /* TODO: Cleanup cpu_is_* checks */
1467 static void omap_gpio_mod_init(struct gpio_bank
*bank
, int id
)
1469 if (cpu_class_is_omap2()) {
1470 if (cpu_is_omap44xx()) {
1471 __raw_writel(0xffffffff, bank
->base
+
1472 OMAP4_GPIO_IRQSTATUSCLR0
);
1473 __raw_writel(0x00000000, bank
->base
+
1474 OMAP4_GPIO_DEBOUNCENABLE
);
1475 /* Initialize interface clk ungated, module enabled */
1476 __raw_writel(0, bank
->base
+ OMAP4_GPIO_CTRL
);
1477 } else if (cpu_is_omap34xx()) {
1478 __raw_writel(0x00000000, bank
->base
+
1479 OMAP24XX_GPIO_IRQENABLE1
);
1480 __raw_writel(0xffffffff, bank
->base
+
1481 OMAP24XX_GPIO_IRQSTATUS1
);
1482 __raw_writel(0x00000000, bank
->base
+
1483 OMAP24XX_GPIO_DEBOUNCE_EN
);
1485 /* Initialize interface clk ungated, module enabled */
1486 __raw_writel(0, bank
->base
+ OMAP24XX_GPIO_CTRL
);
1487 } else if (cpu_is_omap24xx()) {
1488 static const u32 non_wakeup_gpios
[] = {
1489 0xe203ffc0, 0x08700040
1491 if (id
< ARRAY_SIZE(non_wakeup_gpios
))
1492 bank
->non_wakeup_gpios
= non_wakeup_gpios
[id
];
1494 } else if (cpu_class_is_omap1()) {
1495 if (bank_is_mpuio(bank
))
1496 __raw_writew(0xffff, bank
->base
+
1497 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
);
1498 if (cpu_is_omap15xx() && bank
->method
== METHOD_GPIO_1510
) {
1499 __raw_writew(0xffff, bank
->base
1500 + OMAP1510_GPIO_INT_MASK
);
1501 __raw_writew(0x0000, bank
->base
1502 + OMAP1510_GPIO_INT_STATUS
);
1504 if (cpu_is_omap16xx() && bank
->method
== METHOD_GPIO_1610
) {
1505 __raw_writew(0x0000, bank
->base
1506 + OMAP1610_GPIO_IRQENABLE1
);
1507 __raw_writew(0xffff, bank
->base
1508 + OMAP1610_GPIO_IRQSTATUS1
);
1509 __raw_writew(0x0014, bank
->base
1510 + OMAP1610_GPIO_SYSCONFIG
);
1513 * Enable system clock for GPIO module.
1514 * The CAM_CLK_CTRL *is* really the right place.
1516 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL
) | 0x04,
1519 if (cpu_is_omap7xx() && bank
->method
== METHOD_GPIO_7XX
) {
1520 __raw_writel(0xffffffff, bank
->base
1521 + OMAP7XX_GPIO_INT_MASK
);
1522 __raw_writel(0x00000000, bank
->base
1523 + OMAP7XX_GPIO_INT_STATUS
);
1528 static void __devinit
omap_gpio_chip_init(struct gpio_bank
*bank
)
1533 bank
->mod_usage
= 0;
1535 * REVISIT eventually switch from OMAP-specific gpio structs
1536 * over to the generic ones
1538 bank
->chip
.request
= omap_gpio_request
;
1539 bank
->chip
.free
= omap_gpio_free
;
1540 bank
->chip
.direction_input
= gpio_input
;
1541 bank
->chip
.get
= gpio_get
;
1542 bank
->chip
.direction_output
= gpio_output
;
1543 bank
->chip
.set_debounce
= gpio_debounce
;
1544 bank
->chip
.set
= gpio_set
;
1545 bank
->chip
.to_irq
= gpio_2irq
;
1546 if (bank_is_mpuio(bank
)) {
1547 bank
->chip
.label
= "mpuio";
1548 #ifdef CONFIG_ARCH_OMAP16XX
1549 bank
->chip
.dev
= &omap_mpuio_device
.dev
;
1551 bank
->chip
.base
= OMAP_MPUIO(0);
1553 bank
->chip
.label
= "gpio";
1554 bank
->chip
.base
= gpio
;
1557 bank
->chip
.ngpio
= bank_width
;
1559 gpiochip_add(&bank
->chip
);
1561 for (j
= bank
->virtual_irq_start
;
1562 j
< bank
->virtual_irq_start
+ bank_width
; j
++) {
1563 irq_set_lockdep_class(j
, &gpio_lock_class
);
1564 irq_set_chip_data(j
, bank
);
1565 if (bank_is_mpuio(bank
))
1566 irq_set_chip(j
, &mpuio_irq_chip
);
1568 irq_set_chip(j
, &gpio_irq_chip
);
1569 irq_set_handler(j
, handle_simple_irq
);
1570 set_irq_flags(j
, IRQF_VALID
);
1572 irq_set_chained_handler(bank
->irq
, gpio_irq_handler
);
1573 irq_set_handler_data(bank
->irq
, bank
);
1576 static int __devinit
omap_gpio_probe(struct platform_device
*pdev
)
1578 static int gpio_init_done
;
1579 struct omap_gpio_platform_data
*pdata
;
1580 struct resource
*res
;
1582 struct gpio_bank
*bank
;
1584 if (!pdev
->dev
.platform_data
)
1587 pdata
= pdev
->dev
.platform_data
;
1589 if (!gpio_init_done
) {
1592 ret
= init_gpio_info(pdev
);
1598 bank
= &gpio_bank
[id
];
1600 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1601 if (unlikely(!res
)) {
1602 dev_err(&pdev
->dev
, "GPIO Bank %i Invalid IRQ resource\n", id
);
1606 bank
->irq
= res
->start
;
1607 bank
->virtual_irq_start
= pdata
->virtual_irq_start
;
1608 bank
->method
= pdata
->bank_type
;
1609 bank
->dev
= &pdev
->dev
;
1610 bank
->dbck_flag
= pdata
->dbck_flag
;
1611 bank
->stride
= pdata
->bank_stride
;
1612 bank_width
= pdata
->bank_width
;
1614 spin_lock_init(&bank
->lock
);
1616 /* Static mapping, never released */
1617 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1618 if (unlikely(!res
)) {
1619 dev_err(&pdev
->dev
, "GPIO Bank %i Invalid mem resource\n", id
);
1623 bank
->base
= ioremap(res
->start
, resource_size(res
));
1625 dev_err(&pdev
->dev
, "Could not ioremap gpio bank%i\n", id
);
1629 pm_runtime_enable(bank
->dev
);
1630 pm_runtime_get_sync(bank
->dev
);
1632 omap_gpio_mod_init(bank
, id
);
1633 omap_gpio_chip_init(bank
);
1634 omap_gpio_show_rev(bank
);
1636 if (!gpio_init_done
)
1642 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1643 static int omap_gpio_suspend(void)
1647 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1650 for (i
= 0; i
< gpio_bank_count
; i
++) {
1651 struct gpio_bank
*bank
= &gpio_bank
[i
];
1652 void __iomem
*wake_status
;
1653 void __iomem
*wake_clear
;
1654 void __iomem
*wake_set
;
1655 unsigned long flags
;
1657 switch (bank
->method
) {
1658 #ifdef CONFIG_ARCH_OMAP16XX
1659 case METHOD_GPIO_1610
:
1660 wake_status
= bank
->base
+ OMAP1610_GPIO_WAKEUPENABLE
;
1661 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1662 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1665 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1666 case METHOD_GPIO_24XX
:
1667 wake_status
= bank
->base
+ OMAP24XX_GPIO_WAKE_EN
;
1668 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1669 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1672 #ifdef CONFIG_ARCH_OMAP4
1673 case METHOD_GPIO_44XX
:
1674 wake_status
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1675 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1676 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1683 spin_lock_irqsave(&bank
->lock
, flags
);
1684 bank
->saved_wakeup
= __raw_readl(wake_status
);
1685 __raw_writel(0xffffffff, wake_clear
);
1686 __raw_writel(bank
->suspend_wakeup
, wake_set
);
1687 spin_unlock_irqrestore(&bank
->lock
, flags
);
1693 static void omap_gpio_resume(void)
1697 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1700 for (i
= 0; i
< gpio_bank_count
; i
++) {
1701 struct gpio_bank
*bank
= &gpio_bank
[i
];
1702 void __iomem
*wake_clear
;
1703 void __iomem
*wake_set
;
1704 unsigned long flags
;
1706 switch (bank
->method
) {
1707 #ifdef CONFIG_ARCH_OMAP16XX
1708 case METHOD_GPIO_1610
:
1709 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1710 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1713 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1714 case METHOD_GPIO_24XX
:
1715 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1716 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1719 #ifdef CONFIG_ARCH_OMAP4
1720 case METHOD_GPIO_44XX
:
1721 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1722 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1729 spin_lock_irqsave(&bank
->lock
, flags
);
1730 __raw_writel(0xffffffff, wake_clear
);
1731 __raw_writel(bank
->saved_wakeup
, wake_set
);
1732 spin_unlock_irqrestore(&bank
->lock
, flags
);
1736 static struct syscore_ops omap_gpio_syscore_ops
= {
1737 .suspend
= omap_gpio_suspend
,
1738 .resume
= omap_gpio_resume
,
1743 #ifdef CONFIG_ARCH_OMAP2PLUS
1745 static int workaround_enabled
;
1747 void omap2_gpio_prepare_for_idle(int off_mode
)
1752 if (cpu_is_omap34xx())
1755 for (i
= min
; i
< gpio_bank_count
; i
++) {
1756 struct gpio_bank
*bank
= &gpio_bank
[i
];
1760 for (j
= 0; j
< hweight_long(bank
->dbck_enable_mask
); j
++)
1761 clk_disable(bank
->dbck
);
1766 /* If going to OFF, remove triggering for all
1767 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1768 * generated. See OMAP2420 Errata item 1.101. */
1769 if (!(bank
->enabled_non_wakeup_gpios
))
1772 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1773 bank
->saved_datain
= __raw_readl(bank
->base
+
1774 OMAP24XX_GPIO_DATAIN
);
1775 l1
= __raw_readl(bank
->base
+
1776 OMAP24XX_GPIO_FALLINGDETECT
);
1777 l2
= __raw_readl(bank
->base
+
1778 OMAP24XX_GPIO_RISINGDETECT
);
1781 if (cpu_is_omap44xx()) {
1782 bank
->saved_datain
= __raw_readl(bank
->base
+
1784 l1
= __raw_readl(bank
->base
+
1785 OMAP4_GPIO_FALLINGDETECT
);
1786 l2
= __raw_readl(bank
->base
+
1787 OMAP4_GPIO_RISINGDETECT
);
1790 bank
->saved_fallingdetect
= l1
;
1791 bank
->saved_risingdetect
= l2
;
1792 l1
&= ~bank
->enabled_non_wakeup_gpios
;
1793 l2
&= ~bank
->enabled_non_wakeup_gpios
;
1795 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1796 __raw_writel(l1
, bank
->base
+
1797 OMAP24XX_GPIO_FALLINGDETECT
);
1798 __raw_writel(l2
, bank
->base
+
1799 OMAP24XX_GPIO_RISINGDETECT
);
1802 if (cpu_is_omap44xx()) {
1803 __raw_writel(l1
, bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
1804 __raw_writel(l2
, bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
1810 workaround_enabled
= 0;
1813 workaround_enabled
= 1;
1816 void omap2_gpio_resume_after_idle(void)
1821 if (cpu_is_omap34xx())
1823 for (i
= min
; i
< gpio_bank_count
; i
++) {
1824 struct gpio_bank
*bank
= &gpio_bank
[i
];
1825 u32 l
= 0, gen
, gen0
, gen1
;
1828 for (j
= 0; j
< hweight_long(bank
->dbck_enable_mask
); j
++)
1829 clk_enable(bank
->dbck
);
1831 if (!workaround_enabled
)
1834 if (!(bank
->enabled_non_wakeup_gpios
))
1837 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1838 __raw_writel(bank
->saved_fallingdetect
,
1839 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1840 __raw_writel(bank
->saved_risingdetect
,
1841 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1842 l
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
1845 if (cpu_is_omap44xx()) {
1846 __raw_writel(bank
->saved_fallingdetect
,
1847 bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
1848 __raw_writel(bank
->saved_risingdetect
,
1849 bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
1850 l
= __raw_readl(bank
->base
+ OMAP4_GPIO_DATAIN
);
1853 /* Check if any of the non-wakeup interrupt GPIOs have changed
1854 * state. If so, generate an IRQ by software. This is
1855 * horribly racy, but it's the best we can do to work around
1856 * this silicon bug. */
1857 l
^= bank
->saved_datain
;
1858 l
&= bank
->enabled_non_wakeup_gpios
;
1861 * No need to generate IRQs for the rising edge for gpio IRQs
1862 * configured with falling edge only; and vice versa.
1864 gen0
= l
& bank
->saved_fallingdetect
;
1865 gen0
&= bank
->saved_datain
;
1867 gen1
= l
& bank
->saved_risingdetect
;
1868 gen1
&= ~(bank
->saved_datain
);
1870 /* FIXME: Consider GPIO IRQs with level detections properly! */
1871 gen
= l
& (~(bank
->saved_fallingdetect
) &
1872 ~(bank
->saved_risingdetect
));
1873 /* Consider all GPIO IRQs needed to be updated */
1879 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1880 old0
= __raw_readl(bank
->base
+
1881 OMAP24XX_GPIO_LEVELDETECT0
);
1882 old1
= __raw_readl(bank
->base
+
1883 OMAP24XX_GPIO_LEVELDETECT1
);
1884 __raw_writel(old0
| gen
, bank
->base
+
1885 OMAP24XX_GPIO_LEVELDETECT0
);
1886 __raw_writel(old1
| gen
, bank
->base
+
1887 OMAP24XX_GPIO_LEVELDETECT1
);
1888 __raw_writel(old0
, bank
->base
+
1889 OMAP24XX_GPIO_LEVELDETECT0
);
1890 __raw_writel(old1
, bank
->base
+
1891 OMAP24XX_GPIO_LEVELDETECT1
);
1894 if (cpu_is_omap44xx()) {
1895 old0
= __raw_readl(bank
->base
+
1896 OMAP4_GPIO_LEVELDETECT0
);
1897 old1
= __raw_readl(bank
->base
+
1898 OMAP4_GPIO_LEVELDETECT1
);
1899 __raw_writel(old0
| l
, bank
->base
+
1900 OMAP4_GPIO_LEVELDETECT0
);
1901 __raw_writel(old1
| l
, bank
->base
+
1902 OMAP4_GPIO_LEVELDETECT1
);
1903 __raw_writel(old0
, bank
->base
+
1904 OMAP4_GPIO_LEVELDETECT0
);
1905 __raw_writel(old1
, bank
->base
+
1906 OMAP4_GPIO_LEVELDETECT1
);
1915 #ifdef CONFIG_ARCH_OMAP3
1916 /* save the registers of bank 2-6 */
1917 void omap_gpio_save_context(void)
1921 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1922 for (i
= 1; i
< gpio_bank_count
; i
++) {
1923 struct gpio_bank
*bank
= &gpio_bank
[i
];
1924 gpio_context
[i
].irqenable1
=
1925 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
1926 gpio_context
[i
].irqenable2
=
1927 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
1928 gpio_context
[i
].wake_en
=
1929 __raw_readl(bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
1930 gpio_context
[i
].ctrl
=
1931 __raw_readl(bank
->base
+ OMAP24XX_GPIO_CTRL
);
1932 gpio_context
[i
].oe
=
1933 __raw_readl(bank
->base
+ OMAP24XX_GPIO_OE
);
1934 gpio_context
[i
].leveldetect0
=
1935 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1936 gpio_context
[i
].leveldetect1
=
1937 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1938 gpio_context
[i
].risingdetect
=
1939 __raw_readl(bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1940 gpio_context
[i
].fallingdetect
=
1941 __raw_readl(bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1942 gpio_context
[i
].dataout
=
1943 __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
1947 /* restore the required registers of bank 2-6 */
1948 void omap_gpio_restore_context(void)
1952 for (i
= 1; i
< gpio_bank_count
; i
++) {
1953 struct gpio_bank
*bank
= &gpio_bank
[i
];
1954 __raw_writel(gpio_context
[i
].irqenable1
,
1955 bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
1956 __raw_writel(gpio_context
[i
].irqenable2
,
1957 bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
1958 __raw_writel(gpio_context
[i
].wake_en
,
1959 bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
1960 __raw_writel(gpio_context
[i
].ctrl
,
1961 bank
->base
+ OMAP24XX_GPIO_CTRL
);
1962 __raw_writel(gpio_context
[i
].oe
,
1963 bank
->base
+ OMAP24XX_GPIO_OE
);
1964 __raw_writel(gpio_context
[i
].leveldetect0
,
1965 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1966 __raw_writel(gpio_context
[i
].leveldetect1
,
1967 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1968 __raw_writel(gpio_context
[i
].risingdetect
,
1969 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1970 __raw_writel(gpio_context
[i
].fallingdetect
,
1971 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1972 __raw_writel(gpio_context
[i
].dataout
,
1973 bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
1978 static struct platform_driver omap_gpio_driver
= {
1979 .probe
= omap_gpio_probe
,
1981 .name
= "omap_gpio",
1986 * gpio driver register needs to be done before
1987 * machine_init functions access gpio APIs.
1988 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1990 static int __init
omap_gpio_drv_reg(void)
1992 return platform_driver_register(&omap_gpio_driver
);
1994 postcore_initcall(omap_gpio_drv_reg
);
1996 static int __init
omap_gpio_sysinit(void)
2000 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2001 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2002 register_syscore_ops(&omap_gpio_syscore_ops
);
2008 arch_initcall(omap_gpio_sysinit
);