2 * linux/arch/arm/plat-pxa/gpio.c
4 * Generic PXA GPIO handling
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/gpio.h>
17 #include <linux/gpio-pxa.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/syscore_ops.h>
23 #include <linux/slab.h>
25 #include <mach/irqs.h>
28 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
29 * one set of registers. The register offsets are organized below:
31 * GPLR GPDR GPSR GPCR GRER GFER GEDR
32 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
33 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
34 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
36 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
37 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
38 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
41 * BANK 3 is only available on PXA27x and later processors.
42 * BANK 4 and 5 are only available on PXA935
45 #define GPLR_OFFSET 0x00
46 #define GPDR_OFFSET 0x0C
47 #define GPSR_OFFSET 0x18
48 #define GPCR_OFFSET 0x24
49 #define GRER_OFFSET 0x30
50 #define GFER_OFFSET 0x3C
51 #define GEDR_OFFSET 0x48
52 #define GAFR_OFFSET 0x54
53 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
55 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
59 struct pxa_gpio_chip
{
60 struct gpio_chip chip
;
61 void __iomem
*regbase
;
64 unsigned long irq_mask
;
65 unsigned long irq_edge_rise
;
66 unsigned long irq_edge_fall
;
69 unsigned long saved_gplr
;
70 unsigned long saved_gpdr
;
71 unsigned long saved_grer
;
72 unsigned long saved_gfer
;
86 static DEFINE_SPINLOCK(gpio_lock
);
87 static struct pxa_gpio_chip
*pxa_gpio_chips
;
89 static void __iomem
*gpio_reg_base
;
91 #define for_each_gpio_chip(i, c) \
92 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
94 static inline void __iomem
*gpio_chip_base(struct gpio_chip
*c
)
96 return container_of(c
, struct pxa_gpio_chip
, chip
)->regbase
;
99 static inline struct pxa_gpio_chip
*gpio_to_pxachip(unsigned gpio
)
101 return &pxa_gpio_chips
[gpio_to_bank(gpio
)];
104 static inline int gpio_is_pxa_type(int type
)
106 return (type
& MMP_GPIO
) == 0;
109 static inline int gpio_is_mmp_type(int type
)
111 return (type
& MMP_GPIO
) != 0;
114 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
115 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
117 static inline int __gpio_is_inverted(int gpio
)
119 if ((gpio_type
== PXA26X_GPIO
) && (gpio
> 85))
125 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
126 * function of a GPIO, and GPDRx cannot be altered once configured. It
127 * is attributed as "occupied" here (I know this terminology isn't
128 * accurate, you are welcome to propose a better one :-)
130 static inline int __gpio_is_occupied(unsigned gpio
)
132 struct pxa_gpio_chip
*pxachip
;
134 unsigned long gafr
= 0, gpdr
= 0;
135 int ret
, af
= 0, dir
= 0;
137 pxachip
= gpio_to_pxachip(gpio
);
138 base
= gpio_chip_base(&pxachip
->chip
);
139 gpdr
= readl_relaxed(base
+ GPDR_OFFSET
);
145 gafr
= readl_relaxed(base
+ GAFR_OFFSET
);
146 af
= (gafr
>> ((gpio
& 0xf) * 2)) & 0x3;
147 dir
= gpdr
& GPIO_bit(gpio
);
149 if (__gpio_is_inverted(gpio
))
150 ret
= (af
!= 1) || (dir
== 0);
152 ret
= (af
!= 0) || (dir
!= 0);
155 ret
= gpdr
& GPIO_bit(gpio
);
161 #ifdef CONFIG_ARCH_PXA
162 static inline int __pxa_gpio_to_irq(int gpio
)
164 if (gpio_is_pxa_type(gpio_type
))
165 return PXA_GPIO_TO_IRQ(gpio
);
169 static inline int __pxa_irq_to_gpio(int irq
)
171 if (gpio_is_pxa_type(gpio_type
))
172 return irq
- PXA_GPIO_TO_IRQ(0);
176 static inline int __pxa_gpio_to_irq(int gpio
) { return -1; }
177 static inline int __pxa_irq_to_gpio(int irq
) { return -1; }
180 #ifdef CONFIG_ARCH_MMP
181 static inline int __mmp_gpio_to_irq(int gpio
)
183 if (gpio_is_mmp_type(gpio_type
))
184 return MMP_GPIO_TO_IRQ(gpio
);
188 static inline int __mmp_irq_to_gpio(int irq
)
190 if (gpio_is_mmp_type(gpio_type
))
191 return irq
- MMP_GPIO_TO_IRQ(0);
195 static inline int __mmp_gpio_to_irq(int gpio
) { return -1; }
196 static inline int __mmp_irq_to_gpio(int irq
) { return -1; }
199 static int pxa_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
203 gpio
= chip
->base
+ offset
;
204 ret
= __pxa_gpio_to_irq(gpio
);
207 return __mmp_gpio_to_irq(gpio
);
210 int pxa_irq_to_gpio(int irq
)
214 ret
= __pxa_irq_to_gpio(irq
);
217 return __mmp_irq_to_gpio(irq
);
220 static int pxa_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
222 void __iomem
*base
= gpio_chip_base(chip
);
223 uint32_t value
, mask
= 1 << offset
;
226 spin_lock_irqsave(&gpio_lock
, flags
);
228 value
= readl_relaxed(base
+ GPDR_OFFSET
);
229 if (__gpio_is_inverted(chip
->base
+ offset
))
233 writel_relaxed(value
, base
+ GPDR_OFFSET
);
235 spin_unlock_irqrestore(&gpio_lock
, flags
);
239 static int pxa_gpio_direction_output(struct gpio_chip
*chip
,
240 unsigned offset
, int value
)
242 void __iomem
*base
= gpio_chip_base(chip
);
243 uint32_t tmp
, mask
= 1 << offset
;
246 writel_relaxed(mask
, base
+ (value
? GPSR_OFFSET
: GPCR_OFFSET
));
248 spin_lock_irqsave(&gpio_lock
, flags
);
250 tmp
= readl_relaxed(base
+ GPDR_OFFSET
);
251 if (__gpio_is_inverted(chip
->base
+ offset
))
255 writel_relaxed(tmp
, base
+ GPDR_OFFSET
);
257 spin_unlock_irqrestore(&gpio_lock
, flags
);
261 static int pxa_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
263 return readl_relaxed(gpio_chip_base(chip
) + GPLR_OFFSET
) & (1 << offset
);
266 static void pxa_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
268 writel_relaxed(1 << offset
, gpio_chip_base(chip
) +
269 (value
? GPSR_OFFSET
: GPCR_OFFSET
));
272 static int __devinit
pxa_init_gpio_chip(int gpio_end
)
274 int i
, gpio
, nbanks
= gpio_to_bank(gpio_end
) + 1;
275 struct pxa_gpio_chip
*chips
;
277 chips
= kzalloc(nbanks
* sizeof(struct pxa_gpio_chip
), GFP_KERNEL
);
279 pr_err("%s: failed to allocate GPIO chips\n", __func__
);
283 for (i
= 0, gpio
= 0; i
< nbanks
; i
++, gpio
+= 32) {
284 struct gpio_chip
*c
= &chips
[i
].chip
;
286 sprintf(chips
[i
].label
, "gpio-%d", i
);
287 chips
[i
].regbase
= gpio_reg_base
+ BANK_OFF(i
);
290 c
->label
= chips
[i
].label
;
292 c
->direction_input
= pxa_gpio_direction_input
;
293 c
->direction_output
= pxa_gpio_direction_output
;
294 c
->get
= pxa_gpio_get
;
295 c
->set
= pxa_gpio_set
;
296 c
->to_irq
= pxa_gpio_to_irq
;
298 /* number of GPIOs on last bank may be less than 32 */
299 c
->ngpio
= (gpio
+ 31 > gpio_end
) ? (gpio_end
- gpio
+ 1) : 32;
302 pxa_gpio_chips
= chips
;
306 /* Update only those GRERx and GFERx edge detection register bits if those
307 * bits are set in c->irq_mask
309 static inline void update_edge_detect(struct pxa_gpio_chip
*c
)
313 grer
= readl_relaxed(c
->regbase
+ GRER_OFFSET
) & ~c
->irq_mask
;
314 gfer
= readl_relaxed(c
->regbase
+ GFER_OFFSET
) & ~c
->irq_mask
;
315 grer
|= c
->irq_edge_rise
& c
->irq_mask
;
316 gfer
|= c
->irq_edge_fall
& c
->irq_mask
;
317 writel_relaxed(grer
, c
->regbase
+ GRER_OFFSET
);
318 writel_relaxed(gfer
, c
->regbase
+ GFER_OFFSET
);
321 static int pxa_gpio_irq_type(struct irq_data
*d
, unsigned int type
)
323 struct pxa_gpio_chip
*c
;
324 int gpio
= pxa_irq_to_gpio(d
->irq
);
325 unsigned long gpdr
, mask
= GPIO_bit(gpio
);
327 c
= gpio_to_pxachip(gpio
);
329 if (type
== IRQ_TYPE_PROBE
) {
330 /* Don't mess with enabled GPIOs using preconfigured edges or
331 * GPIOs set to alternate function or to output during probe
333 if ((c
->irq_edge_rise
| c
->irq_edge_fall
) & GPIO_bit(gpio
))
336 if (__gpio_is_occupied(gpio
))
339 type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
342 gpdr
= readl_relaxed(c
->regbase
+ GPDR_OFFSET
);
344 if (__gpio_is_inverted(gpio
))
345 writel_relaxed(gpdr
| mask
, c
->regbase
+ GPDR_OFFSET
);
347 writel_relaxed(gpdr
& ~mask
, c
->regbase
+ GPDR_OFFSET
);
349 if (type
& IRQ_TYPE_EDGE_RISING
)
350 c
->irq_edge_rise
|= mask
;
352 c
->irq_edge_rise
&= ~mask
;
354 if (type
& IRQ_TYPE_EDGE_FALLING
)
355 c
->irq_edge_fall
|= mask
;
357 c
->irq_edge_fall
&= ~mask
;
359 update_edge_detect(c
);
361 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__
, d
->irq
, gpio
,
362 ((type
& IRQ_TYPE_EDGE_RISING
) ? " rising" : ""),
363 ((type
& IRQ_TYPE_EDGE_FALLING
) ? " falling" : ""));
367 static void pxa_gpio_demux_handler(unsigned int irq
, struct irq_desc
*desc
)
369 struct pxa_gpio_chip
*c
;
370 int loop
, gpio
, gpio_base
, n
;
375 for_each_gpio_chip(gpio
, c
) {
376 gpio_base
= c
->chip
.base
;
378 gedr
= readl_relaxed(c
->regbase
+ GEDR_OFFSET
);
379 gedr
= gedr
& c
->irq_mask
;
380 writel_relaxed(gedr
, c
->regbase
+ GEDR_OFFSET
);
382 n
= find_first_bit(&gedr
, BITS_PER_LONG
);
383 while (n
< BITS_PER_LONG
) {
386 generic_handle_irq(gpio_to_irq(gpio_base
+ n
));
387 n
= find_next_bit(&gedr
, BITS_PER_LONG
, n
+ 1);
393 static void pxa_ack_muxed_gpio(struct irq_data
*d
)
395 int gpio
= pxa_irq_to_gpio(d
->irq
);
396 struct pxa_gpio_chip
*c
= gpio_to_pxachip(gpio
);
398 writel_relaxed(GPIO_bit(gpio
), c
->regbase
+ GEDR_OFFSET
);
401 static void pxa_mask_muxed_gpio(struct irq_data
*d
)
403 int gpio
= pxa_irq_to_gpio(d
->irq
);
404 struct pxa_gpio_chip
*c
= gpio_to_pxachip(gpio
);
407 c
->irq_mask
&= ~GPIO_bit(gpio
);
409 grer
= readl_relaxed(c
->regbase
+ GRER_OFFSET
) & ~GPIO_bit(gpio
);
410 gfer
= readl_relaxed(c
->regbase
+ GFER_OFFSET
) & ~GPIO_bit(gpio
);
411 writel_relaxed(grer
, c
->regbase
+ GRER_OFFSET
);
412 writel_relaxed(gfer
, c
->regbase
+ GFER_OFFSET
);
415 static void pxa_unmask_muxed_gpio(struct irq_data
*d
)
417 int gpio
= pxa_irq_to_gpio(d
->irq
);
418 struct pxa_gpio_chip
*c
= gpio_to_pxachip(gpio
);
420 c
->irq_mask
|= GPIO_bit(gpio
);
421 update_edge_detect(c
);
424 static struct irq_chip pxa_muxed_gpio_chip
= {
426 .irq_ack
= pxa_ack_muxed_gpio
,
427 .irq_mask
= pxa_mask_muxed_gpio
,
428 .irq_unmask
= pxa_unmask_muxed_gpio
,
429 .irq_set_type
= pxa_gpio_irq_type
,
432 static int pxa_gpio_nums(void)
436 #ifdef CONFIG_ARCH_PXA
437 if (cpu_is_pxa25x()) {
438 #ifdef CONFIG_CPU_PXA26x
440 gpio_type
= PXA26X_GPIO
;
441 #elif defined(CONFIG_PXA25x)
443 gpio_type
= PXA26X_GPIO
;
444 #endif /* CONFIG_CPU_PXA26x */
445 } else if (cpu_is_pxa27x()) {
447 gpio_type
= PXA27X_GPIO
;
448 } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
450 gpio_type
= PXA93X_GPIO
;
451 } else if (cpu_is_pxa3xx()) {
453 gpio_type
= PXA3XX_GPIO
;
455 #endif /* CONFIG_ARCH_PXA */
457 #ifdef CONFIG_ARCH_MMP
458 if (cpu_is_pxa168() || cpu_is_pxa910()) {
460 gpio_type
= MMP_GPIO
;
461 } else if (cpu_is_mmp2()) {
463 gpio_type
= MMP2_GPIO
;
465 #endif /* CONFIG_ARCH_MMP */
469 static int __devinit
pxa_gpio_probe(struct platform_device
*pdev
)
471 struct pxa_gpio_chip
*c
;
472 struct resource
*res
;
475 int irq0
= 0, irq1
= 0, irq_mux
, gpio_offset
= 0;
477 pxa_last_gpio
= pxa_gpio_nums();
481 irq0
= platform_get_irq_byname(pdev
, "gpio0");
482 irq1
= platform_get_irq_byname(pdev
, "gpio1");
483 irq_mux
= platform_get_irq_byname(pdev
, "gpio_mux");
484 if ((irq0
> 0 && irq1
<= 0) || (irq0
<= 0 && irq1
> 0)
487 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
490 gpio_reg_base
= ioremap(res
->start
, resource_size(res
));
497 clk
= clk_get(&pdev
->dev
, NULL
);
499 dev_err(&pdev
->dev
, "Error %ld to get gpio clock\n",
501 iounmap(gpio_reg_base
);
504 ret
= clk_prepare(clk
);
507 iounmap(gpio_reg_base
);
510 ret
= clk_enable(clk
);
514 iounmap(gpio_reg_base
);
518 /* Initialize GPIO chips */
519 pxa_init_gpio_chip(pxa_last_gpio
);
521 /* clear all GPIO edge detects */
522 for_each_gpio_chip(gpio
, c
) {
523 writel_relaxed(0, c
->regbase
+ GFER_OFFSET
);
524 writel_relaxed(0, c
->regbase
+ GRER_OFFSET
);
525 writel_relaxed(~0,c
->regbase
+ GEDR_OFFSET
);
526 /* unmask GPIO edge detect for AP side */
527 if (gpio_is_mmp_type(gpio_type
))
528 writel_relaxed(~0, c
->regbase
+ ED_MASK_OFFSET
);
531 #ifdef CONFIG_ARCH_PXA
532 irq
= gpio_to_irq(0);
533 irq_set_chip_and_handler(irq
, &pxa_muxed_gpio_chip
,
535 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
536 irq_set_chained_handler(IRQ_GPIO0
, pxa_gpio_demux_handler
);
538 irq
= gpio_to_irq(1);
539 irq_set_chip_and_handler(irq
, &pxa_muxed_gpio_chip
,
541 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
542 irq_set_chained_handler(IRQ_GPIO1
, pxa_gpio_demux_handler
);
545 for (irq
= gpio_to_irq(gpio_offset
);
546 irq
<= gpio_to_irq(pxa_last_gpio
); irq
++) {
547 irq_set_chip_and_handler(irq
, &pxa_muxed_gpio_chip
,
549 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
552 irq_set_chained_handler(irq_mux
, pxa_gpio_demux_handler
);
556 static struct platform_driver pxa_gpio_driver
= {
557 .probe
= pxa_gpio_probe
,
563 static int __init
pxa_gpio_init(void)
565 return platform_driver_register(&pxa_gpio_driver
);
567 postcore_initcall(pxa_gpio_init
);
570 static int pxa_gpio_suspend(void)
572 struct pxa_gpio_chip
*c
;
575 for_each_gpio_chip(gpio
, c
) {
576 c
->saved_gplr
= readl_relaxed(c
->regbase
+ GPLR_OFFSET
);
577 c
->saved_gpdr
= readl_relaxed(c
->regbase
+ GPDR_OFFSET
);
578 c
->saved_grer
= readl_relaxed(c
->regbase
+ GRER_OFFSET
);
579 c
->saved_gfer
= readl_relaxed(c
->regbase
+ GFER_OFFSET
);
581 /* Clear GPIO transition detect bits */
582 writel_relaxed(0xffffffff, c
->regbase
+ GEDR_OFFSET
);
587 static void pxa_gpio_resume(void)
589 struct pxa_gpio_chip
*c
;
592 for_each_gpio_chip(gpio
, c
) {
593 /* restore level with set/clear */
594 writel_relaxed( c
->saved_gplr
, c
->regbase
+ GPSR_OFFSET
);
595 writel_relaxed(~c
->saved_gplr
, c
->regbase
+ GPCR_OFFSET
);
597 writel_relaxed(c
->saved_grer
, c
->regbase
+ GRER_OFFSET
);
598 writel_relaxed(c
->saved_gfer
, c
->regbase
+ GFER_OFFSET
);
599 writel_relaxed(c
->saved_gpdr
, c
->regbase
+ GPDR_OFFSET
);
603 #define pxa_gpio_suspend NULL
604 #define pxa_gpio_resume NULL
607 struct syscore_ops pxa_gpio_syscore_ops
= {
608 .suspend
= pxa_gpio_suspend
,
609 .resume
= pxa_gpio_resume
,
612 static int __init
pxa_gpio_sysinit(void)
614 register_syscore_ops(&pxa_gpio_syscore_ops
);
617 postcore_initcall(pxa_gpio_sysinit
);