2 * Renesas R-Car GPIO Support
4 * Copyright (C) 2013 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
21 #include <linux/ioport.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/module.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_data/gpio-rcar.h>
28 #include <linux/platform_device.h>
29 #include <linux/spinlock.h>
30 #include <linux/slab.h>
32 struct gpio_rcar_priv
{
35 struct gpio_rcar_config config
;
36 struct platform_device
*pdev
;
37 struct gpio_chip gpio_chip
;
38 struct irq_chip irq_chip
;
39 struct irq_domain
*irq_domain
;
55 #define RCAR_MAX_GPIO_PER_BANK 32
57 static inline u32
gpio_rcar_read(struct gpio_rcar_priv
*p
, int offs
)
59 return ioread32(p
->base
+ offs
);
62 static inline void gpio_rcar_write(struct gpio_rcar_priv
*p
, int offs
,
65 iowrite32(value
, p
->base
+ offs
);
68 static void gpio_rcar_modify_bit(struct gpio_rcar_priv
*p
, int offs
,
71 u32 tmp
= gpio_rcar_read(p
, offs
);
78 gpio_rcar_write(p
, offs
, tmp
);
81 static void gpio_rcar_irq_disable(struct irq_data
*d
)
83 struct gpio_rcar_priv
*p
= irq_data_get_irq_chip_data(d
);
85 gpio_rcar_write(p
, INTMSK
, ~BIT(irqd_to_hwirq(d
)));
88 static void gpio_rcar_irq_enable(struct irq_data
*d
)
90 struct gpio_rcar_priv
*p
= irq_data_get_irq_chip_data(d
);
92 gpio_rcar_write(p
, MSKCLR
, BIT(irqd_to_hwirq(d
)));
95 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv
*p
,
97 bool active_high_rising_edge
,
103 /* follow steps in the GPIO documentation for
104 * "Setting Edge-Sensitive Interrupt Input Mode" and
105 * "Setting Level-Sensitive Interrupt Input Mode"
108 spin_lock_irqsave(&p
->lock
, flags
);
110 /* Configure postive or negative logic in POSNEG */
111 gpio_rcar_modify_bit(p
, POSNEG
, hwirq
, !active_high_rising_edge
);
113 /* Configure edge or level trigger in EDGLEVEL */
114 gpio_rcar_modify_bit(p
, EDGLEVEL
, hwirq
, !level_trigger
);
116 /* Select one edge or both edges in BOTHEDGE */
117 if (p
->config
.has_both_edge_trigger
)
118 gpio_rcar_modify_bit(p
, BOTHEDGE
, hwirq
, both
);
120 /* Select "Interrupt Input Mode" in IOINTSEL */
121 gpio_rcar_modify_bit(p
, IOINTSEL
, hwirq
, true);
123 /* Write INTCLR in case of edge trigger */
125 gpio_rcar_write(p
, INTCLR
, BIT(hwirq
));
127 spin_unlock_irqrestore(&p
->lock
, flags
);
130 static int gpio_rcar_irq_set_type(struct irq_data
*d
, unsigned int type
)
132 struct gpio_rcar_priv
*p
= irq_data_get_irq_chip_data(d
);
133 unsigned int hwirq
= irqd_to_hwirq(d
);
135 dev_dbg(&p
->pdev
->dev
, "sense irq = %d, type = %d\n", hwirq
, type
);
137 switch (type
& IRQ_TYPE_SENSE_MASK
) {
138 case IRQ_TYPE_LEVEL_HIGH
:
139 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, true,
142 case IRQ_TYPE_LEVEL_LOW
:
143 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, false, true,
146 case IRQ_TYPE_EDGE_RISING
:
147 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, false,
150 case IRQ_TYPE_EDGE_FALLING
:
151 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, false, false,
154 case IRQ_TYPE_EDGE_BOTH
:
155 if (!p
->config
.has_both_edge_trigger
)
157 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, false,
166 static irqreturn_t
gpio_rcar_irq_handler(int irq
, void *dev_id
)
168 struct gpio_rcar_priv
*p
= dev_id
;
170 unsigned int offset
, irqs_handled
= 0;
172 while ((pending
= gpio_rcar_read(p
, INTDT
))) {
173 offset
= __ffs(pending
);
174 gpio_rcar_write(p
, INTCLR
, BIT(offset
));
175 generic_handle_irq(irq_find_mapping(p
->irq_domain
, offset
));
179 return irqs_handled
? IRQ_HANDLED
: IRQ_NONE
;
182 static inline struct gpio_rcar_priv
*gpio_to_priv(struct gpio_chip
*chip
)
184 return container_of(chip
, struct gpio_rcar_priv
, gpio_chip
);
187 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip
*chip
,
191 struct gpio_rcar_priv
*p
= gpio_to_priv(chip
);
194 /* follow steps in the GPIO documentation for
195 * "Setting General Output Mode" and
196 * "Setting General Input Mode"
199 spin_lock_irqsave(&p
->lock
, flags
);
201 /* Configure postive logic in POSNEG */
202 gpio_rcar_modify_bit(p
, POSNEG
, gpio
, false);
204 /* Select "General Input/Output Mode" in IOINTSEL */
205 gpio_rcar_modify_bit(p
, IOINTSEL
, gpio
, false);
207 /* Select Input Mode or Output Mode in INOUTSEL */
208 gpio_rcar_modify_bit(p
, INOUTSEL
, gpio
, output
);
210 spin_unlock_irqrestore(&p
->lock
, flags
);
213 static int gpio_rcar_request(struct gpio_chip
*chip
, unsigned offset
)
215 return pinctrl_request_gpio(chip
->base
+ offset
);
218 static void gpio_rcar_free(struct gpio_chip
*chip
, unsigned offset
)
220 pinctrl_free_gpio(chip
->base
+ offset
);
222 /* Set the GPIO as an input to ensure that the next GPIO request won't
223 * drive the GPIO pin as an output.
225 gpio_rcar_config_general_input_output_mode(chip
, offset
, false);
228 static int gpio_rcar_direction_input(struct gpio_chip
*chip
, unsigned offset
)
230 gpio_rcar_config_general_input_output_mode(chip
, offset
, false);
234 static int gpio_rcar_get(struct gpio_chip
*chip
, unsigned offset
)
236 u32 bit
= BIT(offset
);
238 /* testing on r8a7790 shows that INDT does not show correct pin state
239 * when configured as output, so use OUTDT in case of output pins */
240 if (gpio_rcar_read(gpio_to_priv(chip
), INOUTSEL
) & bit
)
241 return (int)(gpio_rcar_read(gpio_to_priv(chip
), OUTDT
) & bit
);
243 return (int)(gpio_rcar_read(gpio_to_priv(chip
), INDT
) & bit
);
246 static void gpio_rcar_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
248 struct gpio_rcar_priv
*p
= gpio_to_priv(chip
);
251 spin_lock_irqsave(&p
->lock
, flags
);
252 gpio_rcar_modify_bit(p
, OUTDT
, offset
, value
);
253 spin_unlock_irqrestore(&p
->lock
, flags
);
256 static int gpio_rcar_direction_output(struct gpio_chip
*chip
, unsigned offset
,
259 /* write GPIO value to output before selecting output mode of pin */
260 gpio_rcar_set(chip
, offset
, value
);
261 gpio_rcar_config_general_input_output_mode(chip
, offset
, true);
265 static int gpio_rcar_to_irq(struct gpio_chip
*chip
, unsigned offset
)
267 return irq_create_mapping(gpio_to_priv(chip
)->irq_domain
, offset
);
270 static int gpio_rcar_irq_domain_map(struct irq_domain
*h
, unsigned int irq
,
271 irq_hw_number_t hwirq
)
273 struct gpio_rcar_priv
*p
= h
->host_data
;
275 dev_dbg(&p
->pdev
->dev
, "map hw irq = %d, irq = %d\n", (int)hwirq
, irq
);
277 irq_set_chip_data(irq
, h
->host_data
);
278 irq_set_chip_and_handler(irq
, &p
->irq_chip
, handle_level_irq
);
279 set_irq_flags(irq
, IRQF_VALID
); /* kill me now */
283 static struct irq_domain_ops gpio_rcar_irq_domain_ops
= {
284 .map
= gpio_rcar_irq_domain_map
,
287 struct gpio_rcar_info
{
288 bool has_both_edge_trigger
;
291 static const struct of_device_id gpio_rcar_of_table
[] = {
293 .compatible
= "renesas,gpio-r8a7790",
294 .data
= (void *)&(const struct gpio_rcar_info
) {
295 .has_both_edge_trigger
= true,
298 .compatible
= "renesas,gpio-r8a7791",
299 .data
= (void *)&(const struct gpio_rcar_info
) {
300 .has_both_edge_trigger
= true,
303 .compatible
= "renesas,gpio-rcar",
304 .data
= (void *)&(const struct gpio_rcar_info
) {
305 .has_both_edge_trigger
= false,
312 MODULE_DEVICE_TABLE(of
, gpio_rcar_of_table
);
314 static int gpio_rcar_parse_pdata(struct gpio_rcar_priv
*p
)
316 struct gpio_rcar_config
*pdata
= dev_get_platdata(&p
->pdev
->dev
);
317 struct device_node
*np
= p
->pdev
->dev
.of_node
;
318 struct of_phandle_args args
;
323 } else if (IS_ENABLED(CONFIG_OF
) && np
) {
324 const struct of_device_id
*match
;
325 const struct gpio_rcar_info
*info
;
327 match
= of_match_node(gpio_rcar_of_table
, np
);
333 ret
= of_parse_phandle_with_fixed_args(np
, "gpio-ranges", 3, 0,
335 p
->config
.number_of_pins
= ret
== 0 ? args
.args
[2]
336 : RCAR_MAX_GPIO_PER_BANK
;
337 p
->config
.gpio_base
= -1;
338 p
->config
.has_both_edge_trigger
= info
->has_both_edge_trigger
;
341 if (p
->config
.number_of_pins
== 0 ||
342 p
->config
.number_of_pins
> RCAR_MAX_GPIO_PER_BANK
) {
343 dev_warn(&p
->pdev
->dev
,
344 "Invalid number of gpio lines %u, using %u\n",
345 p
->config
.number_of_pins
, RCAR_MAX_GPIO_PER_BANK
);
346 p
->config
.number_of_pins
= RCAR_MAX_GPIO_PER_BANK
;
352 static int gpio_rcar_probe(struct platform_device
*pdev
)
354 struct gpio_rcar_priv
*p
;
355 struct resource
*io
, *irq
;
356 struct gpio_chip
*gpio_chip
;
357 struct irq_chip
*irq_chip
;
358 const char *name
= dev_name(&pdev
->dev
);
361 p
= devm_kzalloc(&pdev
->dev
, sizeof(*p
), GFP_KERNEL
);
363 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
369 spin_lock_init(&p
->lock
);
371 /* Get device configuration from DT node or platform data. */
372 ret
= gpio_rcar_parse_pdata(p
);
376 platform_set_drvdata(pdev
, p
);
378 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
379 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
382 dev_err(&pdev
->dev
, "missing IRQ or IOMEM\n");
387 p
->base
= devm_ioremap_nocache(&pdev
->dev
, io
->start
,
390 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
395 gpio_chip
= &p
->gpio_chip
;
396 gpio_chip
->request
= gpio_rcar_request
;
397 gpio_chip
->free
= gpio_rcar_free
;
398 gpio_chip
->direction_input
= gpio_rcar_direction_input
;
399 gpio_chip
->get
= gpio_rcar_get
;
400 gpio_chip
->direction_output
= gpio_rcar_direction_output
;
401 gpio_chip
->set
= gpio_rcar_set
;
402 gpio_chip
->to_irq
= gpio_rcar_to_irq
;
403 gpio_chip
->label
= name
;
404 gpio_chip
->dev
= &pdev
->dev
;
405 gpio_chip
->owner
= THIS_MODULE
;
406 gpio_chip
->base
= p
->config
.gpio_base
;
407 gpio_chip
->ngpio
= p
->config
.number_of_pins
;
409 irq_chip
= &p
->irq_chip
;
410 irq_chip
->name
= name
;
411 irq_chip
->irq_mask
= gpio_rcar_irq_disable
;
412 irq_chip
->irq_unmask
= gpio_rcar_irq_enable
;
413 irq_chip
->irq_set_type
= gpio_rcar_irq_set_type
;
414 irq_chip
->flags
= IRQCHIP_SKIP_SET_WAKE
| IRQCHIP_SET_TYPE_MASKED
415 | IRQCHIP_MASK_ON_SUSPEND
;
417 p
->irq_domain
= irq_domain_add_simple(pdev
->dev
.of_node
,
418 p
->config
.number_of_pins
,
420 &gpio_rcar_irq_domain_ops
, p
);
421 if (!p
->irq_domain
) {
423 dev_err(&pdev
->dev
, "cannot initialize irq domain\n");
427 if (devm_request_irq(&pdev
->dev
, irq
->start
,
428 gpio_rcar_irq_handler
, IRQF_SHARED
, name
, p
)) {
429 dev_err(&pdev
->dev
, "failed to request IRQ\n");
434 ret
= gpiochip_add(gpio_chip
);
436 dev_err(&pdev
->dev
, "failed to add GPIO controller\n");
440 dev_info(&pdev
->dev
, "driving %d GPIOs\n", p
->config
.number_of_pins
);
442 /* warn in case of mismatch if irq base is specified */
443 if (p
->config
.irq_base
) {
444 ret
= irq_find_mapping(p
->irq_domain
, 0);
445 if (p
->config
.irq_base
!= ret
)
446 dev_warn(&pdev
->dev
, "irq base mismatch (%u/%u)\n",
447 p
->config
.irq_base
, ret
);
450 if (p
->config
.pctl_name
) {
451 ret
= gpiochip_add_pin_range(gpio_chip
, p
->config
.pctl_name
, 0,
452 gpio_chip
->base
, gpio_chip
->ngpio
);
454 dev_warn(&pdev
->dev
, "failed to add pin range\n");
460 irq_domain_remove(p
->irq_domain
);
465 static int gpio_rcar_remove(struct platform_device
*pdev
)
467 struct gpio_rcar_priv
*p
= platform_get_drvdata(pdev
);
470 ret
= gpiochip_remove(&p
->gpio_chip
);
474 irq_domain_remove(p
->irq_domain
);
478 static struct platform_driver gpio_rcar_device_driver
= {
479 .probe
= gpio_rcar_probe
,
480 .remove
= gpio_rcar_remove
,
483 .of_match_table
= of_match_ptr(gpio_rcar_of_table
),
487 module_platform_driver(gpio_rcar_device_driver
);
489 MODULE_AUTHOR("Magnus Damm");
490 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
491 MODULE_LICENSE("GPL v2");