2 * Renesas R-Car GPIO Support
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/err.h>
18 #include <linux/gpio.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/irq.h>
24 #include <linux/module.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_data/gpio-rcar.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/spinlock.h>
31 #include <linux/slab.h>
33 struct gpio_rcar_priv
{
36 struct gpio_rcar_config config
;
37 struct platform_device
*pdev
;
38 struct gpio_chip gpio_chip
;
39 struct irq_chip irq_chip
;
55 #define RCAR_MAX_GPIO_PER_BANK 32
57 static inline u32
gpio_rcar_read(struct gpio_rcar_priv
*p
, int offs
)
59 return ioread32(p
->base
+ offs
);
62 static inline void gpio_rcar_write(struct gpio_rcar_priv
*p
, int offs
,
65 iowrite32(value
, p
->base
+ offs
);
68 static void gpio_rcar_modify_bit(struct gpio_rcar_priv
*p
, int offs
,
71 u32 tmp
= gpio_rcar_read(p
, offs
);
78 gpio_rcar_write(p
, offs
, tmp
);
81 static void gpio_rcar_irq_disable(struct irq_data
*d
)
83 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
84 struct gpio_rcar_priv
*p
= container_of(gc
, struct gpio_rcar_priv
,
87 gpio_rcar_write(p
, INTMSK
, ~BIT(irqd_to_hwirq(d
)));
90 static void gpio_rcar_irq_enable(struct irq_data
*d
)
92 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
93 struct gpio_rcar_priv
*p
= container_of(gc
, struct gpio_rcar_priv
,
96 gpio_rcar_write(p
, MSKCLR
, BIT(irqd_to_hwirq(d
)));
99 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv
*p
,
101 bool active_high_rising_edge
,
107 /* follow steps in the GPIO documentation for
108 * "Setting Edge-Sensitive Interrupt Input Mode" and
109 * "Setting Level-Sensitive Interrupt Input Mode"
112 spin_lock_irqsave(&p
->lock
, flags
);
114 /* Configure postive or negative logic in POSNEG */
115 gpio_rcar_modify_bit(p
, POSNEG
, hwirq
, !active_high_rising_edge
);
117 /* Configure edge or level trigger in EDGLEVEL */
118 gpio_rcar_modify_bit(p
, EDGLEVEL
, hwirq
, !level_trigger
);
120 /* Select one edge or both edges in BOTHEDGE */
121 if (p
->config
.has_both_edge_trigger
)
122 gpio_rcar_modify_bit(p
, BOTHEDGE
, hwirq
, both
);
124 /* Select "Interrupt Input Mode" in IOINTSEL */
125 gpio_rcar_modify_bit(p
, IOINTSEL
, hwirq
, true);
127 /* Write INTCLR in case of edge trigger */
129 gpio_rcar_write(p
, INTCLR
, BIT(hwirq
));
131 spin_unlock_irqrestore(&p
->lock
, flags
);
134 static int gpio_rcar_irq_set_type(struct irq_data
*d
, unsigned int type
)
136 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
137 struct gpio_rcar_priv
*p
= container_of(gc
, struct gpio_rcar_priv
,
139 unsigned int hwirq
= irqd_to_hwirq(d
);
141 dev_dbg(&p
->pdev
->dev
, "sense irq = %d, type = %d\n", hwirq
, type
);
143 switch (type
& IRQ_TYPE_SENSE_MASK
) {
144 case IRQ_TYPE_LEVEL_HIGH
:
145 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, true,
148 case IRQ_TYPE_LEVEL_LOW
:
149 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, false, true,
152 case IRQ_TYPE_EDGE_RISING
:
153 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, false,
156 case IRQ_TYPE_EDGE_FALLING
:
157 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, false, false,
160 case IRQ_TYPE_EDGE_BOTH
:
161 if (!p
->config
.has_both_edge_trigger
)
163 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, false,
172 static irqreturn_t
gpio_rcar_irq_handler(int irq
, void *dev_id
)
174 struct gpio_rcar_priv
*p
= dev_id
;
176 unsigned int offset
, irqs_handled
= 0;
178 while ((pending
= gpio_rcar_read(p
, INTDT
) &
179 gpio_rcar_read(p
, INTMSK
))) {
180 offset
= __ffs(pending
);
181 gpio_rcar_write(p
, INTCLR
, BIT(offset
));
182 generic_handle_irq(irq_find_mapping(p
->gpio_chip
.irqdomain
,
187 return irqs_handled
? IRQ_HANDLED
: IRQ_NONE
;
190 static inline struct gpio_rcar_priv
*gpio_to_priv(struct gpio_chip
*chip
)
192 return container_of(chip
, struct gpio_rcar_priv
, gpio_chip
);
195 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip
*chip
,
199 struct gpio_rcar_priv
*p
= gpio_to_priv(chip
);
202 /* follow steps in the GPIO documentation for
203 * "Setting General Output Mode" and
204 * "Setting General Input Mode"
207 spin_lock_irqsave(&p
->lock
, flags
);
209 /* Configure postive logic in POSNEG */
210 gpio_rcar_modify_bit(p
, POSNEG
, gpio
, false);
212 /* Select "General Input/Output Mode" in IOINTSEL */
213 gpio_rcar_modify_bit(p
, IOINTSEL
, gpio
, false);
215 /* Select Input Mode or Output Mode in INOUTSEL */
216 gpio_rcar_modify_bit(p
, INOUTSEL
, gpio
, output
);
218 spin_unlock_irqrestore(&p
->lock
, flags
);
221 static int gpio_rcar_request(struct gpio_chip
*chip
, unsigned offset
)
223 return pinctrl_request_gpio(chip
->base
+ offset
);
226 static void gpio_rcar_free(struct gpio_chip
*chip
, unsigned offset
)
228 pinctrl_free_gpio(chip
->base
+ offset
);
230 /* Set the GPIO as an input to ensure that the next GPIO request won't
231 * drive the GPIO pin as an output.
233 gpio_rcar_config_general_input_output_mode(chip
, offset
, false);
236 static int gpio_rcar_direction_input(struct gpio_chip
*chip
, unsigned offset
)
238 gpio_rcar_config_general_input_output_mode(chip
, offset
, false);
242 static int gpio_rcar_get(struct gpio_chip
*chip
, unsigned offset
)
244 u32 bit
= BIT(offset
);
246 /* testing on r8a7790 shows that INDT does not show correct pin state
247 * when configured as output, so use OUTDT in case of output pins */
248 if (gpio_rcar_read(gpio_to_priv(chip
), INOUTSEL
) & bit
)
249 return !!(gpio_rcar_read(gpio_to_priv(chip
), OUTDT
) & bit
);
251 return !!(gpio_rcar_read(gpio_to_priv(chip
), INDT
) & bit
);
254 static void gpio_rcar_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
256 struct gpio_rcar_priv
*p
= gpio_to_priv(chip
);
259 spin_lock_irqsave(&p
->lock
, flags
);
260 gpio_rcar_modify_bit(p
, OUTDT
, offset
, value
);
261 spin_unlock_irqrestore(&p
->lock
, flags
);
264 static int gpio_rcar_direction_output(struct gpio_chip
*chip
, unsigned offset
,
267 /* write GPIO value to output before selecting output mode of pin */
268 gpio_rcar_set(chip
, offset
, value
);
269 gpio_rcar_config_general_input_output_mode(chip
, offset
, true);
273 struct gpio_rcar_info
{
274 bool has_both_edge_trigger
;
277 static const struct gpio_rcar_info gpio_rcar_info_gen1
= {
278 .has_both_edge_trigger
= false,
281 static const struct gpio_rcar_info gpio_rcar_info_gen2
= {
282 .has_both_edge_trigger
= true,
285 static const struct of_device_id gpio_rcar_of_table
[] = {
287 .compatible
= "renesas,gpio-r8a7790",
288 .data
= &gpio_rcar_info_gen2
,
290 .compatible
= "renesas,gpio-r8a7791",
291 .data
= &gpio_rcar_info_gen2
,
293 .compatible
= "renesas,gpio-r8a7793",
294 .data
= &gpio_rcar_info_gen2
,
296 .compatible
= "renesas,gpio-r8a7794",
297 .data
= &gpio_rcar_info_gen2
,
299 .compatible
= "renesas,gpio-rcar",
300 .data
= &gpio_rcar_info_gen1
,
306 MODULE_DEVICE_TABLE(of
, gpio_rcar_of_table
);
308 static int gpio_rcar_parse_pdata(struct gpio_rcar_priv
*p
)
310 struct gpio_rcar_config
*pdata
= dev_get_platdata(&p
->pdev
->dev
);
311 struct device_node
*np
= p
->pdev
->dev
.of_node
;
312 struct of_phandle_args args
;
317 } else if (IS_ENABLED(CONFIG_OF
) && np
) {
318 const struct of_device_id
*match
;
319 const struct gpio_rcar_info
*info
;
321 match
= of_match_node(gpio_rcar_of_table
, np
);
327 ret
= of_parse_phandle_with_fixed_args(np
, "gpio-ranges", 3, 0,
329 p
->config
.number_of_pins
= ret
== 0 ? args
.args
[2]
330 : RCAR_MAX_GPIO_PER_BANK
;
331 p
->config
.gpio_base
= -1;
332 p
->config
.has_both_edge_trigger
= info
->has_both_edge_trigger
;
335 if (p
->config
.number_of_pins
== 0 ||
336 p
->config
.number_of_pins
> RCAR_MAX_GPIO_PER_BANK
) {
337 dev_warn(&p
->pdev
->dev
,
338 "Invalid number of gpio lines %u, using %u\n",
339 p
->config
.number_of_pins
, RCAR_MAX_GPIO_PER_BANK
);
340 p
->config
.number_of_pins
= RCAR_MAX_GPIO_PER_BANK
;
346 static int gpio_rcar_probe(struct platform_device
*pdev
)
348 struct gpio_rcar_priv
*p
;
349 struct resource
*io
, *irq
;
350 struct gpio_chip
*gpio_chip
;
351 struct irq_chip
*irq_chip
;
352 struct device
*dev
= &pdev
->dev
;
353 const char *name
= dev_name(dev
);
356 p
= devm_kzalloc(dev
, sizeof(*p
), GFP_KERNEL
);
361 spin_lock_init(&p
->lock
);
363 /* Get device configuration from DT node or platform data. */
364 ret
= gpio_rcar_parse_pdata(p
);
368 platform_set_drvdata(pdev
, p
);
370 pm_runtime_enable(dev
);
371 pm_runtime_get_sync(dev
);
373 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
374 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
377 dev_err(dev
, "missing IRQ or IOMEM\n");
382 p
->base
= devm_ioremap_nocache(dev
, io
->start
, resource_size(io
));
384 dev_err(dev
, "failed to remap I/O memory\n");
389 gpio_chip
= &p
->gpio_chip
;
390 gpio_chip
->request
= gpio_rcar_request
;
391 gpio_chip
->free
= gpio_rcar_free
;
392 gpio_chip
->direction_input
= gpio_rcar_direction_input
;
393 gpio_chip
->get
= gpio_rcar_get
;
394 gpio_chip
->direction_output
= gpio_rcar_direction_output
;
395 gpio_chip
->set
= gpio_rcar_set
;
396 gpio_chip
->label
= name
;
397 gpio_chip
->dev
= dev
;
398 gpio_chip
->owner
= THIS_MODULE
;
399 gpio_chip
->base
= p
->config
.gpio_base
;
400 gpio_chip
->ngpio
= p
->config
.number_of_pins
;
402 irq_chip
= &p
->irq_chip
;
403 irq_chip
->name
= name
;
404 irq_chip
->irq_mask
= gpio_rcar_irq_disable
;
405 irq_chip
->irq_unmask
= gpio_rcar_irq_enable
;
406 irq_chip
->irq_set_type
= gpio_rcar_irq_set_type
;
407 irq_chip
->flags
= IRQCHIP_SKIP_SET_WAKE
| IRQCHIP_SET_TYPE_MASKED
408 | IRQCHIP_MASK_ON_SUSPEND
;
410 ret
= gpiochip_add(gpio_chip
);
412 dev_err(dev
, "failed to add GPIO controller\n");
416 ret
= gpiochip_irqchip_add(&p
->gpio_chip
, irq_chip
, p
->config
.irq_base
,
417 handle_level_irq
, IRQ_TYPE_NONE
);
419 dev_err(dev
, "cannot add irqchip\n");
423 if (devm_request_irq(dev
, irq
->start
, gpio_rcar_irq_handler
,
424 IRQF_SHARED
, name
, p
)) {
425 dev_err(dev
, "failed to request IRQ\n");
430 dev_info(dev
, "driving %d GPIOs\n", p
->config
.number_of_pins
);
432 /* warn in case of mismatch if irq base is specified */
433 if (p
->config
.irq_base
) {
434 ret
= irq_find_mapping(p
->gpio_chip
.irqdomain
, 0);
435 if (p
->config
.irq_base
!= ret
)
436 dev_warn(dev
, "irq base mismatch (%u/%u)\n",
437 p
->config
.irq_base
, ret
);
440 if (p
->config
.pctl_name
) {
441 ret
= gpiochip_add_pin_range(gpio_chip
, p
->config
.pctl_name
, 0,
442 gpio_chip
->base
, gpio_chip
->ngpio
);
444 dev_warn(dev
, "failed to add pin range\n");
450 gpiochip_remove(&p
->gpio_chip
);
453 pm_runtime_disable(dev
);
457 static int gpio_rcar_remove(struct platform_device
*pdev
)
459 struct gpio_rcar_priv
*p
= platform_get_drvdata(pdev
);
461 gpiochip_remove(&p
->gpio_chip
);
463 pm_runtime_put(&pdev
->dev
);
464 pm_runtime_disable(&pdev
->dev
);
468 static struct platform_driver gpio_rcar_device_driver
= {
469 .probe
= gpio_rcar_probe
,
470 .remove
= gpio_rcar_remove
,
473 .of_match_table
= of_match_ptr(gpio_rcar_of_table
),
477 module_platform_driver(gpio_rcar_device_driver
);
479 MODULE_AUTHOR("Magnus Damm");
480 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
481 MODULE_LICENSE("GPL v2");