2 * Renesas R-Car GPIO Support
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/gpio.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/irq.h>
25 #include <linux/module.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_data/gpio-rcar.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/spinlock.h>
32 #include <linux/slab.h>
34 struct gpio_rcar_priv
{
37 struct gpio_rcar_config config
;
38 struct platform_device
*pdev
;
39 struct gpio_chip gpio_chip
;
40 struct irq_chip irq_chip
;
41 unsigned int irq_parent
;
45 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
46 #define INOUTSEL 0x04 /* General Input/Output Switching Register */
47 #define OUTDT 0x08 /* General Output Register */
48 #define INDT 0x0c /* General Input Register */
49 #define INTDT 0x10 /* Interrupt Display Register */
50 #define INTCLR 0x14 /* Interrupt Clear Register */
51 #define INTMSK 0x18 /* Interrupt Mask Register */
52 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
53 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
54 #define EDGLEVEL 0x24 /* Edge/level Select Register */
55 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
56 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
58 #define RCAR_MAX_GPIO_PER_BANK 32
60 static inline u32
gpio_rcar_read(struct gpio_rcar_priv
*p
, int offs
)
62 return ioread32(p
->base
+ offs
);
65 static inline void gpio_rcar_write(struct gpio_rcar_priv
*p
, int offs
,
68 iowrite32(value
, p
->base
+ offs
);
71 static void gpio_rcar_modify_bit(struct gpio_rcar_priv
*p
, int offs
,
74 u32 tmp
= gpio_rcar_read(p
, offs
);
81 gpio_rcar_write(p
, offs
, tmp
);
84 static void gpio_rcar_irq_disable(struct irq_data
*d
)
86 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
87 struct gpio_rcar_priv
*p
= container_of(gc
, struct gpio_rcar_priv
,
90 gpio_rcar_write(p
, INTMSK
, ~BIT(irqd_to_hwirq(d
)));
93 static void gpio_rcar_irq_enable(struct irq_data
*d
)
95 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
96 struct gpio_rcar_priv
*p
= container_of(gc
, struct gpio_rcar_priv
,
99 gpio_rcar_write(p
, MSKCLR
, BIT(irqd_to_hwirq(d
)));
102 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv
*p
,
104 bool active_high_rising_edge
,
110 /* follow steps in the GPIO documentation for
111 * "Setting Edge-Sensitive Interrupt Input Mode" and
112 * "Setting Level-Sensitive Interrupt Input Mode"
115 spin_lock_irqsave(&p
->lock
, flags
);
117 /* Configure postive or negative logic in POSNEG */
118 gpio_rcar_modify_bit(p
, POSNEG
, hwirq
, !active_high_rising_edge
);
120 /* Configure edge or level trigger in EDGLEVEL */
121 gpio_rcar_modify_bit(p
, EDGLEVEL
, hwirq
, !level_trigger
);
123 /* Select one edge or both edges in BOTHEDGE */
124 if (p
->config
.has_both_edge_trigger
)
125 gpio_rcar_modify_bit(p
, BOTHEDGE
, hwirq
, both
);
127 /* Select "Interrupt Input Mode" in IOINTSEL */
128 gpio_rcar_modify_bit(p
, IOINTSEL
, hwirq
, true);
130 /* Write INTCLR in case of edge trigger */
132 gpio_rcar_write(p
, INTCLR
, BIT(hwirq
));
134 spin_unlock_irqrestore(&p
->lock
, flags
);
137 static int gpio_rcar_irq_set_type(struct irq_data
*d
, unsigned int type
)
139 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
140 struct gpio_rcar_priv
*p
= container_of(gc
, struct gpio_rcar_priv
,
142 unsigned int hwirq
= irqd_to_hwirq(d
);
144 dev_dbg(&p
->pdev
->dev
, "sense irq = %d, type = %d\n", hwirq
, type
);
146 switch (type
& IRQ_TYPE_SENSE_MASK
) {
147 case IRQ_TYPE_LEVEL_HIGH
:
148 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, true,
151 case IRQ_TYPE_LEVEL_LOW
:
152 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, false, true,
155 case IRQ_TYPE_EDGE_RISING
:
156 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, false,
159 case IRQ_TYPE_EDGE_FALLING
:
160 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, false, false,
163 case IRQ_TYPE_EDGE_BOTH
:
164 if (!p
->config
.has_both_edge_trigger
)
166 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, false,
175 static int gpio_rcar_irq_set_wake(struct irq_data
*d
, unsigned int on
)
177 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
178 struct gpio_rcar_priv
*p
= container_of(gc
, struct gpio_rcar_priv
,
181 irq_set_irq_wake(p
->irq_parent
, on
);
194 static irqreturn_t
gpio_rcar_irq_handler(int irq
, void *dev_id
)
196 struct gpio_rcar_priv
*p
= dev_id
;
198 unsigned int offset
, irqs_handled
= 0;
200 while ((pending
= gpio_rcar_read(p
, INTDT
) &
201 gpio_rcar_read(p
, INTMSK
))) {
202 offset
= __ffs(pending
);
203 gpio_rcar_write(p
, INTCLR
, BIT(offset
));
204 generic_handle_irq(irq_find_mapping(p
->gpio_chip
.irqdomain
,
209 return irqs_handled
? IRQ_HANDLED
: IRQ_NONE
;
212 static inline struct gpio_rcar_priv
*gpio_to_priv(struct gpio_chip
*chip
)
214 return container_of(chip
, struct gpio_rcar_priv
, gpio_chip
);
217 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip
*chip
,
221 struct gpio_rcar_priv
*p
= gpio_to_priv(chip
);
224 /* follow steps in the GPIO documentation for
225 * "Setting General Output Mode" and
226 * "Setting General Input Mode"
229 spin_lock_irqsave(&p
->lock
, flags
);
231 /* Configure postive logic in POSNEG */
232 gpio_rcar_modify_bit(p
, POSNEG
, gpio
, false);
234 /* Select "General Input/Output Mode" in IOINTSEL */
235 gpio_rcar_modify_bit(p
, IOINTSEL
, gpio
, false);
237 /* Select Input Mode or Output Mode in INOUTSEL */
238 gpio_rcar_modify_bit(p
, INOUTSEL
, gpio
, output
);
240 spin_unlock_irqrestore(&p
->lock
, flags
);
243 static int gpio_rcar_request(struct gpio_chip
*chip
, unsigned offset
)
245 return pinctrl_request_gpio(chip
->base
+ offset
);
248 static void gpio_rcar_free(struct gpio_chip
*chip
, unsigned offset
)
250 pinctrl_free_gpio(chip
->base
+ offset
);
252 /* Set the GPIO as an input to ensure that the next GPIO request won't
253 * drive the GPIO pin as an output.
255 gpio_rcar_config_general_input_output_mode(chip
, offset
, false);
258 static int gpio_rcar_direction_input(struct gpio_chip
*chip
, unsigned offset
)
260 gpio_rcar_config_general_input_output_mode(chip
, offset
, false);
264 static int gpio_rcar_get(struct gpio_chip
*chip
, unsigned offset
)
266 u32 bit
= BIT(offset
);
268 /* testing on r8a7790 shows that INDT does not show correct pin state
269 * when configured as output, so use OUTDT in case of output pins */
270 if (gpio_rcar_read(gpio_to_priv(chip
), INOUTSEL
) & bit
)
271 return !!(gpio_rcar_read(gpio_to_priv(chip
), OUTDT
) & bit
);
273 return !!(gpio_rcar_read(gpio_to_priv(chip
), INDT
) & bit
);
276 static void gpio_rcar_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
278 struct gpio_rcar_priv
*p
= gpio_to_priv(chip
);
281 spin_lock_irqsave(&p
->lock
, flags
);
282 gpio_rcar_modify_bit(p
, OUTDT
, offset
, value
);
283 spin_unlock_irqrestore(&p
->lock
, flags
);
286 static int gpio_rcar_direction_output(struct gpio_chip
*chip
, unsigned offset
,
289 /* write GPIO value to output before selecting output mode of pin */
290 gpio_rcar_set(chip
, offset
, value
);
291 gpio_rcar_config_general_input_output_mode(chip
, offset
, true);
295 struct gpio_rcar_info
{
296 bool has_both_edge_trigger
;
299 static const struct gpio_rcar_info gpio_rcar_info_gen1
= {
300 .has_both_edge_trigger
= false,
303 static const struct gpio_rcar_info gpio_rcar_info_gen2
= {
304 .has_both_edge_trigger
= true,
307 static const struct of_device_id gpio_rcar_of_table
[] = {
309 .compatible
= "renesas,gpio-r8a7790",
310 .data
= &gpio_rcar_info_gen2
,
312 .compatible
= "renesas,gpio-r8a7791",
313 .data
= &gpio_rcar_info_gen2
,
315 .compatible
= "renesas,gpio-r8a7793",
316 .data
= &gpio_rcar_info_gen2
,
318 .compatible
= "renesas,gpio-r8a7794",
319 .data
= &gpio_rcar_info_gen2
,
321 .compatible
= "renesas,gpio-rcar",
322 .data
= &gpio_rcar_info_gen1
,
328 MODULE_DEVICE_TABLE(of
, gpio_rcar_of_table
);
330 static int gpio_rcar_parse_pdata(struct gpio_rcar_priv
*p
)
332 struct gpio_rcar_config
*pdata
= dev_get_platdata(&p
->pdev
->dev
);
333 struct device_node
*np
= p
->pdev
->dev
.of_node
;
334 struct of_phandle_args args
;
339 } else if (IS_ENABLED(CONFIG_OF
) && np
) {
340 const struct of_device_id
*match
;
341 const struct gpio_rcar_info
*info
;
343 match
= of_match_node(gpio_rcar_of_table
, np
);
349 ret
= of_parse_phandle_with_fixed_args(np
, "gpio-ranges", 3, 0,
351 p
->config
.number_of_pins
= ret
== 0 ? args
.args
[2]
352 : RCAR_MAX_GPIO_PER_BANK
;
353 p
->config
.gpio_base
= -1;
354 p
->config
.has_both_edge_trigger
= info
->has_both_edge_trigger
;
357 if (p
->config
.number_of_pins
== 0 ||
358 p
->config
.number_of_pins
> RCAR_MAX_GPIO_PER_BANK
) {
359 dev_warn(&p
->pdev
->dev
,
360 "Invalid number of gpio lines %u, using %u\n",
361 p
->config
.number_of_pins
, RCAR_MAX_GPIO_PER_BANK
);
362 p
->config
.number_of_pins
= RCAR_MAX_GPIO_PER_BANK
;
368 static int gpio_rcar_probe(struct platform_device
*pdev
)
370 struct gpio_rcar_priv
*p
;
371 struct resource
*io
, *irq
;
372 struct gpio_chip
*gpio_chip
;
373 struct irq_chip
*irq_chip
;
374 struct device
*dev
= &pdev
->dev
;
375 const char *name
= dev_name(dev
);
378 p
= devm_kzalloc(dev
, sizeof(*p
), GFP_KERNEL
);
383 spin_lock_init(&p
->lock
);
385 /* Get device configuration from DT node or platform data. */
386 ret
= gpio_rcar_parse_pdata(p
);
390 platform_set_drvdata(pdev
, p
);
392 p
->clk
= devm_clk_get(dev
, NULL
);
393 if (IS_ERR(p
->clk
)) {
394 dev_warn(dev
, "unable to get clock\n");
398 pm_runtime_enable(dev
);
399 pm_runtime_get_sync(dev
);
401 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
402 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
405 dev_err(dev
, "missing IRQ or IOMEM\n");
410 p
->base
= devm_ioremap_nocache(dev
, io
->start
, resource_size(io
));
412 dev_err(dev
, "failed to remap I/O memory\n");
417 gpio_chip
= &p
->gpio_chip
;
418 gpio_chip
->request
= gpio_rcar_request
;
419 gpio_chip
->free
= gpio_rcar_free
;
420 gpio_chip
->direction_input
= gpio_rcar_direction_input
;
421 gpio_chip
->get
= gpio_rcar_get
;
422 gpio_chip
->direction_output
= gpio_rcar_direction_output
;
423 gpio_chip
->set
= gpio_rcar_set
;
424 gpio_chip
->label
= name
;
425 gpio_chip
->dev
= dev
;
426 gpio_chip
->owner
= THIS_MODULE
;
427 gpio_chip
->base
= p
->config
.gpio_base
;
428 gpio_chip
->ngpio
= p
->config
.number_of_pins
;
430 irq_chip
= &p
->irq_chip
;
431 irq_chip
->name
= name
;
432 irq_chip
->irq_mask
= gpio_rcar_irq_disable
;
433 irq_chip
->irq_unmask
= gpio_rcar_irq_enable
;
434 irq_chip
->irq_set_type
= gpio_rcar_irq_set_type
;
435 irq_chip
->irq_set_wake
= gpio_rcar_irq_set_wake
;
436 irq_chip
->flags
= IRQCHIP_SET_TYPE_MASKED
| IRQCHIP_MASK_ON_SUSPEND
;
438 ret
= gpiochip_add(gpio_chip
);
440 dev_err(dev
, "failed to add GPIO controller\n");
444 ret
= gpiochip_irqchip_add(gpio_chip
, irq_chip
, p
->config
.irq_base
,
445 handle_level_irq
, IRQ_TYPE_NONE
);
447 dev_err(dev
, "cannot add irqchip\n");
451 p
->irq_parent
= irq
->start
;
452 if (devm_request_irq(dev
, irq
->start
, gpio_rcar_irq_handler
,
453 IRQF_SHARED
, name
, p
)) {
454 dev_err(dev
, "failed to request IRQ\n");
459 dev_info(dev
, "driving %d GPIOs\n", p
->config
.number_of_pins
);
461 /* warn in case of mismatch if irq base is specified */
462 if (p
->config
.irq_base
) {
463 ret
= irq_find_mapping(gpio_chip
->irqdomain
, 0);
464 if (p
->config
.irq_base
!= ret
)
465 dev_warn(dev
, "irq base mismatch (%u/%u)\n",
466 p
->config
.irq_base
, ret
);
469 if (p
->config
.pctl_name
) {
470 ret
= gpiochip_add_pin_range(gpio_chip
, p
->config
.pctl_name
, 0,
471 gpio_chip
->base
, gpio_chip
->ngpio
);
473 dev_warn(dev
, "failed to add pin range\n");
479 gpiochip_remove(gpio_chip
);
482 pm_runtime_disable(dev
);
486 static int gpio_rcar_remove(struct platform_device
*pdev
)
488 struct gpio_rcar_priv
*p
= platform_get_drvdata(pdev
);
490 gpiochip_remove(&p
->gpio_chip
);
492 pm_runtime_put(&pdev
->dev
);
493 pm_runtime_disable(&pdev
->dev
);
497 static struct platform_driver gpio_rcar_device_driver
= {
498 .probe
= gpio_rcar_probe
,
499 .remove
= gpio_rcar_remove
,
502 .of_match_table
= of_match_ptr(gpio_rcar_of_table
),
506 module_platform_driver(gpio_rcar_device_driver
);
508 MODULE_AUTHOR("Magnus Damm");
509 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
510 MODULE_LICENSE("GPL v2");