2 * Renesas R-Car GPIO Support
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/gpio.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/irq.h>
25 #include <linux/module.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/spinlock.h>
31 #include <linux/slab.h>
33 struct gpio_rcar_priv
{
36 struct platform_device
*pdev
;
37 struct gpio_chip gpio_chip
;
38 struct irq_chip irq_chip
;
40 unsigned int irq_parent
;
41 bool has_both_edge_trigger
;
45 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
46 #define INOUTSEL 0x04 /* General Input/Output Switching Register */
47 #define OUTDT 0x08 /* General Output Register */
48 #define INDT 0x0c /* General Input Register */
49 #define INTDT 0x10 /* Interrupt Display Register */
50 #define INTCLR 0x14 /* Interrupt Clear Register */
51 #define INTMSK 0x18 /* Interrupt Mask Register */
52 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
53 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
54 #define EDGLEVEL 0x24 /* Edge/level Select Register */
55 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
56 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
58 #define RCAR_MAX_GPIO_PER_BANK 32
60 static inline u32
gpio_rcar_read(struct gpio_rcar_priv
*p
, int offs
)
62 return ioread32(p
->base
+ offs
);
65 static inline void gpio_rcar_write(struct gpio_rcar_priv
*p
, int offs
,
68 iowrite32(value
, p
->base
+ offs
);
71 static void gpio_rcar_modify_bit(struct gpio_rcar_priv
*p
, int offs
,
74 u32 tmp
= gpio_rcar_read(p
, offs
);
81 gpio_rcar_write(p
, offs
, tmp
);
84 static void gpio_rcar_irq_disable(struct irq_data
*d
)
86 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
87 struct gpio_rcar_priv
*p
= gpiochip_get_data(gc
);
89 gpio_rcar_write(p
, INTMSK
, ~BIT(irqd_to_hwirq(d
)));
92 static void gpio_rcar_irq_enable(struct irq_data
*d
)
94 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
95 struct gpio_rcar_priv
*p
= gpiochip_get_data(gc
);
97 gpio_rcar_write(p
, MSKCLR
, BIT(irqd_to_hwirq(d
)));
100 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv
*p
,
102 bool active_high_rising_edge
,
108 /* follow steps in the GPIO documentation for
109 * "Setting Edge-Sensitive Interrupt Input Mode" and
110 * "Setting Level-Sensitive Interrupt Input Mode"
113 spin_lock_irqsave(&p
->lock
, flags
);
115 /* Configure postive or negative logic in POSNEG */
116 gpio_rcar_modify_bit(p
, POSNEG
, hwirq
, !active_high_rising_edge
);
118 /* Configure edge or level trigger in EDGLEVEL */
119 gpio_rcar_modify_bit(p
, EDGLEVEL
, hwirq
, !level_trigger
);
121 /* Select one edge or both edges in BOTHEDGE */
122 if (p
->has_both_edge_trigger
)
123 gpio_rcar_modify_bit(p
, BOTHEDGE
, hwirq
, both
);
125 /* Select "Interrupt Input Mode" in IOINTSEL */
126 gpio_rcar_modify_bit(p
, IOINTSEL
, hwirq
, true);
128 /* Write INTCLR in case of edge trigger */
130 gpio_rcar_write(p
, INTCLR
, BIT(hwirq
));
132 spin_unlock_irqrestore(&p
->lock
, flags
);
135 static int gpio_rcar_irq_set_type(struct irq_data
*d
, unsigned int type
)
137 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
138 struct gpio_rcar_priv
*p
= gpiochip_get_data(gc
);
139 unsigned int hwirq
= irqd_to_hwirq(d
);
141 dev_dbg(&p
->pdev
->dev
, "sense irq = %d, type = %d\n", hwirq
, type
);
143 switch (type
& IRQ_TYPE_SENSE_MASK
) {
144 case IRQ_TYPE_LEVEL_HIGH
:
145 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, true,
148 case IRQ_TYPE_LEVEL_LOW
:
149 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, false, true,
152 case IRQ_TYPE_EDGE_RISING
:
153 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, false,
156 case IRQ_TYPE_EDGE_FALLING
:
157 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, false, false,
160 case IRQ_TYPE_EDGE_BOTH
:
161 if (!p
->has_both_edge_trigger
)
163 gpio_rcar_config_interrupt_input_mode(p
, hwirq
, true, false,
172 static int gpio_rcar_irq_set_wake(struct irq_data
*d
, unsigned int on
)
174 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
175 struct gpio_rcar_priv
*p
= gpiochip_get_data(gc
);
179 error
= irq_set_irq_wake(p
->irq_parent
, on
);
181 dev_dbg(&p
->pdev
->dev
,
182 "irq %u doesn't support irq_set_wake\n",
199 static irqreturn_t
gpio_rcar_irq_handler(int irq
, void *dev_id
)
201 struct gpio_rcar_priv
*p
= dev_id
;
203 unsigned int offset
, irqs_handled
= 0;
205 while ((pending
= gpio_rcar_read(p
, INTDT
) &
206 gpio_rcar_read(p
, INTMSK
))) {
207 offset
= __ffs(pending
);
208 gpio_rcar_write(p
, INTCLR
, BIT(offset
));
209 generic_handle_irq(irq_find_mapping(p
->gpio_chip
.irqdomain
,
214 return irqs_handled
? IRQ_HANDLED
: IRQ_NONE
;
217 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip
*chip
,
221 struct gpio_rcar_priv
*p
= gpiochip_get_data(chip
);
224 /* follow steps in the GPIO documentation for
225 * "Setting General Output Mode" and
226 * "Setting General Input Mode"
229 spin_lock_irqsave(&p
->lock
, flags
);
231 /* Configure postive logic in POSNEG */
232 gpio_rcar_modify_bit(p
, POSNEG
, gpio
, false);
234 /* Select "General Input/Output Mode" in IOINTSEL */
235 gpio_rcar_modify_bit(p
, IOINTSEL
, gpio
, false);
237 /* Select Input Mode or Output Mode in INOUTSEL */
238 gpio_rcar_modify_bit(p
, INOUTSEL
, gpio
, output
);
240 spin_unlock_irqrestore(&p
->lock
, flags
);
243 static int gpio_rcar_request(struct gpio_chip
*chip
, unsigned offset
)
245 return pinctrl_request_gpio(chip
->base
+ offset
);
248 static void gpio_rcar_free(struct gpio_chip
*chip
, unsigned offset
)
250 pinctrl_free_gpio(chip
->base
+ offset
);
253 * Set the GPIO as an input to ensure that the next GPIO request won't
254 * drive the GPIO pin as an output.
256 gpio_rcar_config_general_input_output_mode(chip
, offset
, false);
259 static int gpio_rcar_direction_input(struct gpio_chip
*chip
, unsigned offset
)
261 gpio_rcar_config_general_input_output_mode(chip
, offset
, false);
265 static int gpio_rcar_get(struct gpio_chip
*chip
, unsigned offset
)
267 u32 bit
= BIT(offset
);
269 /* testing on r8a7790 shows that INDT does not show correct pin state
270 * when configured as output, so use OUTDT in case of output pins */
271 if (gpio_rcar_read(gpiochip_get_data(chip
), INOUTSEL
) & bit
)
272 return !!(gpio_rcar_read(gpiochip_get_data(chip
), OUTDT
) & bit
);
274 return !!(gpio_rcar_read(gpiochip_get_data(chip
), INDT
) & bit
);
277 static void gpio_rcar_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
279 struct gpio_rcar_priv
*p
= gpiochip_get_data(chip
);
282 spin_lock_irqsave(&p
->lock
, flags
);
283 gpio_rcar_modify_bit(p
, OUTDT
, offset
, value
);
284 spin_unlock_irqrestore(&p
->lock
, flags
);
287 static int gpio_rcar_direction_output(struct gpio_chip
*chip
, unsigned offset
,
290 /* write GPIO value to output before selecting output mode of pin */
291 gpio_rcar_set(chip
, offset
, value
);
292 gpio_rcar_config_general_input_output_mode(chip
, offset
, true);
296 struct gpio_rcar_info
{
297 bool has_both_edge_trigger
;
301 static const struct gpio_rcar_info gpio_rcar_info_gen1
= {
302 .has_both_edge_trigger
= false,
306 static const struct gpio_rcar_info gpio_rcar_info_gen2
= {
307 .has_both_edge_trigger
= true,
311 static const struct of_device_id gpio_rcar_of_table
[] = {
313 .compatible
= "renesas,gpio-r8a7790",
314 .data
= &gpio_rcar_info_gen2
,
316 .compatible
= "renesas,gpio-r8a7791",
317 .data
= &gpio_rcar_info_gen2
,
319 .compatible
= "renesas,gpio-r8a7793",
320 .data
= &gpio_rcar_info_gen2
,
322 .compatible
= "renesas,gpio-r8a7794",
323 .data
= &gpio_rcar_info_gen2
,
325 .compatible
= "renesas,gpio-r8a7795",
326 /* Gen3 GPIO is identical to Gen2. */
327 .data
= &gpio_rcar_info_gen2
,
329 .compatible
= "renesas,gpio-rcar",
330 .data
= &gpio_rcar_info_gen1
,
336 MODULE_DEVICE_TABLE(of
, gpio_rcar_of_table
);
338 static int gpio_rcar_parse_dt(struct gpio_rcar_priv
*p
, unsigned int *npins
)
340 struct device_node
*np
= p
->pdev
->dev
.of_node
;
341 const struct of_device_id
*match
;
342 const struct gpio_rcar_info
*info
;
343 struct of_phandle_args args
;
346 match
= of_match_node(gpio_rcar_of_table
, np
);
352 ret
= of_parse_phandle_with_fixed_args(np
, "gpio-ranges", 3, 0, &args
);
353 *npins
= ret
== 0 ? args
.args
[2] : RCAR_MAX_GPIO_PER_BANK
;
354 p
->has_both_edge_trigger
= info
->has_both_edge_trigger
;
355 p
->needs_clk
= info
->needs_clk
;
357 if (*npins
== 0 || *npins
> RCAR_MAX_GPIO_PER_BANK
) {
358 dev_warn(&p
->pdev
->dev
,
359 "Invalid number of gpio lines %u, using %u\n", *npins
,
360 RCAR_MAX_GPIO_PER_BANK
);
361 *npins
= RCAR_MAX_GPIO_PER_BANK
;
367 static int gpio_rcar_probe(struct platform_device
*pdev
)
369 struct gpio_rcar_priv
*p
;
370 struct resource
*io
, *irq
;
371 struct gpio_chip
*gpio_chip
;
372 struct irq_chip
*irq_chip
;
373 struct device
*dev
= &pdev
->dev
;
374 const char *name
= dev_name(dev
);
378 p
= devm_kzalloc(dev
, sizeof(*p
), GFP_KERNEL
);
383 spin_lock_init(&p
->lock
);
385 /* Get device configuration from DT node */
386 ret
= gpio_rcar_parse_dt(p
, &npins
);
390 platform_set_drvdata(pdev
, p
);
392 p
->clk
= devm_clk_get(dev
, NULL
);
393 if (IS_ERR(p
->clk
)) {
395 dev_err(dev
, "unable to get clock\n");
396 ret
= PTR_ERR(p
->clk
);
402 pm_runtime_enable(dev
);
403 pm_runtime_get_sync(dev
);
405 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
406 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
409 dev_err(dev
, "missing IRQ or IOMEM\n");
414 p
->base
= devm_ioremap_nocache(dev
, io
->start
, resource_size(io
));
416 dev_err(dev
, "failed to remap I/O memory\n");
421 gpio_chip
= &p
->gpio_chip
;
422 gpio_chip
->request
= gpio_rcar_request
;
423 gpio_chip
->free
= gpio_rcar_free
;
424 gpio_chip
->direction_input
= gpio_rcar_direction_input
;
425 gpio_chip
->get
= gpio_rcar_get
;
426 gpio_chip
->direction_output
= gpio_rcar_direction_output
;
427 gpio_chip
->set
= gpio_rcar_set
;
428 gpio_chip
->label
= name
;
429 gpio_chip
->parent
= dev
;
430 gpio_chip
->owner
= THIS_MODULE
;
431 gpio_chip
->base
= -1;
432 gpio_chip
->ngpio
= npins
;
434 irq_chip
= &p
->irq_chip
;
435 irq_chip
->name
= name
;
436 irq_chip
->irq_mask
= gpio_rcar_irq_disable
;
437 irq_chip
->irq_unmask
= gpio_rcar_irq_enable
;
438 irq_chip
->irq_set_type
= gpio_rcar_irq_set_type
;
439 irq_chip
->irq_set_wake
= gpio_rcar_irq_set_wake
;
440 irq_chip
->flags
= IRQCHIP_SET_TYPE_MASKED
| IRQCHIP_MASK_ON_SUSPEND
;
442 ret
= gpiochip_add_data(gpio_chip
, p
);
444 dev_err(dev
, "failed to add GPIO controller\n");
448 ret
= gpiochip_irqchip_add(gpio_chip
, irq_chip
, 0, handle_level_irq
,
451 dev_err(dev
, "cannot add irqchip\n");
455 p
->irq_parent
= irq
->start
;
456 if (devm_request_irq(dev
, irq
->start
, gpio_rcar_irq_handler
,
457 IRQF_SHARED
, name
, p
)) {
458 dev_err(dev
, "failed to request IRQ\n");
463 dev_info(dev
, "driving %d GPIOs\n", npins
);
468 gpiochip_remove(gpio_chip
);
471 pm_runtime_disable(dev
);
475 static int gpio_rcar_remove(struct platform_device
*pdev
)
477 struct gpio_rcar_priv
*p
= platform_get_drvdata(pdev
);
479 gpiochip_remove(&p
->gpio_chip
);
481 pm_runtime_put(&pdev
->dev
);
482 pm_runtime_disable(&pdev
->dev
);
486 static struct platform_driver gpio_rcar_device_driver
= {
487 .probe
= gpio_rcar_probe
,
488 .remove
= gpio_rcar_remove
,
491 .of_match_table
= of_match_ptr(gpio_rcar_of_table
),
495 module_platform_driver(gpio_rcar_device_driver
);
497 MODULE_AUTHOR("Magnus Damm");
498 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
499 MODULE_LICENSE("GPL v2");