drivers/gpio/gpio-stmpe.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License Terms: GNU General Public License, version 2
   5  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/slab.h>
  12 #include <linux/gpio.h>
  13 #include <linux/irq.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/of.h>
  17 #include <linux/mfd/stmpe.h>
  18
  19 /*
  20  * These registers are modified under the irq bus lock and cached to avoid
  21  * unnecessary writes in bus_sync_unlock.
  22  */
  23 enum { REG_RE, REG_FE, REG_IE };
  24
  25 #define CACHE_NR_REGS   3
  26 /* No variant has more than 24 GPIOs */
  27 #define CACHE_NR_BANKS  (24 / 8)
  28
  29 struct stmpe_gpio {
  30         struct gpio_chip chip;
  31         struct stmpe *stmpe;
  32         struct device *dev;
  33         struct mutex irq_lock;
  34         struct irq_domain *domain;
  35         unsigned norequest_mask;
  36
  37         /* Caches of interrupt control registers for bus_lock */
  38         u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  39         u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  40 };
  41
  42 static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
  43 {
  44         return container_of(chip, struct stmpe_gpio, chip);
  45 }
  46
  47 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
  48 {
  49         struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  50         struct stmpe *stmpe = stmpe_gpio->stmpe;
  51         u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
  52         u8 mask = 1 << (offset % 8);
  53         int ret;
  54
  55         ret = stmpe_reg_read(stmpe, reg);
  56         if (ret < 0)
  57                 return ret;
  58
  59         return !!(ret & mask);
  60 }
  61
  62 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  63 {
  64         struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  65         struct stmpe *stmpe = stmpe_gpio->stmpe;
  66         int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
  67         u8 reg = stmpe->regs[which] - (offset / 8);
  68         u8 mask = 1 << (offset % 8);
  69
  70         /*
  71          * Some variants have single register for gpio set/clear functionality.
  72          * For them we need to write 0 to clear and 1 to set.
  73          */
  74         if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
  75                 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
  76         else
  77                 stmpe_reg_write(stmpe, reg, mask);
  78 }
  79
  80 static int stmpe_gpio_direction_output(struct gpio_chip *chip,
  81                                          unsigned offset, int val)
  82 {
  83         struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  84         struct stmpe *stmpe = stmpe_gpio->stmpe;
  85         u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
  86         u8 mask = 1 << (offset % 8);
  87
  88         stmpe_gpio_set(chip, offset, val);
  89
  90         return stmpe_set_bits(stmpe, reg, mask, mask);
  91 }
  92
  93 static int stmpe_gpio_direction_input(struct gpio_chip *chip,
  94                                         unsigned offset)
  95 {
  96         struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  97         struct stmpe *stmpe = stmpe_gpio->stmpe;
  98         u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
  99         u8 mask = 1 << (offset % 8);
 100
 101         return stmpe_set_bits(stmpe, reg, mask, 0);
 102 }
 103
 104 static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 105 {
 106         struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 107
 108         return irq_create_mapping(stmpe_gpio->domain, offset);
 109 }
 110
 111 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
 112 {
 113         struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 114         struct stmpe *stmpe = stmpe_gpio->stmpe;
 115
 116         if (stmpe_gpio->norequest_mask & (1 << offset))
 117                 return -EINVAL;
 118
 119         return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
 120 }
 121
 122 static struct gpio_chip template_chip = {
 123         .label                  = "stmpe",
 124         .owner                  = THIS_MODULE,
 125         .direction_input        = stmpe_gpio_direction_input,
 126         .get                    = stmpe_gpio_get,
 127         .direction_output       = stmpe_gpio_direction_output,
 128         .set                    = stmpe_gpio_set,
 129         .to_irq                 = stmpe_gpio_to_irq,
 130         .request                = stmpe_gpio_request,
 131         .can_sleep              = true,
 132 };
 133
 134 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 135 {
 136         struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
 137         int offset = d->hwirq;
 138         int regoffset = offset / 8;
 139         int mask = 1 << (offset % 8);
 140
 141         if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
 142                 return -EINVAL;
 143
 144         /* STMPE801 doesn't have RE and FE registers */
 145         if (stmpe_gpio->stmpe->partnum == STMPE801)
 146                 return 0;
 147
 148         if (type == IRQ_TYPE_EDGE_RISING)
 149                 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
 150         else
 151                 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
 152
 153         if (type == IRQ_TYPE_EDGE_FALLING)
 154                 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
 155         else
 156                 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
 157
 158         return 0;
 159 }
 160
 161 static void stmpe_gpio_irq_lock(struct irq_data *d)
 162 {
 163         struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
 164
 165         mutex_lock(&stmpe_gpio->irq_lock);
 166 }
 167
 168 static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
 169 {
 170         struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
 171         struct stmpe *stmpe = stmpe_gpio->stmpe;
 172         int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
 173         static const u8 regmap[] = {
 174                 [REG_RE]        = STMPE_IDX_GPRER_LSB,
 175                 [REG_FE]        = STMPE_IDX_GPFER_LSB,
 176                 [REG_IE]        = STMPE_IDX_IEGPIOR_LSB,
 177         };
 178         int i, j;
 179
 180         for (i = 0; i < CACHE_NR_REGS; i++) {
 181                 /* STMPE801 doesn't have RE and FE registers */
 182                 if ((stmpe->partnum == STMPE801) &&
 183                                 (i != REG_IE))
 184                         continue;
 185
 186                 for (j = 0; j < num_banks; j++) {
 187                         u8 old = stmpe_gpio->oldregs[i][j];
 188                         u8 new = stmpe_gpio->regs[i][j];
 189
 190                         if (new == old)
 191                                 continue;
 192
 193                         stmpe_gpio->oldregs[i][j] = new;
 194                         stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
 195                 }
 196         }
 197
 198         mutex_unlock(&stmpe_gpio->irq_lock);
 199 }
 200
 201 static void stmpe_gpio_irq_mask(struct irq_data *d)
 202 {
 203         struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
 204         int offset = d->hwirq;
 205         int regoffset = offset / 8;
 206         int mask = 1 << (offset % 8);
 207
 208         stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
 209 }
 210
 211 static void stmpe_gpio_irq_unmask(struct irq_data *d)
 212 {
 213         struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
 214         int offset = d->hwirq;
 215         int regoffset = offset / 8;
 216         int mask = 1 << (offset % 8);
 217
 218         stmpe_gpio->regs[REG_IE][regoffset] |= mask;
 219 }
 220
 221 static struct irq_chip stmpe_gpio_irq_chip = {
 222         .name                   = "stmpe-gpio",
 223         .irq_bus_lock           = stmpe_gpio_irq_lock,
 224         .irq_bus_sync_unlock    = stmpe_gpio_irq_sync_unlock,
 225         .irq_mask               = stmpe_gpio_irq_mask,
 226         .irq_unmask             = stmpe_gpio_irq_unmask,
 227         .irq_set_type           = stmpe_gpio_irq_set_type,
 228 };
 229
 230 static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
 231 {
 232         struct stmpe_gpio *stmpe_gpio = dev;
 233         struct stmpe *stmpe = stmpe_gpio->stmpe;
 234         u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
 235         int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
 236         u8 status[num_banks];
 237         int ret;
 238         int i;
 239
 240         ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
 241         if (ret < 0)
 242                 return IRQ_NONE;
 243
 244         for (i = 0; i < num_banks; i++) {
 245                 int bank = num_banks - i - 1;
 246                 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
 247                 unsigned int stat = status[i];
 248
 249                 stat &= enabled;
 250                 if (!stat)
 251                         continue;
 252
 253                 while (stat) {
 254                         int bit = __ffs(stat);
 255                         int line = bank * 8 + bit;
 256                         int child_irq = irq_find_mapping(stmpe_gpio->domain,
 257                                                          line);
 258
 259                         handle_nested_irq(child_irq);
 260                         stat &= ~(1 << bit);
 261                 }
 262
 263                 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
 264
 265                 /* Edge detect register is not present on 801 */
 266                 if (stmpe->partnum != STMPE801)
 267                         stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
 268                                         + i, status[i]);
 269         }
 270
 271         return IRQ_HANDLED;
 272 }
 273
 274 static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 275                               irq_hw_number_t hwirq)
 276 {
 277         struct stmpe_gpio *stmpe_gpio = d->host_data;
 278
 279         if (!stmpe_gpio)
 280                 return -EINVAL;
 281
 282         irq_set_chip_data(irq, stmpe_gpio);
 283         irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
 284                                  handle_simple_irq);
 285         irq_set_nested_thread(irq, 1);
 286 #ifdef CONFIG_ARM
 287         set_irq_flags(irq, IRQF_VALID);
 288 #else
 289         irq_set_noprobe(irq);
 290 #endif
 291
 292         return 0;
 293 }
 294
 295 static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
 296 {
 297 #ifdef CONFIG_ARM
 298         set_irq_flags(irq, 0);
 299 #endif
 300         irq_set_chip_and_handler(irq, NULL, NULL);
 301         irq_set_chip_data(irq, NULL);
 302 }
 303
 304 static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
 305         .unmap = stmpe_gpio_irq_unmap,
 306         .map = stmpe_gpio_irq_map,
 307         .xlate = irq_domain_xlate_twocell,
 308 };
 309
 310 static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
 311                 struct device_node *np)
 312 {
 313         stmpe_gpio->domain = irq_domain_add_simple(np,
 314                                 stmpe_gpio->chip.ngpio, 0,
 315                                 &stmpe_gpio_irq_simple_ops, stmpe_gpio);
 316         if (!stmpe_gpio->domain) {
 317                 dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
 318                 return -ENOSYS;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int stmpe_gpio_probe(struct platform_device *pdev)
 325 {
 326         struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
 327         struct device_node *np = pdev->dev.of_node;
 328         struct stmpe_gpio_platform_data *pdata;
 329         struct stmpe_gpio *stmpe_gpio;
 330         int ret;
 331         int irq = 0;
 332
 333         pdata = stmpe->pdata->gpio;
 334
 335         irq = platform_get_irq(pdev, 0);
 336
 337         stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
 338         if (!stmpe_gpio)
 339                 return -ENOMEM;
 340
 341         mutex_init(&stmpe_gpio->irq_lock);
 342
 343         stmpe_gpio->dev = &pdev->dev;
 344         stmpe_gpio->stmpe = stmpe;
 345         stmpe_gpio->chip = template_chip;
 346         stmpe_gpio->chip.ngpio = stmpe->num_gpios;
 347         stmpe_gpio->chip.dev = &pdev->dev;
 348 #ifdef CONFIG_OF
 349         stmpe_gpio->chip.of_node = np;
 350 #endif
 351         stmpe_gpio->chip.base = -1;
 352
 353         if (pdata)
 354                 stmpe_gpio->norequest_mask = pdata->norequest_mask;
 355         else if (np)
 356                 of_property_read_u32(np, "st,norequest-mask",
 357                                 &stmpe_gpio->norequest_mask);
 358
 359         if (irq < 0)
 360                 dev_info(&pdev->dev,
 361                         "device configured in no-irq mode; "
 362                         "irqs are not available\n");
 363
 364         ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
 365         if (ret)
 366                 goto out_free;
 367
 368         if (irq >= 0) {
 369                 ret = stmpe_gpio_irq_init(stmpe_gpio, np);
 370                 if (ret)
 371                         goto out_disable;
 372
 373                 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
 374                                 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
 375                 if (ret) {
 376                         dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
 377                         goto out_disable;
 378                 }
 379         }
 380
 381         ret = gpiochip_add(&stmpe_gpio->chip);
 382         if (ret) {
 383                 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
 384                 goto out_freeirq;
 385         }
 386
 387         if (pdata && pdata->setup)
 388                 pdata->setup(stmpe, stmpe_gpio->chip.base);
 389
 390         platform_set_drvdata(pdev, stmpe_gpio);
 391
 392         return 0;
 393
 394 out_freeirq:
 395         if (irq >= 0)
 396                 free_irq(irq, stmpe_gpio);
 397 out_disable:
 398         stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
 399 out_free:
 400         kfree(stmpe_gpio);
 401         return ret;
 402 }
 403
 404 static int stmpe_gpio_remove(struct platform_device *pdev)
 405 {
 406         struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
 407         struct stmpe *stmpe = stmpe_gpio->stmpe;
 408         struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
 409         int irq = platform_get_irq(pdev, 0);
 410         int ret;
 411
 412         if (pdata && pdata->remove)
 413                 pdata->remove(stmpe, stmpe_gpio->chip.base);
 414
 415         ret = gpiochip_remove(&stmpe_gpio->chip);
 416         if (ret < 0) {
 417                 dev_err(stmpe_gpio->dev,
 418                         "unable to remove gpiochip: %d\n", ret);
 419                 return ret;
 420         }
 421
 422         stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
 423
 424         if (irq >= 0)
 425                 free_irq(irq, stmpe_gpio);
 426
 427         kfree(stmpe_gpio);
 428
 429         return 0;
 430 }
 431
 432 static struct platform_driver stmpe_gpio_driver = {
 433         .driver.name    = "stmpe-gpio",
 434         .driver.owner   = THIS_MODULE,
 435         .probe          = stmpe_gpio_probe,
 436         .remove         = stmpe_gpio_remove,
 437 };
 438
 439 static int __init stmpe_gpio_init(void)
 440 {
 441         return platform_driver_register(&stmpe_gpio_driver);
 442 }
 443 subsys_initcall(stmpe_gpio_init);
 444
 445 static void __exit stmpe_gpio_exit(void)
 446 {
 447         platform_driver_unregister(&stmpe_gpio_driver);
 448 }
 449 module_exit(stmpe_gpio_exit);
 450
 451 MODULE_LICENSE("GPL v2");
 452 MODULE_DESCRIPTION("STMPExxxx GPIO driver");
 453 MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");