drivers/gpio/gpio-tegra.c

   1 /*
   2  * arch/arm/mach-tegra/gpio.c
   3  *
   4  * Copyright (c) 2010 Google, Inc
   5  *
   6  * Author:
   7  *      Erik Gilling <konkers@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/irq.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/gpio.h>
  25 #include <linux/of.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/module.h>
  28 #include <linux/irqdomain.h>
  29
  30 #include <asm/mach/irq.h>
  31
  32 #include <mach/gpio-tegra.h>
  33 #include <mach/iomap.h>
  34 #include <mach/suspend.h>
  35
  36 #define GPIO_BANK(x)            ((x) >> 5)
  37 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
  38 #define GPIO_BIT(x)             ((x) & 0x7)
  39
  40 #define GPIO_REG(x)             (GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4)
  41
  42 #define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
  43 #define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
  44 #define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
  45 #define GPIO_IN(x)              (GPIO_REG(x) + 0x30)
  46 #define GPIO_INT_STA(x)         (GPIO_REG(x) + 0x40)
  47 #define GPIO_INT_ENB(x)         (GPIO_REG(x) + 0x50)
  48 #define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
  49 #define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
  50
  51 #define GPIO_MSK_CNF(x)         (GPIO_REG(x) + 0x800)
  52 #define GPIO_MSK_OE(x)          (GPIO_REG(x) + 0x810)
  53 #define GPIO_MSK_OUT(x)         (GPIO_REG(x) + 0X820)
  54 #define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + 0x840)
  55 #define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + 0x850)
  56 #define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + 0x860)
  57
  58 #define GPIO_INT_LVL_MASK               0x010101
  59 #define GPIO_INT_LVL_EDGE_RISING        0x000101
  60 #define GPIO_INT_LVL_EDGE_FALLING       0x000100
  61 #define GPIO_INT_LVL_EDGE_BOTH          0x010100
  62 #define GPIO_INT_LVL_LEVEL_HIGH         0x000001
  63 #define GPIO_INT_LVL_LEVEL_LOW          0x000000
  64
  65 struct tegra_gpio_bank {
  66         int bank;
  67         int irq;
  68         spinlock_t lvl_lock[4];
  69 #ifdef CONFIG_PM
  70         u32 cnf[4];
  71         u32 out[4];
  72         u32 oe[4];
  73         u32 int_enb[4];
  74         u32 int_lvl[4];
  75 #endif
  76 };
  77
  78 static struct irq_domain *irq_domain;
  79 static void __iomem *regs;
  80 static u32 tegra_gpio_bank_count;
  81 static struct tegra_gpio_bank *tegra_gpio_banks;
  82
  83 static inline void tegra_gpio_writel(u32 val, u32 reg)
  84 {
  85         __raw_writel(val, regs + reg);
  86 }
  87
  88 static inline u32 tegra_gpio_readl(u32 reg)
  89 {
  90         return __raw_readl(regs + reg);
  91 }
  92
  93 static int tegra_gpio_compose(int bank, int port, int bit)
  94 {
  95         return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  96 }
  97
  98 static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
  99 {
 100         u32 val;
 101
 102         val = 0x100 << GPIO_BIT(gpio);
 103         if (value)
 104                 val |= 1 << GPIO_BIT(gpio);
 105         tegra_gpio_writel(val, reg);
 106 }
 107
 108 void tegra_gpio_enable(int gpio)
 109 {
 110         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 111 }
 112 EXPORT_SYMBOL_GPL(tegra_gpio_enable);
 113
 114 void tegra_gpio_disable(int gpio)
 115 {
 116         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 117 }
 118 EXPORT_SYMBOL_GPL(tegra_gpio_disable);
 119
 120 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 121 {
 122         tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
 123 }
 124
 125 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 126 {
 127         return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
 128 }
 129
 130 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 131 {
 132         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
 133         return 0;
 134 }
 135
 136 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 137                                         int value)
 138 {
 139         tegra_gpio_set(chip, offset, value);
 140         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
 141         return 0;
 142 }
 143
 144 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 145 {
 146         return irq_find_mapping(irq_domain, offset);
 147 }
 148
 149 static struct gpio_chip tegra_gpio_chip = {
 150         .label                  = "tegra-gpio",
 151         .direction_input        = tegra_gpio_direction_input,
 152         .get                    = tegra_gpio_get,
 153         .direction_output       = tegra_gpio_direction_output,
 154         .set                    = tegra_gpio_set,
 155         .to_irq                 = tegra_gpio_to_irq,
 156         .base                   = 0,
 157         .ngpio                  = TEGRA_NR_GPIOS,
 158 };
 159
 160 static void tegra_gpio_irq_ack(struct irq_data *d)
 161 {
 162         int gpio = d->hwirq;
 163
 164         tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 165 }
 166
 167 static void tegra_gpio_irq_mask(struct irq_data *d)
 168 {
 169         int gpio = d->hwirq;
 170
 171         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
 172 }
 173
 174 static void tegra_gpio_irq_unmask(struct irq_data *d)
 175 {
 176         int gpio = d->hwirq;
 177
 178         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
 179 }
 180
 181 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 182 {
 183         int gpio = d->hwirq;
 184         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 185         int port = GPIO_PORT(gpio);
 186         int lvl_type;
 187         int val;
 188         unsigned long flags;
 189
 190         switch (type & IRQ_TYPE_SENSE_MASK) {
 191         case IRQ_TYPE_EDGE_RISING:
 192                 lvl_type = GPIO_INT_LVL_EDGE_RISING;
 193                 break;
 194
 195         case IRQ_TYPE_EDGE_FALLING:
 196                 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
 197                 break;
 198
 199         case IRQ_TYPE_EDGE_BOTH:
 200                 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
 201                 break;
 202
 203         case IRQ_TYPE_LEVEL_HIGH:
 204                 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
 205                 break;
 206
 207         case IRQ_TYPE_LEVEL_LOW:
 208                 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
 209                 break;
 210
 211         default:
 212                 return -EINVAL;
 213         }
 214
 215         spin_lock_irqsave(&bank->lvl_lock[port], flags);
 216
 217         val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 218         val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 219         val |= lvl_type << GPIO_BIT(gpio);
 220         tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
 221
 222         spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 223
 224         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 225                 __irq_set_handler_locked(d->irq, handle_level_irq);
 226         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 227                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 228
 229         return 0;
 230 }
 231
 232 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 233 {
 234         struct tegra_gpio_bank *bank;
 235         int port;
 236         int pin;
 237         int unmasked = 0;
 238         struct irq_chip *chip = irq_desc_get_chip(desc);
 239
 240         chained_irq_enter(chip, desc);
 241
 242         bank = irq_get_handler_data(irq);
 243
 244         for (port = 0; port < 4; port++) {
 245                 int gpio = tegra_gpio_compose(bank->bank, port, 0);
 246                 unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
 247                         tegra_gpio_readl(GPIO_INT_ENB(gpio));
 248                 u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 249
 250                 for_each_set_bit(pin, &sta, 8) {
 251                         tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
 252
 253                         /* if gpio is edge triggered, clear condition
 254                          * before executing the hander so that we don't
 255                          * miss edges
 256                          */
 257                         if (lvl & (0x100 << pin)) {
 258                                 unmasked = 1;
 259                                 chained_irq_exit(chip, desc);
 260                         }
 261
 262                         generic_handle_irq(gpio_to_irq(gpio + pin));
 263                 }
 264         }
 265
 266         if (!unmasked)
 267                 chained_irq_exit(chip, desc);
 268
 269 }
 270
 271 #ifdef CONFIG_PM
 272 void tegra_gpio_resume(void)
 273 {
 274         unsigned long flags;
 275         int b;
 276         int p;
 277
 278         local_irq_save(flags);
 279
 280         for (b = 0; b < tegra_gpio_bank_count; b++) {
 281                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 282
 283                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 284                         unsigned int gpio = (b<<5) | (p<<3);
 285                         tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
 286                         tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
 287                         tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
 288                         tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
 289                         tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
 290                 }
 291         }
 292
 293         local_irq_restore(flags);
 294 }
 295
 296 void tegra_gpio_suspend(void)
 297 {
 298         unsigned long flags;
 299         int b;
 300         int p;
 301
 302         local_irq_save(flags);
 303         for (b = 0; b < tegra_gpio_bank_count; b++) {
 304                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 305
 306                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 307                         unsigned int gpio = (b<<5) | (p<<3);
 308                         bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
 309                         bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
 310                         bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
 311                         bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
 312                         bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 313                 }
 314         }
 315         local_irq_restore(flags);
 316 }
 317
 318 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 319 {
 320         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 321         return irq_set_irq_wake(bank->irq, enable);
 322 }
 323 #endif
 324
 325 static struct irq_chip tegra_gpio_irq_chip = {
 326         .name           = "GPIO",
 327         .irq_ack        = tegra_gpio_irq_ack,
 328         .irq_mask       = tegra_gpio_irq_mask,
 329         .irq_unmask     = tegra_gpio_irq_unmask,
 330         .irq_set_type   = tegra_gpio_irq_set_type,
 331 #ifdef CONFIG_PM
 332         .irq_set_wake   = tegra_gpio_wake_enable,
 333 #endif
 334 };
 335
 336
 337 /* This lock class tells lockdep that GPIO irqs are in a different
 338  * category than their parents, so it won't report false recursion.
 339  */
 340 static struct lock_class_key gpio_lock_class;
 341
 342 static int __devinit tegra_gpio_probe(struct platform_device *pdev)
 343 {
 344         int irq_base;
 345         struct resource *res;
 346         struct tegra_gpio_bank *bank;
 347         int gpio;
 348         int i;
 349         int j;
 350
 351         for (;;) {
 352                 res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
 353                 if (!res)
 354                         break;
 355                 tegra_gpio_bank_count++;
 356         }
 357         if (!tegra_gpio_bank_count) {
 358                 dev_err(&pdev->dev, "Missing IRQ resource\n");
 359                 return -ENODEV;
 360         }
 361
 362         tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
 363
 364         tegra_gpio_banks = devm_kzalloc(&pdev->dev,
 365                         tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
 366                         GFP_KERNEL);
 367         if (!tegra_gpio_banks) {
 368                 dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
 369                 return -ENODEV;
 370         }
 371
 372         irq_base = irq_alloc_descs(-1, 0, tegra_gpio_chip.ngpio, 0);
 373         if (irq_base < 0) {
 374                 dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n");
 375                 return -ENODEV;
 376         }
 377         irq_domain = irq_domain_add_legacy(pdev->dev.of_node,
 378                                            tegra_gpio_chip.ngpio, irq_base, 0,
 379                                            &irq_domain_simple_ops, NULL);
 380
 381         for (i = 0; i < tegra_gpio_bank_count; i++) {
 382                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
 383                 if (!res) {
 384                         dev_err(&pdev->dev, "Missing IRQ resource\n");
 385                         return -ENODEV;
 386                 }
 387
 388                 bank = &tegra_gpio_banks[i];
 389                 bank->bank = i;
 390                 bank->irq = res->start;
 391         }
 392
 393         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 394         if (!res) {
 395                 dev_err(&pdev->dev, "Missing MEM resource\n");
 396                 return -ENODEV;
 397         }
 398
 399         regs = devm_request_and_ioremap(&pdev->dev, res);
 400         if (!regs) {
 401                 dev_err(&pdev->dev, "Couldn't ioremap regs\n");
 402                 return -ENODEV;
 403         }
 404
 405         for (i = 0; i < 7; i++) {
 406                 for (j = 0; j < 4; j++) {
 407                         int gpio = tegra_gpio_compose(i, j, 0);
 408                         tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
 409                 }
 410         }
 411
 412 #ifdef CONFIG_OF_GPIO
 413         tegra_gpio_chip.of_node = pdev->dev.of_node;
 414 #endif
 415
 416         gpiochip_add(&tegra_gpio_chip);
 417
 418         for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
 419                 int irq = irq_find_mapping(irq_domain, gpio);
 420                 /* No validity check; all Tegra GPIOs are valid IRQs */
 421
 422                 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
 423
 424                 irq_set_lockdep_class(irq, &gpio_lock_class);
 425                 irq_set_chip_data(irq, bank);
 426                 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
 427                                          handle_simple_irq);
 428                 set_irq_flags(irq, IRQF_VALID);
 429         }
 430
 431         for (i = 0; i < tegra_gpio_bank_count; i++) {
 432                 bank = &tegra_gpio_banks[i];
 433
 434                 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
 435                 irq_set_handler_data(bank->irq, bank);
 436
 437                 for (j = 0; j < 4; j++)
 438                         spin_lock_init(&bank->lvl_lock[j]);
 439         }
 440
 441         return 0;
 442 }
 443
 444 static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
 445         { .compatible = "nvidia,tegra20-gpio", },
 446         { },
 447 };
 448
 449 static struct platform_driver tegra_gpio_driver = {
 450         .driver         = {
 451                 .name   = "tegra-gpio",
 452                 .owner  = THIS_MODULE,
 453                 .of_match_table = tegra_gpio_of_match,
 454         },
 455         .probe          = tegra_gpio_probe,
 456 };
 457
 458 static int __init tegra_gpio_init(void)
 459 {
 460         return platform_driver_register(&tegra_gpio_driver);
 461 }
 462 postcore_initcall(tegra_gpio_init);
 463
 464 void tegra_gpio_config(struct tegra_gpio_table *table, int num)
 465 {
 466         int i;
 467
 468         for (i = 0; i < num; i++) {
 469                 int gpio = table[i].gpio;
 470
 471                 if (table[i].enable)
 472                         tegra_gpio_enable(gpio);
 473                 else
 474                         tegra_gpio_disable(gpio);
 475         }
 476 }
 477
 478 #ifdef  CONFIG_DEBUG_FS
 479
 480 #include <linux/debugfs.h>
 481 #include <linux/seq_file.h>
 482
 483 static int dbg_gpio_show(struct seq_file *s, void *unused)
 484 {
 485         int i;
 486         int j;
 487
 488         for (i = 0; i < 7; i++) {
 489                 for (j = 0; j < 4; j++) {
 490                         int gpio = tegra_gpio_compose(i, j, 0);
 491                         seq_printf(s,
 492                                 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
 493                                 i, j,
 494                                 tegra_gpio_readl(GPIO_CNF(gpio)),
 495                                 tegra_gpio_readl(GPIO_OE(gpio)),
 496                                 tegra_gpio_readl(GPIO_OUT(gpio)),
 497                                 tegra_gpio_readl(GPIO_IN(gpio)),
 498                                 tegra_gpio_readl(GPIO_INT_STA(gpio)),
 499                                 tegra_gpio_readl(GPIO_INT_ENB(gpio)),
 500                                 tegra_gpio_readl(GPIO_INT_LVL(gpio)));
 501                 }
 502         }
 503         return 0;
 504 }
 505
 506 static int dbg_gpio_open(struct inode *inode, struct file *file)
 507 {
 508         return single_open(file, dbg_gpio_show, &inode->i_private);
 509 }
 510
 511 static const struct file_operations debug_fops = {
 512         .open           = dbg_gpio_open,
 513         .read           = seq_read,
 514         .llseek         = seq_lseek,
 515         .release        = single_release,
 516 };
 517
 518 static int __init tegra_gpio_debuginit(void)
 519 {
 520         (void) debugfs_create_file("tegra_gpio", S_IRUGO,
 521                                         NULL, NULL, &debug_fops);
 522         return 0;
 523 }
 524 late_initcall(tegra_gpio_debuginit);
 525 #endif