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gpio/ep93xx: Remove unused inline function and useless pr_err message
[deliverable/linux.git] / drivers / gpio / gpio-tegra.c
1 /*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/of.h>
26 #include <linux/platform_device.h>
27 #include <linux/module.h>
28
29 #include <asm/mach/irq.h>
30
31 #include <mach/gpio-tegra.h>
32 #include <mach/iomap.h>
33 #include <mach/suspend.h>
34
35 #define GPIO_BANK(x) ((x) >> 5)
36 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
37 #define GPIO_BIT(x) ((x) & 0x7)
38
39 #define GPIO_REG(x) (GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4)
40
41 #define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
42 #define GPIO_OE(x) (GPIO_REG(x) + 0x10)
43 #define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
44 #define GPIO_IN(x) (GPIO_REG(x) + 0x30)
45 #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
46 #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
47 #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
48 #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
49
50 #define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800)
51 #define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810)
52 #define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820)
53 #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840)
54 #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850)
55 #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860)
56
57 #define GPIO_INT_LVL_MASK 0x010101
58 #define GPIO_INT_LVL_EDGE_RISING 0x000101
59 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
60 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
61 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
62 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
63
64 struct tegra_gpio_bank {
65 int bank;
66 int irq;
67 spinlock_t lvl_lock[4];
68 #ifdef CONFIG_PM
69 u32 cnf[4];
70 u32 out[4];
71 u32 oe[4];
72 u32 int_enb[4];
73 u32 int_lvl[4];
74 #endif
75 };
76
77
78 static void __iomem *regs;
79 static struct tegra_gpio_bank tegra_gpio_banks[7];
80
81 static inline void tegra_gpio_writel(u32 val, u32 reg)
82 {
83 __raw_writel(val, regs + reg);
84 }
85
86 static inline u32 tegra_gpio_readl(u32 reg)
87 {
88 return __raw_readl(regs + reg);
89 }
90
91 static int tegra_gpio_compose(int bank, int port, int bit)
92 {
93 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
94 }
95
96 static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
97 {
98 u32 val;
99
100 val = 0x100 << GPIO_BIT(gpio);
101 if (value)
102 val |= 1 << GPIO_BIT(gpio);
103 tegra_gpio_writel(val, reg);
104 }
105
106 void tegra_gpio_enable(int gpio)
107 {
108 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
109 }
110 EXPORT_SYMBOL_GPL(tegra_gpio_enable);
111
112 void tegra_gpio_disable(int gpio)
113 {
114 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
115 }
116 EXPORT_SYMBOL_GPL(tegra_gpio_disable);
117
118 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
119 {
120 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
121 }
122
123 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
124 {
125 return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
126 }
127
128 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
129 {
130 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
131 return 0;
132 }
133
134 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
135 int value)
136 {
137 tegra_gpio_set(chip, offset, value);
138 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
139 return 0;
140 }
141
142 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
143 {
144 return TEGRA_GPIO_TO_IRQ(offset);
145 }
146
147 static struct gpio_chip tegra_gpio_chip = {
148 .label = "tegra-gpio",
149 .direction_input = tegra_gpio_direction_input,
150 .get = tegra_gpio_get,
151 .direction_output = tegra_gpio_direction_output,
152 .set = tegra_gpio_set,
153 .to_irq = tegra_gpio_to_irq,
154 .base = 0,
155 .ngpio = TEGRA_NR_GPIOS,
156 };
157
158 static void tegra_gpio_irq_ack(struct irq_data *d)
159 {
160 int gpio = d->irq - INT_GPIO_BASE;
161
162 tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
163 }
164
165 static void tegra_gpio_irq_mask(struct irq_data *d)
166 {
167 int gpio = d->irq - INT_GPIO_BASE;
168
169 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
170 }
171
172 static void tegra_gpio_irq_unmask(struct irq_data *d)
173 {
174 int gpio = d->irq - INT_GPIO_BASE;
175
176 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
177 }
178
179 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
180 {
181 int gpio = d->irq - INT_GPIO_BASE;
182 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
183 int port = GPIO_PORT(gpio);
184 int lvl_type;
185 int val;
186 unsigned long flags;
187
188 switch (type & IRQ_TYPE_SENSE_MASK) {
189 case IRQ_TYPE_EDGE_RISING:
190 lvl_type = GPIO_INT_LVL_EDGE_RISING;
191 break;
192
193 case IRQ_TYPE_EDGE_FALLING:
194 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
195 break;
196
197 case IRQ_TYPE_EDGE_BOTH:
198 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
199 break;
200
201 case IRQ_TYPE_LEVEL_HIGH:
202 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
203 break;
204
205 case IRQ_TYPE_LEVEL_LOW:
206 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
207 break;
208
209 default:
210 return -EINVAL;
211 }
212
213 spin_lock_irqsave(&bank->lvl_lock[port], flags);
214
215 val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
216 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
217 val |= lvl_type << GPIO_BIT(gpio);
218 tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
219
220 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
221
222 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
223 __irq_set_handler_locked(d->irq, handle_level_irq);
224 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
225 __irq_set_handler_locked(d->irq, handle_edge_irq);
226
227 return 0;
228 }
229
230 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
231 {
232 struct tegra_gpio_bank *bank;
233 int port;
234 int pin;
235 int unmasked = 0;
236 struct irq_chip *chip = irq_desc_get_chip(desc);
237
238 chained_irq_enter(chip, desc);
239
240 bank = irq_get_handler_data(irq);
241
242 for (port = 0; port < 4; port++) {
243 int gpio = tegra_gpio_compose(bank->bank, port, 0);
244 unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
245 tegra_gpio_readl(GPIO_INT_ENB(gpio));
246 u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
247
248 for_each_set_bit(pin, &sta, 8) {
249 tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
250
251 /* if gpio is edge triggered, clear condition
252 * before executing the hander so that we don't
253 * miss edges
254 */
255 if (lvl & (0x100 << pin)) {
256 unmasked = 1;
257 chained_irq_exit(chip, desc);
258 }
259
260 generic_handle_irq(gpio_to_irq(gpio + pin));
261 }
262 }
263
264 if (!unmasked)
265 chained_irq_exit(chip, desc);
266
267 }
268
269 #ifdef CONFIG_PM
270 void tegra_gpio_resume(void)
271 {
272 unsigned long flags;
273 int b;
274 int p;
275
276 local_irq_save(flags);
277
278 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
279 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
280
281 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
282 unsigned int gpio = (b<<5) | (p<<3);
283 tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
284 tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
285 tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
286 tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
287 tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
288 }
289 }
290
291 local_irq_restore(flags);
292 }
293
294 void tegra_gpio_suspend(void)
295 {
296 unsigned long flags;
297 int b;
298 int p;
299
300 local_irq_save(flags);
301 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
302 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
303
304 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
305 unsigned int gpio = (b<<5) | (p<<3);
306 bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
307 bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
308 bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
309 bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
310 bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
311 }
312 }
313 local_irq_restore(flags);
314 }
315
316 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
317 {
318 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
319 return irq_set_irq_wake(bank->irq, enable);
320 }
321 #endif
322
323 static struct irq_chip tegra_gpio_irq_chip = {
324 .name = "GPIO",
325 .irq_ack = tegra_gpio_irq_ack,
326 .irq_mask = tegra_gpio_irq_mask,
327 .irq_unmask = tegra_gpio_irq_unmask,
328 .irq_set_type = tegra_gpio_irq_set_type,
329 #ifdef CONFIG_PM
330 .irq_set_wake = tegra_gpio_wake_enable,
331 #endif
332 };
333
334
335 /* This lock class tells lockdep that GPIO irqs are in a different
336 * category than their parents, so it won't report false recursion.
337 */
338 static struct lock_class_key gpio_lock_class;
339
340 static int __devinit tegra_gpio_probe(struct platform_device *pdev)
341 {
342 struct resource *res;
343 struct tegra_gpio_bank *bank;
344 int gpio;
345 int i;
346 int j;
347
348 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
349 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
350 if (!res) {
351 dev_err(&pdev->dev, "Missing IRQ resource\n");
352 return -ENODEV;
353 }
354
355 bank = &tegra_gpio_banks[i];
356 bank->bank = i;
357 bank->irq = res->start;
358 }
359
360 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
361 if (!res) {
362 dev_err(&pdev->dev, "Missing MEM resource\n");
363 return -ENODEV;
364 }
365
366 regs = devm_request_and_ioremap(&pdev->dev, res);
367 if (!regs) {
368 dev_err(&pdev->dev, "Couldn't ioremap regs\n");
369 return -ENODEV;
370 }
371
372 for (i = 0; i < 7; i++) {
373 for (j = 0; j < 4; j++) {
374 int gpio = tegra_gpio_compose(i, j, 0);
375 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
376 }
377 }
378
379 #ifdef CONFIG_OF_GPIO
380 tegra_gpio_chip.of_node = pdev->dev.of_node;
381 #endif
382
383 gpiochip_add(&tegra_gpio_chip);
384
385 for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
386 int irq = TEGRA_GPIO_TO_IRQ(gpio);
387 /* No validity check; all Tegra GPIOs are valid IRQs */
388
389 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
390
391 irq_set_lockdep_class(irq, &gpio_lock_class);
392 irq_set_chip_data(irq, bank);
393 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
394 handle_simple_irq);
395 set_irq_flags(irq, IRQF_VALID);
396 }
397
398 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
399 bank = &tegra_gpio_banks[i];
400
401 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
402 irq_set_handler_data(bank->irq, bank);
403
404 for (j = 0; j < 4; j++)
405 spin_lock_init(&bank->lvl_lock[j]);
406 }
407
408 return 0;
409 }
410
411 static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
412 { .compatible = "nvidia,tegra20-gpio", },
413 { },
414 };
415
416 static struct platform_driver tegra_gpio_driver = {
417 .driver = {
418 .name = "tegra-gpio",
419 .owner = THIS_MODULE,
420 .of_match_table = tegra_gpio_of_match,
421 },
422 .probe = tegra_gpio_probe,
423 };
424
425 static int __init tegra_gpio_init(void)
426 {
427 return platform_driver_register(&tegra_gpio_driver);
428 }
429 postcore_initcall(tegra_gpio_init);
430
431 void tegra_gpio_config(struct tegra_gpio_table *table, int num)
432 {
433 int i;
434
435 for (i = 0; i < num; i++) {
436 int gpio = table[i].gpio;
437
438 if (table[i].enable)
439 tegra_gpio_enable(gpio);
440 else
441 tegra_gpio_disable(gpio);
442 }
443 }
444
445 #ifdef CONFIG_DEBUG_FS
446
447 #include <linux/debugfs.h>
448 #include <linux/seq_file.h>
449
450 static int dbg_gpio_show(struct seq_file *s, void *unused)
451 {
452 int i;
453 int j;
454
455 for (i = 0; i < 7; i++) {
456 for (j = 0; j < 4; j++) {
457 int gpio = tegra_gpio_compose(i, j, 0);
458 seq_printf(s,
459 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
460 i, j,
461 tegra_gpio_readl(GPIO_CNF(gpio)),
462 tegra_gpio_readl(GPIO_OE(gpio)),
463 tegra_gpio_readl(GPIO_OUT(gpio)),
464 tegra_gpio_readl(GPIO_IN(gpio)),
465 tegra_gpio_readl(GPIO_INT_STA(gpio)),
466 tegra_gpio_readl(GPIO_INT_ENB(gpio)),
467 tegra_gpio_readl(GPIO_INT_LVL(gpio)));
468 }
469 }
470 return 0;
471 }
472
473 static int dbg_gpio_open(struct inode *inode, struct file *file)
474 {
475 return single_open(file, dbg_gpio_show, &inode->i_private);
476 }
477
478 static const struct file_operations debug_fops = {
479 .open = dbg_gpio_open,
480 .read = seq_read,
481 .llseek = seq_lseek,
482 .release = single_release,
483 };
484
485 static int __init tegra_gpio_debuginit(void)
486 {
487 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
488 NULL, NULL, &debug_fops);
489 return 0;
490 }
491 late_initcall(tegra_gpio_debuginit);
492 #endif
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