drivers/gpio/gpio-xlp.c

   1 /*
   2  * Copyright (C) 2003-2015 Broadcom Corporation
   3  * All Rights Reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/gpio.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/of_device.h>
  18 #include <linux/module.h>
  19 #include <linux/irq.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irqchip/chained_irq.h>
  22
  23 /*
  24  * XLP GPIO has multiple 32 bit registers for each feature where each register
  25  * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
  26  * require 3 32-bit registers for each feature.
  27  * Here we only define offset of the first register for each feature. Offset of
  28  * the registers for pins greater than 32 can be calculated as following(Use
  29  * GPIO_INT_STAT as example):
  30  *
  31  * offset = (gpio / XLP_GPIO_REGSZ) * 4;
  32  * reg_addr = addr + offset;
  33  *
  34  * where addr is base address of the that feature register and gpio is the pin.
  35  */
  36 #define GPIO_OUTPUT_EN          0x00
  37 #define GPIO_PADDRV             0x08
  38 #define GPIO_INT_EN00           0x18
  39 #define GPIO_INT_EN10           0x20
  40 #define GPIO_INT_EN20           0x28
  41 #define GPIO_INT_EN30           0x30
  42 #define GPIO_INT_POL            0x38
  43 #define GPIO_INT_TYPE           0x40
  44 #define GPIO_INT_STAT           0x48
  45
  46 #define GPIO_9XX_BYTESWAP       0X00
  47 #define GPIO_9XX_CTRL           0X04
  48 #define GPIO_9XX_OUTPUT_EN      0x14
  49 #define GPIO_9XX_PADDRV         0x24
  50 /*
  51  * Only for 4 interrupt enable reg are defined for now,
  52  * total reg available are 12.
  53  */
  54 #define GPIO_9XX_INT_EN00       0x44
  55 #define GPIO_9XX_INT_EN10       0x54
  56 #define GPIO_9XX_INT_EN20       0x64
  57 #define GPIO_9XX_INT_EN30       0x74
  58 #define GPIO_9XX_INT_POL        0x104
  59 #define GPIO_9XX_INT_TYPE       0x114
  60 #define GPIO_9XX_INT_STAT       0x124
  61
  62 #define GPIO_3XX_INT_EN00       0x18
  63 #define GPIO_3XX_INT_EN10       0x20
  64 #define GPIO_3XX_INT_EN20       0x28
  65 #define GPIO_3XX_INT_EN30       0x30
  66 #define GPIO_3XX_INT_POL        0x78
  67 #define GPIO_3XX_INT_TYPE       0x80
  68 #define GPIO_3XX_INT_STAT       0x88
  69
  70 /* Interrupt type register mask */
  71 #define XLP_GPIO_IRQ_TYPE_LVL   0x0
  72 #define XLP_GPIO_IRQ_TYPE_EDGE  0x1
  73
  74 /* Interrupt polarity register mask */
  75 #define XLP_GPIO_IRQ_POL_HIGH   0x0
  76 #define XLP_GPIO_IRQ_POL_LOW    0x1
  77
  78 #define XLP_GPIO_REGSZ          32
  79 #define XLP_GPIO_IRQ_BASE       768
  80 #define XLP_MAX_NR_GPIO         96
  81
  82 /* XLP variants supported by this driver */
  83 enum {
  84         XLP_GPIO_VARIANT_XLP832 = 1,
  85         XLP_GPIO_VARIANT_XLP316,
  86         XLP_GPIO_VARIANT_XLP208,
  87         XLP_GPIO_VARIANT_XLP980,
  88         XLP_GPIO_VARIANT_XLP532
  89 };
  90
  91 struct xlp_gpio_priv {
  92         struct gpio_chip chip;
  93         DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
  94         void __iomem *gpio_intr_en;     /* pointer to first intr enable reg */
  95         void __iomem *gpio_intr_stat;   /* pointer to first intr status reg */
  96         void __iomem *gpio_intr_type;   /* pointer to first intr type reg */
  97         void __iomem *gpio_intr_pol;    /* pointer to first intr polarity reg */
  98         void __iomem *gpio_out_en;      /* pointer to first output enable reg */
  99         void __iomem *gpio_paddrv;      /* pointer to first pad drive reg */
 100         spinlock_t lock;
 101 };
 102
 103 static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
 104 {
 105         u32 pos, regset;
 106
 107         pos = gpio % XLP_GPIO_REGSZ;
 108         regset = (gpio / XLP_GPIO_REGSZ) * 4;
 109         return !!(readl(addr + regset) & BIT(pos));
 110 }
 111
 112 static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
 113 {
 114         u32 value, pos, regset;
 115
 116         pos = gpio % XLP_GPIO_REGSZ;
 117         regset = (gpio / XLP_GPIO_REGSZ) * 4;
 118         value = readl(addr + regset);
 119
 120         if (state)
 121                 value |= BIT(pos);
 122         else
 123                 value &= ~BIT(pos);
 124
 125         writel(value, addr + regset);
 126 }
 127
 128 static void xlp_gpio_irq_disable(struct irq_data *d)
 129 {
 130         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 131         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 132         unsigned long flags;
 133
 134         spin_lock_irqsave(&priv->lock, flags);
 135         xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
 136         __clear_bit(d->hwirq, priv->gpio_enabled_mask);
 137         spin_unlock_irqrestore(&priv->lock, flags);
 138 }
 139
 140 static void xlp_gpio_irq_mask_ack(struct irq_data *d)
 141 {
 142         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 143         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 144         unsigned long flags;
 145
 146         spin_lock_irqsave(&priv->lock, flags);
 147         xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
 148         xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
 149         __clear_bit(d->hwirq, priv->gpio_enabled_mask);
 150         spin_unlock_irqrestore(&priv->lock, flags);
 151 }
 152
 153 static void xlp_gpio_irq_unmask(struct irq_data *d)
 154 {
 155         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 156         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 157         unsigned long flags;
 158
 159         spin_lock_irqsave(&priv->lock, flags);
 160         xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
 161         __set_bit(d->hwirq, priv->gpio_enabled_mask);
 162         spin_unlock_irqrestore(&priv->lock, flags);
 163 }
 164
 165 static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 166 {
 167         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 168         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 169         int pol, irq_type;
 170
 171         switch (type) {
 172         case IRQ_TYPE_EDGE_RISING:
 173                 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
 174                 pol = XLP_GPIO_IRQ_POL_HIGH;
 175                 break;
 176         case IRQ_TYPE_EDGE_FALLING:
 177                 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
 178                 pol = XLP_GPIO_IRQ_POL_LOW;
 179                 break;
 180         case IRQ_TYPE_LEVEL_HIGH:
 181                 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
 182                 pol = XLP_GPIO_IRQ_POL_HIGH;
 183                 break;
 184         case IRQ_TYPE_LEVEL_LOW:
 185                 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
 186                 pol = XLP_GPIO_IRQ_POL_LOW;
 187                 break;
 188         default:
 189                 return -EINVAL;
 190         }
 191
 192         xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
 193         xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
 194
 195         return 0;
 196 }
 197
 198 static struct irq_chip xlp_gpio_irq_chip = {
 199         .name           = "XLP-GPIO",
 200         .irq_mask_ack   = xlp_gpio_irq_mask_ack,
 201         .irq_disable    = xlp_gpio_irq_disable,
 202         .irq_set_type   = xlp_gpio_set_irq_type,
 203         .irq_unmask     = xlp_gpio_irq_unmask,
 204         .flags          = IRQCHIP_ONESHOT_SAFE,
 205 };
 206
 207 static void xlp_gpio_generic_handler(struct irq_desc *desc)
 208 {
 209         struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
 210         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 211         int gpio, regoff;
 212         u32 gpio_stat;
 213
 214         regoff = -1;
 215         gpio_stat = 0;
 216
 217         chained_irq_enter(irqchip, desc);
 218         for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
 219                 if (regoff != gpio / XLP_GPIO_REGSZ) {
 220                         regoff = gpio / XLP_GPIO_REGSZ;
 221                         gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
 222                 }
 223
 224                 if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
 225                         generic_handle_irq(irq_find_mapping(
 226                                                 priv->chip.irqdomain, gpio));
 227         }
 228         chained_irq_exit(irqchip, desc);
 229 }
 230
 231 static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
 232 {
 233         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 234
 235         BUG_ON(gpio >= gc->ngpio);
 236         xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
 237
 238         return 0;
 239 }
 240
 241 static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
 242 {
 243         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 244
 245         BUG_ON(gpio >= gc->ngpio);
 246         xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
 247
 248         return 0;
 249 }
 250
 251 static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
 252 {
 253         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 254
 255         BUG_ON(gpio >= gc->ngpio);
 256         return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
 257 }
 258
 259 static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
 260 {
 261         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 262
 263         BUG_ON(gpio >= gc->ngpio);
 264         xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
 265 }
 266
 267 static const struct of_device_id xlp_gpio_of_ids[] = {
 268         {
 269                 .compatible = "netlogic,xlp832-gpio",
 270                 .data       = (void *)XLP_GPIO_VARIANT_XLP832,
 271         },
 272         {
 273                 .compatible = "netlogic,xlp316-gpio",
 274                 .data       = (void *)XLP_GPIO_VARIANT_XLP316,
 275         },
 276         {
 277                 .compatible = "netlogic,xlp208-gpio",
 278                 .data       = (void *)XLP_GPIO_VARIANT_XLP208,
 279         },
 280         {
 281                 .compatible = "netlogic,xlp980-gpio",
 282                 .data       = (void *)XLP_GPIO_VARIANT_XLP980,
 283         },
 284         {
 285                 .compatible = "netlogic,xlp532-gpio",
 286                 .data       = (void *)XLP_GPIO_VARIANT_XLP532,
 287         },
 288         { /* sentinel */ },
 289 };
 290 MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
 291
 292 static int xlp_gpio_probe(struct platform_device *pdev)
 293 {
 294         struct gpio_chip *gc;
 295         struct resource *iores;
 296         struct xlp_gpio_priv *priv;
 297         const struct of_device_id *of_id;
 298         void __iomem *gpio_base;
 299         int irq_base, irq, err;
 300         int ngpio;
 301         u32 soc_type;
 302
 303         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 304         if (!iores)
 305                 return -ENODEV;
 306
 307         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 308         if (!priv)
 309                 return -ENOMEM;
 310
 311         gpio_base = devm_ioremap_resource(&pdev->dev, iores);
 312         if (IS_ERR(gpio_base))
 313                 return PTR_ERR(gpio_base);
 314
 315         irq = platform_get_irq(pdev, 0);
 316         if (irq < 0)
 317                 return irq;
 318
 319         of_id = of_match_device(xlp_gpio_of_ids, &pdev->dev);
 320         if (!of_id) {
 321                 dev_err(&pdev->dev, "Failed to get soc type!\n");
 322                 return -ENODEV;
 323         }
 324
 325         soc_type = (uintptr_t) of_id->data;
 326
 327         switch (soc_type) {
 328         case XLP_GPIO_VARIANT_XLP832:
 329                 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
 330                 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
 331                 priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
 332                 priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
 333                 priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
 334                 priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
 335                 ngpio = 41;
 336                 break;
 337         case XLP_GPIO_VARIANT_XLP208:
 338         case XLP_GPIO_VARIANT_XLP316:
 339                 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
 340                 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
 341                 priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
 342                 priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
 343                 priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
 344                 priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
 345
 346                 ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
 347                 break;
 348         case XLP_GPIO_VARIANT_XLP980:
 349         case XLP_GPIO_VARIANT_XLP532:
 350                 priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
 351                 priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
 352                 priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
 353                 priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
 354                 priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
 355                 priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
 356
 357                 ngpio = (soc_type == XLP_GPIO_VARIANT_XLP980) ? 66 : 67;
 358                 break;
 359         default:
 360                 dev_err(&pdev->dev, "Unknown Processor type!\n");
 361                 return -ENODEV;
 362         }
 363
 364         bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
 365
 366         gc = &priv->chip;
 367
 368         gc->owner = THIS_MODULE;
 369         gc->label = dev_name(&pdev->dev);
 370         gc->base = 0;
 371         gc->parent = &pdev->dev;
 372         gc->ngpio = ngpio;
 373         gc->of_node = pdev->dev.of_node;
 374         gc->direction_output = xlp_gpio_dir_output;
 375         gc->direction_input = xlp_gpio_dir_input;
 376         gc->set = xlp_gpio_set;
 377         gc->get = xlp_gpio_get;
 378
 379         spin_lock_init(&priv->lock);
 380         irq_base = irq_alloc_descs(-1, XLP_GPIO_IRQ_BASE, gc->ngpio, 0);
 381         if (irq_base < 0) {
 382                 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
 383                 return -ENODEV;
 384         }
 385
 386         err = gpiochip_add_data(gc, priv);
 387         if (err < 0)
 388                 goto out_free_desc;
 389
 390         err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base,
 391                                 handle_level_irq, IRQ_TYPE_NONE);
 392         if (err) {
 393                 dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n");
 394                 goto out_gpio_remove;
 395         }
 396
 397         gpiochip_set_chained_irqchip(gc, &xlp_gpio_irq_chip, irq,
 398                         xlp_gpio_generic_handler);
 399
 400         dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
 401
 402         return 0;
 403
 404 out_gpio_remove:
 405         gpiochip_remove(gc);
 406 out_free_desc:
 407         irq_free_descs(irq_base, gc->ngpio);
 408         return err;
 409 }
 410
 411 static struct platform_driver xlp_gpio_driver = {
 412         .driver         = {
 413                 .name   = "xlp-gpio",
 414                 .of_match_table = xlp_gpio_of_ids,
 415         },
 416         .probe          = xlp_gpio_probe,
 417 };
 418 module_platform_driver(xlp_gpio_driver);
 419
 420 MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
 421 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
 422 MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
 423 MODULE_LICENSE("GPL v2");