2 * Xilinx Zynq GPIO device driver
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
22 #define DRIVER_NAME "zynq-gpio"
25 #define ZYNQ_GPIO_MAX_BANK 4
27 #define ZYNQ_GPIO_BANK0_NGPIO 32
28 #define ZYNQ_GPIO_BANK1_NGPIO 22
29 #define ZYNQ_GPIO_BANK2_NGPIO 32
30 #define ZYNQ_GPIO_BANK3_NGPIO 32
32 #define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
33 ZYNQ_GPIO_BANK1_NGPIO + \
34 ZYNQ_GPIO_BANK2_NGPIO + \
35 ZYNQ_GPIO_BANK3_NGPIO)
37 #define ZYNQ_GPIO_BANK0_PIN_MIN 0
38 #define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
39 ZYNQ_GPIO_BANK0_NGPIO - 1)
40 #define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
41 #define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
42 ZYNQ_GPIO_BANK1_NGPIO - 1)
43 #define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
44 #define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
45 ZYNQ_GPIO_BANK2_NGPIO - 1)
46 #define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
47 #define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
48 ZYNQ_GPIO_BANK3_NGPIO - 1)
51 /* Register offsets for the GPIO device */
52 /* LSW Mask & Data -WO */
53 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
54 /* MSW Mask & Data -WO */
55 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
56 /* Data Register-RW */
57 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
58 /* Direction mode reg-RW */
59 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
60 /* Output enable reg-RW */
61 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
62 /* Interrupt mask reg-RO */
63 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
64 /* Interrupt enable reg-WO */
65 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
66 /* Interrupt disable reg-WO */
67 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
68 /* Interrupt status reg-RO */
69 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
70 /* Interrupt type reg-RW */
71 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
72 /* Interrupt polarity reg-RW */
73 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
74 /* Interrupt on any, reg-RW */
75 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
77 /* Disable all interrupts mask */
78 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
80 /* Mid pin number of a bank */
81 #define ZYNQ_GPIO_MID_PIN_NUM 16
83 /* GPIO upper 16 bit mask */
84 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
87 * struct zynq_gpio - gpio device private data structure
88 * @chip: instance of the gpio_chip
89 * @base_addr: base address of the GPIO device
90 * @clk: clock resource for this controller
93 struct gpio_chip chip
;
94 void __iomem
*base_addr
;
99 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
100 * for a given pin in the GPIO device
101 * @pin_num: gpio pin number within the device
102 * @bank_num: an output parameter used to return the bank number of the gpio
104 * @bank_pin_num: an output parameter used to return pin number within a bank
105 * for the given gpio pin
107 * Returns the bank number and pin offset within the bank.
109 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num
,
110 unsigned int *bank_num
,
111 unsigned int *bank_pin_num
)
114 case ZYNQ_GPIO_BANK0_PIN_MIN
... ZYNQ_GPIO_BANK0_PIN_MAX
:
116 *bank_pin_num
= pin_num
;
118 case ZYNQ_GPIO_BANK1_PIN_MIN
... ZYNQ_GPIO_BANK1_PIN_MAX
:
120 *bank_pin_num
= pin_num
- ZYNQ_GPIO_BANK1_PIN_MIN
;
122 case ZYNQ_GPIO_BANK2_PIN_MIN
... ZYNQ_GPIO_BANK2_PIN_MAX
:
124 *bank_pin_num
= pin_num
- ZYNQ_GPIO_BANK2_PIN_MIN
;
126 case ZYNQ_GPIO_BANK3_PIN_MIN
... ZYNQ_GPIO_BANK3_PIN_MAX
:
128 *bank_pin_num
= pin_num
- ZYNQ_GPIO_BANK3_PIN_MIN
;
131 WARN(true, "invalid GPIO pin number: %u", pin_num
);
139 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
140 * @chip: gpio_chip instance to be worked on
141 * @pin: gpio pin number within the device
143 * This function reads the state of the specified pin of the GPIO device.
145 * Return: 0 if the pin is low, 1 if pin is high.
147 static int zynq_gpio_get_value(struct gpio_chip
*chip
, unsigned int pin
)
150 unsigned int bank_num
, bank_pin_num
;
151 struct zynq_gpio
*gpio
= container_of(chip
, struct zynq_gpio
, chip
);
153 zynq_gpio_get_bank_pin(pin
, &bank_num
, &bank_pin_num
);
155 data
= readl_relaxed(gpio
->base_addr
+
156 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num
));
158 return (data
>> bank_pin_num
) & 1;
162 * zynq_gpio_set_value - Modify the state of the pin with specified value
163 * @chip: gpio_chip instance to be worked on
164 * @pin: gpio pin number within the device
165 * @state: value used to modify the state of the specified pin
167 * This function calculates the register offset (i.e to lower 16 bits or
168 * upper 16 bits) based on the given pin number and sets the state of a
169 * gpio pin to the specified value. The state is either 0 or non-zero.
171 static void zynq_gpio_set_value(struct gpio_chip
*chip
, unsigned int pin
,
174 unsigned int reg_offset
, bank_num
, bank_pin_num
;
175 struct zynq_gpio
*gpio
= container_of(chip
, struct zynq_gpio
, chip
);
177 zynq_gpio_get_bank_pin(pin
, &bank_num
, &bank_pin_num
);
179 if (bank_pin_num
>= ZYNQ_GPIO_MID_PIN_NUM
) {
180 /* only 16 data bits in bit maskable reg */
181 bank_pin_num
-= ZYNQ_GPIO_MID_PIN_NUM
;
182 reg_offset
= ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num
);
184 reg_offset
= ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num
);
188 * get the 32 bit value to be written to the mask/data register where
189 * the upper 16 bits is the mask and lower 16 bits is the data
192 state
= ~(1 << (bank_pin_num
+ ZYNQ_GPIO_MID_PIN_NUM
)) &
193 ((state
<< bank_pin_num
) | ZYNQ_GPIO_UPPER_MASK
);
195 writel_relaxed(state
, gpio
->base_addr
+ reg_offset
);
199 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
200 * @chip: gpio_chip instance to be worked on
201 * @pin: gpio pin number within the device
203 * This function uses the read-modify-write sequence to set the direction of
204 * the gpio pin as input.
208 static int zynq_gpio_dir_in(struct gpio_chip
*chip
, unsigned int pin
)
211 unsigned int bank_num
, bank_pin_num
;
212 struct zynq_gpio
*gpio
= container_of(chip
, struct zynq_gpio
, chip
);
214 zynq_gpio_get_bank_pin(pin
, &bank_num
, &bank_pin_num
);
216 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
217 if (bank_num
== 0 && (bank_pin_num
== 7 || bank_pin_num
== 8))
220 /* clear the bit in direction mode reg to set the pin as input */
221 reg
= readl_relaxed(gpio
->base_addr
+ ZYNQ_GPIO_DIRM_OFFSET(bank_num
));
222 reg
&= ~BIT(bank_pin_num
);
223 writel_relaxed(reg
, gpio
->base_addr
+ ZYNQ_GPIO_DIRM_OFFSET(bank_num
));
229 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
230 * @chip: gpio_chip instance to be worked on
231 * @pin: gpio pin number within the device
232 * @state: value to be written to specified pin
234 * This function sets the direction of specified GPIO pin as output, configures
235 * the Output Enable register for the pin and uses zynq_gpio_set to set
236 * the state of the pin to the value specified.
240 static int zynq_gpio_dir_out(struct gpio_chip
*chip
, unsigned int pin
,
244 unsigned int bank_num
, bank_pin_num
;
245 struct zynq_gpio
*gpio
= container_of(chip
, struct zynq_gpio
, chip
);
247 zynq_gpio_get_bank_pin(pin
, &bank_num
, &bank_pin_num
);
249 /* set the GPIO pin as output */
250 reg
= readl_relaxed(gpio
->base_addr
+ ZYNQ_GPIO_DIRM_OFFSET(bank_num
));
251 reg
|= BIT(bank_pin_num
);
252 writel_relaxed(reg
, gpio
->base_addr
+ ZYNQ_GPIO_DIRM_OFFSET(bank_num
));
254 /* configure the output enable reg for the pin */
255 reg
= readl_relaxed(gpio
->base_addr
+ ZYNQ_GPIO_OUTEN_OFFSET(bank_num
));
256 reg
|= BIT(bank_pin_num
);
257 writel_relaxed(reg
, gpio
->base_addr
+ ZYNQ_GPIO_OUTEN_OFFSET(bank_num
));
259 /* set the state of the pin */
260 zynq_gpio_set_value(chip
, pin
, state
);
265 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
266 * @irq_data: per irq and chip data passed down to chip functions
268 * This function calculates gpio pin number from irq number and sets the
269 * bit in the Interrupt Disable register of the corresponding bank to disable
270 * interrupts for that pin.
272 static void zynq_gpio_irq_mask(struct irq_data
*irq_data
)
274 unsigned int device_pin_num
, bank_num
, bank_pin_num
;
275 struct zynq_gpio
*gpio
= irq_data_get_irq_chip_data(irq_data
);
277 device_pin_num
= irq_data
->hwirq
;
278 zynq_gpio_get_bank_pin(device_pin_num
, &bank_num
, &bank_pin_num
);
279 writel_relaxed(BIT(bank_pin_num
),
280 gpio
->base_addr
+ ZYNQ_GPIO_INTDIS_OFFSET(bank_num
));
284 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
285 * @irq_data: irq data containing irq number of gpio pin for the interrupt
288 * This function calculates the gpio pin number from irq number and sets the
289 * bit in the Interrupt Enable register of the corresponding bank to enable
290 * interrupts for that pin.
292 static void zynq_gpio_irq_unmask(struct irq_data
*irq_data
)
294 unsigned int device_pin_num
, bank_num
, bank_pin_num
;
295 struct zynq_gpio
*gpio
= irq_data_get_irq_chip_data(irq_data
);
297 device_pin_num
= irq_data
->hwirq
;
298 zynq_gpio_get_bank_pin(device_pin_num
, &bank_num
, &bank_pin_num
);
299 writel_relaxed(BIT(bank_pin_num
),
300 gpio
->base_addr
+ ZYNQ_GPIO_INTEN_OFFSET(bank_num
));
304 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
305 * @irq_data: irq data containing irq number of gpio pin for the interrupt
308 * This function calculates gpio pin number from irq number and sets the bit
309 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
311 static void zynq_gpio_irq_ack(struct irq_data
*irq_data
)
313 unsigned int device_pin_num
, bank_num
, bank_pin_num
;
314 struct zynq_gpio
*gpio
= irq_data_get_irq_chip_data(irq_data
);
316 device_pin_num
= irq_data
->hwirq
;
317 zynq_gpio_get_bank_pin(device_pin_num
, &bank_num
, &bank_pin_num
);
318 writel_relaxed(BIT(bank_pin_num
),
319 gpio
->base_addr
+ ZYNQ_GPIO_INTSTS_OFFSET(bank_num
));
323 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
324 * @irq_data: irq data containing irq number of gpio pin for the interrupt
327 * Clears the INTSTS bit and unmasks the given interrrupt.
329 static void zynq_gpio_irq_enable(struct irq_data
*irq_data
)
332 * The Zynq GPIO controller does not disable interrupt detection when
333 * the interrupt is masked and only disables the propagation of the
334 * interrupt. This means when the controller detects an interrupt
335 * condition while the interrupt is logically disabled it will propagate
336 * that interrupt event once the interrupt is enabled. This will cause
337 * the interrupt consumer to see spurious interrupts to prevent this
338 * first make sure that the interrupt is not asserted and then enable
341 zynq_gpio_irq_ack(irq_data
);
342 zynq_gpio_irq_unmask(irq_data
);
346 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
347 * @irq_data: irq data containing irq number of gpio pin
348 * @type: interrupt type that is to be set for the gpio pin
350 * This function gets the gpio pin number and its bank from the gpio pin number
351 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
353 * Return: 0, negative error otherwise.
354 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
355 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
356 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
357 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
358 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
360 static int zynq_gpio_set_irq_type(struct irq_data
*irq_data
, unsigned int type
)
362 u32 int_type
, int_pol
, int_any
;
363 unsigned int device_pin_num
, bank_num
, bank_pin_num
;
364 struct zynq_gpio
*gpio
= irq_data_get_irq_chip_data(irq_data
);
366 device_pin_num
= irq_data
->hwirq
;
367 zynq_gpio_get_bank_pin(device_pin_num
, &bank_num
, &bank_pin_num
);
369 int_type
= readl_relaxed(gpio
->base_addr
+
370 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num
));
371 int_pol
= readl_relaxed(gpio
->base_addr
+
372 ZYNQ_GPIO_INTPOL_OFFSET(bank_num
));
373 int_any
= readl_relaxed(gpio
->base_addr
+
374 ZYNQ_GPIO_INTANY_OFFSET(bank_num
));
377 * based on the type requested, configure the INT_TYPE, INT_POLARITY
378 * and INT_ANY registers
381 case IRQ_TYPE_EDGE_RISING
:
382 int_type
|= BIT(bank_pin_num
);
383 int_pol
|= BIT(bank_pin_num
);
384 int_any
&= ~BIT(bank_pin_num
);
386 case IRQ_TYPE_EDGE_FALLING
:
387 int_type
|= BIT(bank_pin_num
);
388 int_pol
&= ~BIT(bank_pin_num
);
389 int_any
&= ~BIT(bank_pin_num
);
391 case IRQ_TYPE_EDGE_BOTH
:
392 int_type
|= BIT(bank_pin_num
);
393 int_any
|= BIT(bank_pin_num
);
395 case IRQ_TYPE_LEVEL_HIGH
:
396 int_type
&= ~BIT(bank_pin_num
);
397 int_pol
|= BIT(bank_pin_num
);
399 case IRQ_TYPE_LEVEL_LOW
:
400 int_type
&= ~BIT(bank_pin_num
);
401 int_pol
&= ~BIT(bank_pin_num
);
407 writel_relaxed(int_type
,
408 gpio
->base_addr
+ ZYNQ_GPIO_INTTYPE_OFFSET(bank_num
));
409 writel_relaxed(int_pol
,
410 gpio
->base_addr
+ ZYNQ_GPIO_INTPOL_OFFSET(bank_num
));
411 writel_relaxed(int_any
,
412 gpio
->base_addr
+ ZYNQ_GPIO_INTANY_OFFSET(bank_num
));
416 static int zynq_gpio_set_wake(struct irq_data
*data
, unsigned int on
)
419 zynq_gpio_irq_unmask(data
);
421 zynq_gpio_irq_mask(data
);
426 /* irq chip descriptor */
427 static struct irq_chip zynq_gpio_irqchip
= {
429 .irq_enable
= zynq_gpio_irq_enable
,
430 .irq_mask
= zynq_gpio_irq_mask
,
431 .irq_unmask
= zynq_gpio_irq_unmask
,
432 .irq_set_type
= zynq_gpio_set_irq_type
,
433 .irq_set_wake
= zynq_gpio_set_wake
,
437 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
438 * @irq: irq number of the gpio bank where interrupt has occurred
439 * @desc: irq descriptor instance of the 'irq'
441 * This function reads the Interrupt Status Register of each bank to get the
442 * gpio pin number which has triggered an interrupt. It then acks the triggered
443 * interrupt and calls the pin specific handler set by the higher layer
444 * application for that pin.
445 * Note: A bug is reported if no handler is set for the gpio pin.
447 static void zynq_gpio_irqhandler(unsigned int irq
, struct irq_desc
*desc
)
449 u32 int_sts
, int_enb
;
450 unsigned int bank_num
;
451 struct zynq_gpio
*gpio
= irq_get_handler_data(irq
);
452 struct irq_chip
*irqchip
= irq_desc_get_chip(desc
);
454 chained_irq_enter(irqchip
, desc
);
456 for (bank_num
= 0; bank_num
< ZYNQ_GPIO_MAX_BANK
; bank_num
++) {
457 int_sts
= readl_relaxed(gpio
->base_addr
+
458 ZYNQ_GPIO_INTSTS_OFFSET(bank_num
));
459 int_enb
= readl_relaxed(gpio
->base_addr
+
460 ZYNQ_GPIO_INTMASK_OFFSET(bank_num
));
464 unsigned long pending
= int_sts
;
466 for_each_set_bit(offset
, &pending
, 32) {
467 unsigned int gpio_irq
=
468 irq_find_mapping(gpio
->chip
.irqdomain
,
470 generic_handle_irq(gpio_irq
);
473 /* clear IRQ in HW */
474 writel_relaxed(int_sts
, gpio
->base_addr
+
475 ZYNQ_GPIO_INTSTS_OFFSET(bank_num
));
479 chained_irq_exit(irqchip
, desc
);
482 static int __maybe_unused
zynq_gpio_suspend(struct device
*dev
)
484 if (!device_may_wakeup(dev
))
485 return pm_runtime_force_suspend(dev
);
490 static int __maybe_unused
zynq_gpio_resume(struct device
*dev
)
492 if (!device_may_wakeup(dev
))
493 return pm_runtime_force_resume(dev
);
498 static int __maybe_unused
zynq_gpio_runtime_suspend(struct device
*dev
)
500 struct platform_device
*pdev
= to_platform_device(dev
);
501 struct zynq_gpio
*gpio
= platform_get_drvdata(pdev
);
503 clk_disable_unprepare(gpio
->clk
);
508 static int __maybe_unused
zynq_gpio_runtime_resume(struct device
*dev
)
510 struct platform_device
*pdev
= to_platform_device(dev
);
511 struct zynq_gpio
*gpio
= platform_get_drvdata(pdev
);
513 return clk_prepare_enable(gpio
->clk
);
516 static int zynq_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
520 ret
= pm_runtime_get_sync(chip
->dev
);
523 * If the device is already active pm_runtime_get() will return 1 on
524 * success, but gpio_request still needs to return 0.
526 return ret
< 0 ? ret
: 0;
529 static void zynq_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
531 pm_runtime_put(chip
->dev
);
534 static const struct dev_pm_ops zynq_gpio_dev_pm_ops
= {
535 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend
, zynq_gpio_resume
)
536 SET_PM_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend
,
537 zynq_gpio_runtime_resume
, NULL
)
541 * zynq_gpio_probe - Initialization method for a zynq_gpio device
542 * @pdev: platform device instance
544 * This function allocates memory resources for the gpio device and registers
545 * all the banks of the device. It will also set up interrupts for the gpio
547 * Note: Interrupts are disabled for all the banks during initialization.
549 * Return: 0 on success, negative error otherwise.
551 static int zynq_gpio_probe(struct platform_device
*pdev
)
553 int ret
, bank_num
, irq
;
554 struct zynq_gpio
*gpio
;
555 struct gpio_chip
*chip
;
556 struct resource
*res
;
558 gpio
= devm_kzalloc(&pdev
->dev
, sizeof(*gpio
), GFP_KERNEL
);
562 platform_set_drvdata(pdev
, gpio
);
564 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
565 gpio
->base_addr
= devm_ioremap_resource(&pdev
->dev
, res
);
566 if (IS_ERR(gpio
->base_addr
))
567 return PTR_ERR(gpio
->base_addr
);
569 irq
= platform_get_irq(pdev
, 0);
571 dev_err(&pdev
->dev
, "invalid IRQ\n");
575 /* configure the gpio chip */
577 chip
->label
= "zynq_gpio";
578 chip
->owner
= THIS_MODULE
;
579 chip
->dev
= &pdev
->dev
;
580 chip
->get
= zynq_gpio_get_value
;
581 chip
->set
= zynq_gpio_set_value
;
582 chip
->request
= zynq_gpio_request
;
583 chip
->free
= zynq_gpio_free
;
584 chip
->direction_input
= zynq_gpio_dir_in
;
585 chip
->direction_output
= zynq_gpio_dir_out
;
587 chip
->ngpio
= ZYNQ_GPIO_NR_GPIOS
;
589 /* Enable GPIO clock */
590 gpio
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
591 if (IS_ERR(gpio
->clk
)) {
592 dev_err(&pdev
->dev
, "input clock not found.\n");
593 return PTR_ERR(gpio
->clk
);
595 ret
= clk_prepare_enable(gpio
->clk
);
597 dev_err(&pdev
->dev
, "Unable to enable clock.\n");
601 /* report a bug if gpio chip registration fails */
602 ret
= gpiochip_add(chip
);
604 dev_err(&pdev
->dev
, "Failed to add gpio chip\n");
605 goto err_disable_clk
;
608 /* disable interrupts for all banks */
609 for (bank_num
= 0; bank_num
< ZYNQ_GPIO_MAX_BANK
; bank_num
++)
610 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL
, gpio
->base_addr
+
611 ZYNQ_GPIO_INTDIS_OFFSET(bank_num
));
613 ret
= gpiochip_irqchip_add(chip
, &zynq_gpio_irqchip
, 0,
614 handle_simple_irq
, IRQ_TYPE_NONE
);
616 dev_err(&pdev
->dev
, "Failed to add irq chip\n");
617 goto err_rm_gpiochip
;
620 gpiochip_set_chained_irqchip(chip
, &zynq_gpio_irqchip
, irq
,
621 zynq_gpio_irqhandler
);
623 pm_runtime_set_active(&pdev
->dev
);
624 pm_runtime_enable(&pdev
->dev
);
626 device_set_wakeup_capable(&pdev
->dev
, 1);
631 if (gpiochip_remove(chip
))
632 dev_err(&pdev
->dev
, "Failed to remove gpio chip\n");
634 clk_disable_unprepare(gpio
->clk
);
640 * zynq_gpio_remove - Driver removal function
641 * @pdev: platform device instance
645 static int zynq_gpio_remove(struct platform_device
*pdev
)
648 struct zynq_gpio
*gpio
= platform_get_drvdata(pdev
);
650 pm_runtime_get_sync(&pdev
->dev
);
652 ret
= gpiochip_remove(&gpio
->chip
);
654 dev_err(&pdev
->dev
, "Failed to remove gpio chip\n");
657 clk_disable_unprepare(gpio
->clk
);
658 device_set_wakeup_capable(&pdev
->dev
, 0);
662 static struct of_device_id zynq_gpio_of_match
[] = {
663 { .compatible
= "xlnx,zynq-gpio-1.0", },
664 { /* end of table */ }
666 MODULE_DEVICE_TABLE(of
, zynq_gpio_of_match
);
668 static struct platform_driver zynq_gpio_driver
= {
671 .owner
= THIS_MODULE
,
672 .pm
= &zynq_gpio_dev_pm_ops
,
673 .of_match_table
= zynq_gpio_of_match
,
675 .probe
= zynq_gpio_probe
,
676 .remove
= zynq_gpio_remove
,
680 * zynq_gpio_init - Initial driver registration call
682 * Return: value from platform_driver_register
684 static int __init
zynq_gpio_init(void)
686 return platform_driver_register(&zynq_gpio_driver
);
688 postcore_initcall(zynq_gpio_init
);
690 MODULE_AUTHOR("Xilinx Inc.");
691 MODULE_DESCRIPTION("Zynq GPIO driver");
692 MODULE_LICENSE("GPL");