2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
45 #include <drm/drm_gem.h>
47 #include "amdgpu_family.h"
48 #include "amdgpu_mode.h"
49 #include "amdgpu_ih.h"
50 #include "amdgpu_irq.h"
51 #include "amdgpu_ucode.h"
52 #include "amdgpu_gds.h"
57 extern int amdgpu_modeset
;
58 extern int amdgpu_vram_limit
;
59 extern int amdgpu_gart_size
;
60 extern int amdgpu_benchmarking
;
61 extern int amdgpu_testing
;
62 extern int amdgpu_audio
;
63 extern int amdgpu_disp_priority
;
64 extern int amdgpu_hw_i2c
;
65 extern int amdgpu_pcie_gen2
;
66 extern int amdgpu_msi
;
67 extern int amdgpu_lockup_timeout
;
68 extern int amdgpu_dpm
;
69 extern int amdgpu_smc_load_fw
;
70 extern int amdgpu_aspm
;
71 extern int amdgpu_runtime_pm
;
72 extern int amdgpu_hard_reset
;
73 extern unsigned amdgpu_ip_block_mask
;
74 extern int amdgpu_bapm
;
75 extern int amdgpu_deep_color
;
76 extern int amdgpu_vm_size
;
77 extern int amdgpu_vm_block_size
;
79 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
80 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
81 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
82 #define AMDGPU_IB_POOL_SIZE 16
83 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
84 #define AMDGPUFB_CONN_LIMIT 4
85 #define AMDGPU_BIOS_NUM_SCRATCH 8
87 /* fence seq are set to this number when signaled */
88 #define AMDGPU_FENCE_SIGNALED_SEQ 0LL
90 /* max number of rings */
91 #define AMDGPU_MAX_RINGS 16
92 #define AMDGPU_MAX_GFX_RINGS 1
93 #define AMDGPU_MAX_COMPUTE_RINGS 8
94 #define AMDGPU_MAX_VCE_RINGS 2
96 /* number of hw syncs before falling back on blocking */
97 #define AMDGPU_NUM_SYNCS 4
99 /* hardcode that limit for now */
100 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
102 /* hard reset data */
103 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
106 #define AMDGPU_RESET_GFX (1 << 0)
107 #define AMDGPU_RESET_COMPUTE (1 << 1)
108 #define AMDGPU_RESET_DMA (1 << 2)
109 #define AMDGPU_RESET_CP (1 << 3)
110 #define AMDGPU_RESET_GRBM (1 << 4)
111 #define AMDGPU_RESET_DMA1 (1 << 5)
112 #define AMDGPU_RESET_RLC (1 << 6)
113 #define AMDGPU_RESET_SEM (1 << 7)
114 #define AMDGPU_RESET_IH (1 << 8)
115 #define AMDGPU_RESET_VMC (1 << 9)
116 #define AMDGPU_RESET_MC (1 << 10)
117 #define AMDGPU_RESET_DISPLAY (1 << 11)
118 #define AMDGPU_RESET_UVD (1 << 12)
119 #define AMDGPU_RESET_VCE (1 << 13)
120 #define AMDGPU_RESET_VCE1 (1 << 14)
123 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
124 #define AMDGPU_CG_BLOCK_MC (1 << 1)
125 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
126 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
127 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
128 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
129 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
132 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
133 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
134 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
135 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
136 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
137 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
138 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
139 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
140 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
141 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
142 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
143 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
144 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
145 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
146 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
147 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
148 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
151 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
152 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
153 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
154 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
155 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
156 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
157 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
158 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
159 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
160 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
161 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
163 /* GFX current status */
164 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
165 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
166 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
167 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
168 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
170 /* max cursor sizes (in pixels) */
171 #define CIK_CURSOR_WIDTH 128
172 #define CIK_CURSOR_HEIGHT 128
174 struct amdgpu_device
;
179 struct amdgpu_semaphore
;
180 struct amdgpu_cs_parser
;
181 struct amdgpu_irq_src
;
184 AMDGPU_CP_IRQ_GFX_EOP
= 0,
185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
,
188 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
,
189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
,
192 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
,
197 enum amdgpu_sdma_irq
{
198 AMDGPU_SDMA_IRQ_TRAP0
= 0,
199 AMDGPU_SDMA_IRQ_TRAP1
,
204 enum amdgpu_thermal_irq
{
205 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
= 0,
206 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
,
208 AMDGPU_THERMAL_IRQ_LAST
214 enum amdgpu_ip_block_type
{
215 AMDGPU_IP_BLOCK_TYPE_COMMON
,
216 AMDGPU_IP_BLOCK_TYPE_GMC
,
217 AMDGPU_IP_BLOCK_TYPE_IH
,
218 AMDGPU_IP_BLOCK_TYPE_SMC
,
219 AMDGPU_IP_BLOCK_TYPE_DCE
,
220 AMDGPU_IP_BLOCK_TYPE_GFX
,
221 AMDGPU_IP_BLOCK_TYPE_SDMA
,
222 AMDGPU_IP_BLOCK_TYPE_UVD
,
223 AMDGPU_IP_BLOCK_TYPE_VCE
,
226 enum amdgpu_clockgating_state
{
227 AMDGPU_CG_STATE_GATE
= 0,
228 AMDGPU_CG_STATE_UNGATE
,
231 enum amdgpu_powergating_state
{
232 AMDGPU_PG_STATE_GATE
= 0,
233 AMDGPU_PG_STATE_UNGATE
,
236 struct amdgpu_ip_funcs
{
237 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
238 int (*early_init
)(struct amdgpu_device
*adev
);
239 /* sets up late driver/hw state (post hw_init) - Optional */
240 int (*late_init
)(struct amdgpu_device
*adev
);
241 /* sets up driver state, does not configure hw */
242 int (*sw_init
)(struct amdgpu_device
*adev
);
243 /* tears down driver state, does not configure hw */
244 int (*sw_fini
)(struct amdgpu_device
*adev
);
245 /* sets up the hw state */
246 int (*hw_init
)(struct amdgpu_device
*adev
);
247 /* tears down the hw state */
248 int (*hw_fini
)(struct amdgpu_device
*adev
);
249 /* handles IP specific hw/sw changes for suspend */
250 int (*suspend
)(struct amdgpu_device
*adev
);
251 /* handles IP specific hw/sw changes for resume */
252 int (*resume
)(struct amdgpu_device
*adev
);
253 /* returns current IP block idle status */
254 bool (*is_idle
)(struct amdgpu_device
*adev
);
256 int (*wait_for_idle
)(struct amdgpu_device
*adev
);
257 /* soft reset the IP block */
258 int (*soft_reset
)(struct amdgpu_device
*adev
);
259 /* dump the IP block status registers */
260 void (*print_status
)(struct amdgpu_device
*adev
);
261 /* enable/disable cg for the IP block */
262 int (*set_clockgating_state
)(struct amdgpu_device
*adev
,
263 enum amdgpu_clockgating_state state
);
264 /* enable/disable pg for the IP block */
265 int (*set_powergating_state
)(struct amdgpu_device
*adev
,
266 enum amdgpu_powergating_state state
);
269 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
270 enum amdgpu_ip_block_type block_type
,
271 enum amdgpu_clockgating_state state
);
272 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
273 enum amdgpu_ip_block_type block_type
,
274 enum amdgpu_powergating_state state
);
276 struct amdgpu_ip_block_version
{
277 enum amdgpu_ip_block_type type
;
281 const struct amdgpu_ip_funcs
*funcs
;
284 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
285 enum amdgpu_ip_block_type type
,
286 u32 major
, u32 minor
);
288 const struct amdgpu_ip_block_version
* amdgpu_get_ip_block(
289 struct amdgpu_device
*adev
,
290 enum amdgpu_ip_block_type type
);
292 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
293 struct amdgpu_buffer_funcs
{
294 /* maximum bytes in a single operation */
295 uint32_t copy_max_bytes
;
297 /* number of dw to reserve per operation */
298 unsigned copy_num_dw
;
300 /* used for buffer migration */
301 void (*emit_copy_buffer
)(struct amdgpu_ring
*ring
,
302 /* src addr in bytes */
304 /* dst addr in bytes */
306 /* number of byte to transfer */
307 uint32_t byte_count
);
309 /* maximum bytes in a single operation */
310 uint32_t fill_max_bytes
;
312 /* number of dw to reserve per operation */
313 unsigned fill_num_dw
;
315 /* used for buffer clearing */
316 void (*emit_fill_buffer
)(struct amdgpu_ring
*ring
,
317 /* value to write to memory */
319 /* dst addr in bytes */
321 /* number of byte to fill */
322 uint32_t byte_count
);
325 /* provided by hw blocks that can write ptes, e.g., sdma */
326 struct amdgpu_vm_pte_funcs
{
327 /* copy pte entries from GART */
328 void (*copy_pte
)(struct amdgpu_ib
*ib
,
329 uint64_t pe
, uint64_t src
,
331 /* write pte one entry at a time with addr mapping */
332 void (*write_pte
)(struct amdgpu_ib
*ib
,
334 uint64_t addr
, unsigned count
,
335 uint32_t incr
, uint32_t flags
);
336 /* for linear pte/pde updates without addr mapping */
337 void (*set_pte_pde
)(struct amdgpu_ib
*ib
,
339 uint64_t addr
, unsigned count
,
340 uint32_t incr
, uint32_t flags
);
341 /* pad the indirect buffer to the necessary number of dw */
342 void (*pad_ib
)(struct amdgpu_ib
*ib
);
345 /* provided by the gmc block */
346 struct amdgpu_gart_funcs
{
347 /* flush the vm tlb via mmio */
348 void (*flush_gpu_tlb
)(struct amdgpu_device
*adev
,
350 /* write pte/pde updates using the cpu */
351 int (*set_pte_pde
)(struct amdgpu_device
*adev
,
352 void *cpu_pt_addr
, /* cpu addr of page table */
353 uint32_t gpu_page_idx
, /* pte/pde to update */
354 uint64_t addr
, /* addr to write into pte/pde */
355 uint32_t flags
); /* access flags */
358 /* provided by the ih block */
359 struct amdgpu_ih_funcs
{
360 /* ring read/write ptr handling, called from interrupt context */
361 u32 (*get_wptr
)(struct amdgpu_device
*adev
);
362 void (*decode_iv
)(struct amdgpu_device
*adev
,
363 struct amdgpu_iv_entry
*entry
);
364 void (*set_rptr
)(struct amdgpu_device
*adev
);
367 /* provided by hw blocks that expose a ring buffer for commands */
368 struct amdgpu_ring_funcs
{
369 /* ring read/write ptr handling */
370 u32 (*get_rptr
)(struct amdgpu_ring
*ring
);
371 u32 (*get_wptr
)(struct amdgpu_ring
*ring
);
372 void (*set_wptr
)(struct amdgpu_ring
*ring
);
373 /* validating and patching of IBs */
374 int (*parse_cs
)(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
);
375 /* command emit functions */
376 void (*emit_ib
)(struct amdgpu_ring
*ring
,
377 struct amdgpu_ib
*ib
);
378 void (*emit_fence
)(struct amdgpu_ring
*ring
, uint64_t addr
,
379 uint64_t seq
, bool write64bit
);
380 bool (*emit_semaphore
)(struct amdgpu_ring
*ring
,
381 struct amdgpu_semaphore
*semaphore
,
383 void (*emit_vm_flush
)(struct amdgpu_ring
*ring
, unsigned vm_id
,
385 void (*emit_hdp_flush
)(struct amdgpu_ring
*ring
);
386 void (*emit_gds_switch
)(struct amdgpu_ring
*ring
, uint32_t vmid
,
387 uint32_t gds_base
, uint32_t gds_size
,
388 uint32_t gws_base
, uint32_t gws_size
,
389 uint32_t oa_base
, uint32_t oa_size
);
390 /* testing functions */
391 int (*test_ring
)(struct amdgpu_ring
*ring
);
392 int (*test_ib
)(struct amdgpu_ring
*ring
);
393 bool (*is_lockup
)(struct amdgpu_ring
*ring
);
399 bool amdgpu_get_bios(struct amdgpu_device
*adev
);
400 bool amdgpu_read_bios(struct amdgpu_device
*adev
);
405 struct amdgpu_dummy_page
{
409 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
);
410 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
);
417 #define AMDGPU_MAX_PPLL 3
419 struct amdgpu_clock
{
420 struct amdgpu_pll ppll
[AMDGPU_MAX_PPLL
];
421 struct amdgpu_pll spll
;
422 struct amdgpu_pll mpll
;
424 uint32_t default_mclk
;
425 uint32_t default_sclk
;
426 uint32_t default_dispclk
;
427 uint32_t current_dispclk
;
429 uint32_t max_pixel_clock
;
435 struct amdgpu_fence_driver
{
436 struct amdgpu_ring
*ring
;
438 volatile uint32_t *cpu_addr
;
439 /* sync_seq is protected by ring emission lock */
440 uint64_t sync_seq
[AMDGPU_MAX_RINGS
];
444 struct amdgpu_irq_src
*irq_src
;
446 struct delayed_work lockup_work
;
449 /* some special values for the owner field */
450 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
451 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
452 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
454 struct amdgpu_fence
{
458 struct amdgpu_ring
*ring
;
461 /* filp or special value for fence creator */
464 wait_queue_t fence_wake
;
467 struct amdgpu_user_fence
{
469 struct amdgpu_bo
*bo
;
470 /* write-back address offset to bo start */
474 int amdgpu_fence_driver_init(struct amdgpu_device
*adev
);
475 void amdgpu_fence_driver_fini(struct amdgpu_device
*adev
);
476 void amdgpu_fence_driver_force_completion(struct amdgpu_device
*adev
);
478 void amdgpu_fence_driver_init_ring(struct amdgpu_ring
*ring
);
479 int amdgpu_fence_driver_start_ring(struct amdgpu_ring
*ring
,
480 struct amdgpu_irq_src
*irq_src
,
482 int amdgpu_fence_emit(struct amdgpu_ring
*ring
, void *owner
,
483 struct amdgpu_fence
**fence
);
484 void amdgpu_fence_process(struct amdgpu_ring
*ring
);
485 int amdgpu_fence_wait_next(struct amdgpu_ring
*ring
);
486 int amdgpu_fence_wait_empty(struct amdgpu_ring
*ring
);
487 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring
*ring
);
489 bool amdgpu_fence_signaled(struct amdgpu_fence
*fence
);
490 int amdgpu_fence_wait(struct amdgpu_fence
*fence
, bool interruptible
);
491 int amdgpu_fence_wait_any(struct amdgpu_device
*adev
,
492 struct amdgpu_fence
**fences
,
494 long amdgpu_fence_wait_seq_timeout(struct amdgpu_device
*adev
,
495 u64
*target_seq
, bool intr
,
497 struct amdgpu_fence
*amdgpu_fence_ref(struct amdgpu_fence
*fence
);
498 void amdgpu_fence_unref(struct amdgpu_fence
**fence
);
500 bool amdgpu_fence_need_sync(struct amdgpu_fence
*fence
,
501 struct amdgpu_ring
*ring
);
502 void amdgpu_fence_note_sync(struct amdgpu_fence
*fence
,
503 struct amdgpu_ring
*ring
);
505 static inline struct amdgpu_fence
*amdgpu_fence_later(struct amdgpu_fence
*a
,
506 struct amdgpu_fence
*b
)
516 BUG_ON(a
->ring
!= b
->ring
);
518 if (a
->seq
> b
->seq
) {
525 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence
*a
,
526 struct amdgpu_fence
*b
)
536 BUG_ON(a
->ring
!= b
->ring
);
538 return a
->seq
< b
->seq
;
541 int amdgpu_user_fence_emit(struct amdgpu_ring
*ring
, struct amdgpu_user_fence
*user
,
542 void *owner
, struct amdgpu_fence
**fence
);
548 struct ttm_bo_global_ref bo_global_ref
;
549 struct drm_global_reference mem_global_ref
;
550 struct ttm_bo_device bdev
;
551 bool mem_global_referenced
;
554 #if defined(CONFIG_DEBUG_FS)
559 /* buffer handling */
560 const struct amdgpu_buffer_funcs
*buffer_funcs
;
561 struct amdgpu_ring
*buffer_funcs_ring
;
564 int amdgpu_copy_buffer(struct amdgpu_ring
*ring
,
568 struct reservation_object
*resv
,
569 struct amdgpu_fence
**fence
);
570 int amdgpu_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
572 struct amdgpu_bo_list_entry
{
573 struct amdgpu_bo
*robj
;
574 struct ttm_validate_buffer tv
;
575 struct amdgpu_bo_va
*bo_va
;
576 unsigned prefered_domains
;
577 unsigned allowed_domains
;
581 struct amdgpu_bo_va_mapping
{
582 struct list_head list
;
583 struct interval_tree_node it
;
588 /* bo virtual addresses in a specific vm */
589 struct amdgpu_bo_va
{
590 /* protected by bo being reserved */
591 struct list_head bo_list
;
593 struct amdgpu_fence
*last_pt_update
;
596 /* protected by vm mutex */
597 struct list_head mappings
;
598 struct list_head vm_status
;
600 /* constant after initialization */
601 struct amdgpu_vm
*vm
;
602 struct amdgpu_bo
*bo
;
606 /* Protected by gem.mutex */
607 struct list_head list
;
608 /* Protected by tbo.reserved */
610 struct ttm_place placements
[4];
611 struct ttm_placement placement
;
612 struct ttm_buffer_object tbo
;
613 struct ttm_bo_kmap_obj kmap
;
621 /* list of all virtual address to which this bo
625 /* Constant after initialization */
626 struct amdgpu_device
*adev
;
627 struct drm_gem_object gem_base
;
629 struct ttm_bo_kmap_obj dma_buf_vmap
;
631 struct amdgpu_mn
*mn
;
632 struct list_head mn_list
;
634 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
636 void amdgpu_gem_object_free(struct drm_gem_object
*obj
);
637 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
638 struct drm_file
*file_priv
);
639 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
640 struct drm_file
*file_priv
);
641 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
);
642 struct sg_table
*amdgpu_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
643 struct drm_gem_object
*amdgpu_gem_prime_import_sg_table(struct drm_device
*dev
,
644 struct dma_buf_attachment
*attach
,
645 struct sg_table
*sg
);
646 struct dma_buf
*amdgpu_gem_prime_export(struct drm_device
*dev
,
647 struct drm_gem_object
*gobj
,
649 int amdgpu_gem_prime_pin(struct drm_gem_object
*obj
);
650 void amdgpu_gem_prime_unpin(struct drm_gem_object
*obj
);
651 struct reservation_object
*amdgpu_gem_prime_res_obj(struct drm_gem_object
*);
652 void *amdgpu_gem_prime_vmap(struct drm_gem_object
*obj
);
653 void amdgpu_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
654 int amdgpu_gem_debugfs_init(struct amdgpu_device
*adev
);
656 /* sub-allocation manager, it has to be protected by another lock.
657 * By conception this is an helper for other part of the driver
658 * like the indirect buffer or semaphore, which both have their
661 * Principe is simple, we keep a list of sub allocation in offset
662 * order (first entry has offset == 0, last entry has the highest
665 * When allocating new object we first check if there is room at
666 * the end total_size - (last_object_offset + last_object_size) >=
667 * alloc_size. If so we allocate new object there.
669 * When there is not enough room at the end, we start waiting for
670 * each sub object until we reach object_offset+object_size >=
671 * alloc_size, this object then become the sub object we return.
673 * Alignment can't be bigger than page size.
675 * Hole are not considered for allocation to keep things simple.
676 * Assumption is that there won't be hole (all object on same
679 struct amdgpu_sa_manager
{
680 wait_queue_head_t wq
;
681 struct amdgpu_bo
*bo
;
682 struct list_head
*hole
;
683 struct list_head flist
[AMDGPU_MAX_RINGS
];
684 struct list_head olist
;
694 /* sub-allocation buffer */
695 struct amdgpu_sa_bo
{
696 struct list_head olist
;
697 struct list_head flist
;
698 struct amdgpu_sa_manager
*manager
;
701 struct amdgpu_fence
*fence
;
709 struct list_head objects
;
712 int amdgpu_gem_init(struct amdgpu_device
*adev
);
713 void amdgpu_gem_fini(struct amdgpu_device
*adev
);
714 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
715 int alignment
, u32 initial_domain
,
716 u64 flags
, bool kernel
,
717 struct drm_gem_object
**obj
);
719 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
720 struct drm_device
*dev
,
721 struct drm_mode_create_dumb
*args
);
722 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
723 struct drm_device
*dev
,
724 uint32_t handle
, uint64_t *offset_p
);
729 struct amdgpu_semaphore
{
730 struct amdgpu_sa_bo
*sa_bo
;
735 int amdgpu_semaphore_create(struct amdgpu_device
*adev
,
736 struct amdgpu_semaphore
**semaphore
);
737 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring
*ring
,
738 struct amdgpu_semaphore
*semaphore
);
739 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring
*ring
,
740 struct amdgpu_semaphore
*semaphore
);
741 void amdgpu_semaphore_free(struct amdgpu_device
*adev
,
742 struct amdgpu_semaphore
**semaphore
,
743 struct amdgpu_fence
*fence
);
749 struct amdgpu_semaphore
*semaphores
[AMDGPU_NUM_SYNCS
];
750 struct amdgpu_fence
*sync_to
[AMDGPU_MAX_RINGS
];
751 struct amdgpu_fence
*last_vm_update
;
754 void amdgpu_sync_create(struct amdgpu_sync
*sync
);
755 void amdgpu_sync_fence(struct amdgpu_sync
*sync
,
756 struct amdgpu_fence
*fence
);
757 int amdgpu_sync_resv(struct amdgpu_device
*adev
,
758 struct amdgpu_sync
*sync
,
759 struct reservation_object
*resv
,
761 int amdgpu_sync_rings(struct amdgpu_sync
*sync
,
762 struct amdgpu_ring
*ring
);
763 void amdgpu_sync_free(struct amdgpu_device
*adev
, struct amdgpu_sync
*sync
,
764 struct amdgpu_fence
*fence
);
767 * GART structures, functions & helpers
771 #define AMDGPU_GPU_PAGE_SIZE 4096
772 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
773 #define AMDGPU_GPU_PAGE_SHIFT 12
774 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
777 dma_addr_t table_addr
;
778 struct amdgpu_bo
*robj
;
780 unsigned num_gpu_pages
;
781 unsigned num_cpu_pages
;
784 dma_addr_t
*pages_addr
;
786 const struct amdgpu_gart_funcs
*gart_funcs
;
789 int amdgpu_gart_table_ram_alloc(struct amdgpu_device
*adev
);
790 void amdgpu_gart_table_ram_free(struct amdgpu_device
*adev
);
791 int amdgpu_gart_table_vram_alloc(struct amdgpu_device
*adev
);
792 void amdgpu_gart_table_vram_free(struct amdgpu_device
*adev
);
793 int amdgpu_gart_table_vram_pin(struct amdgpu_device
*adev
);
794 void amdgpu_gart_table_vram_unpin(struct amdgpu_device
*adev
);
795 int amdgpu_gart_init(struct amdgpu_device
*adev
);
796 void amdgpu_gart_fini(struct amdgpu_device
*adev
);
797 void amdgpu_gart_unbind(struct amdgpu_device
*adev
, unsigned offset
,
799 int amdgpu_gart_bind(struct amdgpu_device
*adev
, unsigned offset
,
800 int pages
, struct page
**pagelist
,
801 dma_addr_t
*dma_addr
, uint32_t flags
);
804 * GPU MC structures, functions & helpers
807 resource_size_t aper_size
;
808 resource_size_t aper_base
;
809 resource_size_t agp_base
;
810 /* for some chips with <= 32MB we need to lie
811 * about vram size near mc fb location */
813 u64 visible_vram_size
;
824 const struct firmware
*fw
; /* MC firmware */
826 struct amdgpu_irq_src vm_fault
;
831 * GPU doorbell structures, functions & helpers
833 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
835 AMDGPU_DOORBELL_KIQ
= 0x000,
836 AMDGPU_DOORBELL_HIQ
= 0x001,
837 AMDGPU_DOORBELL_DIQ
= 0x002,
838 AMDGPU_DOORBELL_MEC_RING0
= 0x010,
839 AMDGPU_DOORBELL_MEC_RING1
= 0x011,
840 AMDGPU_DOORBELL_MEC_RING2
= 0x012,
841 AMDGPU_DOORBELL_MEC_RING3
= 0x013,
842 AMDGPU_DOORBELL_MEC_RING4
= 0x014,
843 AMDGPU_DOORBELL_MEC_RING5
= 0x015,
844 AMDGPU_DOORBELL_MEC_RING6
= 0x016,
845 AMDGPU_DOORBELL_MEC_RING7
= 0x017,
846 AMDGPU_DOORBELL_GFX_RING0
= 0x020,
847 AMDGPU_DOORBELL_sDMA_ENGINE0
= 0x1E0,
848 AMDGPU_DOORBELL_sDMA_ENGINE1
= 0x1E1,
849 AMDGPU_DOORBELL_IH
= 0x1E8,
850 AMDGPU_DOORBELL_MAX_ASSIGNMENT
= 0x3FF,
851 AMDGPU_DOORBELL_INVALID
= 0xFFFF
852 } AMDGPU_DOORBELL_ASSIGNMENT
;
854 struct amdgpu_doorbell
{
856 resource_size_t base
;
857 resource_size_t size
;
859 u32 num_doorbells
; /* Number of doorbells actually reserved for amdgpu. */
862 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
863 phys_addr_t
*aperture_base
,
864 size_t *aperture_size
,
865 size_t *start_offset
);
871 struct amdgpu_flip_work
{
872 struct work_struct flip_work
;
873 struct work_struct unpin_work
;
874 struct amdgpu_device
*adev
;
877 struct drm_pending_vblank_event
*event
;
878 struct amdgpu_bo
*old_rbo
;
888 struct amdgpu_sa_bo
*sa_bo
;
892 struct amdgpu_ring
*ring
;
893 struct amdgpu_fence
*fence
;
894 struct amdgpu_user_fence
*user
;
895 struct amdgpu_vm
*vm
;
896 struct amdgpu_sync sync
;
897 uint32_t gds_base
, gds_size
;
898 uint32_t gws_base
, gws_size
;
899 uint32_t oa_base
, oa_size
;
903 enum amdgpu_ring_type
{
904 AMDGPU_RING_TYPE_GFX
,
905 AMDGPU_RING_TYPE_COMPUTE
,
906 AMDGPU_RING_TYPE_SDMA
,
907 AMDGPU_RING_TYPE_UVD
,
912 struct amdgpu_device
*adev
;
913 const struct amdgpu_ring_funcs
*funcs
;
914 struct amdgpu_fence_driver fence_drv
;
916 struct mutex
*ring_lock
;
917 struct amdgpu_bo
*ring_obj
;
918 volatile uint32_t *ring
;
920 u64 next_rptr_gpu_addr
;
921 volatile u32
*next_rptr_cpu_addr
;
925 unsigned ring_free_dw
;
928 atomic64_t last_activity
;
935 u64 last_semaphore_signal_addr
;
936 u64 last_semaphore_wait_addr
;
940 struct amdgpu_bo
*mqd_obj
;
944 unsigned next_rptr_offs
;
946 struct drm_file
*current_filp
;
947 unsigned current_ctx
;
948 bool need_ctx_switch
;
949 enum amdgpu_ring_type type
;
957 /* maximum number of VMIDs */
958 #define AMDGPU_NUM_VM 16
960 /* number of entries in page table */
961 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
963 /* PTBs (Page Table Blocks) need to be aligned to 32K */
964 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
965 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
966 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
968 #define AMDGPU_PTE_VALID (1 << 0)
969 #define AMDGPU_PTE_SYSTEM (1 << 1)
970 #define AMDGPU_PTE_SNOOPED (1 << 2)
973 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
975 #define AMDGPU_PTE_READABLE (1 << 5)
976 #define AMDGPU_PTE_WRITEABLE (1 << 6)
978 /* PTE (Page Table Entry) fragment field for different page sizes */
979 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
980 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
981 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
983 struct amdgpu_vm_pt
{
984 struct amdgpu_bo
*bo
;
988 struct amdgpu_vm_id
{
990 uint64_t pd_gpu_addr
;
991 /* last flushed PD/PT update */
992 struct amdgpu_fence
*flushed_updates
;
993 /* last use of vmid */
994 struct amdgpu_fence
*last_id_use
;
1002 /* protecting invalidated and freed */
1003 spinlock_t status_lock
;
1005 /* BOs moved, but not yet updated in the PT */
1006 struct list_head invalidated
;
1008 /* BOs freed, but not yet updated in the PT */
1009 struct list_head freed
;
1011 /* contains the page directory */
1012 struct amdgpu_bo
*page_directory
;
1013 unsigned max_pde_used
;
1015 /* array of page tables, one for each page directory entry */
1016 struct amdgpu_vm_pt
*page_tables
;
1018 /* for id and flush management per ring */
1019 struct amdgpu_vm_id ids
[AMDGPU_MAX_RINGS
];
1022 struct amdgpu_vm_manager
{
1023 struct amdgpu_fence
*active
[AMDGPU_NUM_VM
];
1025 /* number of VMIDs */
1027 /* vram base address for page table entry */
1028 u64 vram_base_offset
;
1029 /* is vm enabled? */
1031 /* for hw to save the PD addr on suspend/resume */
1032 uint32_t saved_table_addr
[AMDGPU_NUM_VM
];
1033 /* vm pte handling */
1034 const struct amdgpu_vm_pte_funcs
*vm_pte_funcs
;
1035 struct amdgpu_ring
*vm_pte_funcs_ring
;
1039 * context related structures
1042 struct amdgpu_ctx_state
{
1048 /* call kref_get()before CS start and kref_put() after CS fence signaled */
1049 struct kref refcount
;
1050 struct amdgpu_fpriv
*fpriv
;
1051 struct amdgpu_ctx_state state
;
1055 struct amdgpu_ctx_mgr
{
1056 struct amdgpu_device
*adev
;
1057 struct idr ctx_handles
;
1058 /* lock for IDR system */
1063 * file private structure
1066 struct amdgpu_fpriv
{
1067 struct amdgpu_vm vm
;
1068 struct mutex bo_list_lock
;
1069 struct idr bo_list_handles
;
1070 struct amdgpu_ctx_mgr ctx_mgr
;
1077 struct amdgpu_bo_list
{
1079 struct amdgpu_bo
*gds_obj
;
1080 struct amdgpu_bo
*gws_obj
;
1081 struct amdgpu_bo
*oa_obj
;
1083 unsigned num_entries
;
1084 struct amdgpu_bo_list_entry
*array
;
1087 struct amdgpu_bo_list
*
1088 amdgpu_bo_list_get(struct amdgpu_fpriv
*fpriv
, int id
);
1089 void amdgpu_bo_list_put(struct amdgpu_bo_list
*list
);
1090 void amdgpu_bo_list_free(struct amdgpu_bo_list
*list
);
1095 #include "clearstate_defs.h"
1098 /* for power gating */
1099 struct amdgpu_bo
*save_restore_obj
;
1100 uint64_t save_restore_gpu_addr
;
1101 volatile uint32_t *sr_ptr
;
1102 const u32
*reg_list
;
1104 /* for clear state */
1105 struct amdgpu_bo
*clear_state_obj
;
1106 uint64_t clear_state_gpu_addr
;
1107 volatile uint32_t *cs_ptr
;
1108 const struct cs_section_def
*cs_data
;
1109 u32 clear_state_size
;
1111 struct amdgpu_bo
*cp_table_obj
;
1112 uint64_t cp_table_gpu_addr
;
1113 volatile uint32_t *cp_table_ptr
;
1118 struct amdgpu_bo
*hpd_eop_obj
;
1119 u64 hpd_eop_gpu_addr
;
1126 * GPU scratch registers structures, functions & helpers
1128 struct amdgpu_scratch
{
1136 * GFX configurations
1138 struct amdgpu_gca_config
{
1139 unsigned max_shader_engines
;
1140 unsigned max_tile_pipes
;
1141 unsigned max_cu_per_sh
;
1142 unsigned max_sh_per_se
;
1143 unsigned max_backends_per_se
;
1144 unsigned max_texture_channel_caches
;
1146 unsigned max_gs_threads
;
1147 unsigned max_hw_contexts
;
1148 unsigned sc_prim_fifo_size_frontend
;
1149 unsigned sc_prim_fifo_size_backend
;
1150 unsigned sc_hiz_tile_fifo_size
;
1151 unsigned sc_earlyz_tile_fifo_size
;
1153 unsigned num_tile_pipes
;
1154 unsigned backend_enable_mask
;
1155 unsigned mem_max_burst_length_bytes
;
1156 unsigned mem_row_size_in_kb
;
1157 unsigned shader_engine_tile_size
;
1159 unsigned multi_gpu_tile_size
;
1160 unsigned mc_arb_ramcfg
;
1161 unsigned gb_addr_config
;
1163 uint32_t tile_mode_array
[32];
1164 uint32_t macrotile_mode_array
[16];
1168 struct mutex gpu_clock_mutex
;
1169 struct amdgpu_gca_config config
;
1170 struct amdgpu_rlc rlc
;
1171 struct amdgpu_mec mec
;
1172 struct amdgpu_scratch scratch
;
1173 const struct firmware
*me_fw
; /* ME firmware */
1174 uint32_t me_fw_version
;
1175 const struct firmware
*pfp_fw
; /* PFP firmware */
1176 uint32_t pfp_fw_version
;
1177 const struct firmware
*ce_fw
; /* CE firmware */
1178 uint32_t ce_fw_version
;
1179 const struct firmware
*rlc_fw
; /* RLC firmware */
1180 uint32_t rlc_fw_version
;
1181 const struct firmware
*mec_fw
; /* MEC firmware */
1182 uint32_t mec_fw_version
;
1183 const struct firmware
*mec2_fw
; /* MEC2 firmware */
1184 uint32_t mec2_fw_version
;
1185 struct amdgpu_ring gfx_ring
[AMDGPU_MAX_GFX_RINGS
];
1186 unsigned num_gfx_rings
;
1187 struct amdgpu_ring compute_ring
[AMDGPU_MAX_COMPUTE_RINGS
];
1188 unsigned num_compute_rings
;
1189 struct amdgpu_irq_src eop_irq
;
1190 struct amdgpu_irq_src priv_reg_irq
;
1191 struct amdgpu_irq_src priv_inst_irq
;
1193 uint32_t gfx_current_status
;
1194 /* sync signal for const engine */
1195 unsigned ce_sync_offs
;
1198 int amdgpu_ib_get(struct amdgpu_ring
*ring
, struct amdgpu_vm
*vm
,
1199 unsigned size
, struct amdgpu_ib
*ib
);
1200 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
);
1201 int amdgpu_ib_schedule(struct amdgpu_device
*adev
, unsigned num_ibs
,
1202 struct amdgpu_ib
*ib
, void *owner
);
1203 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
);
1204 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
);
1205 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
);
1206 /* Ring access between begin & end cannot sleep */
1207 void amdgpu_ring_free_size(struct amdgpu_ring
*ring
);
1208 int amdgpu_ring_alloc(struct amdgpu_ring
*ring
, unsigned ndw
);
1209 int amdgpu_ring_lock(struct amdgpu_ring
*ring
, unsigned ndw
);
1210 void amdgpu_ring_commit(struct amdgpu_ring
*ring
);
1211 void amdgpu_ring_unlock_commit(struct amdgpu_ring
*ring
);
1212 void amdgpu_ring_undo(struct amdgpu_ring
*ring
);
1213 void amdgpu_ring_unlock_undo(struct amdgpu_ring
*ring
);
1214 void amdgpu_ring_lockup_update(struct amdgpu_ring
*ring
);
1215 bool amdgpu_ring_test_lockup(struct amdgpu_ring
*ring
);
1216 unsigned amdgpu_ring_backup(struct amdgpu_ring
*ring
,
1218 int amdgpu_ring_restore(struct amdgpu_ring
*ring
,
1219 unsigned size
, uint32_t *data
);
1220 int amdgpu_ring_init(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
,
1221 unsigned ring_size
, u32 nop
, u32 align_mask
,
1222 struct amdgpu_irq_src
*irq_src
, unsigned irq_type
,
1223 enum amdgpu_ring_type ring_type
);
1224 void amdgpu_ring_fini(struct amdgpu_ring
*ring
);
1229 struct amdgpu_cs_chunk
{
1233 void __user
*user_ptr
;
1236 struct amdgpu_cs_parser
{
1237 struct amdgpu_device
*adev
;
1238 struct drm_file
*filp
;
1240 struct amdgpu_bo_list
*bo_list
;
1243 struct amdgpu_cs_chunk
*chunks
;
1245 struct amdgpu_bo_list_entry
*vm_bos
;
1246 struct amdgpu_bo_list_entry
*ib_bos
;
1247 struct list_head validated
;
1249 struct amdgpu_ib
*ibs
;
1252 struct ww_acquire_ctx ticket
;
1255 struct amdgpu_user_fence uf
;
1258 static inline u32
amdgpu_get_ib_value(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
, int idx
)
1260 return p
->ibs
[ib_idx
].ptr
[idx
];
1266 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1269 struct amdgpu_bo
*wb_obj
;
1270 volatile uint32_t *wb
;
1272 u32 num_wb
; /* Number of wb slots actually reserved for amdgpu. */
1273 unsigned long used
[DIV_ROUND_UP(AMDGPU_MAX_WB
, BITS_PER_LONG
)];
1276 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
);
1277 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
);
1280 * struct amdgpu_pm - power management datas
1281 * It keeps track of various data needed to take powermanagement decision.
1284 enum amdgpu_pm_state_type
{
1285 /* not used for dpm */
1286 POWER_STATE_TYPE_DEFAULT
,
1287 POWER_STATE_TYPE_POWERSAVE
,
1288 /* user selectable states */
1289 POWER_STATE_TYPE_BATTERY
,
1290 POWER_STATE_TYPE_BALANCED
,
1291 POWER_STATE_TYPE_PERFORMANCE
,
1292 /* internal states */
1293 POWER_STATE_TYPE_INTERNAL_UVD
,
1294 POWER_STATE_TYPE_INTERNAL_UVD_SD
,
1295 POWER_STATE_TYPE_INTERNAL_UVD_HD
,
1296 POWER_STATE_TYPE_INTERNAL_UVD_HD2
,
1297 POWER_STATE_TYPE_INTERNAL_UVD_MVC
,
1298 POWER_STATE_TYPE_INTERNAL_BOOT
,
1299 POWER_STATE_TYPE_INTERNAL_THERMAL
,
1300 POWER_STATE_TYPE_INTERNAL_ACPI
,
1301 POWER_STATE_TYPE_INTERNAL_ULV
,
1302 POWER_STATE_TYPE_INTERNAL_3DPERF
,
1305 enum amdgpu_int_thermal_type
{
1307 THERMAL_TYPE_EXTERNAL
,
1308 THERMAL_TYPE_EXTERNAL_GPIO
,
1311 THERMAL_TYPE_ADT7473_WITH_INTERNAL
,
1312 THERMAL_TYPE_EVERGREEN
,
1316 THERMAL_TYPE_EMC2103_WITH_INTERNAL
,
1321 enum amdgpu_dpm_auto_throttle_src
{
1322 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
,
1323 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1326 enum amdgpu_dpm_event_src
{
1327 AMDGPU_DPM_EVENT_SRC_ANALOG
= 0,
1328 AMDGPU_DPM_EVENT_SRC_EXTERNAL
= 1,
1329 AMDGPU_DPM_EVENT_SRC_DIGITAL
= 2,
1330 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
1331 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
= 4
1334 #define AMDGPU_MAX_VCE_LEVELS 6
1336 enum amdgpu_vce_level
{
1337 AMDGPU_VCE_LEVEL_AC_ALL
= 0, /* AC, All cases */
1338 AMDGPU_VCE_LEVEL_DC_EE
= 1, /* DC, entropy encoding */
1339 AMDGPU_VCE_LEVEL_DC_LL_LOW
= 2, /* DC, low latency queue, res <= 720 */
1340 AMDGPU_VCE_LEVEL_DC_LL_HIGH
= 3, /* DC, low latency queue, 1080 >= res > 720 */
1341 AMDGPU_VCE_LEVEL_DC_GP_LOW
= 4, /* DC, general purpose queue, res <= 720 */
1342 AMDGPU_VCE_LEVEL_DC_GP_HIGH
= 5, /* DC, general purpose queue, 1080 >= res > 720 */
1346 u32 caps
; /* vbios flags */
1347 u32
class; /* vbios flags */
1348 u32 class2
; /* vbios flags */
1356 enum amdgpu_vce_level vce_level
;
1361 struct amdgpu_dpm_thermal
{
1362 /* thermal interrupt work */
1363 struct work_struct work
;
1364 /* low temperature threshold */
1366 /* high temperature threshold */
1368 /* was last interrupt low to high or high to low */
1370 /* interrupt source */
1371 struct amdgpu_irq_src irq
;
1374 enum amdgpu_clk_action
1380 struct amdgpu_blacklist_clocks
1384 enum amdgpu_clk_action action
;
1387 struct amdgpu_clock_and_voltage_limits
{
1394 struct amdgpu_clock_array
{
1399 struct amdgpu_clock_voltage_dependency_entry
{
1404 struct amdgpu_clock_voltage_dependency_table
{
1406 struct amdgpu_clock_voltage_dependency_entry
*entries
;
1409 union amdgpu_cac_leakage_entry
{
1421 struct amdgpu_cac_leakage_table
{
1423 union amdgpu_cac_leakage_entry
*entries
;
1426 struct amdgpu_phase_shedding_limits_entry
{
1432 struct amdgpu_phase_shedding_limits_table
{
1434 struct amdgpu_phase_shedding_limits_entry
*entries
;
1437 struct amdgpu_uvd_clock_voltage_dependency_entry
{
1443 struct amdgpu_uvd_clock_voltage_dependency_table
{
1445 struct amdgpu_uvd_clock_voltage_dependency_entry
*entries
;
1448 struct amdgpu_vce_clock_voltage_dependency_entry
{
1454 struct amdgpu_vce_clock_voltage_dependency_table
{
1456 struct amdgpu_vce_clock_voltage_dependency_entry
*entries
;
1459 struct amdgpu_ppm_table
{
1461 u16 cpu_core_number
;
1463 u32 small_ac_platform_tdp
;
1465 u32 small_ac_platform_tdc
;
1472 struct amdgpu_cac_tdp_table
{
1474 u16 configurable_tdp
;
1476 u16 battery_power_limit
;
1477 u16 small_power_limit
;
1478 u16 low_cac_leakage
;
1479 u16 high_cac_leakage
;
1480 u16 maximum_power_delivery_limit
;
1483 struct amdgpu_dpm_dynamic_state
{
1484 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk
;
1485 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk
;
1486 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk
;
1487 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk
;
1488 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk
;
1489 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table
;
1490 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table
;
1491 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table
;
1492 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table
;
1493 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk
;
1494 struct amdgpu_clock_array valid_sclk_values
;
1495 struct amdgpu_clock_array valid_mclk_values
;
1496 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc
;
1497 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac
;
1498 u32 mclk_sclk_ratio
;
1499 u32 sclk_mclk_delta
;
1500 u16 vddc_vddci_delta
;
1501 u16 min_vddc_for_pcie_gen2
;
1502 struct amdgpu_cac_leakage_table cac_leakage_table
;
1503 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table
;
1504 struct amdgpu_ppm_table
*ppm_table
;
1505 struct amdgpu_cac_tdp_table
*cac_tdp_table
;
1508 struct amdgpu_dpm_fan
{
1519 u16 default_max_fan_pwm
;
1520 u16 default_fan_output_sensitivity
;
1521 u16 fan_output_sensitivity
;
1522 bool ucode_fan_control
;
1525 enum amdgpu_pcie_gen
{
1526 AMDGPU_PCIE_GEN1
= 0,
1527 AMDGPU_PCIE_GEN2
= 1,
1528 AMDGPU_PCIE_GEN3
= 2,
1529 AMDGPU_PCIE_GEN_INVALID
= 0xffff
1532 enum amdgpu_dpm_forced_level
{
1533 AMDGPU_DPM_FORCED_LEVEL_AUTO
= 0,
1534 AMDGPU_DPM_FORCED_LEVEL_LOW
= 1,
1535 AMDGPU_DPM_FORCED_LEVEL_HIGH
= 2,
1538 struct amdgpu_vce_state
{
1549 struct amdgpu_dpm_funcs
{
1550 int (*get_temperature
)(struct amdgpu_device
*adev
);
1551 int (*pre_set_power_state
)(struct amdgpu_device
*adev
);
1552 int (*set_power_state
)(struct amdgpu_device
*adev
);
1553 void (*post_set_power_state
)(struct amdgpu_device
*adev
);
1554 void (*display_configuration_changed
)(struct amdgpu_device
*adev
);
1555 u32 (*get_sclk
)(struct amdgpu_device
*adev
, bool low
);
1556 u32 (*get_mclk
)(struct amdgpu_device
*adev
, bool low
);
1557 void (*print_power_state
)(struct amdgpu_device
*adev
, struct amdgpu_ps
*ps
);
1558 void (*debugfs_print_current_performance_level
)(struct amdgpu_device
*adev
, struct seq_file
*m
);
1559 int (*force_performance_level
)(struct amdgpu_device
*adev
, enum amdgpu_dpm_forced_level level
);
1560 bool (*vblank_too_short
)(struct amdgpu_device
*adev
);
1561 void (*powergate_uvd
)(struct amdgpu_device
*adev
, bool gate
);
1562 void (*enable_bapm
)(struct amdgpu_device
*adev
, bool enable
);
1563 void (*set_fan_control_mode
)(struct amdgpu_device
*adev
, u32 mode
);
1564 u32 (*get_fan_control_mode
)(struct amdgpu_device
*adev
);
1565 int (*set_fan_speed_percent
)(struct amdgpu_device
*adev
, u32 speed
);
1566 int (*get_fan_speed_percent
)(struct amdgpu_device
*adev
, u32
*speed
);
1570 struct amdgpu_ps
*ps
;
1571 /* number of valid power states */
1573 /* current power state that is active */
1574 struct amdgpu_ps
*current_ps
;
1575 /* requested power state */
1576 struct amdgpu_ps
*requested_ps
;
1577 /* boot up power state */
1578 struct amdgpu_ps
*boot_ps
;
1579 /* default uvd power state */
1580 struct amdgpu_ps
*uvd_ps
;
1581 /* vce requirements */
1582 struct amdgpu_vce_state vce_states
[AMDGPU_MAX_VCE_LEVELS
];
1583 enum amdgpu_vce_level vce_level
;
1584 enum amdgpu_pm_state_type state
;
1585 enum amdgpu_pm_state_type user_state
;
1587 u32 voltage_response_time
;
1588 u32 backbias_response_time
;
1590 u32 new_active_crtcs
;
1591 int new_active_crtc_count
;
1592 u32 current_active_crtcs
;
1593 int current_active_crtc_count
;
1594 struct amdgpu_dpm_dynamic_state dyn_state
;
1595 struct amdgpu_dpm_fan fan
;
1598 u32 near_tdp_limit_adjusted
;
1599 u32 sq_ramping_threshold
;
1603 u16 load_line_slope
;
1606 /* special states active */
1607 bool thermal_active
;
1610 /* thermal handling */
1611 struct amdgpu_dpm_thermal thermal
;
1613 enum amdgpu_dpm_forced_level forced_level
;
1618 /* write locked while reprogramming mclk */
1619 struct rw_semaphore mclk_lock
;
1624 struct amdgpu_i2c_chan
*i2c_bus
;
1625 /* internal thermal controller on rv6xx+ */
1626 enum amdgpu_int_thermal_type int_thermal_type
;
1627 struct device
*int_hwmon_dev
;
1628 /* fan control parameters */
1630 u8 fan_pulses_per_revolution
;
1635 struct amdgpu_dpm dpm
;
1636 const struct firmware
*fw
; /* SMC firmware */
1637 uint32_t fw_version
;
1638 const struct amdgpu_dpm_funcs
*funcs
;
1644 #define AMDGPU_MAX_UVD_HANDLES 10
1645 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1646 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1647 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1650 struct amdgpu_bo
*vcpu_bo
;
1654 atomic_t handles
[AMDGPU_MAX_UVD_HANDLES
];
1655 struct drm_file
*filp
[AMDGPU_MAX_UVD_HANDLES
];
1656 struct delayed_work idle_work
;
1657 const struct firmware
*fw
; /* UVD firmware */
1658 struct amdgpu_ring ring
;
1659 struct amdgpu_irq_src irq
;
1660 bool address_64_bit
;
1666 #define AMDGPU_MAX_VCE_HANDLES 16
1667 #define AMDGPU_VCE_STACK_SIZE (1024*1024)
1668 #define AMDGPU_VCE_HEAP_SIZE (4*1024*1024)
1669 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1672 struct amdgpu_bo
*vcpu_bo
;
1674 unsigned fw_version
;
1675 unsigned fb_version
;
1676 atomic_t handles
[AMDGPU_MAX_VCE_HANDLES
];
1677 struct drm_file
*filp
[AMDGPU_MAX_VCE_HANDLES
];
1678 struct delayed_work idle_work
;
1679 const struct firmware
*fw
; /* VCE firmware */
1680 struct amdgpu_ring ring
[AMDGPU_MAX_VCE_RINGS
];
1681 struct amdgpu_irq_src irq
;
1687 struct amdgpu_sdma
{
1689 const struct firmware
*fw
;
1690 uint32_t fw_version
;
1692 struct amdgpu_ring ring
;
1698 struct amdgpu_firmware
{
1699 struct amdgpu_firmware_info ucode
[AMDGPU_UCODE_ID_MAXIMUM
];
1701 struct amdgpu_bo
*fw_buf
;
1702 unsigned int fw_size
;
1708 void amdgpu_benchmark(struct amdgpu_device
*adev
, int test_number
);
1714 void amdgpu_test_moves(struct amdgpu_device
*adev
);
1715 void amdgpu_test_ring_sync(struct amdgpu_device
*adev
,
1716 struct amdgpu_ring
*cpA
,
1717 struct amdgpu_ring
*cpB
);
1718 void amdgpu_test_syncing(struct amdgpu_device
*adev
);
1723 #if defined(CONFIG_MMU_NOTIFIER)
1724 int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
);
1725 void amdgpu_mn_unregister(struct amdgpu_bo
*bo
);
1727 static int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
)
1731 static void amdgpu_mn_unregister(struct amdgpu_bo
*bo
) {}
1737 struct amdgpu_debugfs
{
1738 struct drm_info_list
*files
;
1742 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1743 struct drm_info_list
*files
,
1745 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
);
1747 #if defined(CONFIG_DEBUG_FS)
1748 int amdgpu_debugfs_init(struct drm_minor
*minor
);
1749 void amdgpu_debugfs_cleanup(struct drm_minor
*minor
);
1753 * amdgpu smumgr functions
1755 struct amdgpu_smumgr_funcs
{
1756 int (*check_fw_load_finish
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1757 int (*request_smu_load_fw
)(struct amdgpu_device
*adev
);
1758 int (*request_smu_specific_fw
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1764 struct amdgpu_smumgr
{
1765 struct amdgpu_bo
*toc_buf
;
1766 struct amdgpu_bo
*smu_buf
;
1767 /* asic priv smu data */
1769 spinlock_t smu_lock
;
1770 /* smumgr functions */
1771 const struct amdgpu_smumgr_funcs
*smumgr_funcs
;
1772 /* ucode loading complete flag */
1777 * ASIC specific register table accessible by UMD
1779 struct amdgpu_allowed_register_entry
{
1780 uint32_t reg_offset
;
1785 struct amdgpu_cu_info
{
1786 uint32_t number
; /* total active CU number */
1787 uint32_t ao_cu_mask
;
1788 uint32_t bitmap
[4][4];
1793 * ASIC specific functions.
1795 struct amdgpu_asic_funcs
{
1796 bool (*read_disabled_bios
)(struct amdgpu_device
*adev
);
1797 int (*read_register
)(struct amdgpu_device
*adev
, u32 se_num
,
1798 u32 sh_num
, u32 reg_offset
, u32
*value
);
1799 void (*set_vga_state
)(struct amdgpu_device
*adev
, bool state
);
1800 int (*reset
)(struct amdgpu_device
*adev
);
1801 /* wait for mc_idle */
1802 int (*wait_for_mc_idle
)(struct amdgpu_device
*adev
);
1803 /* get the reference clock */
1804 u32 (*get_xclk
)(struct amdgpu_device
*adev
);
1805 /* get the gpu clock counter */
1806 uint64_t (*get_gpu_clock_counter
)(struct amdgpu_device
*adev
);
1807 int (*get_cu_info
)(struct amdgpu_device
*adev
, struct amdgpu_cu_info
*info
);
1808 /* MM block clocks */
1809 int (*set_uvd_clocks
)(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
);
1810 int (*set_vce_clocks
)(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
);
1816 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1817 struct drm_file
*filp
);
1818 int amdgpu_bo_list_ioctl(struct drm_device
*dev
, void *data
,
1819 struct drm_file
*filp
);
1821 int amdgpu_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1822 struct drm_file
*filp
);
1823 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
1824 struct drm_file
*filp
);
1825 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1826 struct drm_file
*filp
);
1827 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1828 struct drm_file
*filp
);
1829 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1830 struct drm_file
*filp
);
1831 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
1832 struct drm_file
*filp
);
1833 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1834 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1836 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
1837 struct drm_file
*filp
);
1839 /* VRAM scratch page for HDP bug, default vram page */
1840 struct amdgpu_vram_scratch
{
1841 struct amdgpu_bo
*robj
;
1842 volatile uint32_t *ptr
;
1849 struct amdgpu_atif_notification_cfg
{
1854 struct amdgpu_atif_notifications
{
1855 bool display_switch
;
1856 bool expansion_mode_change
;
1858 bool forced_power_state
;
1859 bool system_power_state
;
1860 bool display_conf_change
;
1862 bool brightness_change
;
1863 bool dgpu_display_event
;
1866 struct amdgpu_atif_functions
{
1868 bool sbios_requests
;
1869 bool select_active_disp
;
1871 bool get_tv_standard
;
1872 bool set_tv_standard
;
1873 bool get_panel_expansion_mode
;
1874 bool set_panel_expansion_mode
;
1875 bool temperature_change
;
1876 bool graphics_device_types
;
1879 struct amdgpu_atif
{
1880 struct amdgpu_atif_notifications notifications
;
1881 struct amdgpu_atif_functions functions
;
1882 struct amdgpu_atif_notification_cfg notification_cfg
;
1883 struct amdgpu_encoder
*encoder_for_bl
;
1886 struct amdgpu_atcs_functions
{
1890 bool pcie_bus_width
;
1893 struct amdgpu_atcs
{
1894 struct amdgpu_atcs_functions functions
;
1897 int amdgpu_ctx_alloc(struct amdgpu_device
*adev
,struct amdgpu_fpriv
*fpriv
,
1898 uint32_t *id
,uint32_t flags
);
1899 int amdgpu_ctx_free(struct amdgpu_device
*adev
, struct amdgpu_fpriv
*fpriv
,
1901 int amdgpu_ctx_query(struct amdgpu_device
*adev
, struct amdgpu_fpriv
*fpriv
,
1902 uint32_t id
,struct amdgpu_ctx_state
*state
);
1904 void amdgpu_ctx_fini(struct amdgpu_fpriv
*fpriv
);
1905 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
);
1906 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
);
1908 extern int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
1909 struct drm_file
*filp
);
1912 * Core structure, functions and helpers.
1914 typedef uint32_t (*amdgpu_rreg_t
)(struct amdgpu_device
*, uint32_t);
1915 typedef void (*amdgpu_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1917 typedef uint32_t (*amdgpu_block_rreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1918 typedef void (*amdgpu_block_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t, uint32_t);
1920 struct amdgpu_device
{
1922 struct drm_device
*ddev
;
1923 struct pci_dev
*pdev
;
1924 struct rw_semaphore exclusive_lock
;
1927 enum amdgpu_asic_type asic_type
;
1930 uint32_t external_rev_id
;
1931 unsigned long flags
;
1933 const struct amdgpu_asic_funcs
*asic_funcs
;
1939 struct work_struct reset_work
;
1940 struct notifier_block acpi_nb
;
1941 struct amdgpu_i2c_chan
*i2c_bus
[AMDGPU_MAX_I2C_BUS
];
1942 struct amdgpu_debugfs debugfs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1943 unsigned debugfs_count
;
1944 #if defined(CONFIG_DEBUG_FS)
1945 struct dentry
*debugfs_regs
;
1947 struct amdgpu_atif atif
;
1948 struct amdgpu_atcs atcs
;
1949 struct mutex srbm_mutex
;
1950 /* GRBM index mutex. Protects concurrent access to GRBM index */
1951 struct mutex grbm_idx_mutex
;
1952 struct dev_pm_domain vga_pm_domain
;
1953 bool have_disp_power_ref
;
1958 uint16_t bios_header_start
;
1959 struct amdgpu_bo
*stollen_vga_memory
;
1960 uint32_t bios_scratch
[AMDGPU_BIOS_NUM_SCRATCH
];
1962 /* Register/doorbell mmio */
1963 resource_size_t rmmio_base
;
1964 resource_size_t rmmio_size
;
1965 void __iomem
*rmmio
;
1966 /* protects concurrent MM_INDEX/DATA based register access */
1967 spinlock_t mmio_idx_lock
;
1968 /* protects concurrent SMC based register access */
1969 spinlock_t smc_idx_lock
;
1970 amdgpu_rreg_t smc_rreg
;
1971 amdgpu_wreg_t smc_wreg
;
1972 /* protects concurrent PCIE register access */
1973 spinlock_t pcie_idx_lock
;
1974 amdgpu_rreg_t pcie_rreg
;
1975 amdgpu_wreg_t pcie_wreg
;
1976 /* protects concurrent UVD register access */
1977 spinlock_t uvd_ctx_idx_lock
;
1978 amdgpu_rreg_t uvd_ctx_rreg
;
1979 amdgpu_wreg_t uvd_ctx_wreg
;
1980 /* protects concurrent DIDT register access */
1981 spinlock_t didt_idx_lock
;
1982 amdgpu_rreg_t didt_rreg
;
1983 amdgpu_wreg_t didt_wreg
;
1984 /* protects concurrent ENDPOINT (audio) register access */
1985 spinlock_t audio_endpt_idx_lock
;
1986 amdgpu_block_rreg_t audio_endpt_rreg
;
1987 amdgpu_block_wreg_t audio_endpt_wreg
;
1988 void __iomem
*rio_mem
;
1989 resource_size_t rio_mem_size
;
1990 struct amdgpu_doorbell doorbell
;
1992 /* clock/pll info */
1993 struct amdgpu_clock clock
;
1996 struct amdgpu_mc mc
;
1997 struct amdgpu_gart gart
;
1998 struct amdgpu_dummy_page dummy_page
;
1999 struct amdgpu_vm_manager vm_manager
;
2001 /* memory management */
2002 struct amdgpu_mman mman
;
2003 struct amdgpu_gem gem
;
2004 struct amdgpu_vram_scratch vram_scratch
;
2005 struct amdgpu_wb wb
;
2006 atomic64_t vram_usage
;
2007 atomic64_t vram_vis_usage
;
2008 atomic64_t gtt_usage
;
2009 atomic64_t num_bytes_moved
;
2012 struct amdgpu_mode_info mode_info
;
2013 struct work_struct hotplug_work
;
2014 struct amdgpu_irq_src crtc_irq
;
2015 struct amdgpu_irq_src pageflip_irq
;
2016 struct amdgpu_irq_src hpd_irq
;
2019 wait_queue_head_t fence_queue
;
2020 unsigned fence_context
;
2021 struct mutex ring_lock
;
2023 struct amdgpu_ring
*rings
[AMDGPU_MAX_RINGS
];
2025 struct amdgpu_sa_manager ring_tmp_bo
;
2028 struct amdgpu_irq irq
;
2031 struct amdgpu_pm pm
;
2036 struct amdgpu_smumgr smu
;
2039 struct amdgpu_gfx gfx
;
2042 struct amdgpu_sdma sdma
[2];
2043 struct amdgpu_irq_src sdma_trap_irq
;
2044 struct amdgpu_irq_src sdma_illegal_inst_irq
;
2048 struct amdgpu_uvd uvd
;
2051 struct amdgpu_vce vce
;
2054 struct amdgpu_firmware firmware
;
2057 struct amdgpu_gds gds
;
2059 const struct amdgpu_ip_block_version
*ip_blocks
;
2061 bool *ip_block_enabled
;
2062 struct mutex mn_lock
;
2063 DECLARE_HASHTABLE(mn_hash
, 7);
2065 /* tracking pinned memory */
2070 bool amdgpu_device_is_px(struct drm_device
*dev
);
2071 int amdgpu_device_init(struct amdgpu_device
*adev
,
2072 struct drm_device
*ddev
,
2073 struct pci_dev
*pdev
,
2075 void amdgpu_device_fini(struct amdgpu_device
*adev
);
2076 int amdgpu_gpu_wait_for_idle(struct amdgpu_device
*adev
);
2078 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
2079 bool always_indirect
);
2080 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
2081 bool always_indirect
);
2082 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
);
2083 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
);
2085 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
);
2086 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
);
2091 extern const struct fence_ops amdgpu_fence_ops
;
2092 static inline struct amdgpu_fence
*to_amdgpu_fence(struct fence
*f
)
2094 struct amdgpu_fence
*__f
= container_of(f
, struct amdgpu_fence
, base
);
2096 if (__f
->base
.ops
== &amdgpu_fence_ops
)
2103 * Registers read & write functions.
2105 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2106 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2107 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2108 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2109 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2110 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2111 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2112 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2113 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2114 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2115 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2116 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2117 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2118 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2119 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2120 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2121 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2122 #define WREG32_P(reg, val, mask) \
2124 uint32_t tmp_ = RREG32(reg); \
2126 tmp_ |= ((val) & ~(mask)); \
2127 WREG32(reg, tmp_); \
2129 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2130 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2131 #define WREG32_PLL_P(reg, val, mask) \
2133 uint32_t tmp_ = RREG32_PLL(reg); \
2135 tmp_ |= ((val) & ~(mask)); \
2136 WREG32_PLL(reg, tmp_); \
2138 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2139 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2140 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2142 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2143 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2145 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2146 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2148 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2149 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2150 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2152 #define REG_GET_FIELD(value, reg, field) \
2153 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2158 #define RBIOS8(i) (adev->bios[i])
2159 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2160 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2165 static inline void amdgpu_ring_write(struct amdgpu_ring
*ring
, uint32_t v
)
2167 if (ring
->count_dw
<= 0)
2168 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2169 ring
->ring
[ring
->wptr
++] = v
;
2170 ring
->wptr
&= ring
->ptr_mask
;
2172 ring
->ring_free_dw
--;
2178 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2179 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2180 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2181 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2182 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2183 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2184 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2185 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2186 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2187 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2188 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2189 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2190 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2191 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2192 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2193 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2194 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2195 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2196 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2197 #define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2198 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2199 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2200 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2201 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2202 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2203 #define amdgpu_ring_emit_fence(r, addr, seq, write64bit) (r)->funcs->emit_fence((r), (addr), (seq), (write64bit))
2204 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2205 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2206 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2207 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2208 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2209 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2210 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2211 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2212 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2213 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2214 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2215 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2216 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2217 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2218 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2219 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2220 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2221 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2222 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2223 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2224 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2225 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2226 #define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2227 #define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2228 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2229 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2230 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2231 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2232 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2233 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2234 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2235 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2236 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2237 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2238 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2239 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2240 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2241 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2242 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2243 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2244 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2246 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2248 /* Common functions */
2249 int amdgpu_gpu_reset(struct amdgpu_device
*adev
);
2250 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
);
2251 bool amdgpu_card_posted(struct amdgpu_device
*adev
);
2252 void amdgpu_update_display_priority(struct amdgpu_device
*adev
);
2253 bool amdgpu_boot_test_post_card(struct amdgpu_device
*adev
);
2254 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
);
2255 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
2256 u32 ip_instance
, u32 ring
,
2257 struct amdgpu_ring
**out_ring
);
2258 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*rbo
, u32 domain
);
2259 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
);
2260 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
2262 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt
*ttm
);
2263 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
);
2264 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
2265 struct ttm_mem_reg
*mem
);
2266 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
);
2267 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
);
2268 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
);
2269 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
2270 const u32
*registers
,
2271 const u32 array_size
);
2273 bool amdgpu_device_is_px(struct drm_device
*dev
);
2275 #if defined(CONFIG_VGA_SWITCHEROO)
2276 void amdgpu_register_atpx_handler(void);
2277 void amdgpu_unregister_atpx_handler(void);
2279 static inline void amdgpu_register_atpx_handler(void) {}
2280 static inline void amdgpu_unregister_atpx_handler(void) {}
2286 extern const struct drm_ioctl_desc amdgpu_ioctls_kms
[];
2287 extern int amdgpu_max_kms_ioctl
;
2289 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
);
2290 int amdgpu_driver_unload_kms(struct drm_device
*dev
);
2291 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
);
2292 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
);
2293 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
2294 struct drm_file
*file_priv
);
2295 void amdgpu_driver_preclose_kms(struct drm_device
*dev
,
2296 struct drm_file
*file_priv
);
2297 int amdgpu_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
);
2298 int amdgpu_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
);
2299 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, int crtc
);
2300 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, int crtc
);
2301 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, int crtc
);
2302 int amdgpu_get_vblank_timestamp_kms(struct drm_device
*dev
, int crtc
,
2304 struct timeval
*vblank_time
,
2306 long amdgpu_kms_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2312 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
2313 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
2314 struct amdgpu_bo_list_entry
*amdgpu_vm_get_bos(struct amdgpu_device
*adev
,
2315 struct amdgpu_vm
*vm
,
2316 struct list_head
*head
);
2317 struct amdgpu_fence
*amdgpu_vm_grab_id(struct amdgpu_ring
*ring
,
2318 struct amdgpu_vm
*vm
);
2319 void amdgpu_vm_flush(struct amdgpu_ring
*ring
,
2320 struct amdgpu_vm
*vm
,
2321 struct amdgpu_fence
*updates
);
2322 void amdgpu_vm_fence(struct amdgpu_device
*adev
,
2323 struct amdgpu_vm
*vm
,
2324 struct amdgpu_fence
*fence
);
2325 uint64_t amdgpu_vm_map_gart(struct amdgpu_device
*adev
, uint64_t addr
);
2326 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
2327 struct amdgpu_vm
*vm
);
2328 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
2329 struct amdgpu_vm
*vm
);
2330 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
,
2331 struct amdgpu_vm
*vm
);
2332 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
2333 struct amdgpu_bo_va
*bo_va
,
2334 struct ttm_mem_reg
*mem
);
2335 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
2336 struct amdgpu_bo
*bo
);
2337 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
2338 struct amdgpu_bo
*bo
);
2339 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
2340 struct amdgpu_vm
*vm
,
2341 struct amdgpu_bo
*bo
);
2342 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
2343 struct amdgpu_bo_va
*bo_va
,
2344 uint64_t addr
, uint64_t offset
,
2345 uint64_t size
, uint32_t flags
);
2346 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
2347 struct amdgpu_bo_va
*bo_va
,
2349 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
2350 struct amdgpu_bo_va
*bo_va
);
2353 * functions used by amdgpu_encoder.c
2355 struct amdgpu_afmt_acr
{
2369 struct amdgpu_afmt_acr
amdgpu_afmt_acr(uint32_t clock
);
2372 #if defined(CONFIG_ACPI)
2373 int amdgpu_acpi_init(struct amdgpu_device
*adev
);
2374 void amdgpu_acpi_fini(struct amdgpu_device
*adev
);
2375 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device
*adev
);
2376 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device
*adev
,
2377 u8 perf_req
, bool advertise
);
2378 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device
*adev
);
2380 static inline int amdgpu_acpi_init(struct amdgpu_device
*adev
) { return 0; }
2381 static inline void amdgpu_acpi_fini(struct amdgpu_device
*adev
) { }
2384 struct amdgpu_bo_va_mapping
*
2385 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
2386 uint64_t addr
, struct amdgpu_bo
**bo
);
2388 #include "amdgpu_object.h"