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drm/amdgpu: add IP helpers for wait_for_idle and is_idle
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
56 #include "amdgpu_acp.h"
57
58 #include "gpu_scheduler.h"
59
60 /*
61 * Modules parameters.
62 */
63 extern int amdgpu_modeset;
64 extern int amdgpu_vram_limit;
65 extern int amdgpu_gart_size;
66 extern int amdgpu_benchmarking;
67 extern int amdgpu_testing;
68 extern int amdgpu_audio;
69 extern int amdgpu_disp_priority;
70 extern int amdgpu_hw_i2c;
71 extern int amdgpu_pcie_gen2;
72 extern int amdgpu_msi;
73 extern int amdgpu_lockup_timeout;
74 extern int amdgpu_dpm;
75 extern int amdgpu_smc_load_fw;
76 extern int amdgpu_aspm;
77 extern int amdgpu_runtime_pm;
78 extern unsigned amdgpu_ip_block_mask;
79 extern int amdgpu_bapm;
80 extern int amdgpu_deep_color;
81 extern int amdgpu_vm_size;
82 extern int amdgpu_vm_block_size;
83 extern int amdgpu_vm_fault_stop;
84 extern int amdgpu_vm_debug;
85 extern int amdgpu_sched_jobs;
86 extern int amdgpu_sched_hw_submission;
87 extern int amdgpu_powerplay;
88 extern int amdgpu_powercontainment;
89 extern unsigned amdgpu_pcie_gen_cap;
90 extern unsigned amdgpu_pcie_lane_cap;
91 extern unsigned amdgpu_cg_mask;
92 extern unsigned amdgpu_pg_mask;
93 extern char *amdgpu_disable_cu;
94
95 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
96 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
97 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
98 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
99 #define AMDGPU_IB_POOL_SIZE 16
100 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
101 #define AMDGPUFB_CONN_LIMIT 4
102 #define AMDGPU_BIOS_NUM_SCRATCH 8
103
104 /* max number of rings */
105 #define AMDGPU_MAX_RINGS 16
106 #define AMDGPU_MAX_GFX_RINGS 1
107 #define AMDGPU_MAX_COMPUTE_RINGS 8
108 #define AMDGPU_MAX_VCE_RINGS 2
109
110 /* max number of IP instances */
111 #define AMDGPU_MAX_SDMA_INSTANCES 2
112
113 /* hardcode that limit for now */
114 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
115
116 /* hard reset data */
117 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
118
119 /* reset flags */
120 #define AMDGPU_RESET_GFX (1 << 0)
121 #define AMDGPU_RESET_COMPUTE (1 << 1)
122 #define AMDGPU_RESET_DMA (1 << 2)
123 #define AMDGPU_RESET_CP (1 << 3)
124 #define AMDGPU_RESET_GRBM (1 << 4)
125 #define AMDGPU_RESET_DMA1 (1 << 5)
126 #define AMDGPU_RESET_RLC (1 << 6)
127 #define AMDGPU_RESET_SEM (1 << 7)
128 #define AMDGPU_RESET_IH (1 << 8)
129 #define AMDGPU_RESET_VMC (1 << 9)
130 #define AMDGPU_RESET_MC (1 << 10)
131 #define AMDGPU_RESET_DISPLAY (1 << 11)
132 #define AMDGPU_RESET_UVD (1 << 12)
133 #define AMDGPU_RESET_VCE (1 << 13)
134 #define AMDGPU_RESET_VCE1 (1 << 14)
135
136 /* GFX current status */
137 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
138 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
139 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
140 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
141 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
142
143 /* max cursor sizes (in pixels) */
144 #define CIK_CURSOR_WIDTH 128
145 #define CIK_CURSOR_HEIGHT 128
146
147 struct amdgpu_device;
148 struct amdgpu_ib;
149 struct amdgpu_vm;
150 struct amdgpu_ring;
151 struct amdgpu_cs_parser;
152 struct amdgpu_job;
153 struct amdgpu_irq_src;
154 struct amdgpu_fpriv;
155
156 enum amdgpu_cp_irq {
157 AMDGPU_CP_IRQ_GFX_EOP = 0,
158 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
159 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
160 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
162 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
163 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
164 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
166
167 AMDGPU_CP_IRQ_LAST
168 };
169
170 enum amdgpu_sdma_irq {
171 AMDGPU_SDMA_IRQ_TRAP0 = 0,
172 AMDGPU_SDMA_IRQ_TRAP1,
173
174 AMDGPU_SDMA_IRQ_LAST
175 };
176
177 enum amdgpu_thermal_irq {
178 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
179 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
180
181 AMDGPU_THERMAL_IRQ_LAST
182 };
183
184 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
185 enum amd_ip_block_type block_type,
186 enum amd_clockgating_state state);
187 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
188 enum amd_ip_block_type block_type,
189 enum amd_powergating_state state);
190 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
191 enum amd_ip_block_type block_type);
192 bool amdgpu_is_idle(struct amdgpu_device *adev,
193 enum amd_ip_block_type block_type);
194
195 struct amdgpu_ip_block_version {
196 enum amd_ip_block_type type;
197 u32 major;
198 u32 minor;
199 u32 rev;
200 const struct amd_ip_funcs *funcs;
201 };
202
203 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
204 enum amd_ip_block_type type,
205 u32 major, u32 minor);
206
207 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
208 struct amdgpu_device *adev,
209 enum amd_ip_block_type type);
210
211 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
212 struct amdgpu_buffer_funcs {
213 /* maximum bytes in a single operation */
214 uint32_t copy_max_bytes;
215
216 /* number of dw to reserve per operation */
217 unsigned copy_num_dw;
218
219 /* used for buffer migration */
220 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
221 /* src addr in bytes */
222 uint64_t src_offset,
223 /* dst addr in bytes */
224 uint64_t dst_offset,
225 /* number of byte to transfer */
226 uint32_t byte_count);
227
228 /* maximum bytes in a single operation */
229 uint32_t fill_max_bytes;
230
231 /* number of dw to reserve per operation */
232 unsigned fill_num_dw;
233
234 /* used for buffer clearing */
235 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
236 /* value to write to memory */
237 uint32_t src_data,
238 /* dst addr in bytes */
239 uint64_t dst_offset,
240 /* number of byte to fill */
241 uint32_t byte_count);
242 };
243
244 /* provided by hw blocks that can write ptes, e.g., sdma */
245 struct amdgpu_vm_pte_funcs {
246 /* copy pte entries from GART */
247 void (*copy_pte)(struct amdgpu_ib *ib,
248 uint64_t pe, uint64_t src,
249 unsigned count);
250 /* write pte one entry at a time with addr mapping */
251 void (*write_pte)(struct amdgpu_ib *ib,
252 const dma_addr_t *pages_addr, uint64_t pe,
253 uint64_t addr, unsigned count,
254 uint32_t incr, uint32_t flags);
255 /* for linear pte/pde updates without addr mapping */
256 void (*set_pte_pde)(struct amdgpu_ib *ib,
257 uint64_t pe,
258 uint64_t addr, unsigned count,
259 uint32_t incr, uint32_t flags);
260 };
261
262 /* provided by the gmc block */
263 struct amdgpu_gart_funcs {
264 /* flush the vm tlb via mmio */
265 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
266 uint32_t vmid);
267 /* write pte/pde updates using the cpu */
268 int (*set_pte_pde)(struct amdgpu_device *adev,
269 void *cpu_pt_addr, /* cpu addr of page table */
270 uint32_t gpu_page_idx, /* pte/pde to update */
271 uint64_t addr, /* addr to write into pte/pde */
272 uint32_t flags); /* access flags */
273 };
274
275 /* provided by the ih block */
276 struct amdgpu_ih_funcs {
277 /* ring read/write ptr handling, called from interrupt context */
278 u32 (*get_wptr)(struct amdgpu_device *adev);
279 void (*decode_iv)(struct amdgpu_device *adev,
280 struct amdgpu_iv_entry *entry);
281 void (*set_rptr)(struct amdgpu_device *adev);
282 };
283
284 /* provided by hw blocks that expose a ring buffer for commands */
285 struct amdgpu_ring_funcs {
286 /* ring read/write ptr handling */
287 u32 (*get_rptr)(struct amdgpu_ring *ring);
288 u32 (*get_wptr)(struct amdgpu_ring *ring);
289 void (*set_wptr)(struct amdgpu_ring *ring);
290 /* validating and patching of IBs */
291 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
292 /* command emit functions */
293 void (*emit_ib)(struct amdgpu_ring *ring,
294 struct amdgpu_ib *ib,
295 unsigned vm_id, bool ctx_switch);
296 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
297 uint64_t seq, unsigned flags);
298 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
299 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
300 uint64_t pd_addr);
301 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
302 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
303 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
304 uint32_t gds_base, uint32_t gds_size,
305 uint32_t gws_base, uint32_t gws_size,
306 uint32_t oa_base, uint32_t oa_size);
307 /* testing functions */
308 int (*test_ring)(struct amdgpu_ring *ring);
309 int (*test_ib)(struct amdgpu_ring *ring);
310 /* insert NOP packets */
311 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
312 /* pad the indirect buffer to the necessary number of dw */
313 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
314 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
315 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
316 };
317
318 /*
319 * BIOS.
320 */
321 bool amdgpu_get_bios(struct amdgpu_device *adev);
322 bool amdgpu_read_bios(struct amdgpu_device *adev);
323
324 /*
325 * Dummy page
326 */
327 struct amdgpu_dummy_page {
328 struct page *page;
329 dma_addr_t addr;
330 };
331 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
332 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
333
334
335 /*
336 * Clocks
337 */
338
339 #define AMDGPU_MAX_PPLL 3
340
341 struct amdgpu_clock {
342 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
343 struct amdgpu_pll spll;
344 struct amdgpu_pll mpll;
345 /* 10 Khz units */
346 uint32_t default_mclk;
347 uint32_t default_sclk;
348 uint32_t default_dispclk;
349 uint32_t current_dispclk;
350 uint32_t dp_extclk;
351 uint32_t max_pixel_clock;
352 };
353
354 /*
355 * Fences.
356 */
357 struct amdgpu_fence_driver {
358 uint64_t gpu_addr;
359 volatile uint32_t *cpu_addr;
360 /* sync_seq is protected by ring emission lock */
361 uint32_t sync_seq;
362 atomic_t last_seq;
363 bool initialized;
364 struct amdgpu_irq_src *irq_src;
365 unsigned irq_type;
366 struct timer_list fallback_timer;
367 unsigned num_fences_mask;
368 spinlock_t lock;
369 struct fence **fences;
370 };
371
372 /* some special values for the owner field */
373 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
374 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
375
376 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
377 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
378
379 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
380 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
381 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
382
383 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
384 unsigned num_hw_submission);
385 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
386 struct amdgpu_irq_src *irq_src,
387 unsigned irq_type);
388 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
389 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
390 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
391 void amdgpu_fence_process(struct amdgpu_ring *ring);
392 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
393 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
394
395 /*
396 * TTM.
397 */
398
399 #define AMDGPU_TTM_LRU_SIZE 20
400
401 struct amdgpu_mman_lru {
402 struct list_head *lru[TTM_NUM_MEM_TYPES];
403 struct list_head *swap_lru;
404 };
405
406 struct amdgpu_mman {
407 struct ttm_bo_global_ref bo_global_ref;
408 struct drm_global_reference mem_global_ref;
409 struct ttm_bo_device bdev;
410 bool mem_global_referenced;
411 bool initialized;
412
413 #if defined(CONFIG_DEBUG_FS)
414 struct dentry *vram;
415 struct dentry *gtt;
416 #endif
417
418 /* buffer handling */
419 const struct amdgpu_buffer_funcs *buffer_funcs;
420 struct amdgpu_ring *buffer_funcs_ring;
421 /* Scheduler entity for buffer moves */
422 struct amd_sched_entity entity;
423
424 /* custom LRU management */
425 struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE];
426 };
427
428 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
429 uint64_t src_offset,
430 uint64_t dst_offset,
431 uint32_t byte_count,
432 struct reservation_object *resv,
433 struct fence **fence);
434 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
435
436 struct amdgpu_bo_list_entry {
437 struct amdgpu_bo *robj;
438 struct ttm_validate_buffer tv;
439 struct amdgpu_bo_va *bo_va;
440 uint32_t priority;
441 struct page **user_pages;
442 int user_invalidated;
443 };
444
445 struct amdgpu_bo_va_mapping {
446 struct list_head list;
447 struct interval_tree_node it;
448 uint64_t offset;
449 uint32_t flags;
450 };
451
452 /* bo virtual addresses in a specific vm */
453 struct amdgpu_bo_va {
454 /* protected by bo being reserved */
455 struct list_head bo_list;
456 struct fence *last_pt_update;
457 unsigned ref_count;
458
459 /* protected by vm mutex and spinlock */
460 struct list_head vm_status;
461
462 /* mappings for this bo_va */
463 struct list_head invalids;
464 struct list_head valids;
465
466 /* constant after initialization */
467 struct amdgpu_vm *vm;
468 struct amdgpu_bo *bo;
469 };
470
471 #define AMDGPU_GEM_DOMAIN_MAX 0x3
472
473 struct amdgpu_bo {
474 /* Protected by gem.mutex */
475 struct list_head list;
476 /* Protected by tbo.reserved */
477 u32 prefered_domains;
478 u32 allowed_domains;
479 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
480 struct ttm_placement placement;
481 struct ttm_buffer_object tbo;
482 struct ttm_bo_kmap_obj kmap;
483 u64 flags;
484 unsigned pin_count;
485 void *kptr;
486 u64 tiling_flags;
487 u64 metadata_flags;
488 void *metadata;
489 u32 metadata_size;
490 /* list of all virtual address to which this bo
491 * is associated to
492 */
493 struct list_head va;
494 /* Constant after initialization */
495 struct amdgpu_device *adev;
496 struct drm_gem_object gem_base;
497 struct amdgpu_bo *parent;
498
499 struct ttm_bo_kmap_obj dma_buf_vmap;
500 struct amdgpu_mn *mn;
501 struct list_head mn_list;
502 };
503 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
504
505 void amdgpu_gem_object_free(struct drm_gem_object *obj);
506 int amdgpu_gem_object_open(struct drm_gem_object *obj,
507 struct drm_file *file_priv);
508 void amdgpu_gem_object_close(struct drm_gem_object *obj,
509 struct drm_file *file_priv);
510 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
511 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
512 struct drm_gem_object *
513 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
514 struct dma_buf_attachment *attach,
515 struct sg_table *sg);
516 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
517 struct drm_gem_object *gobj,
518 int flags);
519 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
520 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
521 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
522 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
523 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
524 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
525
526 /* sub-allocation manager, it has to be protected by another lock.
527 * By conception this is an helper for other part of the driver
528 * like the indirect buffer or semaphore, which both have their
529 * locking.
530 *
531 * Principe is simple, we keep a list of sub allocation in offset
532 * order (first entry has offset == 0, last entry has the highest
533 * offset).
534 *
535 * When allocating new object we first check if there is room at
536 * the end total_size - (last_object_offset + last_object_size) >=
537 * alloc_size. If so we allocate new object there.
538 *
539 * When there is not enough room at the end, we start waiting for
540 * each sub object until we reach object_offset+object_size >=
541 * alloc_size, this object then become the sub object we return.
542 *
543 * Alignment can't be bigger than page size.
544 *
545 * Hole are not considered for allocation to keep things simple.
546 * Assumption is that there won't be hole (all object on same
547 * alignment).
548 */
549
550 #define AMDGPU_SA_NUM_FENCE_LISTS 32
551
552 struct amdgpu_sa_manager {
553 wait_queue_head_t wq;
554 struct amdgpu_bo *bo;
555 struct list_head *hole;
556 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
557 struct list_head olist;
558 unsigned size;
559 uint64_t gpu_addr;
560 void *cpu_ptr;
561 uint32_t domain;
562 uint32_t align;
563 };
564
565 /* sub-allocation buffer */
566 struct amdgpu_sa_bo {
567 struct list_head olist;
568 struct list_head flist;
569 struct amdgpu_sa_manager *manager;
570 unsigned soffset;
571 unsigned eoffset;
572 struct fence *fence;
573 };
574
575 /*
576 * GEM objects.
577 */
578 void amdgpu_gem_force_release(struct amdgpu_device *adev);
579 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
580 int alignment, u32 initial_domain,
581 u64 flags, bool kernel,
582 struct drm_gem_object **obj);
583
584 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
585 struct drm_device *dev,
586 struct drm_mode_create_dumb *args);
587 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
588 struct drm_device *dev,
589 uint32_t handle, uint64_t *offset_p);
590 /*
591 * Synchronization
592 */
593 struct amdgpu_sync {
594 DECLARE_HASHTABLE(fences, 4);
595 struct fence *last_vm_update;
596 };
597
598 void amdgpu_sync_create(struct amdgpu_sync *sync);
599 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
600 struct fence *f);
601 int amdgpu_sync_resv(struct amdgpu_device *adev,
602 struct amdgpu_sync *sync,
603 struct reservation_object *resv,
604 void *owner);
605 struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
606 struct amdgpu_ring *ring);
607 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
608 void amdgpu_sync_free(struct amdgpu_sync *sync);
609 int amdgpu_sync_init(void);
610 void amdgpu_sync_fini(void);
611 int amdgpu_fence_slab_init(void);
612 void amdgpu_fence_slab_fini(void);
613
614 /*
615 * GART structures, functions & helpers
616 */
617 struct amdgpu_mc;
618
619 #define AMDGPU_GPU_PAGE_SIZE 4096
620 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
621 #define AMDGPU_GPU_PAGE_SHIFT 12
622 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
623
624 struct amdgpu_gart {
625 dma_addr_t table_addr;
626 struct amdgpu_bo *robj;
627 void *ptr;
628 unsigned num_gpu_pages;
629 unsigned num_cpu_pages;
630 unsigned table_size;
631 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
632 struct page **pages;
633 #endif
634 bool ready;
635 const struct amdgpu_gart_funcs *gart_funcs;
636 };
637
638 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
639 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
640 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
641 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
642 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
643 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
644 int amdgpu_gart_init(struct amdgpu_device *adev);
645 void amdgpu_gart_fini(struct amdgpu_device *adev);
646 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
647 int pages);
648 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
649 int pages, struct page **pagelist,
650 dma_addr_t *dma_addr, uint32_t flags);
651
652 /*
653 * GPU MC structures, functions & helpers
654 */
655 struct amdgpu_mc {
656 resource_size_t aper_size;
657 resource_size_t aper_base;
658 resource_size_t agp_base;
659 /* for some chips with <= 32MB we need to lie
660 * about vram size near mc fb location */
661 u64 mc_vram_size;
662 u64 visible_vram_size;
663 u64 gtt_size;
664 u64 gtt_start;
665 u64 gtt_end;
666 u64 vram_start;
667 u64 vram_end;
668 unsigned vram_width;
669 u64 real_vram_size;
670 int vram_mtrr;
671 u64 gtt_base_align;
672 u64 mc_mask;
673 const struct firmware *fw; /* MC firmware */
674 uint32_t fw_version;
675 struct amdgpu_irq_src vm_fault;
676 uint32_t vram_type;
677 };
678
679 /*
680 * GPU doorbell structures, functions & helpers
681 */
682 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
683 {
684 AMDGPU_DOORBELL_KIQ = 0x000,
685 AMDGPU_DOORBELL_HIQ = 0x001,
686 AMDGPU_DOORBELL_DIQ = 0x002,
687 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
688 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
689 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
690 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
691 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
692 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
693 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
694 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
695 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
696 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
697 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
698 AMDGPU_DOORBELL_IH = 0x1E8,
699 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
700 AMDGPU_DOORBELL_INVALID = 0xFFFF
701 } AMDGPU_DOORBELL_ASSIGNMENT;
702
703 struct amdgpu_doorbell {
704 /* doorbell mmio */
705 resource_size_t base;
706 resource_size_t size;
707 u32 __iomem *ptr;
708 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
709 };
710
711 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
712 phys_addr_t *aperture_base,
713 size_t *aperture_size,
714 size_t *start_offset);
715
716 /*
717 * IRQS.
718 */
719
720 struct amdgpu_flip_work {
721 struct work_struct flip_work;
722 struct work_struct unpin_work;
723 struct amdgpu_device *adev;
724 int crtc_id;
725 uint64_t base;
726 struct drm_pending_vblank_event *event;
727 struct amdgpu_bo *old_rbo;
728 struct fence *excl;
729 unsigned shared_count;
730 struct fence **shared;
731 struct fence_cb cb;
732 bool async;
733 };
734
735
736 /*
737 * CP & rings.
738 */
739
740 struct amdgpu_ib {
741 struct amdgpu_sa_bo *sa_bo;
742 uint32_t length_dw;
743 uint64_t gpu_addr;
744 uint32_t *ptr;
745 uint32_t flags;
746 };
747
748 enum amdgpu_ring_type {
749 AMDGPU_RING_TYPE_GFX,
750 AMDGPU_RING_TYPE_COMPUTE,
751 AMDGPU_RING_TYPE_SDMA,
752 AMDGPU_RING_TYPE_UVD,
753 AMDGPU_RING_TYPE_VCE
754 };
755
756 extern const struct amd_sched_backend_ops amdgpu_sched_ops;
757
758 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
759 struct amdgpu_job **job, struct amdgpu_vm *vm);
760 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
761 struct amdgpu_job **job);
762
763 void amdgpu_job_free(struct amdgpu_job *job);
764 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
765 struct amd_sched_entity *entity, void *owner,
766 struct fence **f);
767
768 struct amdgpu_ring {
769 struct amdgpu_device *adev;
770 const struct amdgpu_ring_funcs *funcs;
771 struct amdgpu_fence_driver fence_drv;
772 struct amd_gpu_scheduler sched;
773
774 spinlock_t fence_lock;
775 struct amdgpu_bo *ring_obj;
776 volatile uint32_t *ring;
777 unsigned rptr_offs;
778 u64 next_rptr_gpu_addr;
779 volatile u32 *next_rptr_cpu_addr;
780 unsigned wptr;
781 unsigned wptr_old;
782 unsigned ring_size;
783 unsigned max_dw;
784 int count_dw;
785 uint64_t gpu_addr;
786 uint32_t align_mask;
787 uint32_t ptr_mask;
788 bool ready;
789 u32 nop;
790 u32 idx;
791 u32 me;
792 u32 pipe;
793 u32 queue;
794 struct amdgpu_bo *mqd_obj;
795 u32 doorbell_index;
796 bool use_doorbell;
797 unsigned wptr_offs;
798 unsigned next_rptr_offs;
799 unsigned fence_offs;
800 uint64_t current_ctx;
801 enum amdgpu_ring_type type;
802 char name[16];
803 unsigned cond_exe_offs;
804 u64 cond_exe_gpu_addr;
805 volatile u32 *cond_exe_cpu_addr;
806 #if defined(CONFIG_DEBUG_FS)
807 struct dentry *ent;
808 #endif
809 };
810
811 /*
812 * VM
813 */
814
815 /* maximum number of VMIDs */
816 #define AMDGPU_NUM_VM 16
817
818 /* number of entries in page table */
819 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
820
821 /* PTBs (Page Table Blocks) need to be aligned to 32K */
822 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
823 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
824 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
825
826 #define AMDGPU_PTE_VALID (1 << 0)
827 #define AMDGPU_PTE_SYSTEM (1 << 1)
828 #define AMDGPU_PTE_SNOOPED (1 << 2)
829
830 /* VI only */
831 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
832
833 #define AMDGPU_PTE_READABLE (1 << 5)
834 #define AMDGPU_PTE_WRITEABLE (1 << 6)
835
836 /* PTE (Page Table Entry) fragment field for different page sizes */
837 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
838 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
839 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
840
841 /* How to programm VM fault handling */
842 #define AMDGPU_VM_FAULT_STOP_NEVER 0
843 #define AMDGPU_VM_FAULT_STOP_FIRST 1
844 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
845
846 struct amdgpu_vm_pt {
847 struct amdgpu_bo_list_entry entry;
848 uint64_t addr;
849 };
850
851 struct amdgpu_vm {
852 /* tree of virtual addresses mapped */
853 struct rb_root va;
854
855 /* protecting invalidated */
856 spinlock_t status_lock;
857
858 /* BOs moved, but not yet updated in the PT */
859 struct list_head invalidated;
860
861 /* BOs cleared in the PT because of a move */
862 struct list_head cleared;
863
864 /* BO mappings freed, but not yet updated in the PT */
865 struct list_head freed;
866
867 /* contains the page directory */
868 struct amdgpu_bo *page_directory;
869 unsigned max_pde_used;
870 struct fence *page_directory_fence;
871 uint64_t last_eviction_counter;
872
873 /* array of page tables, one for each page directory entry */
874 struct amdgpu_vm_pt *page_tables;
875
876 /* for id and flush management per ring */
877 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
878
879 /* protecting freed */
880 spinlock_t freed_lock;
881
882 /* Scheduler entity for page table updates */
883 struct amd_sched_entity entity;
884
885 /* client id */
886 u64 client_id;
887 };
888
889 struct amdgpu_vm_id {
890 struct list_head list;
891 struct fence *first;
892 struct amdgpu_sync active;
893 struct fence *last_flush;
894 atomic64_t owner;
895
896 uint64_t pd_gpu_addr;
897 /* last flushed PD/PT update */
898 struct fence *flushed_updates;
899
900 uint32_t gds_base;
901 uint32_t gds_size;
902 uint32_t gws_base;
903 uint32_t gws_size;
904 uint32_t oa_base;
905 uint32_t oa_size;
906 };
907
908 struct amdgpu_vm_manager {
909 /* Handling of VMIDs */
910 struct mutex lock;
911 unsigned num_ids;
912 struct list_head ids_lru;
913 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
914
915 /* Handling of VM fences */
916 u64 fence_context;
917 unsigned seqno[AMDGPU_MAX_RINGS];
918
919 uint32_t max_pfn;
920 /* vram base address for page table entry */
921 u64 vram_base_offset;
922 /* is vm enabled? */
923 bool enabled;
924 /* vm pte handling */
925 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
926 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
927 unsigned vm_pte_num_rings;
928 atomic_t vm_pte_next_ring;
929 /* client id counter */
930 atomic64_t client_counter;
931 };
932
933 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
934 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
935 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
936 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
937 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
938 struct list_head *validated,
939 struct amdgpu_bo_list_entry *entry);
940 void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
941 struct list_head *duplicates);
942 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
943 struct amdgpu_vm *vm);
944 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
945 struct amdgpu_sync *sync, struct fence *fence,
946 unsigned *vm_id, uint64_t *vm_pd_addr);
947 int amdgpu_vm_flush(struct amdgpu_ring *ring,
948 unsigned vm_id, uint64_t pd_addr,
949 uint32_t gds_base, uint32_t gds_size,
950 uint32_t gws_base, uint32_t gws_size,
951 uint32_t oa_base, uint32_t oa_size);
952 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
953 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
954 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
955 struct amdgpu_vm *vm);
956 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
957 struct amdgpu_vm *vm);
958 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
959 struct amdgpu_sync *sync);
960 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
961 struct amdgpu_bo_va *bo_va,
962 struct ttm_mem_reg *mem);
963 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
964 struct amdgpu_bo *bo);
965 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
966 struct amdgpu_bo *bo);
967 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
968 struct amdgpu_vm *vm,
969 struct amdgpu_bo *bo);
970 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
971 struct amdgpu_bo_va *bo_va,
972 uint64_t addr, uint64_t offset,
973 uint64_t size, uint32_t flags);
974 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
975 struct amdgpu_bo_va *bo_va,
976 uint64_t addr);
977 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
978 struct amdgpu_bo_va *bo_va);
979
980 /*
981 * context related structures
982 */
983
984 struct amdgpu_ctx_ring {
985 uint64_t sequence;
986 struct fence **fences;
987 struct amd_sched_entity entity;
988 };
989
990 struct amdgpu_ctx {
991 struct kref refcount;
992 struct amdgpu_device *adev;
993 unsigned reset_counter;
994 spinlock_t ring_lock;
995 struct fence **fences;
996 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
997 };
998
999 struct amdgpu_ctx_mgr {
1000 struct amdgpu_device *adev;
1001 struct mutex lock;
1002 /* protected by lock */
1003 struct idr ctx_handles;
1004 };
1005
1006 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1007 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1008
1009 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1010 struct fence *fence);
1011 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1012 struct amdgpu_ring *ring, uint64_t seq);
1013
1014 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1015 struct drm_file *filp);
1016
1017 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1018 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1019
1020 /*
1021 * file private structure
1022 */
1023
1024 struct amdgpu_fpriv {
1025 struct amdgpu_vm vm;
1026 struct mutex bo_list_lock;
1027 struct idr bo_list_handles;
1028 struct amdgpu_ctx_mgr ctx_mgr;
1029 };
1030
1031 /*
1032 * residency list
1033 */
1034
1035 struct amdgpu_bo_list {
1036 struct mutex lock;
1037 struct amdgpu_bo *gds_obj;
1038 struct amdgpu_bo *gws_obj;
1039 struct amdgpu_bo *oa_obj;
1040 unsigned first_userptr;
1041 unsigned num_entries;
1042 struct amdgpu_bo_list_entry *array;
1043 };
1044
1045 struct amdgpu_bo_list *
1046 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1047 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1048 struct list_head *validated);
1049 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1050 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1051
1052 /*
1053 * GFX stuff
1054 */
1055 #include "clearstate_defs.h"
1056
1057 struct amdgpu_rlc_funcs {
1058 void (*enter_safe_mode)(struct amdgpu_device *adev);
1059 void (*exit_safe_mode)(struct amdgpu_device *adev);
1060 };
1061
1062 struct amdgpu_rlc {
1063 /* for power gating */
1064 struct amdgpu_bo *save_restore_obj;
1065 uint64_t save_restore_gpu_addr;
1066 volatile uint32_t *sr_ptr;
1067 const u32 *reg_list;
1068 u32 reg_list_size;
1069 /* for clear state */
1070 struct amdgpu_bo *clear_state_obj;
1071 uint64_t clear_state_gpu_addr;
1072 volatile uint32_t *cs_ptr;
1073 const struct cs_section_def *cs_data;
1074 u32 clear_state_size;
1075 /* for cp tables */
1076 struct amdgpu_bo *cp_table_obj;
1077 uint64_t cp_table_gpu_addr;
1078 volatile uint32_t *cp_table_ptr;
1079 u32 cp_table_size;
1080
1081 /* safe mode for updating CG/PG state */
1082 bool in_safe_mode;
1083 const struct amdgpu_rlc_funcs *funcs;
1084
1085 /* for firmware data */
1086 u32 save_and_restore_offset;
1087 u32 clear_state_descriptor_offset;
1088 u32 avail_scratch_ram_locations;
1089 u32 reg_restore_list_size;
1090 u32 reg_list_format_start;
1091 u32 reg_list_format_separate_start;
1092 u32 starting_offsets_start;
1093 u32 reg_list_format_size_bytes;
1094 u32 reg_list_size_bytes;
1095
1096 u32 *register_list_format;
1097 u32 *register_restore;
1098 };
1099
1100 struct amdgpu_mec {
1101 struct amdgpu_bo *hpd_eop_obj;
1102 u64 hpd_eop_gpu_addr;
1103 u32 num_pipe;
1104 u32 num_mec;
1105 u32 num_queue;
1106 };
1107
1108 /*
1109 * GPU scratch registers structures, functions & helpers
1110 */
1111 struct amdgpu_scratch {
1112 unsigned num_reg;
1113 uint32_t reg_base;
1114 bool free[32];
1115 uint32_t reg[32];
1116 };
1117
1118 /*
1119 * GFX configurations
1120 */
1121 struct amdgpu_gca_config {
1122 unsigned max_shader_engines;
1123 unsigned max_tile_pipes;
1124 unsigned max_cu_per_sh;
1125 unsigned max_sh_per_se;
1126 unsigned max_backends_per_se;
1127 unsigned max_texture_channel_caches;
1128 unsigned max_gprs;
1129 unsigned max_gs_threads;
1130 unsigned max_hw_contexts;
1131 unsigned sc_prim_fifo_size_frontend;
1132 unsigned sc_prim_fifo_size_backend;
1133 unsigned sc_hiz_tile_fifo_size;
1134 unsigned sc_earlyz_tile_fifo_size;
1135
1136 unsigned num_tile_pipes;
1137 unsigned backend_enable_mask;
1138 unsigned mem_max_burst_length_bytes;
1139 unsigned mem_row_size_in_kb;
1140 unsigned shader_engine_tile_size;
1141 unsigned num_gpus;
1142 unsigned multi_gpu_tile_size;
1143 unsigned mc_arb_ramcfg;
1144 unsigned gb_addr_config;
1145 unsigned num_rbs;
1146
1147 uint32_t tile_mode_array[32];
1148 uint32_t macrotile_mode_array[16];
1149 };
1150
1151 struct amdgpu_cu_info {
1152 uint32_t number; /* total active CU number */
1153 uint32_t ao_cu_mask;
1154 uint32_t bitmap[4][4];
1155 };
1156
1157 struct amdgpu_gfx_funcs {
1158 /* get the gpu clock counter */
1159 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1160 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
1161 };
1162
1163 struct amdgpu_gfx {
1164 struct mutex gpu_clock_mutex;
1165 struct amdgpu_gca_config config;
1166 struct amdgpu_rlc rlc;
1167 struct amdgpu_mec mec;
1168 struct amdgpu_scratch scratch;
1169 const struct firmware *me_fw; /* ME firmware */
1170 uint32_t me_fw_version;
1171 const struct firmware *pfp_fw; /* PFP firmware */
1172 uint32_t pfp_fw_version;
1173 const struct firmware *ce_fw; /* CE firmware */
1174 uint32_t ce_fw_version;
1175 const struct firmware *rlc_fw; /* RLC firmware */
1176 uint32_t rlc_fw_version;
1177 const struct firmware *mec_fw; /* MEC firmware */
1178 uint32_t mec_fw_version;
1179 const struct firmware *mec2_fw; /* MEC2 firmware */
1180 uint32_t mec2_fw_version;
1181 uint32_t me_feature_version;
1182 uint32_t ce_feature_version;
1183 uint32_t pfp_feature_version;
1184 uint32_t rlc_feature_version;
1185 uint32_t mec_feature_version;
1186 uint32_t mec2_feature_version;
1187 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1188 unsigned num_gfx_rings;
1189 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1190 unsigned num_compute_rings;
1191 struct amdgpu_irq_src eop_irq;
1192 struct amdgpu_irq_src priv_reg_irq;
1193 struct amdgpu_irq_src priv_inst_irq;
1194 /* gfx status */
1195 uint32_t gfx_current_status;
1196 /* ce ram size*/
1197 unsigned ce_ram_size;
1198 struct amdgpu_cu_info cu_info;
1199 const struct amdgpu_gfx_funcs *funcs;
1200 };
1201
1202 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1203 unsigned size, struct amdgpu_ib *ib);
1204 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1205 struct fence *f);
1206 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
1207 struct amdgpu_ib *ib, struct fence *last_vm_update,
1208 struct amdgpu_job *job, struct fence **f);
1209 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1210 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1211 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1212 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1213 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1214 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
1215 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1216 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1217 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1218 uint32_t **data);
1219 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1220 unsigned size, uint32_t *data);
1221 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1222 unsigned ring_size, u32 nop, u32 align_mask,
1223 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1224 enum amdgpu_ring_type ring_type);
1225 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1226
1227 /*
1228 * CS.
1229 */
1230 struct amdgpu_cs_chunk {
1231 uint32_t chunk_id;
1232 uint32_t length_dw;
1233 void *kdata;
1234 };
1235
1236 struct amdgpu_cs_parser {
1237 struct amdgpu_device *adev;
1238 struct drm_file *filp;
1239 struct amdgpu_ctx *ctx;
1240
1241 /* chunks */
1242 unsigned nchunks;
1243 struct amdgpu_cs_chunk *chunks;
1244
1245 /* scheduler job object */
1246 struct amdgpu_job *job;
1247
1248 /* buffer objects */
1249 struct ww_acquire_ctx ticket;
1250 struct amdgpu_bo_list *bo_list;
1251 struct amdgpu_bo_list_entry vm_pd;
1252 struct list_head validated;
1253 struct fence *fence;
1254 uint64_t bytes_moved_threshold;
1255 uint64_t bytes_moved;
1256
1257 /* user fence */
1258 struct amdgpu_bo_list_entry uf_entry;
1259 };
1260
1261 struct amdgpu_job {
1262 struct amd_sched_job base;
1263 struct amdgpu_device *adev;
1264 struct amdgpu_vm *vm;
1265 struct amdgpu_ring *ring;
1266 struct amdgpu_sync sync;
1267 struct amdgpu_ib *ibs;
1268 struct fence *fence; /* the hw fence */
1269 uint32_t num_ibs;
1270 void *owner;
1271 uint64_t ctx;
1272 unsigned vm_id;
1273 uint64_t vm_pd_addr;
1274 uint32_t gds_base, gds_size;
1275 uint32_t gws_base, gws_size;
1276 uint32_t oa_base, oa_size;
1277
1278 /* user fence handling */
1279 struct amdgpu_bo *uf_bo;
1280 uint32_t uf_offset;
1281 uint64_t uf_sequence;
1282
1283 };
1284 #define to_amdgpu_job(sched_job) \
1285 container_of((sched_job), struct amdgpu_job, base)
1286
1287 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1288 uint32_t ib_idx, int idx)
1289 {
1290 return p->job->ibs[ib_idx].ptr[idx];
1291 }
1292
1293 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1294 uint32_t ib_idx, int idx,
1295 uint32_t value)
1296 {
1297 p->job->ibs[ib_idx].ptr[idx] = value;
1298 }
1299
1300 /*
1301 * Writeback
1302 */
1303 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1304
1305 struct amdgpu_wb {
1306 struct amdgpu_bo *wb_obj;
1307 volatile uint32_t *wb;
1308 uint64_t gpu_addr;
1309 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1310 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1311 };
1312
1313 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1314 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1315
1316
1317
1318 enum amdgpu_int_thermal_type {
1319 THERMAL_TYPE_NONE,
1320 THERMAL_TYPE_EXTERNAL,
1321 THERMAL_TYPE_EXTERNAL_GPIO,
1322 THERMAL_TYPE_RV6XX,
1323 THERMAL_TYPE_RV770,
1324 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1325 THERMAL_TYPE_EVERGREEN,
1326 THERMAL_TYPE_SUMO,
1327 THERMAL_TYPE_NI,
1328 THERMAL_TYPE_SI,
1329 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1330 THERMAL_TYPE_CI,
1331 THERMAL_TYPE_KV,
1332 };
1333
1334 enum amdgpu_dpm_auto_throttle_src {
1335 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1336 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1337 };
1338
1339 enum amdgpu_dpm_event_src {
1340 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1341 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1342 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1343 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1344 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1345 };
1346
1347 #define AMDGPU_MAX_VCE_LEVELS 6
1348
1349 enum amdgpu_vce_level {
1350 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1351 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1352 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1353 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1354 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1355 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1356 };
1357
1358 struct amdgpu_ps {
1359 u32 caps; /* vbios flags */
1360 u32 class; /* vbios flags */
1361 u32 class2; /* vbios flags */
1362 /* UVD clocks */
1363 u32 vclk;
1364 u32 dclk;
1365 /* VCE clocks */
1366 u32 evclk;
1367 u32 ecclk;
1368 bool vce_active;
1369 enum amdgpu_vce_level vce_level;
1370 /* asic priv */
1371 void *ps_priv;
1372 };
1373
1374 struct amdgpu_dpm_thermal {
1375 /* thermal interrupt work */
1376 struct work_struct work;
1377 /* low temperature threshold */
1378 int min_temp;
1379 /* high temperature threshold */
1380 int max_temp;
1381 /* was last interrupt low to high or high to low */
1382 bool high_to_low;
1383 /* interrupt source */
1384 struct amdgpu_irq_src irq;
1385 };
1386
1387 enum amdgpu_clk_action
1388 {
1389 AMDGPU_SCLK_UP = 1,
1390 AMDGPU_SCLK_DOWN
1391 };
1392
1393 struct amdgpu_blacklist_clocks
1394 {
1395 u32 sclk;
1396 u32 mclk;
1397 enum amdgpu_clk_action action;
1398 };
1399
1400 struct amdgpu_clock_and_voltage_limits {
1401 u32 sclk;
1402 u32 mclk;
1403 u16 vddc;
1404 u16 vddci;
1405 };
1406
1407 struct amdgpu_clock_array {
1408 u32 count;
1409 u32 *values;
1410 };
1411
1412 struct amdgpu_clock_voltage_dependency_entry {
1413 u32 clk;
1414 u16 v;
1415 };
1416
1417 struct amdgpu_clock_voltage_dependency_table {
1418 u32 count;
1419 struct amdgpu_clock_voltage_dependency_entry *entries;
1420 };
1421
1422 union amdgpu_cac_leakage_entry {
1423 struct {
1424 u16 vddc;
1425 u32 leakage;
1426 };
1427 struct {
1428 u16 vddc1;
1429 u16 vddc2;
1430 u16 vddc3;
1431 };
1432 };
1433
1434 struct amdgpu_cac_leakage_table {
1435 u32 count;
1436 union amdgpu_cac_leakage_entry *entries;
1437 };
1438
1439 struct amdgpu_phase_shedding_limits_entry {
1440 u16 voltage;
1441 u32 sclk;
1442 u32 mclk;
1443 };
1444
1445 struct amdgpu_phase_shedding_limits_table {
1446 u32 count;
1447 struct amdgpu_phase_shedding_limits_entry *entries;
1448 };
1449
1450 struct amdgpu_uvd_clock_voltage_dependency_entry {
1451 u32 vclk;
1452 u32 dclk;
1453 u16 v;
1454 };
1455
1456 struct amdgpu_uvd_clock_voltage_dependency_table {
1457 u8 count;
1458 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1459 };
1460
1461 struct amdgpu_vce_clock_voltage_dependency_entry {
1462 u32 ecclk;
1463 u32 evclk;
1464 u16 v;
1465 };
1466
1467 struct amdgpu_vce_clock_voltage_dependency_table {
1468 u8 count;
1469 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1470 };
1471
1472 struct amdgpu_ppm_table {
1473 u8 ppm_design;
1474 u16 cpu_core_number;
1475 u32 platform_tdp;
1476 u32 small_ac_platform_tdp;
1477 u32 platform_tdc;
1478 u32 small_ac_platform_tdc;
1479 u32 apu_tdp;
1480 u32 dgpu_tdp;
1481 u32 dgpu_ulv_power;
1482 u32 tj_max;
1483 };
1484
1485 struct amdgpu_cac_tdp_table {
1486 u16 tdp;
1487 u16 configurable_tdp;
1488 u16 tdc;
1489 u16 battery_power_limit;
1490 u16 small_power_limit;
1491 u16 low_cac_leakage;
1492 u16 high_cac_leakage;
1493 u16 maximum_power_delivery_limit;
1494 };
1495
1496 struct amdgpu_dpm_dynamic_state {
1497 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1498 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1499 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1500 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1501 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1502 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1503 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1504 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1505 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1506 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1507 struct amdgpu_clock_array valid_sclk_values;
1508 struct amdgpu_clock_array valid_mclk_values;
1509 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1510 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1511 u32 mclk_sclk_ratio;
1512 u32 sclk_mclk_delta;
1513 u16 vddc_vddci_delta;
1514 u16 min_vddc_for_pcie_gen2;
1515 struct amdgpu_cac_leakage_table cac_leakage_table;
1516 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1517 struct amdgpu_ppm_table *ppm_table;
1518 struct amdgpu_cac_tdp_table *cac_tdp_table;
1519 };
1520
1521 struct amdgpu_dpm_fan {
1522 u16 t_min;
1523 u16 t_med;
1524 u16 t_high;
1525 u16 pwm_min;
1526 u16 pwm_med;
1527 u16 pwm_high;
1528 u8 t_hyst;
1529 u32 cycle_delay;
1530 u16 t_max;
1531 u8 control_mode;
1532 u16 default_max_fan_pwm;
1533 u16 default_fan_output_sensitivity;
1534 u16 fan_output_sensitivity;
1535 bool ucode_fan_control;
1536 };
1537
1538 enum amdgpu_pcie_gen {
1539 AMDGPU_PCIE_GEN1 = 0,
1540 AMDGPU_PCIE_GEN2 = 1,
1541 AMDGPU_PCIE_GEN3 = 2,
1542 AMDGPU_PCIE_GEN_INVALID = 0xffff
1543 };
1544
1545 enum amdgpu_dpm_forced_level {
1546 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1547 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1548 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1549 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
1550 };
1551
1552 struct amdgpu_vce_state {
1553 /* vce clocks */
1554 u32 evclk;
1555 u32 ecclk;
1556 /* gpu clocks */
1557 u32 sclk;
1558 u32 mclk;
1559 u8 clk_idx;
1560 u8 pstate;
1561 };
1562
1563 struct amdgpu_dpm_funcs {
1564 int (*get_temperature)(struct amdgpu_device *adev);
1565 int (*pre_set_power_state)(struct amdgpu_device *adev);
1566 int (*set_power_state)(struct amdgpu_device *adev);
1567 void (*post_set_power_state)(struct amdgpu_device *adev);
1568 void (*display_configuration_changed)(struct amdgpu_device *adev);
1569 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1570 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1571 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1572 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1573 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1574 bool (*vblank_too_short)(struct amdgpu_device *adev);
1575 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1576 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1577 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1578 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1579 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1580 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1581 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1582 int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
1583 int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
1584 int (*get_sclk_od)(struct amdgpu_device *adev);
1585 int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
1586 int (*get_mclk_od)(struct amdgpu_device *adev);
1587 int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
1588 };
1589
1590 struct amdgpu_dpm {
1591 struct amdgpu_ps *ps;
1592 /* number of valid power states */
1593 int num_ps;
1594 /* current power state that is active */
1595 struct amdgpu_ps *current_ps;
1596 /* requested power state */
1597 struct amdgpu_ps *requested_ps;
1598 /* boot up power state */
1599 struct amdgpu_ps *boot_ps;
1600 /* default uvd power state */
1601 struct amdgpu_ps *uvd_ps;
1602 /* vce requirements */
1603 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1604 enum amdgpu_vce_level vce_level;
1605 enum amd_pm_state_type state;
1606 enum amd_pm_state_type user_state;
1607 u32 platform_caps;
1608 u32 voltage_response_time;
1609 u32 backbias_response_time;
1610 void *priv;
1611 u32 new_active_crtcs;
1612 int new_active_crtc_count;
1613 u32 current_active_crtcs;
1614 int current_active_crtc_count;
1615 struct amdgpu_dpm_dynamic_state dyn_state;
1616 struct amdgpu_dpm_fan fan;
1617 u32 tdp_limit;
1618 u32 near_tdp_limit;
1619 u32 near_tdp_limit_adjusted;
1620 u32 sq_ramping_threshold;
1621 u32 cac_leakage;
1622 u16 tdp_od_limit;
1623 u32 tdp_adjustment;
1624 u16 load_line_slope;
1625 bool power_control;
1626 bool ac_power;
1627 /* special states active */
1628 bool thermal_active;
1629 bool uvd_active;
1630 bool vce_active;
1631 /* thermal handling */
1632 struct amdgpu_dpm_thermal thermal;
1633 /* forced levels */
1634 enum amdgpu_dpm_forced_level forced_level;
1635 };
1636
1637 struct amdgpu_pm {
1638 struct mutex mutex;
1639 u32 current_sclk;
1640 u32 current_mclk;
1641 u32 default_sclk;
1642 u32 default_mclk;
1643 struct amdgpu_i2c_chan *i2c_bus;
1644 /* internal thermal controller on rv6xx+ */
1645 enum amdgpu_int_thermal_type int_thermal_type;
1646 struct device *int_hwmon_dev;
1647 /* fan control parameters */
1648 bool no_fan;
1649 u8 fan_pulses_per_revolution;
1650 u8 fan_min_rpm;
1651 u8 fan_max_rpm;
1652 /* dpm */
1653 bool dpm_enabled;
1654 bool sysfs_initialized;
1655 struct amdgpu_dpm dpm;
1656 const struct firmware *fw; /* SMC firmware */
1657 uint32_t fw_version;
1658 const struct amdgpu_dpm_funcs *funcs;
1659 uint32_t pcie_gen_mask;
1660 uint32_t pcie_mlw_mask;
1661 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
1662 };
1663
1664 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1665
1666 /*
1667 * UVD
1668 */
1669 #define AMDGPU_DEFAULT_UVD_HANDLES 10
1670 #define AMDGPU_MAX_UVD_HANDLES 40
1671 #define AMDGPU_UVD_STACK_SIZE (200*1024)
1672 #define AMDGPU_UVD_HEAP_SIZE (256*1024)
1673 #define AMDGPU_UVD_SESSION_SIZE (50*1024)
1674 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1675
1676 struct amdgpu_uvd {
1677 struct amdgpu_bo *vcpu_bo;
1678 void *cpu_addr;
1679 uint64_t gpu_addr;
1680 unsigned fw_version;
1681 void *saved_bo;
1682 unsigned max_handles;
1683 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1684 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1685 struct delayed_work idle_work;
1686 const struct firmware *fw; /* UVD firmware */
1687 struct amdgpu_ring ring;
1688 struct amdgpu_irq_src irq;
1689 bool address_64_bit;
1690 struct amd_sched_entity entity;
1691 };
1692
1693 /*
1694 * VCE
1695 */
1696 #define AMDGPU_MAX_VCE_HANDLES 16
1697 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1698
1699 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1700 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1701
1702 struct amdgpu_vce {
1703 struct amdgpu_bo *vcpu_bo;
1704 uint64_t gpu_addr;
1705 unsigned fw_version;
1706 unsigned fb_version;
1707 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1708 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1709 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1710 struct delayed_work idle_work;
1711 const struct firmware *fw; /* VCE firmware */
1712 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1713 struct amdgpu_irq_src irq;
1714 unsigned harvest_config;
1715 struct amd_sched_entity entity;
1716 };
1717
1718 /*
1719 * SDMA
1720 */
1721 struct amdgpu_sdma_instance {
1722 /* SDMA firmware */
1723 const struct firmware *fw;
1724 uint32_t fw_version;
1725 uint32_t feature_version;
1726
1727 struct amdgpu_ring ring;
1728 bool burst_nop;
1729 };
1730
1731 struct amdgpu_sdma {
1732 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1733 struct amdgpu_irq_src trap_irq;
1734 struct amdgpu_irq_src illegal_inst_irq;
1735 int num_instances;
1736 };
1737
1738 /*
1739 * Firmware
1740 */
1741 struct amdgpu_firmware {
1742 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1743 bool smu_load;
1744 struct amdgpu_bo *fw_buf;
1745 unsigned int fw_size;
1746 };
1747
1748 /*
1749 * Benchmarking
1750 */
1751 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1752
1753
1754 /*
1755 * Testing
1756 */
1757 void amdgpu_test_moves(struct amdgpu_device *adev);
1758 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1759 struct amdgpu_ring *cpA,
1760 struct amdgpu_ring *cpB);
1761 void amdgpu_test_syncing(struct amdgpu_device *adev);
1762
1763 /*
1764 * MMU Notifier
1765 */
1766 #if defined(CONFIG_MMU_NOTIFIER)
1767 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1768 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1769 #else
1770 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1771 {
1772 return -ENODEV;
1773 }
1774 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1775 #endif
1776
1777 /*
1778 * Debugfs
1779 */
1780 struct amdgpu_debugfs {
1781 const struct drm_info_list *files;
1782 unsigned num_files;
1783 };
1784
1785 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1786 const struct drm_info_list *files,
1787 unsigned nfiles);
1788 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1789
1790 #if defined(CONFIG_DEBUG_FS)
1791 int amdgpu_debugfs_init(struct drm_minor *minor);
1792 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1793 #endif
1794
1795 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1796
1797 /*
1798 * amdgpu smumgr functions
1799 */
1800 struct amdgpu_smumgr_funcs {
1801 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1802 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1803 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1804 };
1805
1806 /*
1807 * amdgpu smumgr
1808 */
1809 struct amdgpu_smumgr {
1810 struct amdgpu_bo *toc_buf;
1811 struct amdgpu_bo *smu_buf;
1812 /* asic priv smu data */
1813 void *priv;
1814 spinlock_t smu_lock;
1815 /* smumgr functions */
1816 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1817 /* ucode loading complete flag */
1818 uint32_t fw_flags;
1819 };
1820
1821 /*
1822 * ASIC specific register table accessible by UMD
1823 */
1824 struct amdgpu_allowed_register_entry {
1825 uint32_t reg_offset;
1826 bool untouched;
1827 bool grbm_indexed;
1828 };
1829
1830 /*
1831 * ASIC specific functions.
1832 */
1833 struct amdgpu_asic_funcs {
1834 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1835 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1836 u8 *bios, u32 length_bytes);
1837 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1838 u32 sh_num, u32 reg_offset, u32 *value);
1839 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1840 int (*reset)(struct amdgpu_device *adev);
1841 /* get the reference clock */
1842 u32 (*get_xclk)(struct amdgpu_device *adev);
1843 /* MM block clocks */
1844 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1845 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1846 /* query virtual capabilities */
1847 u32 (*get_virtual_caps)(struct amdgpu_device *adev);
1848 };
1849
1850 /*
1851 * IOCTL.
1852 */
1853 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1854 struct drm_file *filp);
1855 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1856 struct drm_file *filp);
1857
1858 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1859 struct drm_file *filp);
1860 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1861 struct drm_file *filp);
1862 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1865 struct drm_file *filp);
1866 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1867 struct drm_file *filp);
1868 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1869 struct drm_file *filp);
1870 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1871 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1872
1873 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1874 struct drm_file *filp);
1875
1876 /* VRAM scratch page for HDP bug, default vram page */
1877 struct amdgpu_vram_scratch {
1878 struct amdgpu_bo *robj;
1879 volatile uint32_t *ptr;
1880 u64 gpu_addr;
1881 };
1882
1883 /*
1884 * ACPI
1885 */
1886 struct amdgpu_atif_notification_cfg {
1887 bool enabled;
1888 int command_code;
1889 };
1890
1891 struct amdgpu_atif_notifications {
1892 bool display_switch;
1893 bool expansion_mode_change;
1894 bool thermal_state;
1895 bool forced_power_state;
1896 bool system_power_state;
1897 bool display_conf_change;
1898 bool px_gfx_switch;
1899 bool brightness_change;
1900 bool dgpu_display_event;
1901 };
1902
1903 struct amdgpu_atif_functions {
1904 bool system_params;
1905 bool sbios_requests;
1906 bool select_active_disp;
1907 bool lid_state;
1908 bool get_tv_standard;
1909 bool set_tv_standard;
1910 bool get_panel_expansion_mode;
1911 bool set_panel_expansion_mode;
1912 bool temperature_change;
1913 bool graphics_device_types;
1914 };
1915
1916 struct amdgpu_atif {
1917 struct amdgpu_atif_notifications notifications;
1918 struct amdgpu_atif_functions functions;
1919 struct amdgpu_atif_notification_cfg notification_cfg;
1920 struct amdgpu_encoder *encoder_for_bl;
1921 };
1922
1923 struct amdgpu_atcs_functions {
1924 bool get_ext_state;
1925 bool pcie_perf_req;
1926 bool pcie_dev_rdy;
1927 bool pcie_bus_width;
1928 };
1929
1930 struct amdgpu_atcs {
1931 struct amdgpu_atcs_functions functions;
1932 };
1933
1934 /*
1935 * CGS
1936 */
1937 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1938 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1939
1940
1941 /* GPU virtualization */
1942 #define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
1943 #define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
1944 struct amdgpu_virtualization {
1945 bool supports_sr_iov;
1946 bool is_virtual;
1947 u32 caps;
1948 };
1949
1950 /*
1951 * Core structure, functions and helpers.
1952 */
1953 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1954 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1955
1956 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1957 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1958
1959 struct amdgpu_ip_block_status {
1960 bool valid;
1961 bool sw;
1962 bool hw;
1963 };
1964
1965 struct amdgpu_device {
1966 struct device *dev;
1967 struct drm_device *ddev;
1968 struct pci_dev *pdev;
1969
1970 #ifdef CONFIG_DRM_AMD_ACP
1971 struct amdgpu_acp acp;
1972 #endif
1973
1974 /* ASIC */
1975 enum amd_asic_type asic_type;
1976 uint32_t family;
1977 uint32_t rev_id;
1978 uint32_t external_rev_id;
1979 unsigned long flags;
1980 int usec_timeout;
1981 const struct amdgpu_asic_funcs *asic_funcs;
1982 bool shutdown;
1983 bool need_dma32;
1984 bool accel_working;
1985 struct work_struct reset_work;
1986 struct notifier_block acpi_nb;
1987 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1988 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1989 unsigned debugfs_count;
1990 #if defined(CONFIG_DEBUG_FS)
1991 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1992 #endif
1993 struct amdgpu_atif atif;
1994 struct amdgpu_atcs atcs;
1995 struct mutex srbm_mutex;
1996 /* GRBM index mutex. Protects concurrent access to GRBM index */
1997 struct mutex grbm_idx_mutex;
1998 struct dev_pm_domain vga_pm_domain;
1999 bool have_disp_power_ref;
2000
2001 /* BIOS */
2002 uint8_t *bios;
2003 bool is_atom_bios;
2004 struct amdgpu_bo *stollen_vga_memory;
2005 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
2006
2007 /* Register/doorbell mmio */
2008 resource_size_t rmmio_base;
2009 resource_size_t rmmio_size;
2010 void __iomem *rmmio;
2011 /* protects concurrent MM_INDEX/DATA based register access */
2012 spinlock_t mmio_idx_lock;
2013 /* protects concurrent SMC based register access */
2014 spinlock_t smc_idx_lock;
2015 amdgpu_rreg_t smc_rreg;
2016 amdgpu_wreg_t smc_wreg;
2017 /* protects concurrent PCIE register access */
2018 spinlock_t pcie_idx_lock;
2019 amdgpu_rreg_t pcie_rreg;
2020 amdgpu_wreg_t pcie_wreg;
2021 /* protects concurrent UVD register access */
2022 spinlock_t uvd_ctx_idx_lock;
2023 amdgpu_rreg_t uvd_ctx_rreg;
2024 amdgpu_wreg_t uvd_ctx_wreg;
2025 /* protects concurrent DIDT register access */
2026 spinlock_t didt_idx_lock;
2027 amdgpu_rreg_t didt_rreg;
2028 amdgpu_wreg_t didt_wreg;
2029 /* protects concurrent ENDPOINT (audio) register access */
2030 spinlock_t audio_endpt_idx_lock;
2031 amdgpu_block_rreg_t audio_endpt_rreg;
2032 amdgpu_block_wreg_t audio_endpt_wreg;
2033 void __iomem *rio_mem;
2034 resource_size_t rio_mem_size;
2035 struct amdgpu_doorbell doorbell;
2036
2037 /* clock/pll info */
2038 struct amdgpu_clock clock;
2039
2040 /* MC */
2041 struct amdgpu_mc mc;
2042 struct amdgpu_gart gart;
2043 struct amdgpu_dummy_page dummy_page;
2044 struct amdgpu_vm_manager vm_manager;
2045
2046 /* memory management */
2047 struct amdgpu_mman mman;
2048 struct amdgpu_vram_scratch vram_scratch;
2049 struct amdgpu_wb wb;
2050 atomic64_t vram_usage;
2051 atomic64_t vram_vis_usage;
2052 atomic64_t gtt_usage;
2053 atomic64_t num_bytes_moved;
2054 atomic64_t num_evictions;
2055 atomic_t gpu_reset_counter;
2056
2057 /* display */
2058 struct amdgpu_mode_info mode_info;
2059 struct work_struct hotplug_work;
2060 struct amdgpu_irq_src crtc_irq;
2061 struct amdgpu_irq_src pageflip_irq;
2062 struct amdgpu_irq_src hpd_irq;
2063
2064 /* rings */
2065 u64 fence_context;
2066 unsigned num_rings;
2067 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2068 bool ib_pool_ready;
2069 struct amdgpu_sa_manager ring_tmp_bo;
2070
2071 /* interrupts */
2072 struct amdgpu_irq irq;
2073
2074 /* powerplay */
2075 struct amd_powerplay powerplay;
2076 bool pp_enabled;
2077 bool pp_force_state_enabled;
2078
2079 /* dpm */
2080 struct amdgpu_pm pm;
2081 u32 cg_flags;
2082 u32 pg_flags;
2083
2084 /* amdgpu smumgr */
2085 struct amdgpu_smumgr smu;
2086
2087 /* gfx */
2088 struct amdgpu_gfx gfx;
2089
2090 /* sdma */
2091 struct amdgpu_sdma sdma;
2092
2093 /* uvd */
2094 struct amdgpu_uvd uvd;
2095
2096 /* vce */
2097 struct amdgpu_vce vce;
2098
2099 /* firmwares */
2100 struct amdgpu_firmware firmware;
2101
2102 /* GDS */
2103 struct amdgpu_gds gds;
2104
2105 const struct amdgpu_ip_block_version *ip_blocks;
2106 int num_ip_blocks;
2107 struct amdgpu_ip_block_status *ip_block_status;
2108 struct mutex mn_lock;
2109 DECLARE_HASHTABLE(mn_hash, 7);
2110
2111 /* tracking pinned memory */
2112 u64 vram_pin_size;
2113 u64 invisible_pin_size;
2114 u64 gart_pin_size;
2115
2116 /* amdkfd interface */
2117 struct kfd_dev *kfd;
2118
2119 struct amdgpu_virtualization virtualization;
2120 };
2121
2122 bool amdgpu_device_is_px(struct drm_device *dev);
2123 int amdgpu_device_init(struct amdgpu_device *adev,
2124 struct drm_device *ddev,
2125 struct pci_dev *pdev,
2126 uint32_t flags);
2127 void amdgpu_device_fini(struct amdgpu_device *adev);
2128 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2129
2130 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2131 bool always_indirect);
2132 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2133 bool always_indirect);
2134 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2135 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2136
2137 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2138 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2139
2140 /*
2141 * Registers read & write functions.
2142 */
2143 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2144 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2145 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2146 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2147 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2148 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2149 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2150 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2151 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2152 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2153 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2154 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2155 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2156 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2157 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2158 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2159 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2160 #define WREG32_P(reg, val, mask) \
2161 do { \
2162 uint32_t tmp_ = RREG32(reg); \
2163 tmp_ &= (mask); \
2164 tmp_ |= ((val) & ~(mask)); \
2165 WREG32(reg, tmp_); \
2166 } while (0)
2167 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2168 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2169 #define WREG32_PLL_P(reg, val, mask) \
2170 do { \
2171 uint32_t tmp_ = RREG32_PLL(reg); \
2172 tmp_ &= (mask); \
2173 tmp_ |= ((val) & ~(mask)); \
2174 WREG32_PLL(reg, tmp_); \
2175 } while (0)
2176 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2177 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2178 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2179
2180 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2181 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2182
2183 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2184 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2185
2186 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2187 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2188 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2189
2190 #define REG_GET_FIELD(value, reg, field) \
2191 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2192
2193 /*
2194 * BIOS helpers.
2195 */
2196 #define RBIOS8(i) (adev->bios[i])
2197 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2198 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2199
2200 /*
2201 * RING helpers.
2202 */
2203 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2204 {
2205 if (ring->count_dw <= 0)
2206 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2207 ring->ring[ring->wptr++] = v;
2208 ring->wptr &= ring->ptr_mask;
2209 ring->count_dw--;
2210 }
2211
2212 static inline struct amdgpu_sdma_instance *
2213 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2214 {
2215 struct amdgpu_device *adev = ring->adev;
2216 int i;
2217
2218 for (i = 0; i < adev->sdma.num_instances; i++)
2219 if (&adev->sdma.instance[i].ring == ring)
2220 break;
2221
2222 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2223 return &adev->sdma.instance[i];
2224 else
2225 return NULL;
2226 }
2227
2228 /*
2229 * ASICs macro.
2230 */
2231 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2232 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2233 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2234 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2235 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2236 #define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
2237 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2238 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2239 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2240 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2241 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2242 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2243 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
2244 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2245 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2246 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2247 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2248 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2249 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2250 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2251 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
2252 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
2253 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2254 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2255 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2256 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2257 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
2258 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
2259 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2260 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
2261 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2262 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2263 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2264 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2265 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2266 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2267 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2268 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2269 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2270 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2271 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2272 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2273 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2274 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
2275 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2276 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2277 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2278 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2279 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2280 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2281 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2282 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2283 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2284 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2285 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2286 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2287 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2288 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2289 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
2290 #define amdgpu_gfx_select_se_sh(adev, se, sh) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh))
2291
2292 #define amdgpu_dpm_get_temperature(adev) \
2293 ((adev)->pp_enabled ? \
2294 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2295 (adev)->pm.funcs->get_temperature((adev)))
2296
2297 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2298 ((adev)->pp_enabled ? \
2299 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2300 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2301
2302 #define amdgpu_dpm_get_fan_control_mode(adev) \
2303 ((adev)->pp_enabled ? \
2304 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2305 (adev)->pm.funcs->get_fan_control_mode((adev)))
2306
2307 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2308 ((adev)->pp_enabled ? \
2309 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2310 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2311
2312 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2313 ((adev)->pp_enabled ? \
2314 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2315 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2316
2317 #define amdgpu_dpm_get_sclk(adev, l) \
2318 ((adev)->pp_enabled ? \
2319 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2320 (adev)->pm.funcs->get_sclk((adev), (l)))
2321
2322 #define amdgpu_dpm_get_mclk(adev, l) \
2323 ((adev)->pp_enabled ? \
2324 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2325 (adev)->pm.funcs->get_mclk((adev), (l)))
2326
2327
2328 #define amdgpu_dpm_force_performance_level(adev, l) \
2329 ((adev)->pp_enabled ? \
2330 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2331 (adev)->pm.funcs->force_performance_level((adev), (l)))
2332
2333 #define amdgpu_dpm_powergate_uvd(adev, g) \
2334 ((adev)->pp_enabled ? \
2335 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2336 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2337
2338 #define amdgpu_dpm_powergate_vce(adev, g) \
2339 ((adev)->pp_enabled ? \
2340 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2341 (adev)->pm.funcs->powergate_vce((adev), (g)))
2342
2343 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2344 ((adev)->pp_enabled ? \
2345 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2346 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2347
2348 #define amdgpu_dpm_get_current_power_state(adev) \
2349 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2350
2351 #define amdgpu_dpm_get_performance_level(adev) \
2352 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2353
2354 #define amdgpu_dpm_get_pp_num_states(adev, data) \
2355 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2356
2357 #define amdgpu_dpm_get_pp_table(adev, table) \
2358 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2359
2360 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
2361 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2362
2363 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2364 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2365
2366 #define amdgpu_dpm_force_clock_level(adev, type, level) \
2367 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2368
2369 #define amdgpu_dpm_get_sclk_od(adev) \
2370 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
2371
2372 #define amdgpu_dpm_set_sclk_od(adev, value) \
2373 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
2374
2375 #define amdgpu_dpm_get_mclk_od(adev) \
2376 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
2377
2378 #define amdgpu_dpm_set_mclk_od(adev, value) \
2379 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
2380
2381 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2382 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2383
2384 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2385
2386 /* Common functions */
2387 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2388 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2389 bool amdgpu_card_posted(struct amdgpu_device *adev);
2390 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2391
2392 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2393 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2394 u32 ip_instance, u32 ring,
2395 struct amdgpu_ring **out_ring);
2396 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2397 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2398 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
2399 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2400 uint32_t flags);
2401 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2402 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
2403 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2404 unsigned long end);
2405 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2406 int *last_invalidated);
2407 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2408 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2409 struct ttm_mem_reg *mem);
2410 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2411 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2412 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2413 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2414 const u32 *registers,
2415 const u32 array_size);
2416
2417 bool amdgpu_device_is_px(struct drm_device *dev);
2418 /* atpx handler */
2419 #if defined(CONFIG_VGA_SWITCHEROO)
2420 void amdgpu_register_atpx_handler(void);
2421 void amdgpu_unregister_atpx_handler(void);
2422 bool amdgpu_has_atpx_dgpu_power_cntl(void);
2423 bool amdgpu_is_atpx_hybrid(void);
2424 #else
2425 static inline void amdgpu_register_atpx_handler(void) {}
2426 static inline void amdgpu_unregister_atpx_handler(void) {}
2427 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2428 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
2429 #endif
2430
2431 /*
2432 * KMS
2433 */
2434 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2435 extern const int amdgpu_max_kms_ioctl;
2436
2437 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2438 int amdgpu_driver_unload_kms(struct drm_device *dev);
2439 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2440 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2441 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2442 struct drm_file *file_priv);
2443 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2444 struct drm_file *file_priv);
2445 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2446 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2447 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2448 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2449 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2450 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2451 int *max_error,
2452 struct timeval *vblank_time,
2453 unsigned flags);
2454 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2455 unsigned long arg);
2456
2457 /*
2458 * functions used by amdgpu_encoder.c
2459 */
2460 struct amdgpu_afmt_acr {
2461 u32 clock;
2462
2463 int n_32khz;
2464 int cts_32khz;
2465
2466 int n_44_1khz;
2467 int cts_44_1khz;
2468
2469 int n_48khz;
2470 int cts_48khz;
2471
2472 };
2473
2474 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2475
2476 /* amdgpu_acpi.c */
2477 #if defined(CONFIG_ACPI)
2478 int amdgpu_acpi_init(struct amdgpu_device *adev);
2479 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2480 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2481 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2482 u8 perf_req, bool advertise);
2483 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2484 #else
2485 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2486 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2487 #endif
2488
2489 struct amdgpu_bo_va_mapping *
2490 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2491 uint64_t addr, struct amdgpu_bo **bo);
2492
2493 #include "amdgpu_object.h"
2494 #endif
Linux kernel - Deliverables
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