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drm/amdgpu: abstract amdgpu_job for scheduler
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55
56 #include "gpu_scheduler.h"
57
58 /*
59 * Modules parameters.
60 */
61 extern int amdgpu_modeset;
62 extern int amdgpu_vram_limit;
63 extern int amdgpu_gart_size;
64 extern int amdgpu_benchmarking;
65 extern int amdgpu_testing;
66 extern int amdgpu_audio;
67 extern int amdgpu_disp_priority;
68 extern int amdgpu_hw_i2c;
69 extern int amdgpu_pcie_gen2;
70 extern int amdgpu_msi;
71 extern int amdgpu_lockup_timeout;
72 extern int amdgpu_dpm;
73 extern int amdgpu_smc_load_fw;
74 extern int amdgpu_aspm;
75 extern int amdgpu_runtime_pm;
76 extern int amdgpu_hard_reset;
77 extern unsigned amdgpu_ip_block_mask;
78 extern int amdgpu_bapm;
79 extern int amdgpu_deep_color;
80 extern int amdgpu_vm_size;
81 extern int amdgpu_vm_block_size;
82 extern int amdgpu_enable_scheduler;
83 extern int amdgpu_sched_jobs;
84 extern int amdgpu_sched_hw_submission;
85
86 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
87 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
88 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
89 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
90 #define AMDGPU_IB_POOL_SIZE 16
91 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
92 #define AMDGPUFB_CONN_LIMIT 4
93 #define AMDGPU_BIOS_NUM_SCRATCH 8
94
95 /* max number of rings */
96 #define AMDGPU_MAX_RINGS 16
97 #define AMDGPU_MAX_GFX_RINGS 1
98 #define AMDGPU_MAX_COMPUTE_RINGS 8
99 #define AMDGPU_MAX_VCE_RINGS 2
100
101 /* number of hw syncs before falling back on blocking */
102 #define AMDGPU_NUM_SYNCS 4
103
104 /* hardcode that limit for now */
105 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
106
107 /* hard reset data */
108 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
109
110 /* reset flags */
111 #define AMDGPU_RESET_GFX (1 << 0)
112 #define AMDGPU_RESET_COMPUTE (1 << 1)
113 #define AMDGPU_RESET_DMA (1 << 2)
114 #define AMDGPU_RESET_CP (1 << 3)
115 #define AMDGPU_RESET_GRBM (1 << 4)
116 #define AMDGPU_RESET_DMA1 (1 << 5)
117 #define AMDGPU_RESET_RLC (1 << 6)
118 #define AMDGPU_RESET_SEM (1 << 7)
119 #define AMDGPU_RESET_IH (1 << 8)
120 #define AMDGPU_RESET_VMC (1 << 9)
121 #define AMDGPU_RESET_MC (1 << 10)
122 #define AMDGPU_RESET_DISPLAY (1 << 11)
123 #define AMDGPU_RESET_UVD (1 << 12)
124 #define AMDGPU_RESET_VCE (1 << 13)
125 #define AMDGPU_RESET_VCE1 (1 << 14)
126
127 /* CG block flags */
128 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
129 #define AMDGPU_CG_BLOCK_MC (1 << 1)
130 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
131 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
132 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
133 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
134 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
135
136 /* CG flags */
137 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
138 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
139 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
140 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
141 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
142 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
143 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
144 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
145 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
146 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
147 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
148 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
149 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
150 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
151 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
152 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
153 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
154
155 /* PG flags */
156 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
157 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
158 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
159 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
160 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
161 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
162 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
163 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
164 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
165 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
166 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
167
168 /* GFX current status */
169 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
170 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
171 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
172 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
173 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
174
175 /* max cursor sizes (in pixels) */
176 #define CIK_CURSOR_WIDTH 128
177 #define CIK_CURSOR_HEIGHT 128
178
179 struct amdgpu_device;
180 struct amdgpu_fence;
181 struct amdgpu_ib;
182 struct amdgpu_vm;
183 struct amdgpu_ring;
184 struct amdgpu_semaphore;
185 struct amdgpu_cs_parser;
186 struct amdgpu_job;
187 struct amdgpu_irq_src;
188 struct amdgpu_fpriv;
189
190 enum amdgpu_cp_irq {
191 AMDGPU_CP_IRQ_GFX_EOP = 0,
192 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
193 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
200
201 AMDGPU_CP_IRQ_LAST
202 };
203
204 enum amdgpu_sdma_irq {
205 AMDGPU_SDMA_IRQ_TRAP0 = 0,
206 AMDGPU_SDMA_IRQ_TRAP1,
207
208 AMDGPU_SDMA_IRQ_LAST
209 };
210
211 enum amdgpu_thermal_irq {
212 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
213 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
214
215 AMDGPU_THERMAL_IRQ_LAST
216 };
217
218 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
219 enum amd_ip_block_type block_type,
220 enum amd_clockgating_state state);
221 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
222 enum amd_ip_block_type block_type,
223 enum amd_powergating_state state);
224
225 struct amdgpu_ip_block_version {
226 enum amd_ip_block_type type;
227 u32 major;
228 u32 minor;
229 u32 rev;
230 const struct amd_ip_funcs *funcs;
231 };
232
233 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
234 enum amd_ip_block_type type,
235 u32 major, u32 minor);
236
237 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
238 struct amdgpu_device *adev,
239 enum amd_ip_block_type type);
240
241 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
242 struct amdgpu_buffer_funcs {
243 /* maximum bytes in a single operation */
244 uint32_t copy_max_bytes;
245
246 /* number of dw to reserve per operation */
247 unsigned copy_num_dw;
248
249 /* used for buffer migration */
250 void (*emit_copy_buffer)(struct amdgpu_ring *ring,
251 /* src addr in bytes */
252 uint64_t src_offset,
253 /* dst addr in bytes */
254 uint64_t dst_offset,
255 /* number of byte to transfer */
256 uint32_t byte_count);
257
258 /* maximum bytes in a single operation */
259 uint32_t fill_max_bytes;
260
261 /* number of dw to reserve per operation */
262 unsigned fill_num_dw;
263
264 /* used for buffer clearing */
265 void (*emit_fill_buffer)(struct amdgpu_ring *ring,
266 /* value to write to memory */
267 uint32_t src_data,
268 /* dst addr in bytes */
269 uint64_t dst_offset,
270 /* number of byte to fill */
271 uint32_t byte_count);
272 };
273
274 /* provided by hw blocks that can write ptes, e.g., sdma */
275 struct amdgpu_vm_pte_funcs {
276 /* copy pte entries from GART */
277 void (*copy_pte)(struct amdgpu_ib *ib,
278 uint64_t pe, uint64_t src,
279 unsigned count);
280 /* write pte one entry at a time with addr mapping */
281 void (*write_pte)(struct amdgpu_ib *ib,
282 uint64_t pe,
283 uint64_t addr, unsigned count,
284 uint32_t incr, uint32_t flags);
285 /* for linear pte/pde updates without addr mapping */
286 void (*set_pte_pde)(struct amdgpu_ib *ib,
287 uint64_t pe,
288 uint64_t addr, unsigned count,
289 uint32_t incr, uint32_t flags);
290 /* pad the indirect buffer to the necessary number of dw */
291 void (*pad_ib)(struct amdgpu_ib *ib);
292 };
293
294 /* provided by the gmc block */
295 struct amdgpu_gart_funcs {
296 /* flush the vm tlb via mmio */
297 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
298 uint32_t vmid);
299 /* write pte/pde updates using the cpu */
300 int (*set_pte_pde)(struct amdgpu_device *adev,
301 void *cpu_pt_addr, /* cpu addr of page table */
302 uint32_t gpu_page_idx, /* pte/pde to update */
303 uint64_t addr, /* addr to write into pte/pde */
304 uint32_t flags); /* access flags */
305 };
306
307 /* provided by the ih block */
308 struct amdgpu_ih_funcs {
309 /* ring read/write ptr handling, called from interrupt context */
310 u32 (*get_wptr)(struct amdgpu_device *adev);
311 void (*decode_iv)(struct amdgpu_device *adev,
312 struct amdgpu_iv_entry *entry);
313 void (*set_rptr)(struct amdgpu_device *adev);
314 };
315
316 /* provided by hw blocks that expose a ring buffer for commands */
317 struct amdgpu_ring_funcs {
318 /* ring read/write ptr handling */
319 u32 (*get_rptr)(struct amdgpu_ring *ring);
320 u32 (*get_wptr)(struct amdgpu_ring *ring);
321 void (*set_wptr)(struct amdgpu_ring *ring);
322 /* validating and patching of IBs */
323 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
324 /* command emit functions */
325 void (*emit_ib)(struct amdgpu_ring *ring,
326 struct amdgpu_ib *ib);
327 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
328 uint64_t seq, unsigned flags);
329 bool (*emit_semaphore)(struct amdgpu_ring *ring,
330 struct amdgpu_semaphore *semaphore,
331 bool emit_wait);
332 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
333 uint64_t pd_addr);
334 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
335 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
336 uint32_t gds_base, uint32_t gds_size,
337 uint32_t gws_base, uint32_t gws_size,
338 uint32_t oa_base, uint32_t oa_size);
339 /* testing functions */
340 int (*test_ring)(struct amdgpu_ring *ring);
341 int (*test_ib)(struct amdgpu_ring *ring);
342 bool (*is_lockup)(struct amdgpu_ring *ring);
343 };
344
345 /*
346 * BIOS.
347 */
348 bool amdgpu_get_bios(struct amdgpu_device *adev);
349 bool amdgpu_read_bios(struct amdgpu_device *adev);
350
351 /*
352 * Dummy page
353 */
354 struct amdgpu_dummy_page {
355 struct page *page;
356 dma_addr_t addr;
357 };
358 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
359 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
360
361
362 /*
363 * Clocks
364 */
365
366 #define AMDGPU_MAX_PPLL 3
367
368 struct amdgpu_clock {
369 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
370 struct amdgpu_pll spll;
371 struct amdgpu_pll mpll;
372 /* 10 Khz units */
373 uint32_t default_mclk;
374 uint32_t default_sclk;
375 uint32_t default_dispclk;
376 uint32_t current_dispclk;
377 uint32_t dp_extclk;
378 uint32_t max_pixel_clock;
379 };
380
381 /*
382 * Fences.
383 */
384 struct amdgpu_fence_driver {
385 struct amdgpu_ring *ring;
386 uint64_t gpu_addr;
387 volatile uint32_t *cpu_addr;
388 /* sync_seq is protected by ring emission lock */
389 uint64_t sync_seq[AMDGPU_MAX_RINGS];
390 atomic64_t last_seq;
391 bool initialized;
392 struct amdgpu_irq_src *irq_src;
393 unsigned irq_type;
394 struct delayed_work lockup_work;
395 wait_queue_head_t fence_queue;
396 };
397
398 /* some special values for the owner field */
399 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
400 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
401 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
402
403 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
404 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
405
406 struct amdgpu_fence {
407 struct fence base;
408
409 /* RB, DMA, etc. */
410 struct amdgpu_ring *ring;
411 uint64_t seq;
412
413 /* filp or special value for fence creator */
414 void *owner;
415
416 wait_queue_t fence_wake;
417 };
418
419 struct amdgpu_user_fence {
420 /* write-back bo */
421 struct amdgpu_bo *bo;
422 /* write-back address offset to bo start */
423 uint32_t offset;
424 };
425
426 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
427 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
428 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
429
430 void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
431 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
432 struct amdgpu_irq_src *irq_src,
433 unsigned irq_type);
434 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
435 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
436 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
437 struct amdgpu_fence **fence);
438 void amdgpu_fence_process(struct amdgpu_ring *ring);
439 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
440 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
441 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
442
443 signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
444 struct amdgpu_fence **fences,
445 bool intr, long t);
446 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
447 void amdgpu_fence_unref(struct amdgpu_fence **fence);
448
449 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
450 struct amdgpu_ring *ring);
451 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
452 struct amdgpu_ring *ring);
453
454 static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
455 struct amdgpu_fence *b)
456 {
457 if (!a) {
458 return b;
459 }
460
461 if (!b) {
462 return a;
463 }
464
465 BUG_ON(a->ring != b->ring);
466
467 if (a->seq > b->seq) {
468 return a;
469 } else {
470 return b;
471 }
472 }
473
474 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
475 struct amdgpu_fence *b)
476 {
477 if (!a) {
478 return false;
479 }
480
481 if (!b) {
482 return true;
483 }
484
485 BUG_ON(a->ring != b->ring);
486
487 return a->seq < b->seq;
488 }
489
490 int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
491 void *owner, struct amdgpu_fence **fence);
492
493 /*
494 * TTM.
495 */
496 struct amdgpu_mman {
497 struct ttm_bo_global_ref bo_global_ref;
498 struct drm_global_reference mem_global_ref;
499 struct ttm_bo_device bdev;
500 bool mem_global_referenced;
501 bool initialized;
502
503 #if defined(CONFIG_DEBUG_FS)
504 struct dentry *vram;
505 struct dentry *gtt;
506 #endif
507
508 /* buffer handling */
509 const struct amdgpu_buffer_funcs *buffer_funcs;
510 struct amdgpu_ring *buffer_funcs_ring;
511 };
512
513 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
514 uint64_t src_offset,
515 uint64_t dst_offset,
516 uint32_t byte_count,
517 struct reservation_object *resv,
518 struct amdgpu_fence **fence);
519 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
520
521 struct amdgpu_bo_list_entry {
522 struct amdgpu_bo *robj;
523 struct ttm_validate_buffer tv;
524 struct amdgpu_bo_va *bo_va;
525 unsigned prefered_domains;
526 unsigned allowed_domains;
527 uint32_t priority;
528 };
529
530 struct amdgpu_bo_va_mapping {
531 struct list_head list;
532 struct interval_tree_node it;
533 uint64_t offset;
534 uint32_t flags;
535 };
536
537 /* bo virtual addresses in a specific vm */
538 struct amdgpu_bo_va {
539 /* protected by bo being reserved */
540 struct list_head bo_list;
541 struct fence *last_pt_update;
542 unsigned ref_count;
543
544 /* protected by vm mutex and spinlock */
545 struct list_head vm_status;
546
547 /* mappings for this bo_va */
548 struct list_head invalids;
549 struct list_head valids;
550
551 /* constant after initialization */
552 struct amdgpu_vm *vm;
553 struct amdgpu_bo *bo;
554 };
555
556 #define AMDGPU_GEM_DOMAIN_MAX 0x3
557
558 struct amdgpu_bo {
559 /* Protected by gem.mutex */
560 struct list_head list;
561 /* Protected by tbo.reserved */
562 u32 initial_domain;
563 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
564 struct ttm_placement placement;
565 struct ttm_buffer_object tbo;
566 struct ttm_bo_kmap_obj kmap;
567 u64 flags;
568 unsigned pin_count;
569 void *kptr;
570 u64 tiling_flags;
571 u64 metadata_flags;
572 void *metadata;
573 u32 metadata_size;
574 /* list of all virtual address to which this bo
575 * is associated to
576 */
577 struct list_head va;
578 /* Constant after initialization */
579 struct amdgpu_device *adev;
580 struct drm_gem_object gem_base;
581
582 struct ttm_bo_kmap_obj dma_buf_vmap;
583 pid_t pid;
584 struct amdgpu_mn *mn;
585 struct list_head mn_list;
586 };
587 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
588
589 void amdgpu_gem_object_free(struct drm_gem_object *obj);
590 int amdgpu_gem_object_open(struct drm_gem_object *obj,
591 struct drm_file *file_priv);
592 void amdgpu_gem_object_close(struct drm_gem_object *obj,
593 struct drm_file *file_priv);
594 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
595 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
596 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
597 struct dma_buf_attachment *attach,
598 struct sg_table *sg);
599 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
600 struct drm_gem_object *gobj,
601 int flags);
602 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
603 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
604 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
605 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
606 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
607 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
608
609 /* sub-allocation manager, it has to be protected by another lock.
610 * By conception this is an helper for other part of the driver
611 * like the indirect buffer or semaphore, which both have their
612 * locking.
613 *
614 * Principe is simple, we keep a list of sub allocation in offset
615 * order (first entry has offset == 0, last entry has the highest
616 * offset).
617 *
618 * When allocating new object we first check if there is room at
619 * the end total_size - (last_object_offset + last_object_size) >=
620 * alloc_size. If so we allocate new object there.
621 *
622 * When there is not enough room at the end, we start waiting for
623 * each sub object until we reach object_offset+object_size >=
624 * alloc_size, this object then become the sub object we return.
625 *
626 * Alignment can't be bigger than page size.
627 *
628 * Hole are not considered for allocation to keep things simple.
629 * Assumption is that there won't be hole (all object on same
630 * alignment).
631 */
632 struct amdgpu_sa_manager {
633 wait_queue_head_t wq;
634 struct amdgpu_bo *bo;
635 struct list_head *hole;
636 struct list_head flist[AMDGPU_MAX_RINGS];
637 struct list_head olist;
638 unsigned size;
639 uint64_t gpu_addr;
640 void *cpu_ptr;
641 uint32_t domain;
642 uint32_t align;
643 };
644
645 struct amdgpu_sa_bo;
646
647 /* sub-allocation buffer */
648 struct amdgpu_sa_bo {
649 struct list_head olist;
650 struct list_head flist;
651 struct amdgpu_sa_manager *manager;
652 unsigned soffset;
653 unsigned eoffset;
654 struct amdgpu_fence *fence;
655 };
656
657 /*
658 * GEM objects.
659 */
660 struct amdgpu_gem {
661 struct mutex mutex;
662 struct list_head objects;
663 };
664
665 int amdgpu_gem_init(struct amdgpu_device *adev);
666 void amdgpu_gem_fini(struct amdgpu_device *adev);
667 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
668 int alignment, u32 initial_domain,
669 u64 flags, bool kernel,
670 struct drm_gem_object **obj);
671
672 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
673 struct drm_device *dev,
674 struct drm_mode_create_dumb *args);
675 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
676 struct drm_device *dev,
677 uint32_t handle, uint64_t *offset_p);
678
679 /*
680 * Semaphores.
681 */
682 struct amdgpu_semaphore {
683 struct amdgpu_sa_bo *sa_bo;
684 signed waiters;
685 uint64_t gpu_addr;
686 };
687
688 int amdgpu_semaphore_create(struct amdgpu_device *adev,
689 struct amdgpu_semaphore **semaphore);
690 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
691 struct amdgpu_semaphore *semaphore);
692 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
693 struct amdgpu_semaphore *semaphore);
694 void amdgpu_semaphore_free(struct amdgpu_device *adev,
695 struct amdgpu_semaphore **semaphore,
696 struct amdgpu_fence *fence);
697
698 /*
699 * Synchronization
700 */
701 struct amdgpu_sync {
702 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
703 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
704 struct amdgpu_fence *last_vm_update;
705 };
706
707 void amdgpu_sync_create(struct amdgpu_sync *sync);
708 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
709 struct fence *f);
710 int amdgpu_sync_resv(struct amdgpu_device *adev,
711 struct amdgpu_sync *sync,
712 struct reservation_object *resv,
713 void *owner);
714 int amdgpu_sync_rings(struct amdgpu_sync *sync,
715 struct amdgpu_ring *ring);
716 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
717 struct amdgpu_fence *fence);
718
719 /*
720 * GART structures, functions & helpers
721 */
722 struct amdgpu_mc;
723
724 #define AMDGPU_GPU_PAGE_SIZE 4096
725 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
726 #define AMDGPU_GPU_PAGE_SHIFT 12
727 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
728
729 struct amdgpu_gart {
730 dma_addr_t table_addr;
731 struct amdgpu_bo *robj;
732 void *ptr;
733 unsigned num_gpu_pages;
734 unsigned num_cpu_pages;
735 unsigned table_size;
736 struct page **pages;
737 dma_addr_t *pages_addr;
738 bool ready;
739 const struct amdgpu_gart_funcs *gart_funcs;
740 };
741
742 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
743 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
744 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
745 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
746 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
747 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
748 int amdgpu_gart_init(struct amdgpu_device *adev);
749 void amdgpu_gart_fini(struct amdgpu_device *adev);
750 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
751 int pages);
752 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
753 int pages, struct page **pagelist,
754 dma_addr_t *dma_addr, uint32_t flags);
755
756 /*
757 * GPU MC structures, functions & helpers
758 */
759 struct amdgpu_mc {
760 resource_size_t aper_size;
761 resource_size_t aper_base;
762 resource_size_t agp_base;
763 /* for some chips with <= 32MB we need to lie
764 * about vram size near mc fb location */
765 u64 mc_vram_size;
766 u64 visible_vram_size;
767 u64 gtt_size;
768 u64 gtt_start;
769 u64 gtt_end;
770 u64 vram_start;
771 u64 vram_end;
772 unsigned vram_width;
773 u64 real_vram_size;
774 int vram_mtrr;
775 u64 gtt_base_align;
776 u64 mc_mask;
777 const struct firmware *fw; /* MC firmware */
778 uint32_t fw_version;
779 struct amdgpu_irq_src vm_fault;
780 uint32_t vram_type;
781 };
782
783 /*
784 * GPU doorbell structures, functions & helpers
785 */
786 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
787 {
788 AMDGPU_DOORBELL_KIQ = 0x000,
789 AMDGPU_DOORBELL_HIQ = 0x001,
790 AMDGPU_DOORBELL_DIQ = 0x002,
791 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
792 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
793 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
794 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
795 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
796 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
797 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
798 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
799 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
800 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
801 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
802 AMDGPU_DOORBELL_IH = 0x1E8,
803 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
804 AMDGPU_DOORBELL_INVALID = 0xFFFF
805 } AMDGPU_DOORBELL_ASSIGNMENT;
806
807 struct amdgpu_doorbell {
808 /* doorbell mmio */
809 resource_size_t base;
810 resource_size_t size;
811 u32 __iomem *ptr;
812 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
813 };
814
815 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
816 phys_addr_t *aperture_base,
817 size_t *aperture_size,
818 size_t *start_offset);
819
820 /*
821 * IRQS.
822 */
823
824 struct amdgpu_flip_work {
825 struct work_struct flip_work;
826 struct work_struct unpin_work;
827 struct amdgpu_device *adev;
828 int crtc_id;
829 uint64_t base;
830 struct drm_pending_vblank_event *event;
831 struct amdgpu_bo *old_rbo;
832 struct fence *excl;
833 unsigned shared_count;
834 struct fence **shared;
835 };
836
837
838 /*
839 * CP & rings.
840 */
841
842 struct amdgpu_ib {
843 struct amdgpu_sa_bo *sa_bo;
844 uint32_t length_dw;
845 uint64_t gpu_addr;
846 uint32_t *ptr;
847 struct amdgpu_ring *ring;
848 struct amdgpu_fence *fence;
849 struct amdgpu_user_fence *user;
850 struct amdgpu_vm *vm;
851 struct amdgpu_ctx *ctx;
852 struct amdgpu_sync sync;
853 uint32_t gds_base, gds_size;
854 uint32_t gws_base, gws_size;
855 uint32_t oa_base, oa_size;
856 uint32_t flags;
857 /* resulting sequence number */
858 uint64_t sequence;
859 };
860
861 enum amdgpu_ring_type {
862 AMDGPU_RING_TYPE_GFX,
863 AMDGPU_RING_TYPE_COMPUTE,
864 AMDGPU_RING_TYPE_SDMA,
865 AMDGPU_RING_TYPE_UVD,
866 AMDGPU_RING_TYPE_VCE
867 };
868
869 extern struct amd_sched_backend_ops amdgpu_sched_ops;
870
871 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
872 struct amdgpu_ring *ring,
873 struct amdgpu_ib *ibs,
874 unsigned num_ibs,
875 int (*free_job)(struct amdgpu_job *),
876 void *owner,
877 struct fence **fence);
878
879 struct amdgpu_ring {
880 struct amdgpu_device *adev;
881 const struct amdgpu_ring_funcs *funcs;
882 struct amdgpu_fence_driver fence_drv;
883 struct amd_gpu_scheduler *scheduler;
884
885 spinlock_t fence_lock;
886 struct mutex *ring_lock;
887 struct amdgpu_bo *ring_obj;
888 volatile uint32_t *ring;
889 unsigned rptr_offs;
890 u64 next_rptr_gpu_addr;
891 volatile u32 *next_rptr_cpu_addr;
892 unsigned wptr;
893 unsigned wptr_old;
894 unsigned ring_size;
895 unsigned ring_free_dw;
896 int count_dw;
897 atomic_t last_rptr;
898 atomic64_t last_activity;
899 uint64_t gpu_addr;
900 uint32_t align_mask;
901 uint32_t ptr_mask;
902 bool ready;
903 u32 nop;
904 u32 idx;
905 u64 last_semaphore_signal_addr;
906 u64 last_semaphore_wait_addr;
907 u32 me;
908 u32 pipe;
909 u32 queue;
910 struct amdgpu_bo *mqd_obj;
911 u32 doorbell_index;
912 bool use_doorbell;
913 unsigned wptr_offs;
914 unsigned next_rptr_offs;
915 unsigned fence_offs;
916 struct amdgpu_ctx *current_ctx;
917 enum amdgpu_ring_type type;
918 char name[16];
919 bool is_pte_ring;
920 };
921
922 /*
923 * VM
924 */
925
926 /* maximum number of VMIDs */
927 #define AMDGPU_NUM_VM 16
928
929 /* number of entries in page table */
930 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
931
932 /* PTBs (Page Table Blocks) need to be aligned to 32K */
933 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
934 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
935 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
936
937 #define AMDGPU_PTE_VALID (1 << 0)
938 #define AMDGPU_PTE_SYSTEM (1 << 1)
939 #define AMDGPU_PTE_SNOOPED (1 << 2)
940
941 /* VI only */
942 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
943
944 #define AMDGPU_PTE_READABLE (1 << 5)
945 #define AMDGPU_PTE_WRITEABLE (1 << 6)
946
947 /* PTE (Page Table Entry) fragment field for different page sizes */
948 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
949 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
950 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
951
952 struct amdgpu_vm_pt {
953 struct amdgpu_bo *bo;
954 uint64_t addr;
955 };
956
957 struct amdgpu_vm_id {
958 unsigned id;
959 uint64_t pd_gpu_addr;
960 /* last flushed PD/PT update */
961 struct amdgpu_fence *flushed_updates;
962 /* last use of vmid */
963 struct amdgpu_fence *last_id_use;
964 };
965
966 struct amdgpu_vm {
967 struct mutex mutex;
968
969 struct rb_root va;
970
971 /* protecting invalidated */
972 spinlock_t status_lock;
973
974 /* BOs moved, but not yet updated in the PT */
975 struct list_head invalidated;
976
977 /* BOs cleared in the PT because of a move */
978 struct list_head cleared;
979
980 /* BO mappings freed, but not yet updated in the PT */
981 struct list_head freed;
982
983 /* contains the page directory */
984 struct amdgpu_bo *page_directory;
985 unsigned max_pde_used;
986 struct fence *page_directory_fence;
987
988 /* array of page tables, one for each page directory entry */
989 struct amdgpu_vm_pt *page_tables;
990
991 /* for id and flush management per ring */
992 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
993 };
994
995 struct amdgpu_vm_manager {
996 struct amdgpu_fence *active[AMDGPU_NUM_VM];
997 uint32_t max_pfn;
998 /* number of VMIDs */
999 unsigned nvm;
1000 /* vram base address for page table entry */
1001 u64 vram_base_offset;
1002 /* is vm enabled? */
1003 bool enabled;
1004 /* for hw to save the PD addr on suspend/resume */
1005 uint32_t saved_table_addr[AMDGPU_NUM_VM];
1006 /* vm pte handling */
1007 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
1008 struct amdgpu_ring *vm_pte_funcs_ring;
1009 };
1010
1011 /*
1012 * context related structures
1013 */
1014
1015 #define AMDGPU_CTX_MAX_CS_PENDING 16
1016
1017 struct amdgpu_ctx_ring {
1018 uint64_t sequence;
1019 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
1020 struct amd_sched_entity entity;
1021 };
1022
1023 struct amdgpu_ctx {
1024 struct kref refcount;
1025 struct amdgpu_device *adev;
1026 unsigned reset_counter;
1027 spinlock_t ring_lock;
1028 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
1029 };
1030
1031 struct amdgpu_ctx_mgr {
1032 struct amdgpu_device *adev;
1033 struct mutex lock;
1034 /* protected by lock */
1035 struct idr ctx_handles;
1036 };
1037
1038 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
1039 struct amdgpu_ctx *ctx);
1040 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
1041
1042 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1043 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1044 struct amdgpu_ctx *amdgpu_ctx_get_ref(struct amdgpu_ctx *ctx);
1045
1046 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1047 struct fence *fence, uint64_t queued_seq);
1048 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1049 struct amdgpu_ring *ring, uint64_t seq);
1050
1051 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1052 struct drm_file *filp);
1053
1054 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1055 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1056
1057 /*
1058 * file private structure
1059 */
1060
1061 struct amdgpu_fpriv {
1062 struct amdgpu_vm vm;
1063 struct mutex bo_list_lock;
1064 struct idr bo_list_handles;
1065 struct amdgpu_ctx_mgr ctx_mgr;
1066 };
1067
1068 /*
1069 * residency list
1070 */
1071
1072 struct amdgpu_bo_list {
1073 struct mutex lock;
1074 struct amdgpu_bo *gds_obj;
1075 struct amdgpu_bo *gws_obj;
1076 struct amdgpu_bo *oa_obj;
1077 bool has_userptr;
1078 unsigned num_entries;
1079 struct amdgpu_bo_list_entry *array;
1080 };
1081
1082 struct amdgpu_bo_list *
1083 amdgpu_bo_list_clone(struct amdgpu_bo_list *list);
1084 struct amdgpu_bo_list *
1085 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1086 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1087 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1088
1089 /*
1090 * GFX stuff
1091 */
1092 #include "clearstate_defs.h"
1093
1094 struct amdgpu_rlc {
1095 /* for power gating */
1096 struct amdgpu_bo *save_restore_obj;
1097 uint64_t save_restore_gpu_addr;
1098 volatile uint32_t *sr_ptr;
1099 const u32 *reg_list;
1100 u32 reg_list_size;
1101 /* for clear state */
1102 struct amdgpu_bo *clear_state_obj;
1103 uint64_t clear_state_gpu_addr;
1104 volatile uint32_t *cs_ptr;
1105 const struct cs_section_def *cs_data;
1106 u32 clear_state_size;
1107 /* for cp tables */
1108 struct amdgpu_bo *cp_table_obj;
1109 uint64_t cp_table_gpu_addr;
1110 volatile uint32_t *cp_table_ptr;
1111 u32 cp_table_size;
1112 };
1113
1114 struct amdgpu_mec {
1115 struct amdgpu_bo *hpd_eop_obj;
1116 u64 hpd_eop_gpu_addr;
1117 u32 num_pipe;
1118 u32 num_mec;
1119 u32 num_queue;
1120 };
1121
1122 /*
1123 * GPU scratch registers structures, functions & helpers
1124 */
1125 struct amdgpu_scratch {
1126 unsigned num_reg;
1127 uint32_t reg_base;
1128 bool free[32];
1129 uint32_t reg[32];
1130 };
1131
1132 /*
1133 * GFX configurations
1134 */
1135 struct amdgpu_gca_config {
1136 unsigned max_shader_engines;
1137 unsigned max_tile_pipes;
1138 unsigned max_cu_per_sh;
1139 unsigned max_sh_per_se;
1140 unsigned max_backends_per_se;
1141 unsigned max_texture_channel_caches;
1142 unsigned max_gprs;
1143 unsigned max_gs_threads;
1144 unsigned max_hw_contexts;
1145 unsigned sc_prim_fifo_size_frontend;
1146 unsigned sc_prim_fifo_size_backend;
1147 unsigned sc_hiz_tile_fifo_size;
1148 unsigned sc_earlyz_tile_fifo_size;
1149
1150 unsigned num_tile_pipes;
1151 unsigned backend_enable_mask;
1152 unsigned mem_max_burst_length_bytes;
1153 unsigned mem_row_size_in_kb;
1154 unsigned shader_engine_tile_size;
1155 unsigned num_gpus;
1156 unsigned multi_gpu_tile_size;
1157 unsigned mc_arb_ramcfg;
1158 unsigned gb_addr_config;
1159
1160 uint32_t tile_mode_array[32];
1161 uint32_t macrotile_mode_array[16];
1162 };
1163
1164 struct amdgpu_gfx {
1165 struct mutex gpu_clock_mutex;
1166 struct amdgpu_gca_config config;
1167 struct amdgpu_rlc rlc;
1168 struct amdgpu_mec mec;
1169 struct amdgpu_scratch scratch;
1170 const struct firmware *me_fw; /* ME firmware */
1171 uint32_t me_fw_version;
1172 const struct firmware *pfp_fw; /* PFP firmware */
1173 uint32_t pfp_fw_version;
1174 const struct firmware *ce_fw; /* CE firmware */
1175 uint32_t ce_fw_version;
1176 const struct firmware *rlc_fw; /* RLC firmware */
1177 uint32_t rlc_fw_version;
1178 const struct firmware *mec_fw; /* MEC firmware */
1179 uint32_t mec_fw_version;
1180 const struct firmware *mec2_fw; /* MEC2 firmware */
1181 uint32_t mec2_fw_version;
1182 uint32_t me_feature_version;
1183 uint32_t ce_feature_version;
1184 uint32_t pfp_feature_version;
1185 uint32_t rlc_feature_version;
1186 uint32_t mec_feature_version;
1187 uint32_t mec2_feature_version;
1188 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1189 unsigned num_gfx_rings;
1190 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1191 unsigned num_compute_rings;
1192 struct amdgpu_irq_src eop_irq;
1193 struct amdgpu_irq_src priv_reg_irq;
1194 struct amdgpu_irq_src priv_inst_irq;
1195 /* gfx status */
1196 uint32_t gfx_current_status;
1197 /* sync signal for const engine */
1198 unsigned ce_sync_offs;
1199 /* ce ram size*/
1200 unsigned ce_ram_size;
1201 };
1202
1203 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1204 unsigned size, struct amdgpu_ib *ib);
1205 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1206 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1207 struct amdgpu_ib *ib, void *owner);
1208 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1209 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1210 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1211 /* Ring access between begin & end cannot sleep */
1212 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1213 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1214 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1215 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1216 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1217 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1218 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1219 void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1220 bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1221 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1222 uint32_t **data);
1223 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1224 unsigned size, uint32_t *data);
1225 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1226 unsigned ring_size, u32 nop, u32 align_mask,
1227 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1228 enum amdgpu_ring_type ring_type);
1229 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1230
1231 /*
1232 * CS.
1233 */
1234 struct amdgpu_cs_chunk {
1235 uint32_t chunk_id;
1236 uint32_t length_dw;
1237 uint32_t *kdata;
1238 void __user *user_ptr;
1239 };
1240
1241 struct amdgpu_cs_parser {
1242 struct amdgpu_device *adev;
1243 struct drm_file *filp;
1244 struct amdgpu_ctx *ctx;
1245 struct amdgpu_bo_list *bo_list;
1246 /* chunks */
1247 unsigned nchunks;
1248 struct amdgpu_cs_chunk *chunks;
1249 /* relocations */
1250 struct amdgpu_bo_list_entry *vm_bos;
1251 struct list_head validated;
1252
1253 struct amdgpu_ib *ibs;
1254 uint32_t num_ibs;
1255
1256 struct ww_acquire_ctx ticket;
1257
1258 /* user fence */
1259 struct amdgpu_user_fence uf;
1260
1261 struct amdgpu_ring *ring;
1262 struct mutex job_lock;
1263 struct work_struct job_work;
1264 int (*prepare_job)(struct amdgpu_cs_parser *sched_job);
1265 int (*run_job)(struct amdgpu_cs_parser *sched_job);
1266 int (*free_job)(struct amdgpu_cs_parser *sched_job);
1267 struct amd_sched_fence *s_fence;
1268 };
1269
1270 struct amdgpu_job {
1271 struct amd_sched_job base;
1272 struct amdgpu_device *adev;
1273 struct amdgpu_ctx *ctx;
1274 struct drm_file *owner;
1275 struct amdgpu_ib *ibs;
1276 uint32_t num_ibs;
1277 struct mutex job_lock;
1278 struct amdgpu_user_fence uf;
1279 int (*free_job)(struct amdgpu_job *sched_job);
1280 };
1281
1282 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1283 {
1284 return p->ibs[ib_idx].ptr[idx];
1285 }
1286
1287 /*
1288 * Writeback
1289 */
1290 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1291
1292 struct amdgpu_wb {
1293 struct amdgpu_bo *wb_obj;
1294 volatile uint32_t *wb;
1295 uint64_t gpu_addr;
1296 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1297 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1298 };
1299
1300 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1301 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1302
1303 /**
1304 * struct amdgpu_pm - power management datas
1305 * It keeps track of various data needed to take powermanagement decision.
1306 */
1307
1308 enum amdgpu_pm_state_type {
1309 /* not used for dpm */
1310 POWER_STATE_TYPE_DEFAULT,
1311 POWER_STATE_TYPE_POWERSAVE,
1312 /* user selectable states */
1313 POWER_STATE_TYPE_BATTERY,
1314 POWER_STATE_TYPE_BALANCED,
1315 POWER_STATE_TYPE_PERFORMANCE,
1316 /* internal states */
1317 POWER_STATE_TYPE_INTERNAL_UVD,
1318 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1319 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1320 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1321 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1322 POWER_STATE_TYPE_INTERNAL_BOOT,
1323 POWER_STATE_TYPE_INTERNAL_THERMAL,
1324 POWER_STATE_TYPE_INTERNAL_ACPI,
1325 POWER_STATE_TYPE_INTERNAL_ULV,
1326 POWER_STATE_TYPE_INTERNAL_3DPERF,
1327 };
1328
1329 enum amdgpu_int_thermal_type {
1330 THERMAL_TYPE_NONE,
1331 THERMAL_TYPE_EXTERNAL,
1332 THERMAL_TYPE_EXTERNAL_GPIO,
1333 THERMAL_TYPE_RV6XX,
1334 THERMAL_TYPE_RV770,
1335 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1336 THERMAL_TYPE_EVERGREEN,
1337 THERMAL_TYPE_SUMO,
1338 THERMAL_TYPE_NI,
1339 THERMAL_TYPE_SI,
1340 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1341 THERMAL_TYPE_CI,
1342 THERMAL_TYPE_KV,
1343 };
1344
1345 enum amdgpu_dpm_auto_throttle_src {
1346 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1347 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1348 };
1349
1350 enum amdgpu_dpm_event_src {
1351 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1352 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1353 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1354 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1355 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1356 };
1357
1358 #define AMDGPU_MAX_VCE_LEVELS 6
1359
1360 enum amdgpu_vce_level {
1361 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1362 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1363 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1364 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1365 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1366 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1367 };
1368
1369 struct amdgpu_ps {
1370 u32 caps; /* vbios flags */
1371 u32 class; /* vbios flags */
1372 u32 class2; /* vbios flags */
1373 /* UVD clocks */
1374 u32 vclk;
1375 u32 dclk;
1376 /* VCE clocks */
1377 u32 evclk;
1378 u32 ecclk;
1379 bool vce_active;
1380 enum amdgpu_vce_level vce_level;
1381 /* asic priv */
1382 void *ps_priv;
1383 };
1384
1385 struct amdgpu_dpm_thermal {
1386 /* thermal interrupt work */
1387 struct work_struct work;
1388 /* low temperature threshold */
1389 int min_temp;
1390 /* high temperature threshold */
1391 int max_temp;
1392 /* was last interrupt low to high or high to low */
1393 bool high_to_low;
1394 /* interrupt source */
1395 struct amdgpu_irq_src irq;
1396 };
1397
1398 enum amdgpu_clk_action
1399 {
1400 AMDGPU_SCLK_UP = 1,
1401 AMDGPU_SCLK_DOWN
1402 };
1403
1404 struct amdgpu_blacklist_clocks
1405 {
1406 u32 sclk;
1407 u32 mclk;
1408 enum amdgpu_clk_action action;
1409 };
1410
1411 struct amdgpu_clock_and_voltage_limits {
1412 u32 sclk;
1413 u32 mclk;
1414 u16 vddc;
1415 u16 vddci;
1416 };
1417
1418 struct amdgpu_clock_array {
1419 u32 count;
1420 u32 *values;
1421 };
1422
1423 struct amdgpu_clock_voltage_dependency_entry {
1424 u32 clk;
1425 u16 v;
1426 };
1427
1428 struct amdgpu_clock_voltage_dependency_table {
1429 u32 count;
1430 struct amdgpu_clock_voltage_dependency_entry *entries;
1431 };
1432
1433 union amdgpu_cac_leakage_entry {
1434 struct {
1435 u16 vddc;
1436 u32 leakage;
1437 };
1438 struct {
1439 u16 vddc1;
1440 u16 vddc2;
1441 u16 vddc3;
1442 };
1443 };
1444
1445 struct amdgpu_cac_leakage_table {
1446 u32 count;
1447 union amdgpu_cac_leakage_entry *entries;
1448 };
1449
1450 struct amdgpu_phase_shedding_limits_entry {
1451 u16 voltage;
1452 u32 sclk;
1453 u32 mclk;
1454 };
1455
1456 struct amdgpu_phase_shedding_limits_table {
1457 u32 count;
1458 struct amdgpu_phase_shedding_limits_entry *entries;
1459 };
1460
1461 struct amdgpu_uvd_clock_voltage_dependency_entry {
1462 u32 vclk;
1463 u32 dclk;
1464 u16 v;
1465 };
1466
1467 struct amdgpu_uvd_clock_voltage_dependency_table {
1468 u8 count;
1469 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1470 };
1471
1472 struct amdgpu_vce_clock_voltage_dependency_entry {
1473 u32 ecclk;
1474 u32 evclk;
1475 u16 v;
1476 };
1477
1478 struct amdgpu_vce_clock_voltage_dependency_table {
1479 u8 count;
1480 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1481 };
1482
1483 struct amdgpu_ppm_table {
1484 u8 ppm_design;
1485 u16 cpu_core_number;
1486 u32 platform_tdp;
1487 u32 small_ac_platform_tdp;
1488 u32 platform_tdc;
1489 u32 small_ac_platform_tdc;
1490 u32 apu_tdp;
1491 u32 dgpu_tdp;
1492 u32 dgpu_ulv_power;
1493 u32 tj_max;
1494 };
1495
1496 struct amdgpu_cac_tdp_table {
1497 u16 tdp;
1498 u16 configurable_tdp;
1499 u16 tdc;
1500 u16 battery_power_limit;
1501 u16 small_power_limit;
1502 u16 low_cac_leakage;
1503 u16 high_cac_leakage;
1504 u16 maximum_power_delivery_limit;
1505 };
1506
1507 struct amdgpu_dpm_dynamic_state {
1508 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1509 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1510 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1511 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1512 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1513 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1514 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1515 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1516 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1517 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1518 struct amdgpu_clock_array valid_sclk_values;
1519 struct amdgpu_clock_array valid_mclk_values;
1520 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1521 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1522 u32 mclk_sclk_ratio;
1523 u32 sclk_mclk_delta;
1524 u16 vddc_vddci_delta;
1525 u16 min_vddc_for_pcie_gen2;
1526 struct amdgpu_cac_leakage_table cac_leakage_table;
1527 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1528 struct amdgpu_ppm_table *ppm_table;
1529 struct amdgpu_cac_tdp_table *cac_tdp_table;
1530 };
1531
1532 struct amdgpu_dpm_fan {
1533 u16 t_min;
1534 u16 t_med;
1535 u16 t_high;
1536 u16 pwm_min;
1537 u16 pwm_med;
1538 u16 pwm_high;
1539 u8 t_hyst;
1540 u32 cycle_delay;
1541 u16 t_max;
1542 u8 control_mode;
1543 u16 default_max_fan_pwm;
1544 u16 default_fan_output_sensitivity;
1545 u16 fan_output_sensitivity;
1546 bool ucode_fan_control;
1547 };
1548
1549 enum amdgpu_pcie_gen {
1550 AMDGPU_PCIE_GEN1 = 0,
1551 AMDGPU_PCIE_GEN2 = 1,
1552 AMDGPU_PCIE_GEN3 = 2,
1553 AMDGPU_PCIE_GEN_INVALID = 0xffff
1554 };
1555
1556 enum amdgpu_dpm_forced_level {
1557 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1558 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1559 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1560 };
1561
1562 struct amdgpu_vce_state {
1563 /* vce clocks */
1564 u32 evclk;
1565 u32 ecclk;
1566 /* gpu clocks */
1567 u32 sclk;
1568 u32 mclk;
1569 u8 clk_idx;
1570 u8 pstate;
1571 };
1572
1573 struct amdgpu_dpm_funcs {
1574 int (*get_temperature)(struct amdgpu_device *adev);
1575 int (*pre_set_power_state)(struct amdgpu_device *adev);
1576 int (*set_power_state)(struct amdgpu_device *adev);
1577 void (*post_set_power_state)(struct amdgpu_device *adev);
1578 void (*display_configuration_changed)(struct amdgpu_device *adev);
1579 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1580 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1581 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1582 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1583 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1584 bool (*vblank_too_short)(struct amdgpu_device *adev);
1585 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1586 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1587 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1588 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1589 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1590 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1591 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1592 };
1593
1594 struct amdgpu_dpm {
1595 struct amdgpu_ps *ps;
1596 /* number of valid power states */
1597 int num_ps;
1598 /* current power state that is active */
1599 struct amdgpu_ps *current_ps;
1600 /* requested power state */
1601 struct amdgpu_ps *requested_ps;
1602 /* boot up power state */
1603 struct amdgpu_ps *boot_ps;
1604 /* default uvd power state */
1605 struct amdgpu_ps *uvd_ps;
1606 /* vce requirements */
1607 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1608 enum amdgpu_vce_level vce_level;
1609 enum amdgpu_pm_state_type state;
1610 enum amdgpu_pm_state_type user_state;
1611 u32 platform_caps;
1612 u32 voltage_response_time;
1613 u32 backbias_response_time;
1614 void *priv;
1615 u32 new_active_crtcs;
1616 int new_active_crtc_count;
1617 u32 current_active_crtcs;
1618 int current_active_crtc_count;
1619 struct amdgpu_dpm_dynamic_state dyn_state;
1620 struct amdgpu_dpm_fan fan;
1621 u32 tdp_limit;
1622 u32 near_tdp_limit;
1623 u32 near_tdp_limit_adjusted;
1624 u32 sq_ramping_threshold;
1625 u32 cac_leakage;
1626 u16 tdp_od_limit;
1627 u32 tdp_adjustment;
1628 u16 load_line_slope;
1629 bool power_control;
1630 bool ac_power;
1631 /* special states active */
1632 bool thermal_active;
1633 bool uvd_active;
1634 bool vce_active;
1635 /* thermal handling */
1636 struct amdgpu_dpm_thermal thermal;
1637 /* forced levels */
1638 enum amdgpu_dpm_forced_level forced_level;
1639 };
1640
1641 struct amdgpu_pm {
1642 struct mutex mutex;
1643 u32 current_sclk;
1644 u32 current_mclk;
1645 u32 default_sclk;
1646 u32 default_mclk;
1647 struct amdgpu_i2c_chan *i2c_bus;
1648 /* internal thermal controller on rv6xx+ */
1649 enum amdgpu_int_thermal_type int_thermal_type;
1650 struct device *int_hwmon_dev;
1651 /* fan control parameters */
1652 bool no_fan;
1653 u8 fan_pulses_per_revolution;
1654 u8 fan_min_rpm;
1655 u8 fan_max_rpm;
1656 /* dpm */
1657 bool dpm_enabled;
1658 struct amdgpu_dpm dpm;
1659 const struct firmware *fw; /* SMC firmware */
1660 uint32_t fw_version;
1661 const struct amdgpu_dpm_funcs *funcs;
1662 };
1663
1664 /*
1665 * UVD
1666 */
1667 #define AMDGPU_MAX_UVD_HANDLES 10
1668 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1669 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1670 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1671
1672 struct amdgpu_uvd {
1673 struct amdgpu_bo *vcpu_bo;
1674 void *cpu_addr;
1675 uint64_t gpu_addr;
1676 void *saved_bo;
1677 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1678 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1679 struct delayed_work idle_work;
1680 const struct firmware *fw; /* UVD firmware */
1681 struct amdgpu_ring ring;
1682 struct amdgpu_irq_src irq;
1683 bool address_64_bit;
1684 };
1685
1686 /*
1687 * VCE
1688 */
1689 #define AMDGPU_MAX_VCE_HANDLES 16
1690 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1691
1692 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1693 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1694
1695 struct amdgpu_vce {
1696 struct amdgpu_bo *vcpu_bo;
1697 uint64_t gpu_addr;
1698 unsigned fw_version;
1699 unsigned fb_version;
1700 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1701 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1702 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1703 struct delayed_work idle_work;
1704 const struct firmware *fw; /* VCE firmware */
1705 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1706 struct amdgpu_irq_src irq;
1707 unsigned harvest_config;
1708 };
1709
1710 /*
1711 * SDMA
1712 */
1713 struct amdgpu_sdma {
1714 /* SDMA firmware */
1715 const struct firmware *fw;
1716 uint32_t fw_version;
1717 uint32_t feature_version;
1718
1719 struct amdgpu_ring ring;
1720 };
1721
1722 /*
1723 * Firmware
1724 */
1725 struct amdgpu_firmware {
1726 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1727 bool smu_load;
1728 struct amdgpu_bo *fw_buf;
1729 unsigned int fw_size;
1730 };
1731
1732 /*
1733 * Benchmarking
1734 */
1735 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1736
1737
1738 /*
1739 * Testing
1740 */
1741 void amdgpu_test_moves(struct amdgpu_device *adev);
1742 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1743 struct amdgpu_ring *cpA,
1744 struct amdgpu_ring *cpB);
1745 void amdgpu_test_syncing(struct amdgpu_device *adev);
1746
1747 /*
1748 * MMU Notifier
1749 */
1750 #if defined(CONFIG_MMU_NOTIFIER)
1751 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1752 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1753 #else
1754 static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1755 {
1756 return -ENODEV;
1757 }
1758 static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1759 #endif
1760
1761 /*
1762 * Debugfs
1763 */
1764 struct amdgpu_debugfs {
1765 struct drm_info_list *files;
1766 unsigned num_files;
1767 };
1768
1769 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1770 struct drm_info_list *files,
1771 unsigned nfiles);
1772 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1773
1774 #if defined(CONFIG_DEBUG_FS)
1775 int amdgpu_debugfs_init(struct drm_minor *minor);
1776 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1777 #endif
1778
1779 /*
1780 * amdgpu smumgr functions
1781 */
1782 struct amdgpu_smumgr_funcs {
1783 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1784 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1785 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1786 };
1787
1788 /*
1789 * amdgpu smumgr
1790 */
1791 struct amdgpu_smumgr {
1792 struct amdgpu_bo *toc_buf;
1793 struct amdgpu_bo *smu_buf;
1794 /* asic priv smu data */
1795 void *priv;
1796 spinlock_t smu_lock;
1797 /* smumgr functions */
1798 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1799 /* ucode loading complete flag */
1800 uint32_t fw_flags;
1801 };
1802
1803 /*
1804 * ASIC specific register table accessible by UMD
1805 */
1806 struct amdgpu_allowed_register_entry {
1807 uint32_t reg_offset;
1808 bool untouched;
1809 bool grbm_indexed;
1810 };
1811
1812 struct amdgpu_cu_info {
1813 uint32_t number; /* total active CU number */
1814 uint32_t ao_cu_mask;
1815 uint32_t bitmap[4][4];
1816 };
1817
1818
1819 /*
1820 * ASIC specific functions.
1821 */
1822 struct amdgpu_asic_funcs {
1823 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1824 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1825 u32 sh_num, u32 reg_offset, u32 *value);
1826 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1827 int (*reset)(struct amdgpu_device *adev);
1828 /* wait for mc_idle */
1829 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1830 /* get the reference clock */
1831 u32 (*get_xclk)(struct amdgpu_device *adev);
1832 /* get the gpu clock counter */
1833 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1834 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1835 /* MM block clocks */
1836 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1837 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1838 };
1839
1840 /*
1841 * IOCTL.
1842 */
1843 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1844 struct drm_file *filp);
1845 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1846 struct drm_file *filp);
1847
1848 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1849 struct drm_file *filp);
1850 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1851 struct drm_file *filp);
1852 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1853 struct drm_file *filp);
1854 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1855 struct drm_file *filp);
1856 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1857 struct drm_file *filp);
1858 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1859 struct drm_file *filp);
1860 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1861 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1862
1863 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1864 struct drm_file *filp);
1865
1866 /* VRAM scratch page for HDP bug, default vram page */
1867 struct amdgpu_vram_scratch {
1868 struct amdgpu_bo *robj;
1869 volatile uint32_t *ptr;
1870 u64 gpu_addr;
1871 };
1872
1873 /*
1874 * ACPI
1875 */
1876 struct amdgpu_atif_notification_cfg {
1877 bool enabled;
1878 int command_code;
1879 };
1880
1881 struct amdgpu_atif_notifications {
1882 bool display_switch;
1883 bool expansion_mode_change;
1884 bool thermal_state;
1885 bool forced_power_state;
1886 bool system_power_state;
1887 bool display_conf_change;
1888 bool px_gfx_switch;
1889 bool brightness_change;
1890 bool dgpu_display_event;
1891 };
1892
1893 struct amdgpu_atif_functions {
1894 bool system_params;
1895 bool sbios_requests;
1896 bool select_active_disp;
1897 bool lid_state;
1898 bool get_tv_standard;
1899 bool set_tv_standard;
1900 bool get_panel_expansion_mode;
1901 bool set_panel_expansion_mode;
1902 bool temperature_change;
1903 bool graphics_device_types;
1904 };
1905
1906 struct amdgpu_atif {
1907 struct amdgpu_atif_notifications notifications;
1908 struct amdgpu_atif_functions functions;
1909 struct amdgpu_atif_notification_cfg notification_cfg;
1910 struct amdgpu_encoder *encoder_for_bl;
1911 };
1912
1913 struct amdgpu_atcs_functions {
1914 bool get_ext_state;
1915 bool pcie_perf_req;
1916 bool pcie_dev_rdy;
1917 bool pcie_bus_width;
1918 };
1919
1920 struct amdgpu_atcs {
1921 struct amdgpu_atcs_functions functions;
1922 };
1923
1924 /*
1925 * CGS
1926 */
1927 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1928 void amdgpu_cgs_destroy_device(void *cgs_device);
1929
1930
1931 /*
1932 * Core structure, functions and helpers.
1933 */
1934 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1935 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1936
1937 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1938 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1939
1940 struct amdgpu_ip_block_status {
1941 bool valid;
1942 bool sw;
1943 bool hw;
1944 };
1945
1946 struct amdgpu_device {
1947 struct device *dev;
1948 struct drm_device *ddev;
1949 struct pci_dev *pdev;
1950 struct rw_semaphore exclusive_lock;
1951
1952 /* ASIC */
1953 enum amd_asic_type asic_type;
1954 uint32_t family;
1955 uint32_t rev_id;
1956 uint32_t external_rev_id;
1957 unsigned long flags;
1958 int usec_timeout;
1959 const struct amdgpu_asic_funcs *asic_funcs;
1960 bool shutdown;
1961 bool suspend;
1962 bool need_dma32;
1963 bool accel_working;
1964 bool needs_reset;
1965 struct work_struct reset_work;
1966 struct notifier_block acpi_nb;
1967 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1968 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1969 unsigned debugfs_count;
1970 #if defined(CONFIG_DEBUG_FS)
1971 struct dentry *debugfs_regs;
1972 #endif
1973 struct amdgpu_atif atif;
1974 struct amdgpu_atcs atcs;
1975 struct mutex srbm_mutex;
1976 /* GRBM index mutex. Protects concurrent access to GRBM index */
1977 struct mutex grbm_idx_mutex;
1978 struct dev_pm_domain vga_pm_domain;
1979 bool have_disp_power_ref;
1980
1981 /* BIOS */
1982 uint8_t *bios;
1983 bool is_atom_bios;
1984 uint16_t bios_header_start;
1985 struct amdgpu_bo *stollen_vga_memory;
1986 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1987
1988 /* Register/doorbell mmio */
1989 resource_size_t rmmio_base;
1990 resource_size_t rmmio_size;
1991 void __iomem *rmmio;
1992 /* protects concurrent MM_INDEX/DATA based register access */
1993 spinlock_t mmio_idx_lock;
1994 /* protects concurrent SMC based register access */
1995 spinlock_t smc_idx_lock;
1996 amdgpu_rreg_t smc_rreg;
1997 amdgpu_wreg_t smc_wreg;
1998 /* protects concurrent PCIE register access */
1999 spinlock_t pcie_idx_lock;
2000 amdgpu_rreg_t pcie_rreg;
2001 amdgpu_wreg_t pcie_wreg;
2002 /* protects concurrent UVD register access */
2003 spinlock_t uvd_ctx_idx_lock;
2004 amdgpu_rreg_t uvd_ctx_rreg;
2005 amdgpu_wreg_t uvd_ctx_wreg;
2006 /* protects concurrent DIDT register access */
2007 spinlock_t didt_idx_lock;
2008 amdgpu_rreg_t didt_rreg;
2009 amdgpu_wreg_t didt_wreg;
2010 /* protects concurrent ENDPOINT (audio) register access */
2011 spinlock_t audio_endpt_idx_lock;
2012 amdgpu_block_rreg_t audio_endpt_rreg;
2013 amdgpu_block_wreg_t audio_endpt_wreg;
2014 void __iomem *rio_mem;
2015 resource_size_t rio_mem_size;
2016 struct amdgpu_doorbell doorbell;
2017
2018 /* clock/pll info */
2019 struct amdgpu_clock clock;
2020
2021 /* MC */
2022 struct amdgpu_mc mc;
2023 struct amdgpu_gart gart;
2024 struct amdgpu_dummy_page dummy_page;
2025 struct amdgpu_vm_manager vm_manager;
2026
2027 /* memory management */
2028 struct amdgpu_mman mman;
2029 struct amdgpu_gem gem;
2030 struct amdgpu_vram_scratch vram_scratch;
2031 struct amdgpu_wb wb;
2032 atomic64_t vram_usage;
2033 atomic64_t vram_vis_usage;
2034 atomic64_t gtt_usage;
2035 atomic64_t num_bytes_moved;
2036 atomic_t gpu_reset_counter;
2037
2038 /* display */
2039 struct amdgpu_mode_info mode_info;
2040 struct work_struct hotplug_work;
2041 struct amdgpu_irq_src crtc_irq;
2042 struct amdgpu_irq_src pageflip_irq;
2043 struct amdgpu_irq_src hpd_irq;
2044
2045 /* rings */
2046 unsigned fence_context;
2047 struct mutex ring_lock;
2048 unsigned num_rings;
2049 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2050 bool ib_pool_ready;
2051 struct amdgpu_sa_manager ring_tmp_bo;
2052
2053 /* interrupts */
2054 struct amdgpu_irq irq;
2055
2056 /* dpm */
2057 struct amdgpu_pm pm;
2058 u32 cg_flags;
2059 u32 pg_flags;
2060
2061 /* amdgpu smumgr */
2062 struct amdgpu_smumgr smu;
2063
2064 /* gfx */
2065 struct amdgpu_gfx gfx;
2066
2067 /* sdma */
2068 struct amdgpu_sdma sdma[2];
2069 struct amdgpu_irq_src sdma_trap_irq;
2070 struct amdgpu_irq_src sdma_illegal_inst_irq;
2071
2072 /* uvd */
2073 bool has_uvd;
2074 struct amdgpu_uvd uvd;
2075
2076 /* vce */
2077 struct amdgpu_vce vce;
2078
2079 /* firmwares */
2080 struct amdgpu_firmware firmware;
2081
2082 /* GDS */
2083 struct amdgpu_gds gds;
2084
2085 const struct amdgpu_ip_block_version *ip_blocks;
2086 int num_ip_blocks;
2087 struct amdgpu_ip_block_status *ip_block_status;
2088 struct mutex mn_lock;
2089 DECLARE_HASHTABLE(mn_hash, 7);
2090
2091 /* tracking pinned memory */
2092 u64 vram_pin_size;
2093 u64 gart_pin_size;
2094
2095 /* amdkfd interface */
2096 struct kfd_dev *kfd;
2097
2098 /* kernel conext for IB submission */
2099 struct amdgpu_ctx kernel_ctx;
2100 };
2101
2102 bool amdgpu_device_is_px(struct drm_device *dev);
2103 int amdgpu_device_init(struct amdgpu_device *adev,
2104 struct drm_device *ddev,
2105 struct pci_dev *pdev,
2106 uint32_t flags);
2107 void amdgpu_device_fini(struct amdgpu_device *adev);
2108 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2109
2110 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2111 bool always_indirect);
2112 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2113 bool always_indirect);
2114 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2115 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2116
2117 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2118 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2119
2120 /*
2121 * Cast helper
2122 */
2123 extern const struct fence_ops amdgpu_fence_ops;
2124 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2125 {
2126 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2127
2128 if (__f->base.ops == &amdgpu_fence_ops)
2129 return __f;
2130
2131 return NULL;
2132 }
2133
2134 /*
2135 * Registers read & write functions.
2136 */
2137 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2138 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2139 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2140 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2141 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2142 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2143 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2144 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2145 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2146 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2147 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2148 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2149 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2150 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2151 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2152 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2153 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2154 #define WREG32_P(reg, val, mask) \
2155 do { \
2156 uint32_t tmp_ = RREG32(reg); \
2157 tmp_ &= (mask); \
2158 tmp_ |= ((val) & ~(mask)); \
2159 WREG32(reg, tmp_); \
2160 } while (0)
2161 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2162 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2163 #define WREG32_PLL_P(reg, val, mask) \
2164 do { \
2165 uint32_t tmp_ = RREG32_PLL(reg); \
2166 tmp_ &= (mask); \
2167 tmp_ |= ((val) & ~(mask)); \
2168 WREG32_PLL(reg, tmp_); \
2169 } while (0)
2170 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2171 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2172 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2173
2174 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2175 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2176
2177 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2178 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2179
2180 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2181 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2182 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2183
2184 #define REG_GET_FIELD(value, reg, field) \
2185 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2186
2187 /*
2188 * BIOS helpers.
2189 */
2190 #define RBIOS8(i) (adev->bios[i])
2191 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2192 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2193
2194 /*
2195 * RING helpers.
2196 */
2197 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2198 {
2199 if (ring->count_dw <= 0)
2200 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2201 ring->ring[ring->wptr++] = v;
2202 ring->wptr &= ring->ptr_mask;
2203 ring->count_dw--;
2204 ring->ring_free_dw--;
2205 }
2206
2207 /*
2208 * ASICs macro.
2209 */
2210 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2211 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2212 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2213 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2214 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2215 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2216 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2217 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2218 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2219 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2220 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2221 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2222 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2223 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2224 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2225 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2226 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2227 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2228 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2229 #define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2230 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2231 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2232 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2233 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2234 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2235 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2236 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2237 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2238 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2239 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2240 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2241 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2242 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2243 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2244 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2245 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2246 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2247 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2248 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2249 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2250 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2251 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2252 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2253 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2254 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2255 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2256 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2257 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2258 #define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2259 #define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2260 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2261 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2262 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2263 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2264 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2265 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2266 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2267 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2268 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2269 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2270 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2271 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2272 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2273 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2274 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2275 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2276 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2277 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2278
2279 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2280
2281 /* Common functions */
2282 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2283 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2284 bool amdgpu_card_posted(struct amdgpu_device *adev);
2285 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2286 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2287 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
2288 struct drm_file *filp,
2289 struct amdgpu_ctx *ctx,
2290 struct amdgpu_ib *ibs,
2291 uint32_t num_ibs);
2292
2293 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2294 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2295 u32 ip_instance, u32 ring,
2296 struct amdgpu_ring **out_ring);
2297 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2298 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2299 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2300 uint32_t flags);
2301 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2302 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2303 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2304 struct ttm_mem_reg *mem);
2305 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2306 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2307 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2308 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2309 const u32 *registers,
2310 const u32 array_size);
2311
2312 bool amdgpu_device_is_px(struct drm_device *dev);
2313 /* atpx handler */
2314 #if defined(CONFIG_VGA_SWITCHEROO)
2315 void amdgpu_register_atpx_handler(void);
2316 void amdgpu_unregister_atpx_handler(void);
2317 #else
2318 static inline void amdgpu_register_atpx_handler(void) {}
2319 static inline void amdgpu_unregister_atpx_handler(void) {}
2320 #endif
2321
2322 /*
2323 * KMS
2324 */
2325 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2326 extern int amdgpu_max_kms_ioctl;
2327
2328 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2329 int amdgpu_driver_unload_kms(struct drm_device *dev);
2330 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2331 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2332 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2333 struct drm_file *file_priv);
2334 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2335 struct drm_file *file_priv);
2336 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2337 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2338 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2339 int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2340 void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2341 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2342 int *max_error,
2343 struct timeval *vblank_time,
2344 unsigned flags);
2345 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2346 unsigned long arg);
2347
2348 /*
2349 * vm
2350 */
2351 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2352 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2353 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2354 struct amdgpu_vm *vm,
2355 struct list_head *head);
2356 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
2357 struct amdgpu_sync *sync);
2358 void amdgpu_vm_flush(struct amdgpu_ring *ring,
2359 struct amdgpu_vm *vm,
2360 struct amdgpu_fence *updates);
2361 void amdgpu_vm_fence(struct amdgpu_device *adev,
2362 struct amdgpu_vm *vm,
2363 struct amdgpu_fence *fence);
2364 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2365 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2366 struct amdgpu_vm *vm);
2367 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2368 struct amdgpu_vm *vm);
2369 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
2370 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
2371 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2372 struct amdgpu_bo_va *bo_va,
2373 struct ttm_mem_reg *mem);
2374 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2375 struct amdgpu_bo *bo);
2376 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2377 struct amdgpu_bo *bo);
2378 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2379 struct amdgpu_vm *vm,
2380 struct amdgpu_bo *bo);
2381 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2382 struct amdgpu_bo_va *bo_va,
2383 uint64_t addr, uint64_t offset,
2384 uint64_t size, uint32_t flags);
2385 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2386 struct amdgpu_bo_va *bo_va,
2387 uint64_t addr);
2388 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2389 struct amdgpu_bo_va *bo_va);
2390
2391 /*
2392 * functions used by amdgpu_encoder.c
2393 */
2394 struct amdgpu_afmt_acr {
2395 u32 clock;
2396
2397 int n_32khz;
2398 int cts_32khz;
2399
2400 int n_44_1khz;
2401 int cts_44_1khz;
2402
2403 int n_48khz;
2404 int cts_48khz;
2405
2406 };
2407
2408 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2409
2410 /* amdgpu_acpi.c */
2411 #if defined(CONFIG_ACPI)
2412 int amdgpu_acpi_init(struct amdgpu_device *adev);
2413 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2414 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2415 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2416 u8 perf_req, bool advertise);
2417 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2418 #else
2419 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2420 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2421 #endif
2422
2423 struct amdgpu_bo_va_mapping *
2424 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2425 uint64_t addr, struct amdgpu_bo **bo);
2426
2427 #include "amdgpu_object.h"
2428
2429 #endif
Linux kernel - Deliverables
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