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drm/amdgpu: clean up non-scheduler code path (v2)
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
56
57 #include "gpu_scheduler.h"
58
59 /*
60 * Modules parameters.
61 */
62 extern int amdgpu_modeset;
63 extern int amdgpu_vram_limit;
64 extern int amdgpu_gart_size;
65 extern int amdgpu_benchmarking;
66 extern int amdgpu_testing;
67 extern int amdgpu_audio;
68 extern int amdgpu_disp_priority;
69 extern int amdgpu_hw_i2c;
70 extern int amdgpu_pcie_gen2;
71 extern int amdgpu_msi;
72 extern int amdgpu_lockup_timeout;
73 extern int amdgpu_dpm;
74 extern int amdgpu_smc_load_fw;
75 extern int amdgpu_aspm;
76 extern int amdgpu_runtime_pm;
77 extern int amdgpu_hard_reset;
78 extern unsigned amdgpu_ip_block_mask;
79 extern int amdgpu_bapm;
80 extern int amdgpu_deep_color;
81 extern int amdgpu_vm_size;
82 extern int amdgpu_vm_block_size;
83 extern int amdgpu_vm_fault_stop;
84 extern int amdgpu_vm_debug;
85 extern int amdgpu_sched_jobs;
86 extern int amdgpu_sched_hw_submission;
87 extern int amdgpu_enable_semaphores;
88 extern int amdgpu_powerplay;
89
90 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
91 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
92 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
93 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
94 #define AMDGPU_IB_POOL_SIZE 16
95 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
96 #define AMDGPUFB_CONN_LIMIT 4
97 #define AMDGPU_BIOS_NUM_SCRATCH 8
98
99 /* max number of rings */
100 #define AMDGPU_MAX_RINGS 16
101 #define AMDGPU_MAX_GFX_RINGS 1
102 #define AMDGPU_MAX_COMPUTE_RINGS 8
103 #define AMDGPU_MAX_VCE_RINGS 2
104
105 /* max number of IP instances */
106 #define AMDGPU_MAX_SDMA_INSTANCES 2
107
108 /* number of hw syncs before falling back on blocking */
109 #define AMDGPU_NUM_SYNCS 4
110
111 /* hardcode that limit for now */
112 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
113
114 /* hard reset data */
115 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
116
117 /* reset flags */
118 #define AMDGPU_RESET_GFX (1 << 0)
119 #define AMDGPU_RESET_COMPUTE (1 << 1)
120 #define AMDGPU_RESET_DMA (1 << 2)
121 #define AMDGPU_RESET_CP (1 << 3)
122 #define AMDGPU_RESET_GRBM (1 << 4)
123 #define AMDGPU_RESET_DMA1 (1 << 5)
124 #define AMDGPU_RESET_RLC (1 << 6)
125 #define AMDGPU_RESET_SEM (1 << 7)
126 #define AMDGPU_RESET_IH (1 << 8)
127 #define AMDGPU_RESET_VMC (1 << 9)
128 #define AMDGPU_RESET_MC (1 << 10)
129 #define AMDGPU_RESET_DISPLAY (1 << 11)
130 #define AMDGPU_RESET_UVD (1 << 12)
131 #define AMDGPU_RESET_VCE (1 << 13)
132 #define AMDGPU_RESET_VCE1 (1 << 14)
133
134 /* CG block flags */
135 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
136 #define AMDGPU_CG_BLOCK_MC (1 << 1)
137 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
138 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
139 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
140 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
141 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
142
143 /* CG flags */
144 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
145 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
146 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
147 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
148 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
149 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
150 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
151 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
152 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
153 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
154 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
155 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
156 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
157 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
158 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
159 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
160 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
161
162 /* PG flags */
163 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
164 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
165 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
166 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
167 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
168 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
169 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
170 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
171 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
172 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
173 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
174
175 /* GFX current status */
176 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
177 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
178 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
179 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
180 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
181
182 /* max cursor sizes (in pixels) */
183 #define CIK_CURSOR_WIDTH 128
184 #define CIK_CURSOR_HEIGHT 128
185
186 struct amdgpu_device;
187 struct amdgpu_fence;
188 struct amdgpu_ib;
189 struct amdgpu_vm;
190 struct amdgpu_ring;
191 struct amdgpu_semaphore;
192 struct amdgpu_cs_parser;
193 struct amdgpu_job;
194 struct amdgpu_irq_src;
195 struct amdgpu_fpriv;
196
197 enum amdgpu_cp_irq {
198 AMDGPU_CP_IRQ_GFX_EOP = 0,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
206 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
207
208 AMDGPU_CP_IRQ_LAST
209 };
210
211 enum amdgpu_sdma_irq {
212 AMDGPU_SDMA_IRQ_TRAP0 = 0,
213 AMDGPU_SDMA_IRQ_TRAP1,
214
215 AMDGPU_SDMA_IRQ_LAST
216 };
217
218 enum amdgpu_thermal_irq {
219 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
220 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
221
222 AMDGPU_THERMAL_IRQ_LAST
223 };
224
225 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
226 enum amd_ip_block_type block_type,
227 enum amd_clockgating_state state);
228 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
229 enum amd_ip_block_type block_type,
230 enum amd_powergating_state state);
231
232 struct amdgpu_ip_block_version {
233 enum amd_ip_block_type type;
234 u32 major;
235 u32 minor;
236 u32 rev;
237 const struct amd_ip_funcs *funcs;
238 };
239
240 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
241 enum amd_ip_block_type type,
242 u32 major, u32 minor);
243
244 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
245 struct amdgpu_device *adev,
246 enum amd_ip_block_type type);
247
248 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
249 struct amdgpu_buffer_funcs {
250 /* maximum bytes in a single operation */
251 uint32_t copy_max_bytes;
252
253 /* number of dw to reserve per operation */
254 unsigned copy_num_dw;
255
256 /* used for buffer migration */
257 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
258 /* src addr in bytes */
259 uint64_t src_offset,
260 /* dst addr in bytes */
261 uint64_t dst_offset,
262 /* number of byte to transfer */
263 uint32_t byte_count);
264
265 /* maximum bytes in a single operation */
266 uint32_t fill_max_bytes;
267
268 /* number of dw to reserve per operation */
269 unsigned fill_num_dw;
270
271 /* used for buffer clearing */
272 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
273 /* value to write to memory */
274 uint32_t src_data,
275 /* dst addr in bytes */
276 uint64_t dst_offset,
277 /* number of byte to fill */
278 uint32_t byte_count);
279 };
280
281 /* provided by hw blocks that can write ptes, e.g., sdma */
282 struct amdgpu_vm_pte_funcs {
283 /* copy pte entries from GART */
284 void (*copy_pte)(struct amdgpu_ib *ib,
285 uint64_t pe, uint64_t src,
286 unsigned count);
287 /* write pte one entry at a time with addr mapping */
288 void (*write_pte)(struct amdgpu_ib *ib,
289 uint64_t pe,
290 uint64_t addr, unsigned count,
291 uint32_t incr, uint32_t flags);
292 /* for linear pte/pde updates without addr mapping */
293 void (*set_pte_pde)(struct amdgpu_ib *ib,
294 uint64_t pe,
295 uint64_t addr, unsigned count,
296 uint32_t incr, uint32_t flags);
297 /* pad the indirect buffer to the necessary number of dw */
298 void (*pad_ib)(struct amdgpu_ib *ib);
299 };
300
301 /* provided by the gmc block */
302 struct amdgpu_gart_funcs {
303 /* flush the vm tlb via mmio */
304 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
305 uint32_t vmid);
306 /* write pte/pde updates using the cpu */
307 int (*set_pte_pde)(struct amdgpu_device *adev,
308 void *cpu_pt_addr, /* cpu addr of page table */
309 uint32_t gpu_page_idx, /* pte/pde to update */
310 uint64_t addr, /* addr to write into pte/pde */
311 uint32_t flags); /* access flags */
312 };
313
314 /* provided by the ih block */
315 struct amdgpu_ih_funcs {
316 /* ring read/write ptr handling, called from interrupt context */
317 u32 (*get_wptr)(struct amdgpu_device *adev);
318 void (*decode_iv)(struct amdgpu_device *adev,
319 struct amdgpu_iv_entry *entry);
320 void (*set_rptr)(struct amdgpu_device *adev);
321 };
322
323 /* provided by hw blocks that expose a ring buffer for commands */
324 struct amdgpu_ring_funcs {
325 /* ring read/write ptr handling */
326 u32 (*get_rptr)(struct amdgpu_ring *ring);
327 u32 (*get_wptr)(struct amdgpu_ring *ring);
328 void (*set_wptr)(struct amdgpu_ring *ring);
329 /* validating and patching of IBs */
330 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
331 /* command emit functions */
332 void (*emit_ib)(struct amdgpu_ring *ring,
333 struct amdgpu_ib *ib);
334 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
335 uint64_t seq, unsigned flags);
336 bool (*emit_semaphore)(struct amdgpu_ring *ring,
337 struct amdgpu_semaphore *semaphore,
338 bool emit_wait);
339 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
340 uint64_t pd_addr);
341 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
342 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
343 uint32_t gds_base, uint32_t gds_size,
344 uint32_t gws_base, uint32_t gws_size,
345 uint32_t oa_base, uint32_t oa_size);
346 /* testing functions */
347 int (*test_ring)(struct amdgpu_ring *ring);
348 int (*test_ib)(struct amdgpu_ring *ring);
349 /* insert NOP packets */
350 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
351 };
352
353 /*
354 * BIOS.
355 */
356 bool amdgpu_get_bios(struct amdgpu_device *adev);
357 bool amdgpu_read_bios(struct amdgpu_device *adev);
358
359 /*
360 * Dummy page
361 */
362 struct amdgpu_dummy_page {
363 struct page *page;
364 dma_addr_t addr;
365 };
366 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
367 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
368
369
370 /*
371 * Clocks
372 */
373
374 #define AMDGPU_MAX_PPLL 3
375
376 struct amdgpu_clock {
377 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
378 struct amdgpu_pll spll;
379 struct amdgpu_pll mpll;
380 /* 10 Khz units */
381 uint32_t default_mclk;
382 uint32_t default_sclk;
383 uint32_t default_dispclk;
384 uint32_t current_dispclk;
385 uint32_t dp_extclk;
386 uint32_t max_pixel_clock;
387 };
388
389 /*
390 * Fences.
391 */
392 struct amdgpu_fence_driver {
393 uint64_t gpu_addr;
394 volatile uint32_t *cpu_addr;
395 /* sync_seq is protected by ring emission lock */
396 uint64_t sync_seq[AMDGPU_MAX_RINGS];
397 atomic64_t last_seq;
398 bool initialized;
399 struct amdgpu_irq_src *irq_src;
400 unsigned irq_type;
401 struct timer_list fallback_timer;
402 wait_queue_head_t fence_queue;
403 };
404
405 /* some special values for the owner field */
406 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
407 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
408
409 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
410 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
411
412 struct amdgpu_fence {
413 struct fence base;
414
415 /* RB, DMA, etc. */
416 struct amdgpu_ring *ring;
417 uint64_t seq;
418
419 /* filp or special value for fence creator */
420 void *owner;
421
422 wait_queue_t fence_wake;
423 };
424
425 struct amdgpu_user_fence {
426 /* write-back bo */
427 struct amdgpu_bo *bo;
428 /* write-back address offset to bo start */
429 uint32_t offset;
430 };
431
432 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
433 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
434 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
435
436 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
437 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
438 struct amdgpu_irq_src *irq_src,
439 unsigned irq_type);
440 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
441 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
442 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
443 struct amdgpu_fence **fence);
444 void amdgpu_fence_process(struct amdgpu_ring *ring);
445 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
446 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
447 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
448
449 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
450 struct amdgpu_ring *ring);
451 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
452 struct amdgpu_ring *ring);
453
454 /*
455 * TTM.
456 */
457 struct amdgpu_mman {
458 struct ttm_bo_global_ref bo_global_ref;
459 struct drm_global_reference mem_global_ref;
460 struct ttm_bo_device bdev;
461 bool mem_global_referenced;
462 bool initialized;
463
464 #if defined(CONFIG_DEBUG_FS)
465 struct dentry *vram;
466 struct dentry *gtt;
467 #endif
468
469 /* buffer handling */
470 const struct amdgpu_buffer_funcs *buffer_funcs;
471 struct amdgpu_ring *buffer_funcs_ring;
472 };
473
474 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
475 uint64_t src_offset,
476 uint64_t dst_offset,
477 uint32_t byte_count,
478 struct reservation_object *resv,
479 struct fence **fence);
480 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
481
482 struct amdgpu_bo_list_entry {
483 struct amdgpu_bo *robj;
484 struct ttm_validate_buffer tv;
485 struct amdgpu_bo_va *bo_va;
486 uint32_t priority;
487 };
488
489 struct amdgpu_bo_va_mapping {
490 struct list_head list;
491 struct interval_tree_node it;
492 uint64_t offset;
493 uint32_t flags;
494 };
495
496 /* bo virtual addresses in a specific vm */
497 struct amdgpu_bo_va {
498 struct mutex mutex;
499 /* protected by bo being reserved */
500 struct list_head bo_list;
501 struct fence *last_pt_update;
502 unsigned ref_count;
503
504 /* protected by vm mutex and spinlock */
505 struct list_head vm_status;
506
507 /* mappings for this bo_va */
508 struct list_head invalids;
509 struct list_head valids;
510
511 /* constant after initialization */
512 struct amdgpu_vm *vm;
513 struct amdgpu_bo *bo;
514 };
515
516 #define AMDGPU_GEM_DOMAIN_MAX 0x3
517
518 struct amdgpu_bo {
519 /* Protected by gem.mutex */
520 struct list_head list;
521 /* Protected by tbo.reserved */
522 u32 prefered_domains;
523 u32 allowed_domains;
524 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
525 struct ttm_placement placement;
526 struct ttm_buffer_object tbo;
527 struct ttm_bo_kmap_obj kmap;
528 u64 flags;
529 unsigned pin_count;
530 void *kptr;
531 u64 tiling_flags;
532 u64 metadata_flags;
533 void *metadata;
534 u32 metadata_size;
535 /* list of all virtual address to which this bo
536 * is associated to
537 */
538 struct list_head va;
539 /* Constant after initialization */
540 struct amdgpu_device *adev;
541 struct drm_gem_object gem_base;
542 struct amdgpu_bo *parent;
543
544 struct ttm_bo_kmap_obj dma_buf_vmap;
545 pid_t pid;
546 struct amdgpu_mn *mn;
547 struct list_head mn_list;
548 };
549 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
550
551 void amdgpu_gem_object_free(struct drm_gem_object *obj);
552 int amdgpu_gem_object_open(struct drm_gem_object *obj,
553 struct drm_file *file_priv);
554 void amdgpu_gem_object_close(struct drm_gem_object *obj,
555 struct drm_file *file_priv);
556 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
557 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
558 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
559 struct dma_buf_attachment *attach,
560 struct sg_table *sg);
561 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
562 struct drm_gem_object *gobj,
563 int flags);
564 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
565 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
566 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
567 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
568 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
569 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
570
571 /* sub-allocation manager, it has to be protected by another lock.
572 * By conception this is an helper for other part of the driver
573 * like the indirect buffer or semaphore, which both have their
574 * locking.
575 *
576 * Principe is simple, we keep a list of sub allocation in offset
577 * order (first entry has offset == 0, last entry has the highest
578 * offset).
579 *
580 * When allocating new object we first check if there is room at
581 * the end total_size - (last_object_offset + last_object_size) >=
582 * alloc_size. If so we allocate new object there.
583 *
584 * When there is not enough room at the end, we start waiting for
585 * each sub object until we reach object_offset+object_size >=
586 * alloc_size, this object then become the sub object we return.
587 *
588 * Alignment can't be bigger than page size.
589 *
590 * Hole are not considered for allocation to keep things simple.
591 * Assumption is that there won't be hole (all object on same
592 * alignment).
593 */
594 struct amdgpu_sa_manager {
595 wait_queue_head_t wq;
596 struct amdgpu_bo *bo;
597 struct list_head *hole;
598 struct list_head flist[AMDGPU_MAX_RINGS];
599 struct list_head olist;
600 unsigned size;
601 uint64_t gpu_addr;
602 void *cpu_ptr;
603 uint32_t domain;
604 uint32_t align;
605 };
606
607 struct amdgpu_sa_bo;
608
609 /* sub-allocation buffer */
610 struct amdgpu_sa_bo {
611 struct list_head olist;
612 struct list_head flist;
613 struct amdgpu_sa_manager *manager;
614 unsigned soffset;
615 unsigned eoffset;
616 struct fence *fence;
617 };
618
619 /*
620 * GEM objects.
621 */
622 struct amdgpu_gem {
623 struct mutex mutex;
624 struct list_head objects;
625 };
626
627 int amdgpu_gem_init(struct amdgpu_device *adev);
628 void amdgpu_gem_fini(struct amdgpu_device *adev);
629 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
630 int alignment, u32 initial_domain,
631 u64 flags, bool kernel,
632 struct drm_gem_object **obj);
633
634 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
635 struct drm_device *dev,
636 struct drm_mode_create_dumb *args);
637 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
638 struct drm_device *dev,
639 uint32_t handle, uint64_t *offset_p);
640 /*
641 * Synchronization
642 */
643 struct amdgpu_sync {
644 struct fence *sync_to[AMDGPU_MAX_RINGS];
645 DECLARE_HASHTABLE(fences, 4);
646 struct fence *last_vm_update;
647 };
648
649 void amdgpu_sync_create(struct amdgpu_sync *sync);
650 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
651 struct fence *f);
652 int amdgpu_sync_resv(struct amdgpu_device *adev,
653 struct amdgpu_sync *sync,
654 struct reservation_object *resv,
655 void *owner);
656 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
657 int amdgpu_sync_wait(struct amdgpu_sync *sync);
658 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
659 struct fence *fence);
660
661 /*
662 * GART structures, functions & helpers
663 */
664 struct amdgpu_mc;
665
666 #define AMDGPU_GPU_PAGE_SIZE 4096
667 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
668 #define AMDGPU_GPU_PAGE_SHIFT 12
669 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
670
671 struct amdgpu_gart {
672 dma_addr_t table_addr;
673 struct amdgpu_bo *robj;
674 void *ptr;
675 unsigned num_gpu_pages;
676 unsigned num_cpu_pages;
677 unsigned table_size;
678 struct page **pages;
679 dma_addr_t *pages_addr;
680 bool ready;
681 const struct amdgpu_gart_funcs *gart_funcs;
682 };
683
684 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
685 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
686 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
687 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
688 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
689 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
690 int amdgpu_gart_init(struct amdgpu_device *adev);
691 void amdgpu_gart_fini(struct amdgpu_device *adev);
692 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
693 int pages);
694 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
695 int pages, struct page **pagelist,
696 dma_addr_t *dma_addr, uint32_t flags);
697
698 /*
699 * GPU MC structures, functions & helpers
700 */
701 struct amdgpu_mc {
702 resource_size_t aper_size;
703 resource_size_t aper_base;
704 resource_size_t agp_base;
705 /* for some chips with <= 32MB we need to lie
706 * about vram size near mc fb location */
707 u64 mc_vram_size;
708 u64 visible_vram_size;
709 u64 gtt_size;
710 u64 gtt_start;
711 u64 gtt_end;
712 u64 vram_start;
713 u64 vram_end;
714 unsigned vram_width;
715 u64 real_vram_size;
716 int vram_mtrr;
717 u64 gtt_base_align;
718 u64 mc_mask;
719 const struct firmware *fw; /* MC firmware */
720 uint32_t fw_version;
721 struct amdgpu_irq_src vm_fault;
722 uint32_t vram_type;
723 };
724
725 /*
726 * GPU doorbell structures, functions & helpers
727 */
728 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
729 {
730 AMDGPU_DOORBELL_KIQ = 0x000,
731 AMDGPU_DOORBELL_HIQ = 0x001,
732 AMDGPU_DOORBELL_DIQ = 0x002,
733 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
734 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
735 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
736 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
737 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
738 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
739 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
740 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
741 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
742 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
743 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
744 AMDGPU_DOORBELL_IH = 0x1E8,
745 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
746 AMDGPU_DOORBELL_INVALID = 0xFFFF
747 } AMDGPU_DOORBELL_ASSIGNMENT;
748
749 struct amdgpu_doorbell {
750 /* doorbell mmio */
751 resource_size_t base;
752 resource_size_t size;
753 u32 __iomem *ptr;
754 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
755 };
756
757 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
758 phys_addr_t *aperture_base,
759 size_t *aperture_size,
760 size_t *start_offset);
761
762 /*
763 * IRQS.
764 */
765
766 struct amdgpu_flip_work {
767 struct work_struct flip_work;
768 struct work_struct unpin_work;
769 struct amdgpu_device *adev;
770 int crtc_id;
771 uint64_t base;
772 struct drm_pending_vblank_event *event;
773 struct amdgpu_bo *old_rbo;
774 struct fence *excl;
775 unsigned shared_count;
776 struct fence **shared;
777 };
778
779
780 /*
781 * CP & rings.
782 */
783
784 struct amdgpu_ib {
785 struct amdgpu_sa_bo *sa_bo;
786 uint32_t length_dw;
787 uint64_t gpu_addr;
788 uint32_t *ptr;
789 struct amdgpu_ring *ring;
790 struct amdgpu_fence *fence;
791 struct amdgpu_user_fence *user;
792 struct amdgpu_vm *vm;
793 struct amdgpu_ctx *ctx;
794 struct amdgpu_sync sync;
795 uint32_t gds_base, gds_size;
796 uint32_t gws_base, gws_size;
797 uint32_t oa_base, oa_size;
798 uint32_t flags;
799 /* resulting sequence number */
800 uint64_t sequence;
801 };
802
803 enum amdgpu_ring_type {
804 AMDGPU_RING_TYPE_GFX,
805 AMDGPU_RING_TYPE_COMPUTE,
806 AMDGPU_RING_TYPE_SDMA,
807 AMDGPU_RING_TYPE_UVD,
808 AMDGPU_RING_TYPE_VCE
809 };
810
811 extern struct amd_sched_backend_ops amdgpu_sched_ops;
812
813 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
814 struct amdgpu_ring *ring,
815 struct amdgpu_ib *ibs,
816 unsigned num_ibs,
817 int (*free_job)(struct amdgpu_job *),
818 void *owner,
819 struct fence **fence);
820
821 struct amdgpu_ring {
822 struct amdgpu_device *adev;
823 const struct amdgpu_ring_funcs *funcs;
824 struct amdgpu_fence_driver fence_drv;
825 struct amd_gpu_scheduler sched;
826
827 spinlock_t fence_lock;
828 struct mutex *ring_lock;
829 struct amdgpu_bo *ring_obj;
830 volatile uint32_t *ring;
831 unsigned rptr_offs;
832 u64 next_rptr_gpu_addr;
833 volatile u32 *next_rptr_cpu_addr;
834 unsigned wptr;
835 unsigned wptr_old;
836 unsigned ring_size;
837 unsigned ring_free_dw;
838 int count_dw;
839 uint64_t gpu_addr;
840 uint32_t align_mask;
841 uint32_t ptr_mask;
842 bool ready;
843 u32 nop;
844 u32 idx;
845 u64 last_semaphore_signal_addr;
846 u64 last_semaphore_wait_addr;
847 u32 me;
848 u32 pipe;
849 u32 queue;
850 struct amdgpu_bo *mqd_obj;
851 u32 doorbell_index;
852 bool use_doorbell;
853 unsigned wptr_offs;
854 unsigned next_rptr_offs;
855 unsigned fence_offs;
856 struct amdgpu_ctx *current_ctx;
857 enum amdgpu_ring_type type;
858 char name[16];
859 bool is_pte_ring;
860 };
861
862 /*
863 * VM
864 */
865
866 /* maximum number of VMIDs */
867 #define AMDGPU_NUM_VM 16
868
869 /* number of entries in page table */
870 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
871
872 /* PTBs (Page Table Blocks) need to be aligned to 32K */
873 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
874 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
875 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
876
877 #define AMDGPU_PTE_VALID (1 << 0)
878 #define AMDGPU_PTE_SYSTEM (1 << 1)
879 #define AMDGPU_PTE_SNOOPED (1 << 2)
880
881 /* VI only */
882 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
883
884 #define AMDGPU_PTE_READABLE (1 << 5)
885 #define AMDGPU_PTE_WRITEABLE (1 << 6)
886
887 /* PTE (Page Table Entry) fragment field for different page sizes */
888 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
889 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
890 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
891
892 /* How to programm VM fault handling */
893 #define AMDGPU_VM_FAULT_STOP_NEVER 0
894 #define AMDGPU_VM_FAULT_STOP_FIRST 1
895 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
896
897 struct amdgpu_vm_pt {
898 struct amdgpu_bo_list_entry entry;
899 uint64_t addr;
900 };
901
902 struct amdgpu_vm_id {
903 unsigned id;
904 uint64_t pd_gpu_addr;
905 /* last flushed PD/PT update */
906 struct fence *flushed_updates;
907 };
908
909 struct amdgpu_vm {
910 /* tree of virtual addresses mapped */
911 spinlock_t it_lock;
912 struct rb_root va;
913
914 /* protecting invalidated */
915 spinlock_t status_lock;
916
917 /* BOs moved, but not yet updated in the PT */
918 struct list_head invalidated;
919
920 /* BOs cleared in the PT because of a move */
921 struct list_head cleared;
922
923 /* BO mappings freed, but not yet updated in the PT */
924 struct list_head freed;
925
926 /* contains the page directory */
927 struct amdgpu_bo *page_directory;
928 unsigned max_pde_used;
929 struct fence *page_directory_fence;
930
931 /* array of page tables, one for each page directory entry */
932 struct amdgpu_vm_pt *page_tables;
933
934 /* for id and flush management per ring */
935 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
936
937 /* protecting freed */
938 spinlock_t freed_lock;
939 };
940
941 struct amdgpu_vm_manager {
942 struct {
943 struct fence *active;
944 atomic_long_t owner;
945 } ids[AMDGPU_NUM_VM];
946
947 uint32_t max_pfn;
948 /* number of VMIDs */
949 unsigned nvm;
950 /* vram base address for page table entry */
951 u64 vram_base_offset;
952 /* is vm enabled? */
953 bool enabled;
954 /* vm pte handling */
955 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
956 struct amdgpu_ring *vm_pte_funcs_ring;
957 };
958
959 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
960 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
961 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
962 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
963 struct list_head *validated,
964 struct amdgpu_bo_list_entry *entry);
965 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
966 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
967 struct amdgpu_vm *vm);
968 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
969 struct amdgpu_sync *sync);
970 void amdgpu_vm_flush(struct amdgpu_ring *ring,
971 struct amdgpu_vm *vm,
972 struct fence *updates);
973 void amdgpu_vm_fence(struct amdgpu_device *adev,
974 struct amdgpu_vm *vm,
975 struct fence *fence);
976 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
977 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
978 struct amdgpu_vm *vm);
979 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
980 struct amdgpu_vm *vm);
981 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
982 struct amdgpu_sync *sync);
983 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
984 struct amdgpu_bo_va *bo_va,
985 struct ttm_mem_reg *mem);
986 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
987 struct amdgpu_bo *bo);
988 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
989 struct amdgpu_bo *bo);
990 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
991 struct amdgpu_vm *vm,
992 struct amdgpu_bo *bo);
993 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
994 struct amdgpu_bo_va *bo_va,
995 uint64_t addr, uint64_t offset,
996 uint64_t size, uint32_t flags);
997 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
998 struct amdgpu_bo_va *bo_va,
999 uint64_t addr);
1000 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1001 struct amdgpu_bo_va *bo_va);
1002 int amdgpu_vm_free_job(struct amdgpu_job *job);
1003
1004 /*
1005 * context related structures
1006 */
1007
1008 struct amdgpu_ctx_ring {
1009 uint64_t sequence;
1010 struct fence **fences;
1011 struct amd_sched_entity entity;
1012 };
1013
1014 struct amdgpu_ctx {
1015 struct kref refcount;
1016 struct amdgpu_device *adev;
1017 unsigned reset_counter;
1018 spinlock_t ring_lock;
1019 struct fence **fences;
1020 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
1021 };
1022
1023 struct amdgpu_ctx_mgr {
1024 struct amdgpu_device *adev;
1025 struct mutex lock;
1026 /* protected by lock */
1027 struct idr ctx_handles;
1028 };
1029
1030 int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
1031 struct amdgpu_ctx *ctx);
1032 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
1033
1034 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1035 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1036
1037 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1038 struct fence *fence);
1039 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1040 struct amdgpu_ring *ring, uint64_t seq);
1041
1042 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1043 struct drm_file *filp);
1044
1045 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1046 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1047
1048 /*
1049 * file private structure
1050 */
1051
1052 struct amdgpu_fpriv {
1053 struct amdgpu_vm vm;
1054 struct mutex bo_list_lock;
1055 struct idr bo_list_handles;
1056 struct amdgpu_ctx_mgr ctx_mgr;
1057 };
1058
1059 /*
1060 * residency list
1061 */
1062
1063 struct amdgpu_bo_list {
1064 struct mutex lock;
1065 struct amdgpu_bo *gds_obj;
1066 struct amdgpu_bo *gws_obj;
1067 struct amdgpu_bo *oa_obj;
1068 bool has_userptr;
1069 unsigned num_entries;
1070 struct amdgpu_bo_list_entry *array;
1071 };
1072
1073 struct amdgpu_bo_list *
1074 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1075 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1076 struct list_head *validated);
1077 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1078 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1079
1080 /*
1081 * GFX stuff
1082 */
1083 #include "clearstate_defs.h"
1084
1085 struct amdgpu_rlc {
1086 /* for power gating */
1087 struct amdgpu_bo *save_restore_obj;
1088 uint64_t save_restore_gpu_addr;
1089 volatile uint32_t *sr_ptr;
1090 const u32 *reg_list;
1091 u32 reg_list_size;
1092 /* for clear state */
1093 struct amdgpu_bo *clear_state_obj;
1094 uint64_t clear_state_gpu_addr;
1095 volatile uint32_t *cs_ptr;
1096 const struct cs_section_def *cs_data;
1097 u32 clear_state_size;
1098 /* for cp tables */
1099 struct amdgpu_bo *cp_table_obj;
1100 uint64_t cp_table_gpu_addr;
1101 volatile uint32_t *cp_table_ptr;
1102 u32 cp_table_size;
1103 };
1104
1105 struct amdgpu_mec {
1106 struct amdgpu_bo *hpd_eop_obj;
1107 u64 hpd_eop_gpu_addr;
1108 u32 num_pipe;
1109 u32 num_mec;
1110 u32 num_queue;
1111 };
1112
1113 /*
1114 * GPU scratch registers structures, functions & helpers
1115 */
1116 struct amdgpu_scratch {
1117 unsigned num_reg;
1118 uint32_t reg_base;
1119 bool free[32];
1120 uint32_t reg[32];
1121 };
1122
1123 /*
1124 * GFX configurations
1125 */
1126 struct amdgpu_gca_config {
1127 unsigned max_shader_engines;
1128 unsigned max_tile_pipes;
1129 unsigned max_cu_per_sh;
1130 unsigned max_sh_per_se;
1131 unsigned max_backends_per_se;
1132 unsigned max_texture_channel_caches;
1133 unsigned max_gprs;
1134 unsigned max_gs_threads;
1135 unsigned max_hw_contexts;
1136 unsigned sc_prim_fifo_size_frontend;
1137 unsigned sc_prim_fifo_size_backend;
1138 unsigned sc_hiz_tile_fifo_size;
1139 unsigned sc_earlyz_tile_fifo_size;
1140
1141 unsigned num_tile_pipes;
1142 unsigned backend_enable_mask;
1143 unsigned mem_max_burst_length_bytes;
1144 unsigned mem_row_size_in_kb;
1145 unsigned shader_engine_tile_size;
1146 unsigned num_gpus;
1147 unsigned multi_gpu_tile_size;
1148 unsigned mc_arb_ramcfg;
1149 unsigned gb_addr_config;
1150
1151 uint32_t tile_mode_array[32];
1152 uint32_t macrotile_mode_array[16];
1153 };
1154
1155 struct amdgpu_gfx {
1156 struct mutex gpu_clock_mutex;
1157 struct amdgpu_gca_config config;
1158 struct amdgpu_rlc rlc;
1159 struct amdgpu_mec mec;
1160 struct amdgpu_scratch scratch;
1161 const struct firmware *me_fw; /* ME firmware */
1162 uint32_t me_fw_version;
1163 const struct firmware *pfp_fw; /* PFP firmware */
1164 uint32_t pfp_fw_version;
1165 const struct firmware *ce_fw; /* CE firmware */
1166 uint32_t ce_fw_version;
1167 const struct firmware *rlc_fw; /* RLC firmware */
1168 uint32_t rlc_fw_version;
1169 const struct firmware *mec_fw; /* MEC firmware */
1170 uint32_t mec_fw_version;
1171 const struct firmware *mec2_fw; /* MEC2 firmware */
1172 uint32_t mec2_fw_version;
1173 uint32_t me_feature_version;
1174 uint32_t ce_feature_version;
1175 uint32_t pfp_feature_version;
1176 uint32_t rlc_feature_version;
1177 uint32_t mec_feature_version;
1178 uint32_t mec2_feature_version;
1179 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1180 unsigned num_gfx_rings;
1181 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1182 unsigned num_compute_rings;
1183 struct amdgpu_irq_src eop_irq;
1184 struct amdgpu_irq_src priv_reg_irq;
1185 struct amdgpu_irq_src priv_inst_irq;
1186 /* gfx status */
1187 uint32_t gfx_current_status;
1188 /* ce ram size*/
1189 unsigned ce_ram_size;
1190 };
1191
1192 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1193 unsigned size, struct amdgpu_ib *ib);
1194 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1195 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1196 struct amdgpu_ib *ib, void *owner);
1197 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1198 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1199 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1200 /* Ring access between begin & end cannot sleep */
1201 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1202 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1203 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1204 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1205 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1206 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1207 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1208 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1209 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1210 uint32_t **data);
1211 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1212 unsigned size, uint32_t *data);
1213 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1214 unsigned ring_size, u32 nop, u32 align_mask,
1215 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1216 enum amdgpu_ring_type ring_type);
1217 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1218 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
1219
1220 /*
1221 * CS.
1222 */
1223 struct amdgpu_cs_chunk {
1224 uint32_t chunk_id;
1225 uint32_t length_dw;
1226 uint32_t *kdata;
1227 };
1228
1229 struct amdgpu_cs_parser {
1230 struct amdgpu_device *adev;
1231 struct drm_file *filp;
1232 struct amdgpu_ctx *ctx;
1233
1234 /* chunks */
1235 unsigned nchunks;
1236 struct amdgpu_cs_chunk *chunks;
1237
1238 /* indirect buffers */
1239 uint32_t num_ibs;
1240 struct amdgpu_ib *ibs;
1241
1242 /* buffer objects */
1243 struct ww_acquire_ctx ticket;
1244 struct amdgpu_bo_list *bo_list;
1245 struct amdgpu_bo_list_entry vm_pd;
1246 struct list_head validated;
1247 struct fence *fence;
1248 uint64_t bytes_moved_threshold;
1249 uint64_t bytes_moved;
1250
1251 /* user fence */
1252 struct amdgpu_user_fence uf;
1253 struct amdgpu_bo_list_entry uf_entry;
1254 };
1255
1256 struct amdgpu_job {
1257 struct amd_sched_job base;
1258 struct amdgpu_device *adev;
1259 struct amdgpu_ib *ibs;
1260 uint32_t num_ibs;
1261 void *owner;
1262 struct amdgpu_user_fence uf;
1263 int (*free_job)(struct amdgpu_job *job);
1264 };
1265 #define to_amdgpu_job(sched_job) \
1266 container_of((sched_job), struct amdgpu_job, base)
1267
1268 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1269 {
1270 return p->ibs[ib_idx].ptr[idx];
1271 }
1272
1273 /*
1274 * Writeback
1275 */
1276 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1277
1278 struct amdgpu_wb {
1279 struct amdgpu_bo *wb_obj;
1280 volatile uint32_t *wb;
1281 uint64_t gpu_addr;
1282 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1283 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1284 };
1285
1286 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1287 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1288
1289
1290
1291 enum amdgpu_int_thermal_type {
1292 THERMAL_TYPE_NONE,
1293 THERMAL_TYPE_EXTERNAL,
1294 THERMAL_TYPE_EXTERNAL_GPIO,
1295 THERMAL_TYPE_RV6XX,
1296 THERMAL_TYPE_RV770,
1297 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1298 THERMAL_TYPE_EVERGREEN,
1299 THERMAL_TYPE_SUMO,
1300 THERMAL_TYPE_NI,
1301 THERMAL_TYPE_SI,
1302 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1303 THERMAL_TYPE_CI,
1304 THERMAL_TYPE_KV,
1305 };
1306
1307 enum amdgpu_dpm_auto_throttle_src {
1308 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1309 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1310 };
1311
1312 enum amdgpu_dpm_event_src {
1313 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1314 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1315 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1316 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1317 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1318 };
1319
1320 #define AMDGPU_MAX_VCE_LEVELS 6
1321
1322 enum amdgpu_vce_level {
1323 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1324 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1325 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1326 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1327 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1328 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1329 };
1330
1331 struct amdgpu_ps {
1332 u32 caps; /* vbios flags */
1333 u32 class; /* vbios flags */
1334 u32 class2; /* vbios flags */
1335 /* UVD clocks */
1336 u32 vclk;
1337 u32 dclk;
1338 /* VCE clocks */
1339 u32 evclk;
1340 u32 ecclk;
1341 bool vce_active;
1342 enum amdgpu_vce_level vce_level;
1343 /* asic priv */
1344 void *ps_priv;
1345 };
1346
1347 struct amdgpu_dpm_thermal {
1348 /* thermal interrupt work */
1349 struct work_struct work;
1350 /* low temperature threshold */
1351 int min_temp;
1352 /* high temperature threshold */
1353 int max_temp;
1354 /* was last interrupt low to high or high to low */
1355 bool high_to_low;
1356 /* interrupt source */
1357 struct amdgpu_irq_src irq;
1358 };
1359
1360 enum amdgpu_clk_action
1361 {
1362 AMDGPU_SCLK_UP = 1,
1363 AMDGPU_SCLK_DOWN
1364 };
1365
1366 struct amdgpu_blacklist_clocks
1367 {
1368 u32 sclk;
1369 u32 mclk;
1370 enum amdgpu_clk_action action;
1371 };
1372
1373 struct amdgpu_clock_and_voltage_limits {
1374 u32 sclk;
1375 u32 mclk;
1376 u16 vddc;
1377 u16 vddci;
1378 };
1379
1380 struct amdgpu_clock_array {
1381 u32 count;
1382 u32 *values;
1383 };
1384
1385 struct amdgpu_clock_voltage_dependency_entry {
1386 u32 clk;
1387 u16 v;
1388 };
1389
1390 struct amdgpu_clock_voltage_dependency_table {
1391 u32 count;
1392 struct amdgpu_clock_voltage_dependency_entry *entries;
1393 };
1394
1395 union amdgpu_cac_leakage_entry {
1396 struct {
1397 u16 vddc;
1398 u32 leakage;
1399 };
1400 struct {
1401 u16 vddc1;
1402 u16 vddc2;
1403 u16 vddc3;
1404 };
1405 };
1406
1407 struct amdgpu_cac_leakage_table {
1408 u32 count;
1409 union amdgpu_cac_leakage_entry *entries;
1410 };
1411
1412 struct amdgpu_phase_shedding_limits_entry {
1413 u16 voltage;
1414 u32 sclk;
1415 u32 mclk;
1416 };
1417
1418 struct amdgpu_phase_shedding_limits_table {
1419 u32 count;
1420 struct amdgpu_phase_shedding_limits_entry *entries;
1421 };
1422
1423 struct amdgpu_uvd_clock_voltage_dependency_entry {
1424 u32 vclk;
1425 u32 dclk;
1426 u16 v;
1427 };
1428
1429 struct amdgpu_uvd_clock_voltage_dependency_table {
1430 u8 count;
1431 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1432 };
1433
1434 struct amdgpu_vce_clock_voltage_dependency_entry {
1435 u32 ecclk;
1436 u32 evclk;
1437 u16 v;
1438 };
1439
1440 struct amdgpu_vce_clock_voltage_dependency_table {
1441 u8 count;
1442 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1443 };
1444
1445 struct amdgpu_ppm_table {
1446 u8 ppm_design;
1447 u16 cpu_core_number;
1448 u32 platform_tdp;
1449 u32 small_ac_platform_tdp;
1450 u32 platform_tdc;
1451 u32 small_ac_platform_tdc;
1452 u32 apu_tdp;
1453 u32 dgpu_tdp;
1454 u32 dgpu_ulv_power;
1455 u32 tj_max;
1456 };
1457
1458 struct amdgpu_cac_tdp_table {
1459 u16 tdp;
1460 u16 configurable_tdp;
1461 u16 tdc;
1462 u16 battery_power_limit;
1463 u16 small_power_limit;
1464 u16 low_cac_leakage;
1465 u16 high_cac_leakage;
1466 u16 maximum_power_delivery_limit;
1467 };
1468
1469 struct amdgpu_dpm_dynamic_state {
1470 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1471 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1472 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1473 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1474 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1475 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1476 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1477 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1478 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1479 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1480 struct amdgpu_clock_array valid_sclk_values;
1481 struct amdgpu_clock_array valid_mclk_values;
1482 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1483 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1484 u32 mclk_sclk_ratio;
1485 u32 sclk_mclk_delta;
1486 u16 vddc_vddci_delta;
1487 u16 min_vddc_for_pcie_gen2;
1488 struct amdgpu_cac_leakage_table cac_leakage_table;
1489 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1490 struct amdgpu_ppm_table *ppm_table;
1491 struct amdgpu_cac_tdp_table *cac_tdp_table;
1492 };
1493
1494 struct amdgpu_dpm_fan {
1495 u16 t_min;
1496 u16 t_med;
1497 u16 t_high;
1498 u16 pwm_min;
1499 u16 pwm_med;
1500 u16 pwm_high;
1501 u8 t_hyst;
1502 u32 cycle_delay;
1503 u16 t_max;
1504 u8 control_mode;
1505 u16 default_max_fan_pwm;
1506 u16 default_fan_output_sensitivity;
1507 u16 fan_output_sensitivity;
1508 bool ucode_fan_control;
1509 };
1510
1511 enum amdgpu_pcie_gen {
1512 AMDGPU_PCIE_GEN1 = 0,
1513 AMDGPU_PCIE_GEN2 = 1,
1514 AMDGPU_PCIE_GEN3 = 2,
1515 AMDGPU_PCIE_GEN_INVALID = 0xffff
1516 };
1517
1518 enum amdgpu_dpm_forced_level {
1519 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1520 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1521 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1522 };
1523
1524 struct amdgpu_vce_state {
1525 /* vce clocks */
1526 u32 evclk;
1527 u32 ecclk;
1528 /* gpu clocks */
1529 u32 sclk;
1530 u32 mclk;
1531 u8 clk_idx;
1532 u8 pstate;
1533 };
1534
1535 struct amdgpu_dpm_funcs {
1536 int (*get_temperature)(struct amdgpu_device *adev);
1537 int (*pre_set_power_state)(struct amdgpu_device *adev);
1538 int (*set_power_state)(struct amdgpu_device *adev);
1539 void (*post_set_power_state)(struct amdgpu_device *adev);
1540 void (*display_configuration_changed)(struct amdgpu_device *adev);
1541 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1542 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1543 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1544 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1545 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1546 bool (*vblank_too_short)(struct amdgpu_device *adev);
1547 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1548 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1549 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1550 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1551 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1552 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1553 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1554 };
1555
1556 struct amdgpu_dpm {
1557 struct amdgpu_ps *ps;
1558 /* number of valid power states */
1559 int num_ps;
1560 /* current power state that is active */
1561 struct amdgpu_ps *current_ps;
1562 /* requested power state */
1563 struct amdgpu_ps *requested_ps;
1564 /* boot up power state */
1565 struct amdgpu_ps *boot_ps;
1566 /* default uvd power state */
1567 struct amdgpu_ps *uvd_ps;
1568 /* vce requirements */
1569 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1570 enum amdgpu_vce_level vce_level;
1571 enum amd_pm_state_type state;
1572 enum amd_pm_state_type user_state;
1573 u32 platform_caps;
1574 u32 voltage_response_time;
1575 u32 backbias_response_time;
1576 void *priv;
1577 u32 new_active_crtcs;
1578 int new_active_crtc_count;
1579 u32 current_active_crtcs;
1580 int current_active_crtc_count;
1581 struct amdgpu_dpm_dynamic_state dyn_state;
1582 struct amdgpu_dpm_fan fan;
1583 u32 tdp_limit;
1584 u32 near_tdp_limit;
1585 u32 near_tdp_limit_adjusted;
1586 u32 sq_ramping_threshold;
1587 u32 cac_leakage;
1588 u16 tdp_od_limit;
1589 u32 tdp_adjustment;
1590 u16 load_line_slope;
1591 bool power_control;
1592 bool ac_power;
1593 /* special states active */
1594 bool thermal_active;
1595 bool uvd_active;
1596 bool vce_active;
1597 /* thermal handling */
1598 struct amdgpu_dpm_thermal thermal;
1599 /* forced levels */
1600 enum amdgpu_dpm_forced_level forced_level;
1601 };
1602
1603 struct amdgpu_pm {
1604 struct mutex mutex;
1605 u32 current_sclk;
1606 u32 current_mclk;
1607 u32 default_sclk;
1608 u32 default_mclk;
1609 struct amdgpu_i2c_chan *i2c_bus;
1610 /* internal thermal controller on rv6xx+ */
1611 enum amdgpu_int_thermal_type int_thermal_type;
1612 struct device *int_hwmon_dev;
1613 /* fan control parameters */
1614 bool no_fan;
1615 u8 fan_pulses_per_revolution;
1616 u8 fan_min_rpm;
1617 u8 fan_max_rpm;
1618 /* dpm */
1619 bool dpm_enabled;
1620 bool sysfs_initialized;
1621 struct amdgpu_dpm dpm;
1622 const struct firmware *fw; /* SMC firmware */
1623 uint32_t fw_version;
1624 const struct amdgpu_dpm_funcs *funcs;
1625 uint32_t pcie_gen_mask;
1626 uint32_t pcie_mlw_mask;
1627 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
1628 };
1629
1630 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1631
1632 /*
1633 * UVD
1634 */
1635 #define AMDGPU_MAX_UVD_HANDLES 10
1636 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1637 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1638 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1639
1640 struct amdgpu_uvd {
1641 struct amdgpu_bo *vcpu_bo;
1642 void *cpu_addr;
1643 uint64_t gpu_addr;
1644 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1645 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1646 struct delayed_work idle_work;
1647 const struct firmware *fw; /* UVD firmware */
1648 struct amdgpu_ring ring;
1649 struct amdgpu_irq_src irq;
1650 bool address_64_bit;
1651 };
1652
1653 /*
1654 * VCE
1655 */
1656 #define AMDGPU_MAX_VCE_HANDLES 16
1657 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1658
1659 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1660 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1661
1662 struct amdgpu_vce {
1663 struct amdgpu_bo *vcpu_bo;
1664 uint64_t gpu_addr;
1665 unsigned fw_version;
1666 unsigned fb_version;
1667 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1668 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1669 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1670 struct delayed_work idle_work;
1671 const struct firmware *fw; /* VCE firmware */
1672 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1673 struct amdgpu_irq_src irq;
1674 unsigned harvest_config;
1675 };
1676
1677 /*
1678 * SDMA
1679 */
1680 struct amdgpu_sdma_instance {
1681 /* SDMA firmware */
1682 const struct firmware *fw;
1683 uint32_t fw_version;
1684 uint32_t feature_version;
1685
1686 struct amdgpu_ring ring;
1687 bool burst_nop;
1688 };
1689
1690 struct amdgpu_sdma {
1691 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1692 struct amdgpu_irq_src trap_irq;
1693 struct amdgpu_irq_src illegal_inst_irq;
1694 int num_instances;
1695 };
1696
1697 /*
1698 * Firmware
1699 */
1700 struct amdgpu_firmware {
1701 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1702 bool smu_load;
1703 struct amdgpu_bo *fw_buf;
1704 unsigned int fw_size;
1705 };
1706
1707 /*
1708 * Benchmarking
1709 */
1710 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1711
1712
1713 /*
1714 * Testing
1715 */
1716 void amdgpu_test_moves(struct amdgpu_device *adev);
1717 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1718 struct amdgpu_ring *cpA,
1719 struct amdgpu_ring *cpB);
1720 void amdgpu_test_syncing(struct amdgpu_device *adev);
1721
1722 /*
1723 * MMU Notifier
1724 */
1725 #if defined(CONFIG_MMU_NOTIFIER)
1726 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1727 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1728 #else
1729 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1730 {
1731 return -ENODEV;
1732 }
1733 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1734 #endif
1735
1736 /*
1737 * Debugfs
1738 */
1739 struct amdgpu_debugfs {
1740 struct drm_info_list *files;
1741 unsigned num_files;
1742 };
1743
1744 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1745 struct drm_info_list *files,
1746 unsigned nfiles);
1747 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1748
1749 #if defined(CONFIG_DEBUG_FS)
1750 int amdgpu_debugfs_init(struct drm_minor *minor);
1751 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1752 #endif
1753
1754 /*
1755 * amdgpu smumgr functions
1756 */
1757 struct amdgpu_smumgr_funcs {
1758 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1759 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1760 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1761 };
1762
1763 /*
1764 * amdgpu smumgr
1765 */
1766 struct amdgpu_smumgr {
1767 struct amdgpu_bo *toc_buf;
1768 struct amdgpu_bo *smu_buf;
1769 /* asic priv smu data */
1770 void *priv;
1771 spinlock_t smu_lock;
1772 /* smumgr functions */
1773 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1774 /* ucode loading complete flag */
1775 uint32_t fw_flags;
1776 };
1777
1778 /*
1779 * ASIC specific register table accessible by UMD
1780 */
1781 struct amdgpu_allowed_register_entry {
1782 uint32_t reg_offset;
1783 bool untouched;
1784 bool grbm_indexed;
1785 };
1786
1787 struct amdgpu_cu_info {
1788 uint32_t number; /* total active CU number */
1789 uint32_t ao_cu_mask;
1790 uint32_t bitmap[4][4];
1791 };
1792
1793
1794 /*
1795 * ASIC specific functions.
1796 */
1797 struct amdgpu_asic_funcs {
1798 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1799 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1800 u8 *bios, u32 length_bytes);
1801 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1802 u32 sh_num, u32 reg_offset, u32 *value);
1803 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1804 int (*reset)(struct amdgpu_device *adev);
1805 /* wait for mc_idle */
1806 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1807 /* get the reference clock */
1808 u32 (*get_xclk)(struct amdgpu_device *adev);
1809 /* get the gpu clock counter */
1810 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1811 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1812 /* MM block clocks */
1813 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1814 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1815 };
1816
1817 /*
1818 * IOCTL.
1819 */
1820 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1821 struct drm_file *filp);
1822 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1823 struct drm_file *filp);
1824
1825 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1826 struct drm_file *filp);
1827 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1828 struct drm_file *filp);
1829 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1830 struct drm_file *filp);
1831 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1832 struct drm_file *filp);
1833 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1834 struct drm_file *filp);
1835 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1836 struct drm_file *filp);
1837 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1838 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1839
1840 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1841 struct drm_file *filp);
1842
1843 /* VRAM scratch page for HDP bug, default vram page */
1844 struct amdgpu_vram_scratch {
1845 struct amdgpu_bo *robj;
1846 volatile uint32_t *ptr;
1847 u64 gpu_addr;
1848 };
1849
1850 /*
1851 * ACPI
1852 */
1853 struct amdgpu_atif_notification_cfg {
1854 bool enabled;
1855 int command_code;
1856 };
1857
1858 struct amdgpu_atif_notifications {
1859 bool display_switch;
1860 bool expansion_mode_change;
1861 bool thermal_state;
1862 bool forced_power_state;
1863 bool system_power_state;
1864 bool display_conf_change;
1865 bool px_gfx_switch;
1866 bool brightness_change;
1867 bool dgpu_display_event;
1868 };
1869
1870 struct amdgpu_atif_functions {
1871 bool system_params;
1872 bool sbios_requests;
1873 bool select_active_disp;
1874 bool lid_state;
1875 bool get_tv_standard;
1876 bool set_tv_standard;
1877 bool get_panel_expansion_mode;
1878 bool set_panel_expansion_mode;
1879 bool temperature_change;
1880 bool graphics_device_types;
1881 };
1882
1883 struct amdgpu_atif {
1884 struct amdgpu_atif_notifications notifications;
1885 struct amdgpu_atif_functions functions;
1886 struct amdgpu_atif_notification_cfg notification_cfg;
1887 struct amdgpu_encoder *encoder_for_bl;
1888 };
1889
1890 struct amdgpu_atcs_functions {
1891 bool get_ext_state;
1892 bool pcie_perf_req;
1893 bool pcie_dev_rdy;
1894 bool pcie_bus_width;
1895 };
1896
1897 struct amdgpu_atcs {
1898 struct amdgpu_atcs_functions functions;
1899 };
1900
1901 /*
1902 * CGS
1903 */
1904 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1905 void amdgpu_cgs_destroy_device(void *cgs_device);
1906
1907
1908 /*
1909 * Core structure, functions and helpers.
1910 */
1911 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1912 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1913
1914 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1915 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1916
1917 struct amdgpu_ip_block_status {
1918 bool valid;
1919 bool sw;
1920 bool hw;
1921 };
1922
1923 struct amdgpu_device {
1924 struct device *dev;
1925 struct drm_device *ddev;
1926 struct pci_dev *pdev;
1927
1928 /* ASIC */
1929 enum amd_asic_type asic_type;
1930 uint32_t family;
1931 uint32_t rev_id;
1932 uint32_t external_rev_id;
1933 unsigned long flags;
1934 int usec_timeout;
1935 const struct amdgpu_asic_funcs *asic_funcs;
1936 bool shutdown;
1937 bool suspend;
1938 bool need_dma32;
1939 bool accel_working;
1940 struct work_struct reset_work;
1941 struct notifier_block acpi_nb;
1942 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1943 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1944 unsigned debugfs_count;
1945 #if defined(CONFIG_DEBUG_FS)
1946 struct dentry *debugfs_regs;
1947 #endif
1948 struct amdgpu_atif atif;
1949 struct amdgpu_atcs atcs;
1950 struct mutex srbm_mutex;
1951 /* GRBM index mutex. Protects concurrent access to GRBM index */
1952 struct mutex grbm_idx_mutex;
1953 struct dev_pm_domain vga_pm_domain;
1954 bool have_disp_power_ref;
1955
1956 /* BIOS */
1957 uint8_t *bios;
1958 bool is_atom_bios;
1959 uint16_t bios_header_start;
1960 struct amdgpu_bo *stollen_vga_memory;
1961 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1962
1963 /* Register/doorbell mmio */
1964 resource_size_t rmmio_base;
1965 resource_size_t rmmio_size;
1966 void __iomem *rmmio;
1967 /* protects concurrent MM_INDEX/DATA based register access */
1968 spinlock_t mmio_idx_lock;
1969 /* protects concurrent SMC based register access */
1970 spinlock_t smc_idx_lock;
1971 amdgpu_rreg_t smc_rreg;
1972 amdgpu_wreg_t smc_wreg;
1973 /* protects concurrent PCIE register access */
1974 spinlock_t pcie_idx_lock;
1975 amdgpu_rreg_t pcie_rreg;
1976 amdgpu_wreg_t pcie_wreg;
1977 /* protects concurrent UVD register access */
1978 spinlock_t uvd_ctx_idx_lock;
1979 amdgpu_rreg_t uvd_ctx_rreg;
1980 amdgpu_wreg_t uvd_ctx_wreg;
1981 /* protects concurrent DIDT register access */
1982 spinlock_t didt_idx_lock;
1983 amdgpu_rreg_t didt_rreg;
1984 amdgpu_wreg_t didt_wreg;
1985 /* protects concurrent ENDPOINT (audio) register access */
1986 spinlock_t audio_endpt_idx_lock;
1987 amdgpu_block_rreg_t audio_endpt_rreg;
1988 amdgpu_block_wreg_t audio_endpt_wreg;
1989 void __iomem *rio_mem;
1990 resource_size_t rio_mem_size;
1991 struct amdgpu_doorbell doorbell;
1992
1993 /* clock/pll info */
1994 struct amdgpu_clock clock;
1995
1996 /* MC */
1997 struct amdgpu_mc mc;
1998 struct amdgpu_gart gart;
1999 struct amdgpu_dummy_page dummy_page;
2000 struct amdgpu_vm_manager vm_manager;
2001
2002 /* memory management */
2003 struct amdgpu_mman mman;
2004 struct amdgpu_gem gem;
2005 struct amdgpu_vram_scratch vram_scratch;
2006 struct amdgpu_wb wb;
2007 atomic64_t vram_usage;
2008 atomic64_t vram_vis_usage;
2009 atomic64_t gtt_usage;
2010 atomic64_t num_bytes_moved;
2011 atomic_t gpu_reset_counter;
2012
2013 /* display */
2014 struct amdgpu_mode_info mode_info;
2015 struct work_struct hotplug_work;
2016 struct amdgpu_irq_src crtc_irq;
2017 struct amdgpu_irq_src pageflip_irq;
2018 struct amdgpu_irq_src hpd_irq;
2019
2020 /* rings */
2021 unsigned fence_context;
2022 struct mutex ring_lock;
2023 unsigned num_rings;
2024 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2025 bool ib_pool_ready;
2026 struct amdgpu_sa_manager ring_tmp_bo;
2027
2028 /* interrupts */
2029 struct amdgpu_irq irq;
2030
2031 /* powerplay */
2032 struct amd_powerplay powerplay;
2033 bool pp_enabled;
2034
2035 /* dpm */
2036 struct amdgpu_pm pm;
2037 u32 cg_flags;
2038 u32 pg_flags;
2039
2040 /* amdgpu smumgr */
2041 struct amdgpu_smumgr smu;
2042
2043 /* gfx */
2044 struct amdgpu_gfx gfx;
2045
2046 /* sdma */
2047 struct amdgpu_sdma sdma;
2048
2049 /* uvd */
2050 bool has_uvd;
2051 struct amdgpu_uvd uvd;
2052
2053 /* vce */
2054 struct amdgpu_vce vce;
2055
2056 /* firmwares */
2057 struct amdgpu_firmware firmware;
2058
2059 /* GDS */
2060 struct amdgpu_gds gds;
2061
2062 const struct amdgpu_ip_block_version *ip_blocks;
2063 int num_ip_blocks;
2064 struct amdgpu_ip_block_status *ip_block_status;
2065 struct mutex mn_lock;
2066 DECLARE_HASHTABLE(mn_hash, 7);
2067
2068 /* tracking pinned memory */
2069 u64 vram_pin_size;
2070 u64 gart_pin_size;
2071
2072 /* amdkfd interface */
2073 struct kfd_dev *kfd;
2074
2075 /* kernel conext for IB submission */
2076 struct amdgpu_ctx kernel_ctx;
2077 };
2078
2079 bool amdgpu_device_is_px(struct drm_device *dev);
2080 int amdgpu_device_init(struct amdgpu_device *adev,
2081 struct drm_device *ddev,
2082 struct pci_dev *pdev,
2083 uint32_t flags);
2084 void amdgpu_device_fini(struct amdgpu_device *adev);
2085 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2086
2087 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2088 bool always_indirect);
2089 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2090 bool always_indirect);
2091 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2092 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2093
2094 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2095 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2096
2097 /*
2098 * Cast helper
2099 */
2100 extern const struct fence_ops amdgpu_fence_ops;
2101 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2102 {
2103 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2104
2105 if (__f->base.ops == &amdgpu_fence_ops)
2106 return __f;
2107
2108 return NULL;
2109 }
2110
2111 /*
2112 * Registers read & write functions.
2113 */
2114 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2115 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2116 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2117 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2118 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2119 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2120 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2121 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2122 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2123 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2124 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2125 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2126 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2127 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2128 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2129 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2130 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2131 #define WREG32_P(reg, val, mask) \
2132 do { \
2133 uint32_t tmp_ = RREG32(reg); \
2134 tmp_ &= (mask); \
2135 tmp_ |= ((val) & ~(mask)); \
2136 WREG32(reg, tmp_); \
2137 } while (0)
2138 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2139 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2140 #define WREG32_PLL_P(reg, val, mask) \
2141 do { \
2142 uint32_t tmp_ = RREG32_PLL(reg); \
2143 tmp_ &= (mask); \
2144 tmp_ |= ((val) & ~(mask)); \
2145 WREG32_PLL(reg, tmp_); \
2146 } while (0)
2147 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2148 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2149 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2150
2151 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2152 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2153
2154 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2155 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2156
2157 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2158 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2159 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2160
2161 #define REG_GET_FIELD(value, reg, field) \
2162 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2163
2164 /*
2165 * BIOS helpers.
2166 */
2167 #define RBIOS8(i) (adev->bios[i])
2168 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2169 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2170
2171 /*
2172 * RING helpers.
2173 */
2174 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2175 {
2176 if (ring->count_dw <= 0)
2177 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2178 ring->ring[ring->wptr++] = v;
2179 ring->wptr &= ring->ptr_mask;
2180 ring->count_dw--;
2181 ring->ring_free_dw--;
2182 }
2183
2184 static inline struct amdgpu_sdma_instance *
2185 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2186 {
2187 struct amdgpu_device *adev = ring->adev;
2188 int i;
2189
2190 for (i = 0; i < adev->sdma.num_instances; i++)
2191 if (&adev->sdma.instance[i].ring == ring)
2192 break;
2193
2194 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2195 return &adev->sdma.instance[i];
2196 else
2197 return NULL;
2198 }
2199
2200 /*
2201 * ASICs macro.
2202 */
2203 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2204 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2205 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2206 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2207 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2208 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2209 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2210 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2211 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2212 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2213 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2214 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2215 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2216 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2217 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2218 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2219 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2220 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2221 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2222 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2223 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2224 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2225 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2226 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2227 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2228 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2229 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2230 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2231 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2232 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2233 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2234 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2235 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2236 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2237 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2238 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2239 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2240 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2241 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2242 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2243 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2244 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2245 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2246 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2247 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2248 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2249 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2250 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2251 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2252 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2253 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2254 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2255 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2256 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2257 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2258 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2259 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2260
2261 #define amdgpu_dpm_get_temperature(adev) \
2262 ((adev)->pp_enabled ? \
2263 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2264 (adev)->pm.funcs->get_temperature((adev)))
2265
2266 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2267 ((adev)->pp_enabled ? \
2268 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2269 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2270
2271 #define amdgpu_dpm_get_fan_control_mode(adev) \
2272 ((adev)->pp_enabled ? \
2273 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2274 (adev)->pm.funcs->get_fan_control_mode((adev)))
2275
2276 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2277 ((adev)->pp_enabled ? \
2278 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2279 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2280
2281 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2282 ((adev)->pp_enabled ? \
2283 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2284 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2285
2286 #define amdgpu_dpm_get_sclk(adev, l) \
2287 ((adev)->pp_enabled ? \
2288 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2289 (adev)->pm.funcs->get_sclk((adev), (l)))
2290
2291 #define amdgpu_dpm_get_mclk(adev, l) \
2292 ((adev)->pp_enabled ? \
2293 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2294 (adev)->pm.funcs->get_mclk((adev), (l)))
2295
2296
2297 #define amdgpu_dpm_force_performance_level(adev, l) \
2298 ((adev)->pp_enabled ? \
2299 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2300 (adev)->pm.funcs->force_performance_level((adev), (l)))
2301
2302 #define amdgpu_dpm_powergate_uvd(adev, g) \
2303 ((adev)->pp_enabled ? \
2304 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2305 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2306
2307 #define amdgpu_dpm_powergate_vce(adev, g) \
2308 ((adev)->pp_enabled ? \
2309 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2310 (adev)->pm.funcs->powergate_vce((adev), (g)))
2311
2312 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2313 ((adev)->pp_enabled ? \
2314 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2315 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2316
2317 #define amdgpu_dpm_get_current_power_state(adev) \
2318 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2319
2320 #define amdgpu_dpm_get_performance_level(adev) \
2321 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2322
2323 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2324 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2325
2326 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2327
2328 /* Common functions */
2329 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2330 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2331 bool amdgpu_card_posted(struct amdgpu_device *adev);
2332 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2333 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2334
2335 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2336 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2337 u32 ip_instance, u32 ring,
2338 struct amdgpu_ring **out_ring);
2339 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2340 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2341 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2342 uint32_t flags);
2343 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2344 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2345 unsigned long end);
2346 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2347 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2348 struct ttm_mem_reg *mem);
2349 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2350 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2351 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2352 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2353 const u32 *registers,
2354 const u32 array_size);
2355
2356 bool amdgpu_device_is_px(struct drm_device *dev);
2357 /* atpx handler */
2358 #if defined(CONFIG_VGA_SWITCHEROO)
2359 void amdgpu_register_atpx_handler(void);
2360 void amdgpu_unregister_atpx_handler(void);
2361 #else
2362 static inline void amdgpu_register_atpx_handler(void) {}
2363 static inline void amdgpu_unregister_atpx_handler(void) {}
2364 #endif
2365
2366 /*
2367 * KMS
2368 */
2369 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2370 extern int amdgpu_max_kms_ioctl;
2371
2372 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2373 int amdgpu_driver_unload_kms(struct drm_device *dev);
2374 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2375 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2376 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2377 struct drm_file *file_priv);
2378 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2379 struct drm_file *file_priv);
2380 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2381 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2382 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2383 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2384 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2385 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2386 int *max_error,
2387 struct timeval *vblank_time,
2388 unsigned flags);
2389 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2390 unsigned long arg);
2391
2392 /*
2393 * functions used by amdgpu_encoder.c
2394 */
2395 struct amdgpu_afmt_acr {
2396 u32 clock;
2397
2398 int n_32khz;
2399 int cts_32khz;
2400
2401 int n_44_1khz;
2402 int cts_44_1khz;
2403
2404 int n_48khz;
2405 int cts_48khz;
2406
2407 };
2408
2409 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2410
2411 /* amdgpu_acpi.c */
2412 #if defined(CONFIG_ACPI)
2413 int amdgpu_acpi_init(struct amdgpu_device *adev);
2414 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2415 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2416 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2417 u8 perf_req, bool advertise);
2418 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2419 #else
2420 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2421 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2422 #endif
2423
2424 struct amdgpu_bo_va_mapping *
2425 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2426 uint64_t addr, struct amdgpu_bo **bo);
2427
2428 #include "amdgpu_object.h"
2429
2430 #endif
Linux kernel - Deliverables
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