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drm/amdgpu: keep the owner for VMIDs
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55
56 #include "gpu_scheduler.h"
57
58 /*
59 * Modules parameters.
60 */
61 extern int amdgpu_modeset;
62 extern int amdgpu_vram_limit;
63 extern int amdgpu_gart_size;
64 extern int amdgpu_benchmarking;
65 extern int amdgpu_testing;
66 extern int amdgpu_audio;
67 extern int amdgpu_disp_priority;
68 extern int amdgpu_hw_i2c;
69 extern int amdgpu_pcie_gen2;
70 extern int amdgpu_msi;
71 extern int amdgpu_lockup_timeout;
72 extern int amdgpu_dpm;
73 extern int amdgpu_smc_load_fw;
74 extern int amdgpu_aspm;
75 extern int amdgpu_runtime_pm;
76 extern int amdgpu_hard_reset;
77 extern unsigned amdgpu_ip_block_mask;
78 extern int amdgpu_bapm;
79 extern int amdgpu_deep_color;
80 extern int amdgpu_vm_size;
81 extern int amdgpu_vm_block_size;
82 extern int amdgpu_vm_fault_stop;
83 extern int amdgpu_vm_debug;
84 extern int amdgpu_enable_scheduler;
85 extern int amdgpu_sched_jobs;
86 extern int amdgpu_sched_hw_submission;
87 extern int amdgpu_enable_semaphores;
88
89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93 #define AMDGPU_IB_POOL_SIZE 16
94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95 #define AMDGPUFB_CONN_LIMIT 4
96 #define AMDGPU_BIOS_NUM_SCRATCH 8
97
98 /* max number of rings */
99 #define AMDGPU_MAX_RINGS 16
100 #define AMDGPU_MAX_GFX_RINGS 1
101 #define AMDGPU_MAX_COMPUTE_RINGS 8
102 #define AMDGPU_MAX_VCE_RINGS 2
103
104 /* max number of IP instances */
105 #define AMDGPU_MAX_SDMA_INSTANCES 2
106
107 /* number of hw syncs before falling back on blocking */
108 #define AMDGPU_NUM_SYNCS 4
109
110 /* hardcode that limit for now */
111 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
112
113 /* hard reset data */
114 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
115
116 /* reset flags */
117 #define AMDGPU_RESET_GFX (1 << 0)
118 #define AMDGPU_RESET_COMPUTE (1 << 1)
119 #define AMDGPU_RESET_DMA (1 << 2)
120 #define AMDGPU_RESET_CP (1 << 3)
121 #define AMDGPU_RESET_GRBM (1 << 4)
122 #define AMDGPU_RESET_DMA1 (1 << 5)
123 #define AMDGPU_RESET_RLC (1 << 6)
124 #define AMDGPU_RESET_SEM (1 << 7)
125 #define AMDGPU_RESET_IH (1 << 8)
126 #define AMDGPU_RESET_VMC (1 << 9)
127 #define AMDGPU_RESET_MC (1 << 10)
128 #define AMDGPU_RESET_DISPLAY (1 << 11)
129 #define AMDGPU_RESET_UVD (1 << 12)
130 #define AMDGPU_RESET_VCE (1 << 13)
131 #define AMDGPU_RESET_VCE1 (1 << 14)
132
133 /* CG block flags */
134 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
135 #define AMDGPU_CG_BLOCK_MC (1 << 1)
136 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
137 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
138 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
139 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
140 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
141
142 /* CG flags */
143 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
144 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
145 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
146 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
147 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
148 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
149 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
150 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
151 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
152 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
153 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
154 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
155 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
156 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
157 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
158 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
159 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
160
161 /* PG flags */
162 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
163 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
164 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
165 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
166 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
167 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
168 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
169 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
170 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
171 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
172 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
173
174 /* GFX current status */
175 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
176 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
177 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
178 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
179 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
180
181 /* max cursor sizes (in pixels) */
182 #define CIK_CURSOR_WIDTH 128
183 #define CIK_CURSOR_HEIGHT 128
184
185 struct amdgpu_device;
186 struct amdgpu_fence;
187 struct amdgpu_ib;
188 struct amdgpu_vm;
189 struct amdgpu_ring;
190 struct amdgpu_semaphore;
191 struct amdgpu_cs_parser;
192 struct amdgpu_job;
193 struct amdgpu_irq_src;
194 struct amdgpu_fpriv;
195
196 enum amdgpu_cp_irq {
197 AMDGPU_CP_IRQ_GFX_EOP = 0,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
206
207 AMDGPU_CP_IRQ_LAST
208 };
209
210 enum amdgpu_sdma_irq {
211 AMDGPU_SDMA_IRQ_TRAP0 = 0,
212 AMDGPU_SDMA_IRQ_TRAP1,
213
214 AMDGPU_SDMA_IRQ_LAST
215 };
216
217 enum amdgpu_thermal_irq {
218 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
219 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
220
221 AMDGPU_THERMAL_IRQ_LAST
222 };
223
224 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
225 enum amd_ip_block_type block_type,
226 enum amd_clockgating_state state);
227 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
228 enum amd_ip_block_type block_type,
229 enum amd_powergating_state state);
230
231 struct amdgpu_ip_block_version {
232 enum amd_ip_block_type type;
233 u32 major;
234 u32 minor;
235 u32 rev;
236 const struct amd_ip_funcs *funcs;
237 };
238
239 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
240 enum amd_ip_block_type type,
241 u32 major, u32 minor);
242
243 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
244 struct amdgpu_device *adev,
245 enum amd_ip_block_type type);
246
247 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
248 struct amdgpu_buffer_funcs {
249 /* maximum bytes in a single operation */
250 uint32_t copy_max_bytes;
251
252 /* number of dw to reserve per operation */
253 unsigned copy_num_dw;
254
255 /* used for buffer migration */
256 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
257 /* src addr in bytes */
258 uint64_t src_offset,
259 /* dst addr in bytes */
260 uint64_t dst_offset,
261 /* number of byte to transfer */
262 uint32_t byte_count);
263
264 /* maximum bytes in a single operation */
265 uint32_t fill_max_bytes;
266
267 /* number of dw to reserve per operation */
268 unsigned fill_num_dw;
269
270 /* used for buffer clearing */
271 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
272 /* value to write to memory */
273 uint32_t src_data,
274 /* dst addr in bytes */
275 uint64_t dst_offset,
276 /* number of byte to fill */
277 uint32_t byte_count);
278 };
279
280 /* provided by hw blocks that can write ptes, e.g., sdma */
281 struct amdgpu_vm_pte_funcs {
282 /* copy pte entries from GART */
283 void (*copy_pte)(struct amdgpu_ib *ib,
284 uint64_t pe, uint64_t src,
285 unsigned count);
286 /* write pte one entry at a time with addr mapping */
287 void (*write_pte)(struct amdgpu_ib *ib,
288 uint64_t pe,
289 uint64_t addr, unsigned count,
290 uint32_t incr, uint32_t flags);
291 /* for linear pte/pde updates without addr mapping */
292 void (*set_pte_pde)(struct amdgpu_ib *ib,
293 uint64_t pe,
294 uint64_t addr, unsigned count,
295 uint32_t incr, uint32_t flags);
296 /* pad the indirect buffer to the necessary number of dw */
297 void (*pad_ib)(struct amdgpu_ib *ib);
298 };
299
300 /* provided by the gmc block */
301 struct amdgpu_gart_funcs {
302 /* flush the vm tlb via mmio */
303 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
304 uint32_t vmid);
305 /* write pte/pde updates using the cpu */
306 int (*set_pte_pde)(struct amdgpu_device *adev,
307 void *cpu_pt_addr, /* cpu addr of page table */
308 uint32_t gpu_page_idx, /* pte/pde to update */
309 uint64_t addr, /* addr to write into pte/pde */
310 uint32_t flags); /* access flags */
311 };
312
313 /* provided by the ih block */
314 struct amdgpu_ih_funcs {
315 /* ring read/write ptr handling, called from interrupt context */
316 u32 (*get_wptr)(struct amdgpu_device *adev);
317 void (*decode_iv)(struct amdgpu_device *adev,
318 struct amdgpu_iv_entry *entry);
319 void (*set_rptr)(struct amdgpu_device *adev);
320 };
321
322 /* provided by hw blocks that expose a ring buffer for commands */
323 struct amdgpu_ring_funcs {
324 /* ring read/write ptr handling */
325 u32 (*get_rptr)(struct amdgpu_ring *ring);
326 u32 (*get_wptr)(struct amdgpu_ring *ring);
327 void (*set_wptr)(struct amdgpu_ring *ring);
328 /* validating and patching of IBs */
329 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
330 /* command emit functions */
331 void (*emit_ib)(struct amdgpu_ring *ring,
332 struct amdgpu_ib *ib);
333 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
334 uint64_t seq, unsigned flags);
335 bool (*emit_semaphore)(struct amdgpu_ring *ring,
336 struct amdgpu_semaphore *semaphore,
337 bool emit_wait);
338 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
339 uint64_t pd_addr);
340 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
341 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
342 uint32_t gds_base, uint32_t gds_size,
343 uint32_t gws_base, uint32_t gws_size,
344 uint32_t oa_base, uint32_t oa_size);
345 /* testing functions */
346 int (*test_ring)(struct amdgpu_ring *ring);
347 int (*test_ib)(struct amdgpu_ring *ring);
348 /* insert NOP packets */
349 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
350 };
351
352 /*
353 * BIOS.
354 */
355 bool amdgpu_get_bios(struct amdgpu_device *adev);
356 bool amdgpu_read_bios(struct amdgpu_device *adev);
357
358 /*
359 * Dummy page
360 */
361 struct amdgpu_dummy_page {
362 struct page *page;
363 dma_addr_t addr;
364 };
365 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
366 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
367
368
369 /*
370 * Clocks
371 */
372
373 #define AMDGPU_MAX_PPLL 3
374
375 struct amdgpu_clock {
376 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
377 struct amdgpu_pll spll;
378 struct amdgpu_pll mpll;
379 /* 10 Khz units */
380 uint32_t default_mclk;
381 uint32_t default_sclk;
382 uint32_t default_dispclk;
383 uint32_t current_dispclk;
384 uint32_t dp_extclk;
385 uint32_t max_pixel_clock;
386 };
387
388 /*
389 * Fences.
390 */
391 struct amdgpu_fence_driver {
392 uint64_t gpu_addr;
393 volatile uint32_t *cpu_addr;
394 /* sync_seq is protected by ring emission lock */
395 uint64_t sync_seq[AMDGPU_MAX_RINGS];
396 atomic64_t last_seq;
397 bool initialized;
398 struct amdgpu_irq_src *irq_src;
399 unsigned irq_type;
400 struct timer_list fallback_timer;
401 wait_queue_head_t fence_queue;
402 };
403
404 /* some special values for the owner field */
405 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
406 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
407
408 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
409 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
410
411 struct amdgpu_fence {
412 struct fence base;
413
414 /* RB, DMA, etc. */
415 struct amdgpu_ring *ring;
416 uint64_t seq;
417
418 /* filp or special value for fence creator */
419 void *owner;
420
421 wait_queue_t fence_wake;
422 };
423
424 struct amdgpu_user_fence {
425 /* write-back bo */
426 struct amdgpu_bo *bo;
427 /* write-back address offset to bo start */
428 uint32_t offset;
429 };
430
431 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
432 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
433 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
434
435 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
436 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
437 struct amdgpu_irq_src *irq_src,
438 unsigned irq_type);
439 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
440 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
441 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
442 struct amdgpu_fence **fence);
443 void amdgpu_fence_process(struct amdgpu_ring *ring);
444 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
445 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
446 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
447
448 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
449 struct amdgpu_ring *ring);
450 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
451 struct amdgpu_ring *ring);
452
453 /*
454 * TTM.
455 */
456 struct amdgpu_mman {
457 struct ttm_bo_global_ref bo_global_ref;
458 struct drm_global_reference mem_global_ref;
459 struct ttm_bo_device bdev;
460 bool mem_global_referenced;
461 bool initialized;
462
463 #if defined(CONFIG_DEBUG_FS)
464 struct dentry *vram;
465 struct dentry *gtt;
466 #endif
467
468 /* buffer handling */
469 const struct amdgpu_buffer_funcs *buffer_funcs;
470 struct amdgpu_ring *buffer_funcs_ring;
471 };
472
473 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
474 uint64_t src_offset,
475 uint64_t dst_offset,
476 uint32_t byte_count,
477 struct reservation_object *resv,
478 struct fence **fence);
479 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
480
481 struct amdgpu_bo_list_entry {
482 struct amdgpu_bo *robj;
483 struct ttm_validate_buffer tv;
484 struct amdgpu_bo_va *bo_va;
485 unsigned prefered_domains;
486 unsigned allowed_domains;
487 uint32_t priority;
488 };
489
490 struct amdgpu_bo_va_mapping {
491 struct list_head list;
492 struct interval_tree_node it;
493 uint64_t offset;
494 uint32_t flags;
495 };
496
497 /* bo virtual addresses in a specific vm */
498 struct amdgpu_bo_va {
499 /* protected by bo being reserved */
500 struct list_head bo_list;
501 struct fence *last_pt_update;
502 unsigned ref_count;
503
504 /* protected by vm mutex and spinlock */
505 struct list_head vm_status;
506
507 /* mappings for this bo_va */
508 struct list_head invalids;
509 struct list_head valids;
510
511 /* constant after initialization */
512 struct amdgpu_vm *vm;
513 struct amdgpu_bo *bo;
514 };
515
516 #define AMDGPU_GEM_DOMAIN_MAX 0x3
517
518 struct amdgpu_bo {
519 /* Protected by gem.mutex */
520 struct list_head list;
521 /* Protected by tbo.reserved */
522 u32 initial_domain;
523 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
524 struct ttm_placement placement;
525 struct ttm_buffer_object tbo;
526 struct ttm_bo_kmap_obj kmap;
527 u64 flags;
528 unsigned pin_count;
529 void *kptr;
530 u64 tiling_flags;
531 u64 metadata_flags;
532 void *metadata;
533 u32 metadata_size;
534 /* list of all virtual address to which this bo
535 * is associated to
536 */
537 struct list_head va;
538 /* Constant after initialization */
539 struct amdgpu_device *adev;
540 struct drm_gem_object gem_base;
541
542 struct ttm_bo_kmap_obj dma_buf_vmap;
543 pid_t pid;
544 struct amdgpu_mn *mn;
545 struct list_head mn_list;
546 };
547 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
548
549 void amdgpu_gem_object_free(struct drm_gem_object *obj);
550 int amdgpu_gem_object_open(struct drm_gem_object *obj,
551 struct drm_file *file_priv);
552 void amdgpu_gem_object_close(struct drm_gem_object *obj,
553 struct drm_file *file_priv);
554 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
555 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
556 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
557 struct dma_buf_attachment *attach,
558 struct sg_table *sg);
559 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
560 struct drm_gem_object *gobj,
561 int flags);
562 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
563 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
564 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
565 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
566 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
567 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
568
569 /* sub-allocation manager, it has to be protected by another lock.
570 * By conception this is an helper for other part of the driver
571 * like the indirect buffer or semaphore, which both have their
572 * locking.
573 *
574 * Principe is simple, we keep a list of sub allocation in offset
575 * order (first entry has offset == 0, last entry has the highest
576 * offset).
577 *
578 * When allocating new object we first check if there is room at
579 * the end total_size - (last_object_offset + last_object_size) >=
580 * alloc_size. If so we allocate new object there.
581 *
582 * When there is not enough room at the end, we start waiting for
583 * each sub object until we reach object_offset+object_size >=
584 * alloc_size, this object then become the sub object we return.
585 *
586 * Alignment can't be bigger than page size.
587 *
588 * Hole are not considered for allocation to keep things simple.
589 * Assumption is that there won't be hole (all object on same
590 * alignment).
591 */
592 struct amdgpu_sa_manager {
593 wait_queue_head_t wq;
594 struct amdgpu_bo *bo;
595 struct list_head *hole;
596 struct list_head flist[AMDGPU_MAX_RINGS];
597 struct list_head olist;
598 unsigned size;
599 uint64_t gpu_addr;
600 void *cpu_ptr;
601 uint32_t domain;
602 uint32_t align;
603 };
604
605 struct amdgpu_sa_bo;
606
607 /* sub-allocation buffer */
608 struct amdgpu_sa_bo {
609 struct list_head olist;
610 struct list_head flist;
611 struct amdgpu_sa_manager *manager;
612 unsigned soffset;
613 unsigned eoffset;
614 struct fence *fence;
615 };
616
617 /*
618 * GEM objects.
619 */
620 struct amdgpu_gem {
621 struct mutex mutex;
622 struct list_head objects;
623 };
624
625 int amdgpu_gem_init(struct amdgpu_device *adev);
626 void amdgpu_gem_fini(struct amdgpu_device *adev);
627 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
628 int alignment, u32 initial_domain,
629 u64 flags, bool kernel,
630 struct drm_gem_object **obj);
631
632 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
633 struct drm_device *dev,
634 struct drm_mode_create_dumb *args);
635 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
636 struct drm_device *dev,
637 uint32_t handle, uint64_t *offset_p);
638
639 /*
640 * Semaphores.
641 */
642 struct amdgpu_semaphore {
643 struct amdgpu_sa_bo *sa_bo;
644 signed waiters;
645 uint64_t gpu_addr;
646 };
647
648 int amdgpu_semaphore_create(struct amdgpu_device *adev,
649 struct amdgpu_semaphore **semaphore);
650 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
651 struct amdgpu_semaphore *semaphore);
652 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
653 struct amdgpu_semaphore *semaphore);
654 void amdgpu_semaphore_free(struct amdgpu_device *adev,
655 struct amdgpu_semaphore **semaphore,
656 struct fence *fence);
657
658 /*
659 * Synchronization
660 */
661 struct amdgpu_sync {
662 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
663 struct fence *sync_to[AMDGPU_MAX_RINGS];
664 DECLARE_HASHTABLE(fences, 4);
665 struct fence *last_vm_update;
666 };
667
668 void amdgpu_sync_create(struct amdgpu_sync *sync);
669 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
670 struct fence *f);
671 int amdgpu_sync_resv(struct amdgpu_device *adev,
672 struct amdgpu_sync *sync,
673 struct reservation_object *resv,
674 void *owner);
675 int amdgpu_sync_rings(struct amdgpu_sync *sync,
676 struct amdgpu_ring *ring);
677 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
678 int amdgpu_sync_wait(struct amdgpu_sync *sync);
679 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
680 struct fence *fence);
681
682 /*
683 * GART structures, functions & helpers
684 */
685 struct amdgpu_mc;
686
687 #define AMDGPU_GPU_PAGE_SIZE 4096
688 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
689 #define AMDGPU_GPU_PAGE_SHIFT 12
690 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
691
692 struct amdgpu_gart {
693 dma_addr_t table_addr;
694 struct amdgpu_bo *robj;
695 void *ptr;
696 unsigned num_gpu_pages;
697 unsigned num_cpu_pages;
698 unsigned table_size;
699 struct page **pages;
700 dma_addr_t *pages_addr;
701 bool ready;
702 const struct amdgpu_gart_funcs *gart_funcs;
703 };
704
705 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
706 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
707 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
708 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
709 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
710 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
711 int amdgpu_gart_init(struct amdgpu_device *adev);
712 void amdgpu_gart_fini(struct amdgpu_device *adev);
713 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
714 int pages);
715 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
716 int pages, struct page **pagelist,
717 dma_addr_t *dma_addr, uint32_t flags);
718
719 /*
720 * GPU MC structures, functions & helpers
721 */
722 struct amdgpu_mc {
723 resource_size_t aper_size;
724 resource_size_t aper_base;
725 resource_size_t agp_base;
726 /* for some chips with <= 32MB we need to lie
727 * about vram size near mc fb location */
728 u64 mc_vram_size;
729 u64 visible_vram_size;
730 u64 gtt_size;
731 u64 gtt_start;
732 u64 gtt_end;
733 u64 vram_start;
734 u64 vram_end;
735 unsigned vram_width;
736 u64 real_vram_size;
737 int vram_mtrr;
738 u64 gtt_base_align;
739 u64 mc_mask;
740 const struct firmware *fw; /* MC firmware */
741 uint32_t fw_version;
742 struct amdgpu_irq_src vm_fault;
743 uint32_t vram_type;
744 };
745
746 /*
747 * GPU doorbell structures, functions & helpers
748 */
749 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
750 {
751 AMDGPU_DOORBELL_KIQ = 0x000,
752 AMDGPU_DOORBELL_HIQ = 0x001,
753 AMDGPU_DOORBELL_DIQ = 0x002,
754 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
755 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
756 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
757 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
758 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
759 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
760 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
761 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
762 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
763 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
764 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
765 AMDGPU_DOORBELL_IH = 0x1E8,
766 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
767 AMDGPU_DOORBELL_INVALID = 0xFFFF
768 } AMDGPU_DOORBELL_ASSIGNMENT;
769
770 struct amdgpu_doorbell {
771 /* doorbell mmio */
772 resource_size_t base;
773 resource_size_t size;
774 u32 __iomem *ptr;
775 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
776 };
777
778 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
779 phys_addr_t *aperture_base,
780 size_t *aperture_size,
781 size_t *start_offset);
782
783 /*
784 * IRQS.
785 */
786
787 struct amdgpu_flip_work {
788 struct work_struct flip_work;
789 struct work_struct unpin_work;
790 struct amdgpu_device *adev;
791 int crtc_id;
792 uint64_t base;
793 struct drm_pending_vblank_event *event;
794 struct amdgpu_bo *old_rbo;
795 struct fence *excl;
796 unsigned shared_count;
797 struct fence **shared;
798 };
799
800
801 /*
802 * CP & rings.
803 */
804
805 struct amdgpu_ib {
806 struct amdgpu_sa_bo *sa_bo;
807 uint32_t length_dw;
808 uint64_t gpu_addr;
809 uint32_t *ptr;
810 struct amdgpu_ring *ring;
811 struct amdgpu_fence *fence;
812 struct amdgpu_user_fence *user;
813 struct amdgpu_vm *vm;
814 struct amdgpu_ctx *ctx;
815 struct amdgpu_sync sync;
816 uint32_t gds_base, gds_size;
817 uint32_t gws_base, gws_size;
818 uint32_t oa_base, oa_size;
819 uint32_t flags;
820 /* resulting sequence number */
821 uint64_t sequence;
822 };
823
824 enum amdgpu_ring_type {
825 AMDGPU_RING_TYPE_GFX,
826 AMDGPU_RING_TYPE_COMPUTE,
827 AMDGPU_RING_TYPE_SDMA,
828 AMDGPU_RING_TYPE_UVD,
829 AMDGPU_RING_TYPE_VCE
830 };
831
832 extern struct amd_sched_backend_ops amdgpu_sched_ops;
833
834 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
835 struct amdgpu_ring *ring,
836 struct amdgpu_ib *ibs,
837 unsigned num_ibs,
838 int (*free_job)(struct amdgpu_job *),
839 void *owner,
840 struct fence **fence);
841
842 struct amdgpu_ring {
843 struct amdgpu_device *adev;
844 const struct amdgpu_ring_funcs *funcs;
845 struct amdgpu_fence_driver fence_drv;
846 struct amd_gpu_scheduler sched;
847
848 spinlock_t fence_lock;
849 struct mutex *ring_lock;
850 struct amdgpu_bo *ring_obj;
851 volatile uint32_t *ring;
852 unsigned rptr_offs;
853 u64 next_rptr_gpu_addr;
854 volatile u32 *next_rptr_cpu_addr;
855 unsigned wptr;
856 unsigned wptr_old;
857 unsigned ring_size;
858 unsigned ring_free_dw;
859 int count_dw;
860 uint64_t gpu_addr;
861 uint32_t align_mask;
862 uint32_t ptr_mask;
863 bool ready;
864 u32 nop;
865 u32 idx;
866 u64 last_semaphore_signal_addr;
867 u64 last_semaphore_wait_addr;
868 u32 me;
869 u32 pipe;
870 u32 queue;
871 struct amdgpu_bo *mqd_obj;
872 u32 doorbell_index;
873 bool use_doorbell;
874 unsigned wptr_offs;
875 unsigned next_rptr_offs;
876 unsigned fence_offs;
877 struct amdgpu_ctx *current_ctx;
878 enum amdgpu_ring_type type;
879 char name[16];
880 bool is_pte_ring;
881 };
882
883 /*
884 * VM
885 */
886
887 /* maximum number of VMIDs */
888 #define AMDGPU_NUM_VM 16
889
890 /* number of entries in page table */
891 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
892
893 /* PTBs (Page Table Blocks) need to be aligned to 32K */
894 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
895 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
896 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
897
898 #define AMDGPU_PTE_VALID (1 << 0)
899 #define AMDGPU_PTE_SYSTEM (1 << 1)
900 #define AMDGPU_PTE_SNOOPED (1 << 2)
901
902 /* VI only */
903 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
904
905 #define AMDGPU_PTE_READABLE (1 << 5)
906 #define AMDGPU_PTE_WRITEABLE (1 << 6)
907
908 /* PTE (Page Table Entry) fragment field for different page sizes */
909 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
910 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
911 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
912
913 /* How to programm VM fault handling */
914 #define AMDGPU_VM_FAULT_STOP_NEVER 0
915 #define AMDGPU_VM_FAULT_STOP_FIRST 1
916 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
917
918 struct amdgpu_vm_pt {
919 struct amdgpu_bo *bo;
920 uint64_t addr;
921 };
922
923 struct amdgpu_vm_id {
924 unsigned id;
925 uint64_t pd_gpu_addr;
926 /* last flushed PD/PT update */
927 struct fence *flushed_updates;
928 };
929
930 struct amdgpu_vm {
931 struct mutex mutex;
932
933 struct rb_root va;
934
935 /* protecting invalidated */
936 spinlock_t status_lock;
937
938 /* BOs moved, but not yet updated in the PT */
939 struct list_head invalidated;
940
941 /* BOs cleared in the PT because of a move */
942 struct list_head cleared;
943
944 /* BO mappings freed, but not yet updated in the PT */
945 struct list_head freed;
946
947 /* contains the page directory */
948 struct amdgpu_bo *page_directory;
949 unsigned max_pde_used;
950 struct fence *page_directory_fence;
951
952 /* array of page tables, one for each page directory entry */
953 struct amdgpu_vm_pt *page_tables;
954
955 /* for id and flush management per ring */
956 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
957 };
958
959 struct amdgpu_vm_manager {
960 struct {
961 struct fence *active;
962 atomic_long_t owner;
963 } ids[AMDGPU_NUM_VM];
964
965 uint32_t max_pfn;
966 /* number of VMIDs */
967 unsigned nvm;
968 /* vram base address for page table entry */
969 u64 vram_base_offset;
970 /* is vm enabled? */
971 bool enabled;
972 /* vm pte handling */
973 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
974 struct amdgpu_ring *vm_pte_funcs_ring;
975 };
976
977 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
978 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
979 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
980 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
981 struct amdgpu_vm *vm,
982 struct list_head *head);
983 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
984 struct amdgpu_sync *sync);
985 void amdgpu_vm_flush(struct amdgpu_ring *ring,
986 struct amdgpu_vm *vm,
987 struct fence *updates);
988 void amdgpu_vm_fence(struct amdgpu_device *adev,
989 struct amdgpu_vm *vm,
990 struct fence *fence);
991 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
992 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
993 struct amdgpu_vm *vm);
994 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
995 struct amdgpu_vm *vm);
996 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
997 struct amdgpu_sync *sync);
998 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
999 struct amdgpu_bo_va *bo_va,
1000 struct ttm_mem_reg *mem);
1001 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1002 struct amdgpu_bo *bo);
1003 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1004 struct amdgpu_bo *bo);
1005 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1006 struct amdgpu_vm *vm,
1007 struct amdgpu_bo *bo);
1008 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1009 struct amdgpu_bo_va *bo_va,
1010 uint64_t addr, uint64_t offset,
1011 uint64_t size, uint32_t flags);
1012 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1013 struct amdgpu_bo_va *bo_va,
1014 uint64_t addr);
1015 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1016 struct amdgpu_bo_va *bo_va);
1017 int amdgpu_vm_free_job(struct amdgpu_job *job);
1018
1019 /*
1020 * context related structures
1021 */
1022
1023 #define AMDGPU_CTX_MAX_CS_PENDING 16
1024
1025 struct amdgpu_ctx_ring {
1026 uint64_t sequence;
1027 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
1028 struct amd_sched_entity entity;
1029 };
1030
1031 struct amdgpu_ctx {
1032 struct kref refcount;
1033 struct amdgpu_device *adev;
1034 unsigned reset_counter;
1035 spinlock_t ring_lock;
1036 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
1037 };
1038
1039 struct amdgpu_ctx_mgr {
1040 struct amdgpu_device *adev;
1041 struct mutex lock;
1042 /* protected by lock */
1043 struct idr ctx_handles;
1044 };
1045
1046 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
1047 struct amdgpu_ctx *ctx);
1048 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
1049
1050 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1051 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1052
1053 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1054 struct fence *fence);
1055 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1056 struct amdgpu_ring *ring, uint64_t seq);
1057
1058 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1059 struct drm_file *filp);
1060
1061 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1062 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1063
1064 /*
1065 * file private structure
1066 */
1067
1068 struct amdgpu_fpriv {
1069 struct amdgpu_vm vm;
1070 struct mutex bo_list_lock;
1071 struct idr bo_list_handles;
1072 struct amdgpu_ctx_mgr ctx_mgr;
1073 };
1074
1075 /*
1076 * residency list
1077 */
1078
1079 struct amdgpu_bo_list {
1080 struct mutex lock;
1081 struct amdgpu_bo *gds_obj;
1082 struct amdgpu_bo *gws_obj;
1083 struct amdgpu_bo *oa_obj;
1084 bool has_userptr;
1085 unsigned num_entries;
1086 struct amdgpu_bo_list_entry *array;
1087 };
1088
1089 struct amdgpu_bo_list *
1090 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1091 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1092 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1093
1094 /*
1095 * GFX stuff
1096 */
1097 #include "clearstate_defs.h"
1098
1099 struct amdgpu_rlc {
1100 /* for power gating */
1101 struct amdgpu_bo *save_restore_obj;
1102 uint64_t save_restore_gpu_addr;
1103 volatile uint32_t *sr_ptr;
1104 const u32 *reg_list;
1105 u32 reg_list_size;
1106 /* for clear state */
1107 struct amdgpu_bo *clear_state_obj;
1108 uint64_t clear_state_gpu_addr;
1109 volatile uint32_t *cs_ptr;
1110 const struct cs_section_def *cs_data;
1111 u32 clear_state_size;
1112 /* for cp tables */
1113 struct amdgpu_bo *cp_table_obj;
1114 uint64_t cp_table_gpu_addr;
1115 volatile uint32_t *cp_table_ptr;
1116 u32 cp_table_size;
1117 };
1118
1119 struct amdgpu_mec {
1120 struct amdgpu_bo *hpd_eop_obj;
1121 u64 hpd_eop_gpu_addr;
1122 u32 num_pipe;
1123 u32 num_mec;
1124 u32 num_queue;
1125 };
1126
1127 /*
1128 * GPU scratch registers structures, functions & helpers
1129 */
1130 struct amdgpu_scratch {
1131 unsigned num_reg;
1132 uint32_t reg_base;
1133 bool free[32];
1134 uint32_t reg[32];
1135 };
1136
1137 /*
1138 * GFX configurations
1139 */
1140 struct amdgpu_gca_config {
1141 unsigned max_shader_engines;
1142 unsigned max_tile_pipes;
1143 unsigned max_cu_per_sh;
1144 unsigned max_sh_per_se;
1145 unsigned max_backends_per_se;
1146 unsigned max_texture_channel_caches;
1147 unsigned max_gprs;
1148 unsigned max_gs_threads;
1149 unsigned max_hw_contexts;
1150 unsigned sc_prim_fifo_size_frontend;
1151 unsigned sc_prim_fifo_size_backend;
1152 unsigned sc_hiz_tile_fifo_size;
1153 unsigned sc_earlyz_tile_fifo_size;
1154
1155 unsigned num_tile_pipes;
1156 unsigned backend_enable_mask;
1157 unsigned mem_max_burst_length_bytes;
1158 unsigned mem_row_size_in_kb;
1159 unsigned shader_engine_tile_size;
1160 unsigned num_gpus;
1161 unsigned multi_gpu_tile_size;
1162 unsigned mc_arb_ramcfg;
1163 unsigned gb_addr_config;
1164
1165 uint32_t tile_mode_array[32];
1166 uint32_t macrotile_mode_array[16];
1167 };
1168
1169 struct amdgpu_gfx {
1170 struct mutex gpu_clock_mutex;
1171 struct amdgpu_gca_config config;
1172 struct amdgpu_rlc rlc;
1173 struct amdgpu_mec mec;
1174 struct amdgpu_scratch scratch;
1175 const struct firmware *me_fw; /* ME firmware */
1176 uint32_t me_fw_version;
1177 const struct firmware *pfp_fw; /* PFP firmware */
1178 uint32_t pfp_fw_version;
1179 const struct firmware *ce_fw; /* CE firmware */
1180 uint32_t ce_fw_version;
1181 const struct firmware *rlc_fw; /* RLC firmware */
1182 uint32_t rlc_fw_version;
1183 const struct firmware *mec_fw; /* MEC firmware */
1184 uint32_t mec_fw_version;
1185 const struct firmware *mec2_fw; /* MEC2 firmware */
1186 uint32_t mec2_fw_version;
1187 uint32_t me_feature_version;
1188 uint32_t ce_feature_version;
1189 uint32_t pfp_feature_version;
1190 uint32_t rlc_feature_version;
1191 uint32_t mec_feature_version;
1192 uint32_t mec2_feature_version;
1193 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1194 unsigned num_gfx_rings;
1195 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1196 unsigned num_compute_rings;
1197 struct amdgpu_irq_src eop_irq;
1198 struct amdgpu_irq_src priv_reg_irq;
1199 struct amdgpu_irq_src priv_inst_irq;
1200 /* gfx status */
1201 uint32_t gfx_current_status;
1202 /* ce ram size*/
1203 unsigned ce_ram_size;
1204 };
1205
1206 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1207 unsigned size, struct amdgpu_ib *ib);
1208 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1209 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1210 struct amdgpu_ib *ib, void *owner);
1211 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1212 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1213 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1214 /* Ring access between begin & end cannot sleep */
1215 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1216 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1217 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1218 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1219 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1220 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1221 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1222 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1223 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1224 uint32_t **data);
1225 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1226 unsigned size, uint32_t *data);
1227 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1228 unsigned ring_size, u32 nop, u32 align_mask,
1229 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1230 enum amdgpu_ring_type ring_type);
1231 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1232 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
1233
1234 /*
1235 * CS.
1236 */
1237 struct amdgpu_cs_chunk {
1238 uint32_t chunk_id;
1239 uint32_t length_dw;
1240 uint32_t *kdata;
1241 void __user *user_ptr;
1242 };
1243
1244 struct amdgpu_cs_parser {
1245 struct amdgpu_device *adev;
1246 struct drm_file *filp;
1247 struct amdgpu_ctx *ctx;
1248 struct amdgpu_bo_list *bo_list;
1249 /* chunks */
1250 unsigned nchunks;
1251 struct amdgpu_cs_chunk *chunks;
1252 /* relocations */
1253 struct amdgpu_bo_list_entry *vm_bos;
1254 struct list_head validated;
1255 struct fence *fence;
1256
1257 struct amdgpu_ib *ibs;
1258 uint32_t num_ibs;
1259
1260 struct ww_acquire_ctx ticket;
1261
1262 /* user fence */
1263 struct amdgpu_user_fence uf;
1264 };
1265
1266 struct amdgpu_job {
1267 struct amd_sched_job base;
1268 struct amdgpu_device *adev;
1269 struct amdgpu_ib *ibs;
1270 uint32_t num_ibs;
1271 void *owner;
1272 struct amdgpu_user_fence uf;
1273 int (*free_job)(struct amdgpu_job *job);
1274 };
1275 #define to_amdgpu_job(sched_job) \
1276 container_of((sched_job), struct amdgpu_job, base)
1277
1278 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1279 {
1280 return p->ibs[ib_idx].ptr[idx];
1281 }
1282
1283 /*
1284 * Writeback
1285 */
1286 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1287
1288 struct amdgpu_wb {
1289 struct amdgpu_bo *wb_obj;
1290 volatile uint32_t *wb;
1291 uint64_t gpu_addr;
1292 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1293 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1294 };
1295
1296 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1297 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1298
1299 /**
1300 * struct amdgpu_pm - power management datas
1301 * It keeps track of various data needed to take powermanagement decision.
1302 */
1303
1304 enum amdgpu_pm_state_type {
1305 /* not used for dpm */
1306 POWER_STATE_TYPE_DEFAULT,
1307 POWER_STATE_TYPE_POWERSAVE,
1308 /* user selectable states */
1309 POWER_STATE_TYPE_BATTERY,
1310 POWER_STATE_TYPE_BALANCED,
1311 POWER_STATE_TYPE_PERFORMANCE,
1312 /* internal states */
1313 POWER_STATE_TYPE_INTERNAL_UVD,
1314 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1315 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1316 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1317 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1318 POWER_STATE_TYPE_INTERNAL_BOOT,
1319 POWER_STATE_TYPE_INTERNAL_THERMAL,
1320 POWER_STATE_TYPE_INTERNAL_ACPI,
1321 POWER_STATE_TYPE_INTERNAL_ULV,
1322 POWER_STATE_TYPE_INTERNAL_3DPERF,
1323 };
1324
1325 enum amdgpu_int_thermal_type {
1326 THERMAL_TYPE_NONE,
1327 THERMAL_TYPE_EXTERNAL,
1328 THERMAL_TYPE_EXTERNAL_GPIO,
1329 THERMAL_TYPE_RV6XX,
1330 THERMAL_TYPE_RV770,
1331 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1332 THERMAL_TYPE_EVERGREEN,
1333 THERMAL_TYPE_SUMO,
1334 THERMAL_TYPE_NI,
1335 THERMAL_TYPE_SI,
1336 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1337 THERMAL_TYPE_CI,
1338 THERMAL_TYPE_KV,
1339 };
1340
1341 enum amdgpu_dpm_auto_throttle_src {
1342 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1343 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1344 };
1345
1346 enum amdgpu_dpm_event_src {
1347 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1348 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1349 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1350 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1351 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1352 };
1353
1354 #define AMDGPU_MAX_VCE_LEVELS 6
1355
1356 enum amdgpu_vce_level {
1357 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1358 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1359 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1360 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1361 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1362 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1363 };
1364
1365 struct amdgpu_ps {
1366 u32 caps; /* vbios flags */
1367 u32 class; /* vbios flags */
1368 u32 class2; /* vbios flags */
1369 /* UVD clocks */
1370 u32 vclk;
1371 u32 dclk;
1372 /* VCE clocks */
1373 u32 evclk;
1374 u32 ecclk;
1375 bool vce_active;
1376 enum amdgpu_vce_level vce_level;
1377 /* asic priv */
1378 void *ps_priv;
1379 };
1380
1381 struct amdgpu_dpm_thermal {
1382 /* thermal interrupt work */
1383 struct work_struct work;
1384 /* low temperature threshold */
1385 int min_temp;
1386 /* high temperature threshold */
1387 int max_temp;
1388 /* was last interrupt low to high or high to low */
1389 bool high_to_low;
1390 /* interrupt source */
1391 struct amdgpu_irq_src irq;
1392 };
1393
1394 enum amdgpu_clk_action
1395 {
1396 AMDGPU_SCLK_UP = 1,
1397 AMDGPU_SCLK_DOWN
1398 };
1399
1400 struct amdgpu_blacklist_clocks
1401 {
1402 u32 sclk;
1403 u32 mclk;
1404 enum amdgpu_clk_action action;
1405 };
1406
1407 struct amdgpu_clock_and_voltage_limits {
1408 u32 sclk;
1409 u32 mclk;
1410 u16 vddc;
1411 u16 vddci;
1412 };
1413
1414 struct amdgpu_clock_array {
1415 u32 count;
1416 u32 *values;
1417 };
1418
1419 struct amdgpu_clock_voltage_dependency_entry {
1420 u32 clk;
1421 u16 v;
1422 };
1423
1424 struct amdgpu_clock_voltage_dependency_table {
1425 u32 count;
1426 struct amdgpu_clock_voltage_dependency_entry *entries;
1427 };
1428
1429 union amdgpu_cac_leakage_entry {
1430 struct {
1431 u16 vddc;
1432 u32 leakage;
1433 };
1434 struct {
1435 u16 vddc1;
1436 u16 vddc2;
1437 u16 vddc3;
1438 };
1439 };
1440
1441 struct amdgpu_cac_leakage_table {
1442 u32 count;
1443 union amdgpu_cac_leakage_entry *entries;
1444 };
1445
1446 struct amdgpu_phase_shedding_limits_entry {
1447 u16 voltage;
1448 u32 sclk;
1449 u32 mclk;
1450 };
1451
1452 struct amdgpu_phase_shedding_limits_table {
1453 u32 count;
1454 struct amdgpu_phase_shedding_limits_entry *entries;
1455 };
1456
1457 struct amdgpu_uvd_clock_voltage_dependency_entry {
1458 u32 vclk;
1459 u32 dclk;
1460 u16 v;
1461 };
1462
1463 struct amdgpu_uvd_clock_voltage_dependency_table {
1464 u8 count;
1465 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1466 };
1467
1468 struct amdgpu_vce_clock_voltage_dependency_entry {
1469 u32 ecclk;
1470 u32 evclk;
1471 u16 v;
1472 };
1473
1474 struct amdgpu_vce_clock_voltage_dependency_table {
1475 u8 count;
1476 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1477 };
1478
1479 struct amdgpu_ppm_table {
1480 u8 ppm_design;
1481 u16 cpu_core_number;
1482 u32 platform_tdp;
1483 u32 small_ac_platform_tdp;
1484 u32 platform_tdc;
1485 u32 small_ac_platform_tdc;
1486 u32 apu_tdp;
1487 u32 dgpu_tdp;
1488 u32 dgpu_ulv_power;
1489 u32 tj_max;
1490 };
1491
1492 struct amdgpu_cac_tdp_table {
1493 u16 tdp;
1494 u16 configurable_tdp;
1495 u16 tdc;
1496 u16 battery_power_limit;
1497 u16 small_power_limit;
1498 u16 low_cac_leakage;
1499 u16 high_cac_leakage;
1500 u16 maximum_power_delivery_limit;
1501 };
1502
1503 struct amdgpu_dpm_dynamic_state {
1504 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1505 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1506 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1507 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1508 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1509 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1510 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1511 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1512 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1513 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1514 struct amdgpu_clock_array valid_sclk_values;
1515 struct amdgpu_clock_array valid_mclk_values;
1516 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1517 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1518 u32 mclk_sclk_ratio;
1519 u32 sclk_mclk_delta;
1520 u16 vddc_vddci_delta;
1521 u16 min_vddc_for_pcie_gen2;
1522 struct amdgpu_cac_leakage_table cac_leakage_table;
1523 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1524 struct amdgpu_ppm_table *ppm_table;
1525 struct amdgpu_cac_tdp_table *cac_tdp_table;
1526 };
1527
1528 struct amdgpu_dpm_fan {
1529 u16 t_min;
1530 u16 t_med;
1531 u16 t_high;
1532 u16 pwm_min;
1533 u16 pwm_med;
1534 u16 pwm_high;
1535 u8 t_hyst;
1536 u32 cycle_delay;
1537 u16 t_max;
1538 u8 control_mode;
1539 u16 default_max_fan_pwm;
1540 u16 default_fan_output_sensitivity;
1541 u16 fan_output_sensitivity;
1542 bool ucode_fan_control;
1543 };
1544
1545 enum amdgpu_pcie_gen {
1546 AMDGPU_PCIE_GEN1 = 0,
1547 AMDGPU_PCIE_GEN2 = 1,
1548 AMDGPU_PCIE_GEN3 = 2,
1549 AMDGPU_PCIE_GEN_INVALID = 0xffff
1550 };
1551
1552 enum amdgpu_dpm_forced_level {
1553 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1554 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1555 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1556 };
1557
1558 struct amdgpu_vce_state {
1559 /* vce clocks */
1560 u32 evclk;
1561 u32 ecclk;
1562 /* gpu clocks */
1563 u32 sclk;
1564 u32 mclk;
1565 u8 clk_idx;
1566 u8 pstate;
1567 };
1568
1569 struct amdgpu_dpm_funcs {
1570 int (*get_temperature)(struct amdgpu_device *adev);
1571 int (*pre_set_power_state)(struct amdgpu_device *adev);
1572 int (*set_power_state)(struct amdgpu_device *adev);
1573 void (*post_set_power_state)(struct amdgpu_device *adev);
1574 void (*display_configuration_changed)(struct amdgpu_device *adev);
1575 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1576 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1577 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1578 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1579 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1580 bool (*vblank_too_short)(struct amdgpu_device *adev);
1581 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1582 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1583 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1584 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1585 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1586 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1587 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1588 };
1589
1590 struct amdgpu_dpm {
1591 struct amdgpu_ps *ps;
1592 /* number of valid power states */
1593 int num_ps;
1594 /* current power state that is active */
1595 struct amdgpu_ps *current_ps;
1596 /* requested power state */
1597 struct amdgpu_ps *requested_ps;
1598 /* boot up power state */
1599 struct amdgpu_ps *boot_ps;
1600 /* default uvd power state */
1601 struct amdgpu_ps *uvd_ps;
1602 /* vce requirements */
1603 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1604 enum amdgpu_vce_level vce_level;
1605 enum amdgpu_pm_state_type state;
1606 enum amdgpu_pm_state_type user_state;
1607 u32 platform_caps;
1608 u32 voltage_response_time;
1609 u32 backbias_response_time;
1610 void *priv;
1611 u32 new_active_crtcs;
1612 int new_active_crtc_count;
1613 u32 current_active_crtcs;
1614 int current_active_crtc_count;
1615 struct amdgpu_dpm_dynamic_state dyn_state;
1616 struct amdgpu_dpm_fan fan;
1617 u32 tdp_limit;
1618 u32 near_tdp_limit;
1619 u32 near_tdp_limit_adjusted;
1620 u32 sq_ramping_threshold;
1621 u32 cac_leakage;
1622 u16 tdp_od_limit;
1623 u32 tdp_adjustment;
1624 u16 load_line_slope;
1625 bool power_control;
1626 bool ac_power;
1627 /* special states active */
1628 bool thermal_active;
1629 bool uvd_active;
1630 bool vce_active;
1631 /* thermal handling */
1632 struct amdgpu_dpm_thermal thermal;
1633 /* forced levels */
1634 enum amdgpu_dpm_forced_level forced_level;
1635 };
1636
1637 struct amdgpu_pm {
1638 struct mutex mutex;
1639 u32 current_sclk;
1640 u32 current_mclk;
1641 u32 default_sclk;
1642 u32 default_mclk;
1643 struct amdgpu_i2c_chan *i2c_bus;
1644 /* internal thermal controller on rv6xx+ */
1645 enum amdgpu_int_thermal_type int_thermal_type;
1646 struct device *int_hwmon_dev;
1647 /* fan control parameters */
1648 bool no_fan;
1649 u8 fan_pulses_per_revolution;
1650 u8 fan_min_rpm;
1651 u8 fan_max_rpm;
1652 /* dpm */
1653 bool dpm_enabled;
1654 bool sysfs_initialized;
1655 struct amdgpu_dpm dpm;
1656 const struct firmware *fw; /* SMC firmware */
1657 uint32_t fw_version;
1658 const struct amdgpu_dpm_funcs *funcs;
1659 };
1660
1661 /*
1662 * UVD
1663 */
1664 #define AMDGPU_MAX_UVD_HANDLES 10
1665 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1666 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1667 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1668
1669 struct amdgpu_uvd {
1670 struct amdgpu_bo *vcpu_bo;
1671 void *cpu_addr;
1672 uint64_t gpu_addr;
1673 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1674 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1675 struct delayed_work idle_work;
1676 const struct firmware *fw; /* UVD firmware */
1677 struct amdgpu_ring ring;
1678 struct amdgpu_irq_src irq;
1679 bool address_64_bit;
1680 };
1681
1682 /*
1683 * VCE
1684 */
1685 #define AMDGPU_MAX_VCE_HANDLES 16
1686 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1687
1688 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1689 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1690
1691 struct amdgpu_vce {
1692 struct amdgpu_bo *vcpu_bo;
1693 uint64_t gpu_addr;
1694 unsigned fw_version;
1695 unsigned fb_version;
1696 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1697 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1698 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1699 struct delayed_work idle_work;
1700 const struct firmware *fw; /* VCE firmware */
1701 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1702 struct amdgpu_irq_src irq;
1703 unsigned harvest_config;
1704 };
1705
1706 /*
1707 * SDMA
1708 */
1709 struct amdgpu_sdma_instance {
1710 /* SDMA firmware */
1711 const struct firmware *fw;
1712 uint32_t fw_version;
1713 uint32_t feature_version;
1714
1715 struct amdgpu_ring ring;
1716 bool burst_nop;
1717 };
1718
1719 struct amdgpu_sdma {
1720 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1721 struct amdgpu_irq_src trap_irq;
1722 struct amdgpu_irq_src illegal_inst_irq;
1723 int num_instances;
1724 };
1725
1726 /*
1727 * Firmware
1728 */
1729 struct amdgpu_firmware {
1730 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1731 bool smu_load;
1732 struct amdgpu_bo *fw_buf;
1733 unsigned int fw_size;
1734 };
1735
1736 /*
1737 * Benchmarking
1738 */
1739 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1740
1741
1742 /*
1743 * Testing
1744 */
1745 void amdgpu_test_moves(struct amdgpu_device *adev);
1746 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1747 struct amdgpu_ring *cpA,
1748 struct amdgpu_ring *cpB);
1749 void amdgpu_test_syncing(struct amdgpu_device *adev);
1750
1751 /*
1752 * MMU Notifier
1753 */
1754 #if defined(CONFIG_MMU_NOTIFIER)
1755 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1756 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1757 #else
1758 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1759 {
1760 return -ENODEV;
1761 }
1762 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1763 #endif
1764
1765 /*
1766 * Debugfs
1767 */
1768 struct amdgpu_debugfs {
1769 struct drm_info_list *files;
1770 unsigned num_files;
1771 };
1772
1773 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1774 struct drm_info_list *files,
1775 unsigned nfiles);
1776 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1777
1778 #if defined(CONFIG_DEBUG_FS)
1779 int amdgpu_debugfs_init(struct drm_minor *minor);
1780 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1781 #endif
1782
1783 /*
1784 * amdgpu smumgr functions
1785 */
1786 struct amdgpu_smumgr_funcs {
1787 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1788 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1789 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1790 };
1791
1792 /*
1793 * amdgpu smumgr
1794 */
1795 struct amdgpu_smumgr {
1796 struct amdgpu_bo *toc_buf;
1797 struct amdgpu_bo *smu_buf;
1798 /* asic priv smu data */
1799 void *priv;
1800 spinlock_t smu_lock;
1801 /* smumgr functions */
1802 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1803 /* ucode loading complete flag */
1804 uint32_t fw_flags;
1805 };
1806
1807 /*
1808 * ASIC specific register table accessible by UMD
1809 */
1810 struct amdgpu_allowed_register_entry {
1811 uint32_t reg_offset;
1812 bool untouched;
1813 bool grbm_indexed;
1814 };
1815
1816 struct amdgpu_cu_info {
1817 uint32_t number; /* total active CU number */
1818 uint32_t ao_cu_mask;
1819 uint32_t bitmap[4][4];
1820 };
1821
1822
1823 /*
1824 * ASIC specific functions.
1825 */
1826 struct amdgpu_asic_funcs {
1827 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1828 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1829 u32 sh_num, u32 reg_offset, u32 *value);
1830 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1831 int (*reset)(struct amdgpu_device *adev);
1832 /* wait for mc_idle */
1833 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1834 /* get the reference clock */
1835 u32 (*get_xclk)(struct amdgpu_device *adev);
1836 /* get the gpu clock counter */
1837 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1838 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1839 /* MM block clocks */
1840 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1841 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1842 };
1843
1844 /*
1845 * IOCTL.
1846 */
1847 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1848 struct drm_file *filp);
1849 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1850 struct drm_file *filp);
1851
1852 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1853 struct drm_file *filp);
1854 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1855 struct drm_file *filp);
1856 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1857 struct drm_file *filp);
1858 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1859 struct drm_file *filp);
1860 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1861 struct drm_file *filp);
1862 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1865 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1866
1867 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1868 struct drm_file *filp);
1869
1870 /* VRAM scratch page for HDP bug, default vram page */
1871 struct amdgpu_vram_scratch {
1872 struct amdgpu_bo *robj;
1873 volatile uint32_t *ptr;
1874 u64 gpu_addr;
1875 };
1876
1877 /*
1878 * ACPI
1879 */
1880 struct amdgpu_atif_notification_cfg {
1881 bool enabled;
1882 int command_code;
1883 };
1884
1885 struct amdgpu_atif_notifications {
1886 bool display_switch;
1887 bool expansion_mode_change;
1888 bool thermal_state;
1889 bool forced_power_state;
1890 bool system_power_state;
1891 bool display_conf_change;
1892 bool px_gfx_switch;
1893 bool brightness_change;
1894 bool dgpu_display_event;
1895 };
1896
1897 struct amdgpu_atif_functions {
1898 bool system_params;
1899 bool sbios_requests;
1900 bool select_active_disp;
1901 bool lid_state;
1902 bool get_tv_standard;
1903 bool set_tv_standard;
1904 bool get_panel_expansion_mode;
1905 bool set_panel_expansion_mode;
1906 bool temperature_change;
1907 bool graphics_device_types;
1908 };
1909
1910 struct amdgpu_atif {
1911 struct amdgpu_atif_notifications notifications;
1912 struct amdgpu_atif_functions functions;
1913 struct amdgpu_atif_notification_cfg notification_cfg;
1914 struct amdgpu_encoder *encoder_for_bl;
1915 };
1916
1917 struct amdgpu_atcs_functions {
1918 bool get_ext_state;
1919 bool pcie_perf_req;
1920 bool pcie_dev_rdy;
1921 bool pcie_bus_width;
1922 };
1923
1924 struct amdgpu_atcs {
1925 struct amdgpu_atcs_functions functions;
1926 };
1927
1928 /*
1929 * CGS
1930 */
1931 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1932 void amdgpu_cgs_destroy_device(void *cgs_device);
1933
1934
1935 /*
1936 * Core structure, functions and helpers.
1937 */
1938 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1939 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1940
1941 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1942 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1943
1944 struct amdgpu_ip_block_status {
1945 bool valid;
1946 bool sw;
1947 bool hw;
1948 };
1949
1950 struct amdgpu_device {
1951 struct device *dev;
1952 struct drm_device *ddev;
1953 struct pci_dev *pdev;
1954
1955 /* ASIC */
1956 enum amd_asic_type asic_type;
1957 uint32_t family;
1958 uint32_t rev_id;
1959 uint32_t external_rev_id;
1960 unsigned long flags;
1961 int usec_timeout;
1962 const struct amdgpu_asic_funcs *asic_funcs;
1963 bool shutdown;
1964 bool suspend;
1965 bool need_dma32;
1966 bool accel_working;
1967 struct work_struct reset_work;
1968 struct notifier_block acpi_nb;
1969 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1970 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1971 unsigned debugfs_count;
1972 #if defined(CONFIG_DEBUG_FS)
1973 struct dentry *debugfs_regs;
1974 #endif
1975 struct amdgpu_atif atif;
1976 struct amdgpu_atcs atcs;
1977 struct mutex srbm_mutex;
1978 /* GRBM index mutex. Protects concurrent access to GRBM index */
1979 struct mutex grbm_idx_mutex;
1980 struct dev_pm_domain vga_pm_domain;
1981 bool have_disp_power_ref;
1982
1983 /* BIOS */
1984 uint8_t *bios;
1985 bool is_atom_bios;
1986 uint16_t bios_header_start;
1987 struct amdgpu_bo *stollen_vga_memory;
1988 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1989
1990 /* Register/doorbell mmio */
1991 resource_size_t rmmio_base;
1992 resource_size_t rmmio_size;
1993 void __iomem *rmmio;
1994 /* protects concurrent MM_INDEX/DATA based register access */
1995 spinlock_t mmio_idx_lock;
1996 /* protects concurrent SMC based register access */
1997 spinlock_t smc_idx_lock;
1998 amdgpu_rreg_t smc_rreg;
1999 amdgpu_wreg_t smc_wreg;
2000 /* protects concurrent PCIE register access */
2001 spinlock_t pcie_idx_lock;
2002 amdgpu_rreg_t pcie_rreg;
2003 amdgpu_wreg_t pcie_wreg;
2004 /* protects concurrent UVD register access */
2005 spinlock_t uvd_ctx_idx_lock;
2006 amdgpu_rreg_t uvd_ctx_rreg;
2007 amdgpu_wreg_t uvd_ctx_wreg;
2008 /* protects concurrent DIDT register access */
2009 spinlock_t didt_idx_lock;
2010 amdgpu_rreg_t didt_rreg;
2011 amdgpu_wreg_t didt_wreg;
2012 /* protects concurrent ENDPOINT (audio) register access */
2013 spinlock_t audio_endpt_idx_lock;
2014 amdgpu_block_rreg_t audio_endpt_rreg;
2015 amdgpu_block_wreg_t audio_endpt_wreg;
2016 void __iomem *rio_mem;
2017 resource_size_t rio_mem_size;
2018 struct amdgpu_doorbell doorbell;
2019
2020 /* clock/pll info */
2021 struct amdgpu_clock clock;
2022
2023 /* MC */
2024 struct amdgpu_mc mc;
2025 struct amdgpu_gart gart;
2026 struct amdgpu_dummy_page dummy_page;
2027 struct amdgpu_vm_manager vm_manager;
2028
2029 /* memory management */
2030 struct amdgpu_mman mman;
2031 struct amdgpu_gem gem;
2032 struct amdgpu_vram_scratch vram_scratch;
2033 struct amdgpu_wb wb;
2034 atomic64_t vram_usage;
2035 atomic64_t vram_vis_usage;
2036 atomic64_t gtt_usage;
2037 atomic64_t num_bytes_moved;
2038 atomic_t gpu_reset_counter;
2039
2040 /* display */
2041 struct amdgpu_mode_info mode_info;
2042 struct work_struct hotplug_work;
2043 struct amdgpu_irq_src crtc_irq;
2044 struct amdgpu_irq_src pageflip_irq;
2045 struct amdgpu_irq_src hpd_irq;
2046
2047 /* rings */
2048 unsigned fence_context;
2049 struct mutex ring_lock;
2050 unsigned num_rings;
2051 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2052 bool ib_pool_ready;
2053 struct amdgpu_sa_manager ring_tmp_bo;
2054
2055 /* interrupts */
2056 struct amdgpu_irq irq;
2057
2058 /* dpm */
2059 struct amdgpu_pm pm;
2060 u32 cg_flags;
2061 u32 pg_flags;
2062
2063 /* amdgpu smumgr */
2064 struct amdgpu_smumgr smu;
2065
2066 /* gfx */
2067 struct amdgpu_gfx gfx;
2068
2069 /* sdma */
2070 struct amdgpu_sdma sdma;
2071
2072 /* uvd */
2073 bool has_uvd;
2074 struct amdgpu_uvd uvd;
2075
2076 /* vce */
2077 struct amdgpu_vce vce;
2078
2079 /* firmwares */
2080 struct amdgpu_firmware firmware;
2081
2082 /* GDS */
2083 struct amdgpu_gds gds;
2084
2085 const struct amdgpu_ip_block_version *ip_blocks;
2086 int num_ip_blocks;
2087 struct amdgpu_ip_block_status *ip_block_status;
2088 struct mutex mn_lock;
2089 DECLARE_HASHTABLE(mn_hash, 7);
2090
2091 /* tracking pinned memory */
2092 u64 vram_pin_size;
2093 u64 gart_pin_size;
2094
2095 /* amdkfd interface */
2096 struct kfd_dev *kfd;
2097
2098 /* kernel conext for IB submission */
2099 struct amdgpu_ctx kernel_ctx;
2100 };
2101
2102 bool amdgpu_device_is_px(struct drm_device *dev);
2103 int amdgpu_device_init(struct amdgpu_device *adev,
2104 struct drm_device *ddev,
2105 struct pci_dev *pdev,
2106 uint32_t flags);
2107 void amdgpu_device_fini(struct amdgpu_device *adev);
2108 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2109
2110 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2111 bool always_indirect);
2112 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2113 bool always_indirect);
2114 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2115 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2116
2117 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2118 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2119
2120 /*
2121 * Cast helper
2122 */
2123 extern const struct fence_ops amdgpu_fence_ops;
2124 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2125 {
2126 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2127
2128 if (__f->base.ops == &amdgpu_fence_ops)
2129 return __f;
2130
2131 return NULL;
2132 }
2133
2134 /*
2135 * Registers read & write functions.
2136 */
2137 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2138 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2139 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2140 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2141 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2142 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2143 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2144 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2145 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2146 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2147 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2148 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2149 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2150 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2151 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2152 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2153 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2154 #define WREG32_P(reg, val, mask) \
2155 do { \
2156 uint32_t tmp_ = RREG32(reg); \
2157 tmp_ &= (mask); \
2158 tmp_ |= ((val) & ~(mask)); \
2159 WREG32(reg, tmp_); \
2160 } while (0)
2161 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2162 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2163 #define WREG32_PLL_P(reg, val, mask) \
2164 do { \
2165 uint32_t tmp_ = RREG32_PLL(reg); \
2166 tmp_ &= (mask); \
2167 tmp_ |= ((val) & ~(mask)); \
2168 WREG32_PLL(reg, tmp_); \
2169 } while (0)
2170 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2171 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2172 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2173
2174 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2175 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2176
2177 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2178 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2179
2180 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2181 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2182 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2183
2184 #define REG_GET_FIELD(value, reg, field) \
2185 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2186
2187 /*
2188 * BIOS helpers.
2189 */
2190 #define RBIOS8(i) (adev->bios[i])
2191 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2192 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2193
2194 /*
2195 * RING helpers.
2196 */
2197 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2198 {
2199 if (ring->count_dw <= 0)
2200 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2201 ring->ring[ring->wptr++] = v;
2202 ring->wptr &= ring->ptr_mask;
2203 ring->count_dw--;
2204 ring->ring_free_dw--;
2205 }
2206
2207 static inline struct amdgpu_sdma_instance *
2208 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2209 {
2210 struct amdgpu_device *adev = ring->adev;
2211 int i;
2212
2213 for (i = 0; i < adev->sdma.num_instances; i++)
2214 if (&adev->sdma.instance[i].ring == ring)
2215 break;
2216
2217 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2218 return &adev->sdma.instance[i];
2219 else
2220 return NULL;
2221 }
2222
2223 /*
2224 * ASICs macro.
2225 */
2226 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2227 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2228 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2229 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2230 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2231 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2232 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2233 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2234 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2235 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2236 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2237 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2238 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2239 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2240 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2241 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2242 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2243 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2244 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2245 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2246 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2247 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2248 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2249 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2250 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2251 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2252 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2253 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2254 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2255 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2256 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2257 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2258 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2259 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2260 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2261 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2262 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2263 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2264 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2265 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2266 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2267 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2268 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2269 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2270 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2271 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2272 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2273 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2274 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2275 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2276 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2277 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2278 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2279 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2280 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2281 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2282 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2283 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2284 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2285 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2286 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2287 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2288 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2289 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2290 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2291 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2292 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2293
2294 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2295
2296 /* Common functions */
2297 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2298 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2299 bool amdgpu_card_posted(struct amdgpu_device *adev);
2300 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2301 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2302
2303 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2304 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2305 u32 ip_instance, u32 ring,
2306 struct amdgpu_ring **out_ring);
2307 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2308 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2309 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2310 uint32_t flags);
2311 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2312 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2313 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2314 struct ttm_mem_reg *mem);
2315 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2316 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2317 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2318 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2319 const u32 *registers,
2320 const u32 array_size);
2321
2322 bool amdgpu_device_is_px(struct drm_device *dev);
2323 /* atpx handler */
2324 #if defined(CONFIG_VGA_SWITCHEROO)
2325 void amdgpu_register_atpx_handler(void);
2326 void amdgpu_unregister_atpx_handler(void);
2327 #else
2328 static inline void amdgpu_register_atpx_handler(void) {}
2329 static inline void amdgpu_unregister_atpx_handler(void) {}
2330 #endif
2331
2332 /*
2333 * KMS
2334 */
2335 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2336 extern int amdgpu_max_kms_ioctl;
2337
2338 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2339 int amdgpu_driver_unload_kms(struct drm_device *dev);
2340 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2341 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2342 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2343 struct drm_file *file_priv);
2344 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2345 struct drm_file *file_priv);
2346 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2347 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2348 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2349 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2350 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2351 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2352 int *max_error,
2353 struct timeval *vblank_time,
2354 unsigned flags);
2355 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2356 unsigned long arg);
2357
2358 /*
2359 * functions used by amdgpu_encoder.c
2360 */
2361 struct amdgpu_afmt_acr {
2362 u32 clock;
2363
2364 int n_32khz;
2365 int cts_32khz;
2366
2367 int n_44_1khz;
2368 int cts_44_1khz;
2369
2370 int n_48khz;
2371 int cts_48khz;
2372
2373 };
2374
2375 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2376
2377 /* amdgpu_acpi.c */
2378 #if defined(CONFIG_ACPI)
2379 int amdgpu_acpi_init(struct amdgpu_device *adev);
2380 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2381 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2382 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2383 u8 perf_req, bool advertise);
2384 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2385 #else
2386 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2387 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2388 #endif
2389
2390 struct amdgpu_bo_va_mapping *
2391 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2392 uint64_t addr, struct amdgpu_bo **bo);
2393
2394 #include "amdgpu_object.h"
2395
2396 #endif
Linux kernel - Deliverables
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