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[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55
56 #include "gpu_scheduler.h"
57
58 /*
59 * Modules parameters.
60 */
61 extern int amdgpu_modeset;
62 extern int amdgpu_vram_limit;
63 extern int amdgpu_gart_size;
64 extern int amdgpu_benchmarking;
65 extern int amdgpu_testing;
66 extern int amdgpu_audio;
67 extern int amdgpu_disp_priority;
68 extern int amdgpu_hw_i2c;
69 extern int amdgpu_pcie_gen2;
70 extern int amdgpu_msi;
71 extern int amdgpu_lockup_timeout;
72 extern int amdgpu_dpm;
73 extern int amdgpu_smc_load_fw;
74 extern int amdgpu_aspm;
75 extern int amdgpu_runtime_pm;
76 extern int amdgpu_hard_reset;
77 extern unsigned amdgpu_ip_block_mask;
78 extern int amdgpu_bapm;
79 extern int amdgpu_deep_color;
80 extern int amdgpu_vm_size;
81 extern int amdgpu_vm_block_size;
82 extern int amdgpu_vm_fault_stop;
83 extern int amdgpu_vm_debug;
84 extern int amdgpu_enable_scheduler;
85 extern int amdgpu_sched_jobs;
86 extern int amdgpu_sched_hw_submission;
87 extern int amdgpu_enable_semaphores;
88
89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93 #define AMDGPU_IB_POOL_SIZE 16
94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95 #define AMDGPUFB_CONN_LIMIT 4
96 #define AMDGPU_BIOS_NUM_SCRATCH 8
97
98 /* max number of rings */
99 #define AMDGPU_MAX_RINGS 16
100 #define AMDGPU_MAX_GFX_RINGS 1
101 #define AMDGPU_MAX_COMPUTE_RINGS 8
102 #define AMDGPU_MAX_VCE_RINGS 2
103
104 /* max number of IP instances */
105 #define AMDGPU_MAX_SDMA_INSTANCES 2
106
107 /* number of hw syncs before falling back on blocking */
108 #define AMDGPU_NUM_SYNCS 4
109
110 /* hardcode that limit for now */
111 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
112
113 /* hard reset data */
114 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
115
116 /* reset flags */
117 #define AMDGPU_RESET_GFX (1 << 0)
118 #define AMDGPU_RESET_COMPUTE (1 << 1)
119 #define AMDGPU_RESET_DMA (1 << 2)
120 #define AMDGPU_RESET_CP (1 << 3)
121 #define AMDGPU_RESET_GRBM (1 << 4)
122 #define AMDGPU_RESET_DMA1 (1 << 5)
123 #define AMDGPU_RESET_RLC (1 << 6)
124 #define AMDGPU_RESET_SEM (1 << 7)
125 #define AMDGPU_RESET_IH (1 << 8)
126 #define AMDGPU_RESET_VMC (1 << 9)
127 #define AMDGPU_RESET_MC (1 << 10)
128 #define AMDGPU_RESET_DISPLAY (1 << 11)
129 #define AMDGPU_RESET_UVD (1 << 12)
130 #define AMDGPU_RESET_VCE (1 << 13)
131 #define AMDGPU_RESET_VCE1 (1 << 14)
132
133 /* CG block flags */
134 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
135 #define AMDGPU_CG_BLOCK_MC (1 << 1)
136 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
137 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
138 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
139 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
140 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
141
142 /* CG flags */
143 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
144 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
145 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
146 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
147 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
148 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
149 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
150 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
151 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
152 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
153 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
154 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
155 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
156 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
157 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
158 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
159 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
160
161 /* PG flags */
162 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
163 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
164 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
165 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
166 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
167 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
168 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
169 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
170 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
171 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
172 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
173
174 /* GFX current status */
175 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
176 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
177 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
178 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
179 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
180
181 /* max cursor sizes (in pixels) */
182 #define CIK_CURSOR_WIDTH 128
183 #define CIK_CURSOR_HEIGHT 128
184
185 struct amdgpu_device;
186 struct amdgpu_fence;
187 struct amdgpu_ib;
188 struct amdgpu_vm;
189 struct amdgpu_ring;
190 struct amdgpu_semaphore;
191 struct amdgpu_cs_parser;
192 struct amdgpu_job;
193 struct amdgpu_irq_src;
194 struct amdgpu_fpriv;
195
196 enum amdgpu_cp_irq {
197 AMDGPU_CP_IRQ_GFX_EOP = 0,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
206
207 AMDGPU_CP_IRQ_LAST
208 };
209
210 enum amdgpu_sdma_irq {
211 AMDGPU_SDMA_IRQ_TRAP0 = 0,
212 AMDGPU_SDMA_IRQ_TRAP1,
213
214 AMDGPU_SDMA_IRQ_LAST
215 };
216
217 enum amdgpu_thermal_irq {
218 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
219 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
220
221 AMDGPU_THERMAL_IRQ_LAST
222 };
223
224 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
225 enum amd_ip_block_type block_type,
226 enum amd_clockgating_state state);
227 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
228 enum amd_ip_block_type block_type,
229 enum amd_powergating_state state);
230
231 struct amdgpu_ip_block_version {
232 enum amd_ip_block_type type;
233 u32 major;
234 u32 minor;
235 u32 rev;
236 const struct amd_ip_funcs *funcs;
237 };
238
239 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
240 enum amd_ip_block_type type,
241 u32 major, u32 minor);
242
243 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
244 struct amdgpu_device *adev,
245 enum amd_ip_block_type type);
246
247 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
248 struct amdgpu_buffer_funcs {
249 /* maximum bytes in a single operation */
250 uint32_t copy_max_bytes;
251
252 /* number of dw to reserve per operation */
253 unsigned copy_num_dw;
254
255 /* used for buffer migration */
256 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
257 /* src addr in bytes */
258 uint64_t src_offset,
259 /* dst addr in bytes */
260 uint64_t dst_offset,
261 /* number of byte to transfer */
262 uint32_t byte_count);
263
264 /* maximum bytes in a single operation */
265 uint32_t fill_max_bytes;
266
267 /* number of dw to reserve per operation */
268 unsigned fill_num_dw;
269
270 /* used for buffer clearing */
271 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
272 /* value to write to memory */
273 uint32_t src_data,
274 /* dst addr in bytes */
275 uint64_t dst_offset,
276 /* number of byte to fill */
277 uint32_t byte_count);
278 };
279
280 /* provided by hw blocks that can write ptes, e.g., sdma */
281 struct amdgpu_vm_pte_funcs {
282 /* copy pte entries from GART */
283 void (*copy_pte)(struct amdgpu_ib *ib,
284 uint64_t pe, uint64_t src,
285 unsigned count);
286 /* write pte one entry at a time with addr mapping */
287 void (*write_pte)(struct amdgpu_ib *ib,
288 uint64_t pe,
289 uint64_t addr, unsigned count,
290 uint32_t incr, uint32_t flags);
291 /* for linear pte/pde updates without addr mapping */
292 void (*set_pte_pde)(struct amdgpu_ib *ib,
293 uint64_t pe,
294 uint64_t addr, unsigned count,
295 uint32_t incr, uint32_t flags);
296 /* pad the indirect buffer to the necessary number of dw */
297 void (*pad_ib)(struct amdgpu_ib *ib);
298 };
299
300 /* provided by the gmc block */
301 struct amdgpu_gart_funcs {
302 /* flush the vm tlb via mmio */
303 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
304 uint32_t vmid);
305 /* write pte/pde updates using the cpu */
306 int (*set_pte_pde)(struct amdgpu_device *adev,
307 void *cpu_pt_addr, /* cpu addr of page table */
308 uint32_t gpu_page_idx, /* pte/pde to update */
309 uint64_t addr, /* addr to write into pte/pde */
310 uint32_t flags); /* access flags */
311 };
312
313 /* provided by the ih block */
314 struct amdgpu_ih_funcs {
315 /* ring read/write ptr handling, called from interrupt context */
316 u32 (*get_wptr)(struct amdgpu_device *adev);
317 void (*decode_iv)(struct amdgpu_device *adev,
318 struct amdgpu_iv_entry *entry);
319 void (*set_rptr)(struct amdgpu_device *adev);
320 };
321
322 /* provided by hw blocks that expose a ring buffer for commands */
323 struct amdgpu_ring_funcs {
324 /* ring read/write ptr handling */
325 u32 (*get_rptr)(struct amdgpu_ring *ring);
326 u32 (*get_wptr)(struct amdgpu_ring *ring);
327 void (*set_wptr)(struct amdgpu_ring *ring);
328 /* validating and patching of IBs */
329 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
330 /* command emit functions */
331 void (*emit_ib)(struct amdgpu_ring *ring,
332 struct amdgpu_ib *ib);
333 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
334 uint64_t seq, unsigned flags);
335 bool (*emit_semaphore)(struct amdgpu_ring *ring,
336 struct amdgpu_semaphore *semaphore,
337 bool emit_wait);
338 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
339 uint64_t pd_addr);
340 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
341 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
342 uint32_t gds_base, uint32_t gds_size,
343 uint32_t gws_base, uint32_t gws_size,
344 uint32_t oa_base, uint32_t oa_size);
345 /* testing functions */
346 int (*test_ring)(struct amdgpu_ring *ring);
347 int (*test_ib)(struct amdgpu_ring *ring);
348 /* insert NOP packets */
349 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
350 };
351
352 /*
353 * BIOS.
354 */
355 bool amdgpu_get_bios(struct amdgpu_device *adev);
356 bool amdgpu_read_bios(struct amdgpu_device *adev);
357
358 /*
359 * Dummy page
360 */
361 struct amdgpu_dummy_page {
362 struct page *page;
363 dma_addr_t addr;
364 };
365 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
366 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
367
368
369 /*
370 * Clocks
371 */
372
373 #define AMDGPU_MAX_PPLL 3
374
375 struct amdgpu_clock {
376 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
377 struct amdgpu_pll spll;
378 struct amdgpu_pll mpll;
379 /* 10 Khz units */
380 uint32_t default_mclk;
381 uint32_t default_sclk;
382 uint32_t default_dispclk;
383 uint32_t current_dispclk;
384 uint32_t dp_extclk;
385 uint32_t max_pixel_clock;
386 };
387
388 /*
389 * Fences.
390 */
391 struct amdgpu_fence_driver {
392 struct amdgpu_ring *ring;
393 uint64_t gpu_addr;
394 volatile uint32_t *cpu_addr;
395 /* sync_seq is protected by ring emission lock */
396 uint64_t sync_seq[AMDGPU_MAX_RINGS];
397 atomic64_t last_seq;
398 bool initialized;
399 struct amdgpu_irq_src *irq_src;
400 unsigned irq_type;
401 struct delayed_work lockup_work;
402 wait_queue_head_t fence_queue;
403 };
404
405 /* some special values for the owner field */
406 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
407 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
408 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
409
410 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
411 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
412
413 struct amdgpu_fence {
414 struct fence base;
415
416 /* RB, DMA, etc. */
417 struct amdgpu_ring *ring;
418 uint64_t seq;
419
420 /* filp or special value for fence creator */
421 void *owner;
422
423 wait_queue_t fence_wake;
424 };
425
426 struct amdgpu_user_fence {
427 /* write-back bo */
428 struct amdgpu_bo *bo;
429 /* write-back address offset to bo start */
430 uint32_t offset;
431 };
432
433 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
434 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
435 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
436
437 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
438 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
439 struct amdgpu_irq_src *irq_src,
440 unsigned irq_type);
441 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
442 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
443 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
444 struct amdgpu_fence **fence);
445 void amdgpu_fence_process(struct amdgpu_ring *ring);
446 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
447 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
448 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
449
450 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
451 void amdgpu_fence_unref(struct amdgpu_fence **fence);
452
453 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
454 struct amdgpu_ring *ring);
455 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
456 struct amdgpu_ring *ring);
457
458 static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
459 struct amdgpu_fence *b)
460 {
461 if (!a) {
462 return b;
463 }
464
465 if (!b) {
466 return a;
467 }
468
469 BUG_ON(a->ring != b->ring);
470
471 if (a->seq > b->seq) {
472 return a;
473 } else {
474 return b;
475 }
476 }
477
478 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
479 struct amdgpu_fence *b)
480 {
481 if (!a) {
482 return false;
483 }
484
485 if (!b) {
486 return true;
487 }
488
489 BUG_ON(a->ring != b->ring);
490
491 return a->seq < b->seq;
492 }
493
494 int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
495 void *owner, struct amdgpu_fence **fence);
496
497 /*
498 * TTM.
499 */
500 struct amdgpu_mman {
501 struct ttm_bo_global_ref bo_global_ref;
502 struct drm_global_reference mem_global_ref;
503 struct ttm_bo_device bdev;
504 bool mem_global_referenced;
505 bool initialized;
506
507 #if defined(CONFIG_DEBUG_FS)
508 struct dentry *vram;
509 struct dentry *gtt;
510 #endif
511
512 /* buffer handling */
513 const struct amdgpu_buffer_funcs *buffer_funcs;
514 struct amdgpu_ring *buffer_funcs_ring;
515 };
516
517 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
518 uint64_t src_offset,
519 uint64_t dst_offset,
520 uint32_t byte_count,
521 struct reservation_object *resv,
522 struct fence **fence);
523 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
524
525 struct amdgpu_bo_list_entry {
526 struct amdgpu_bo *robj;
527 struct ttm_validate_buffer tv;
528 struct amdgpu_bo_va *bo_va;
529 unsigned prefered_domains;
530 unsigned allowed_domains;
531 uint32_t priority;
532 };
533
534 struct amdgpu_bo_va_mapping {
535 struct list_head list;
536 struct interval_tree_node it;
537 uint64_t offset;
538 uint32_t flags;
539 };
540
541 /* bo virtual addresses in a specific vm */
542 struct amdgpu_bo_va {
543 /* protected by bo being reserved */
544 struct list_head bo_list;
545 struct fence *last_pt_update;
546 unsigned ref_count;
547
548 /* protected by vm mutex and spinlock */
549 struct list_head vm_status;
550
551 /* mappings for this bo_va */
552 struct list_head invalids;
553 struct list_head valids;
554
555 /* constant after initialization */
556 struct amdgpu_vm *vm;
557 struct amdgpu_bo *bo;
558 };
559
560 #define AMDGPU_GEM_DOMAIN_MAX 0x3
561
562 struct amdgpu_bo {
563 /* Protected by gem.mutex */
564 struct list_head list;
565 /* Protected by tbo.reserved */
566 u32 initial_domain;
567 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
568 struct ttm_placement placement;
569 struct ttm_buffer_object tbo;
570 struct ttm_bo_kmap_obj kmap;
571 u64 flags;
572 unsigned pin_count;
573 void *kptr;
574 u64 tiling_flags;
575 u64 metadata_flags;
576 void *metadata;
577 u32 metadata_size;
578 /* list of all virtual address to which this bo
579 * is associated to
580 */
581 struct list_head va;
582 /* Constant after initialization */
583 struct amdgpu_device *adev;
584 struct drm_gem_object gem_base;
585
586 struct ttm_bo_kmap_obj dma_buf_vmap;
587 pid_t pid;
588 struct amdgpu_mn *mn;
589 struct list_head mn_list;
590 };
591 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
592
593 void amdgpu_gem_object_free(struct drm_gem_object *obj);
594 int amdgpu_gem_object_open(struct drm_gem_object *obj,
595 struct drm_file *file_priv);
596 void amdgpu_gem_object_close(struct drm_gem_object *obj,
597 struct drm_file *file_priv);
598 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
599 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
600 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
601 struct dma_buf_attachment *attach,
602 struct sg_table *sg);
603 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
604 struct drm_gem_object *gobj,
605 int flags);
606 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
607 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
608 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
609 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
610 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
611 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
612
613 /* sub-allocation manager, it has to be protected by another lock.
614 * By conception this is an helper for other part of the driver
615 * like the indirect buffer or semaphore, which both have their
616 * locking.
617 *
618 * Principe is simple, we keep a list of sub allocation in offset
619 * order (first entry has offset == 0, last entry has the highest
620 * offset).
621 *
622 * When allocating new object we first check if there is room at
623 * the end total_size - (last_object_offset + last_object_size) >=
624 * alloc_size. If so we allocate new object there.
625 *
626 * When there is not enough room at the end, we start waiting for
627 * each sub object until we reach object_offset+object_size >=
628 * alloc_size, this object then become the sub object we return.
629 *
630 * Alignment can't be bigger than page size.
631 *
632 * Hole are not considered for allocation to keep things simple.
633 * Assumption is that there won't be hole (all object on same
634 * alignment).
635 */
636 struct amdgpu_sa_manager {
637 wait_queue_head_t wq;
638 struct amdgpu_bo *bo;
639 struct list_head *hole;
640 struct list_head flist[AMDGPU_MAX_RINGS];
641 struct list_head olist;
642 unsigned size;
643 uint64_t gpu_addr;
644 void *cpu_ptr;
645 uint32_t domain;
646 uint32_t align;
647 };
648
649 struct amdgpu_sa_bo;
650
651 /* sub-allocation buffer */
652 struct amdgpu_sa_bo {
653 struct list_head olist;
654 struct list_head flist;
655 struct amdgpu_sa_manager *manager;
656 unsigned soffset;
657 unsigned eoffset;
658 struct fence *fence;
659 };
660
661 /*
662 * GEM objects.
663 */
664 struct amdgpu_gem {
665 struct mutex mutex;
666 struct list_head objects;
667 };
668
669 int amdgpu_gem_init(struct amdgpu_device *adev);
670 void amdgpu_gem_fini(struct amdgpu_device *adev);
671 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
672 int alignment, u32 initial_domain,
673 u64 flags, bool kernel,
674 struct drm_gem_object **obj);
675
676 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
677 struct drm_device *dev,
678 struct drm_mode_create_dumb *args);
679 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
680 struct drm_device *dev,
681 uint32_t handle, uint64_t *offset_p);
682
683 /*
684 * Semaphores.
685 */
686 struct amdgpu_semaphore {
687 struct amdgpu_sa_bo *sa_bo;
688 signed waiters;
689 uint64_t gpu_addr;
690 };
691
692 int amdgpu_semaphore_create(struct amdgpu_device *adev,
693 struct amdgpu_semaphore **semaphore);
694 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
695 struct amdgpu_semaphore *semaphore);
696 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
697 struct amdgpu_semaphore *semaphore);
698 void amdgpu_semaphore_free(struct amdgpu_device *adev,
699 struct amdgpu_semaphore **semaphore,
700 struct fence *fence);
701
702 /*
703 * Synchronization
704 */
705 struct amdgpu_sync {
706 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
707 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
708 DECLARE_HASHTABLE(fences, 4);
709 struct fence *last_vm_update;
710 };
711
712 void amdgpu_sync_create(struct amdgpu_sync *sync);
713 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
714 struct fence *f);
715 int amdgpu_sync_resv(struct amdgpu_device *adev,
716 struct amdgpu_sync *sync,
717 struct reservation_object *resv,
718 void *owner);
719 int amdgpu_sync_rings(struct amdgpu_sync *sync,
720 struct amdgpu_ring *ring);
721 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
722 int amdgpu_sync_wait(struct amdgpu_sync *sync);
723 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
724 struct fence *fence);
725
726 /*
727 * GART structures, functions & helpers
728 */
729 struct amdgpu_mc;
730
731 #define AMDGPU_GPU_PAGE_SIZE 4096
732 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
733 #define AMDGPU_GPU_PAGE_SHIFT 12
734 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
735
736 struct amdgpu_gart {
737 dma_addr_t table_addr;
738 struct amdgpu_bo *robj;
739 void *ptr;
740 unsigned num_gpu_pages;
741 unsigned num_cpu_pages;
742 unsigned table_size;
743 struct page **pages;
744 dma_addr_t *pages_addr;
745 bool ready;
746 const struct amdgpu_gart_funcs *gart_funcs;
747 };
748
749 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
750 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
751 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
752 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
753 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
754 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
755 int amdgpu_gart_init(struct amdgpu_device *adev);
756 void amdgpu_gart_fini(struct amdgpu_device *adev);
757 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
758 int pages);
759 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
760 int pages, struct page **pagelist,
761 dma_addr_t *dma_addr, uint32_t flags);
762
763 /*
764 * GPU MC structures, functions & helpers
765 */
766 struct amdgpu_mc {
767 resource_size_t aper_size;
768 resource_size_t aper_base;
769 resource_size_t agp_base;
770 /* for some chips with <= 32MB we need to lie
771 * about vram size near mc fb location */
772 u64 mc_vram_size;
773 u64 visible_vram_size;
774 u64 gtt_size;
775 u64 gtt_start;
776 u64 gtt_end;
777 u64 vram_start;
778 u64 vram_end;
779 unsigned vram_width;
780 u64 real_vram_size;
781 int vram_mtrr;
782 u64 gtt_base_align;
783 u64 mc_mask;
784 const struct firmware *fw; /* MC firmware */
785 uint32_t fw_version;
786 struct amdgpu_irq_src vm_fault;
787 uint32_t vram_type;
788 };
789
790 /*
791 * GPU doorbell structures, functions & helpers
792 */
793 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
794 {
795 AMDGPU_DOORBELL_KIQ = 0x000,
796 AMDGPU_DOORBELL_HIQ = 0x001,
797 AMDGPU_DOORBELL_DIQ = 0x002,
798 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
799 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
800 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
801 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
802 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
803 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
804 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
805 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
806 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
807 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
808 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
809 AMDGPU_DOORBELL_IH = 0x1E8,
810 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
811 AMDGPU_DOORBELL_INVALID = 0xFFFF
812 } AMDGPU_DOORBELL_ASSIGNMENT;
813
814 struct amdgpu_doorbell {
815 /* doorbell mmio */
816 resource_size_t base;
817 resource_size_t size;
818 u32 __iomem *ptr;
819 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
820 };
821
822 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
823 phys_addr_t *aperture_base,
824 size_t *aperture_size,
825 size_t *start_offset);
826
827 /*
828 * IRQS.
829 */
830
831 struct amdgpu_flip_work {
832 struct work_struct flip_work;
833 struct work_struct unpin_work;
834 struct amdgpu_device *adev;
835 int crtc_id;
836 uint64_t base;
837 struct drm_pending_vblank_event *event;
838 struct amdgpu_bo *old_rbo;
839 struct fence *excl;
840 unsigned shared_count;
841 struct fence **shared;
842 };
843
844
845 /*
846 * CP & rings.
847 */
848
849 struct amdgpu_ib {
850 struct amdgpu_sa_bo *sa_bo;
851 uint32_t length_dw;
852 uint64_t gpu_addr;
853 uint32_t *ptr;
854 struct amdgpu_ring *ring;
855 struct amdgpu_fence *fence;
856 struct amdgpu_user_fence *user;
857 struct amdgpu_vm *vm;
858 struct amdgpu_ctx *ctx;
859 struct amdgpu_sync sync;
860 uint32_t gds_base, gds_size;
861 uint32_t gws_base, gws_size;
862 uint32_t oa_base, oa_size;
863 uint32_t flags;
864 /* resulting sequence number */
865 uint64_t sequence;
866 };
867
868 enum amdgpu_ring_type {
869 AMDGPU_RING_TYPE_GFX,
870 AMDGPU_RING_TYPE_COMPUTE,
871 AMDGPU_RING_TYPE_SDMA,
872 AMDGPU_RING_TYPE_UVD,
873 AMDGPU_RING_TYPE_VCE
874 };
875
876 extern struct amd_sched_backend_ops amdgpu_sched_ops;
877
878 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
879 struct amdgpu_ring *ring,
880 struct amdgpu_ib *ibs,
881 unsigned num_ibs,
882 int (*free_job)(struct amdgpu_job *),
883 void *owner,
884 struct fence **fence);
885
886 struct amdgpu_ring {
887 struct amdgpu_device *adev;
888 const struct amdgpu_ring_funcs *funcs;
889 struct amdgpu_fence_driver fence_drv;
890 struct amd_gpu_scheduler sched;
891
892 spinlock_t fence_lock;
893 struct mutex *ring_lock;
894 struct amdgpu_bo *ring_obj;
895 volatile uint32_t *ring;
896 unsigned rptr_offs;
897 u64 next_rptr_gpu_addr;
898 volatile u32 *next_rptr_cpu_addr;
899 unsigned wptr;
900 unsigned wptr_old;
901 unsigned ring_size;
902 unsigned ring_free_dw;
903 int count_dw;
904 uint64_t gpu_addr;
905 uint32_t align_mask;
906 uint32_t ptr_mask;
907 bool ready;
908 u32 nop;
909 u32 idx;
910 u64 last_semaphore_signal_addr;
911 u64 last_semaphore_wait_addr;
912 u32 me;
913 u32 pipe;
914 u32 queue;
915 struct amdgpu_bo *mqd_obj;
916 u32 doorbell_index;
917 bool use_doorbell;
918 unsigned wptr_offs;
919 unsigned next_rptr_offs;
920 unsigned fence_offs;
921 struct amdgpu_ctx *current_ctx;
922 enum amdgpu_ring_type type;
923 char name[16];
924 bool is_pte_ring;
925 };
926
927 /*
928 * VM
929 */
930
931 /* maximum number of VMIDs */
932 #define AMDGPU_NUM_VM 16
933
934 /* number of entries in page table */
935 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
936
937 /* PTBs (Page Table Blocks) need to be aligned to 32K */
938 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
939 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
940 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
941
942 #define AMDGPU_PTE_VALID (1 << 0)
943 #define AMDGPU_PTE_SYSTEM (1 << 1)
944 #define AMDGPU_PTE_SNOOPED (1 << 2)
945
946 /* VI only */
947 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
948
949 #define AMDGPU_PTE_READABLE (1 << 5)
950 #define AMDGPU_PTE_WRITEABLE (1 << 6)
951
952 /* PTE (Page Table Entry) fragment field for different page sizes */
953 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
954 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
955 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
956
957 /* How to programm VM fault handling */
958 #define AMDGPU_VM_FAULT_STOP_NEVER 0
959 #define AMDGPU_VM_FAULT_STOP_FIRST 1
960 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
961
962 struct amdgpu_vm_pt {
963 struct amdgpu_bo *bo;
964 uint64_t addr;
965 };
966
967 struct amdgpu_vm_id {
968 unsigned id;
969 uint64_t pd_gpu_addr;
970 /* last flushed PD/PT update */
971 struct fence *flushed_updates;
972 /* last use of vmid */
973 struct amdgpu_fence *last_id_use;
974 };
975
976 struct amdgpu_vm {
977 struct mutex mutex;
978
979 struct rb_root va;
980
981 /* protecting invalidated */
982 spinlock_t status_lock;
983
984 /* BOs moved, but not yet updated in the PT */
985 struct list_head invalidated;
986
987 /* BOs cleared in the PT because of a move */
988 struct list_head cleared;
989
990 /* BO mappings freed, but not yet updated in the PT */
991 struct list_head freed;
992
993 /* contains the page directory */
994 struct amdgpu_bo *page_directory;
995 unsigned max_pde_used;
996 struct fence *page_directory_fence;
997
998 /* array of page tables, one for each page directory entry */
999 struct amdgpu_vm_pt *page_tables;
1000
1001 /* for id and flush management per ring */
1002 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
1003 };
1004
1005 struct amdgpu_vm_manager {
1006 struct amdgpu_fence *active[AMDGPU_NUM_VM];
1007 uint32_t max_pfn;
1008 /* number of VMIDs */
1009 unsigned nvm;
1010 /* vram base address for page table entry */
1011 u64 vram_base_offset;
1012 /* is vm enabled? */
1013 bool enabled;
1014 /* for hw to save the PD addr on suspend/resume */
1015 uint32_t saved_table_addr[AMDGPU_NUM_VM];
1016 /* vm pte handling */
1017 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
1018 struct amdgpu_ring *vm_pte_funcs_ring;
1019 };
1020
1021 /*
1022 * context related structures
1023 */
1024
1025 #define AMDGPU_CTX_MAX_CS_PENDING 16
1026
1027 struct amdgpu_ctx_ring {
1028 uint64_t sequence;
1029 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
1030 struct amd_sched_entity entity;
1031 };
1032
1033 struct amdgpu_ctx {
1034 struct kref refcount;
1035 struct amdgpu_device *adev;
1036 unsigned reset_counter;
1037 spinlock_t ring_lock;
1038 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
1039 };
1040
1041 struct amdgpu_ctx_mgr {
1042 struct amdgpu_device *adev;
1043 struct mutex lock;
1044 /* protected by lock */
1045 struct idr ctx_handles;
1046 };
1047
1048 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
1049 struct amdgpu_ctx *ctx);
1050 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
1051
1052 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1053 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1054
1055 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1056 struct fence *fence);
1057 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1058 struct amdgpu_ring *ring, uint64_t seq);
1059
1060 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1061 struct drm_file *filp);
1062
1063 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1064 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1065
1066 /*
1067 * file private structure
1068 */
1069
1070 struct amdgpu_fpriv {
1071 struct amdgpu_vm vm;
1072 struct mutex bo_list_lock;
1073 struct idr bo_list_handles;
1074 struct amdgpu_ctx_mgr ctx_mgr;
1075 };
1076
1077 /*
1078 * residency list
1079 */
1080
1081 struct amdgpu_bo_list {
1082 struct mutex lock;
1083 struct amdgpu_bo *gds_obj;
1084 struct amdgpu_bo *gws_obj;
1085 struct amdgpu_bo *oa_obj;
1086 bool has_userptr;
1087 unsigned num_entries;
1088 struct amdgpu_bo_list_entry *array;
1089 };
1090
1091 struct amdgpu_bo_list *
1092 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1093 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1094 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1095
1096 /*
1097 * GFX stuff
1098 */
1099 #include "clearstate_defs.h"
1100
1101 struct amdgpu_rlc {
1102 /* for power gating */
1103 struct amdgpu_bo *save_restore_obj;
1104 uint64_t save_restore_gpu_addr;
1105 volatile uint32_t *sr_ptr;
1106 const u32 *reg_list;
1107 u32 reg_list_size;
1108 /* for clear state */
1109 struct amdgpu_bo *clear_state_obj;
1110 uint64_t clear_state_gpu_addr;
1111 volatile uint32_t *cs_ptr;
1112 const struct cs_section_def *cs_data;
1113 u32 clear_state_size;
1114 /* for cp tables */
1115 struct amdgpu_bo *cp_table_obj;
1116 uint64_t cp_table_gpu_addr;
1117 volatile uint32_t *cp_table_ptr;
1118 u32 cp_table_size;
1119 };
1120
1121 struct amdgpu_mec {
1122 struct amdgpu_bo *hpd_eop_obj;
1123 u64 hpd_eop_gpu_addr;
1124 u32 num_pipe;
1125 u32 num_mec;
1126 u32 num_queue;
1127 };
1128
1129 /*
1130 * GPU scratch registers structures, functions & helpers
1131 */
1132 struct amdgpu_scratch {
1133 unsigned num_reg;
1134 uint32_t reg_base;
1135 bool free[32];
1136 uint32_t reg[32];
1137 };
1138
1139 /*
1140 * GFX configurations
1141 */
1142 struct amdgpu_gca_config {
1143 unsigned max_shader_engines;
1144 unsigned max_tile_pipes;
1145 unsigned max_cu_per_sh;
1146 unsigned max_sh_per_se;
1147 unsigned max_backends_per_se;
1148 unsigned max_texture_channel_caches;
1149 unsigned max_gprs;
1150 unsigned max_gs_threads;
1151 unsigned max_hw_contexts;
1152 unsigned sc_prim_fifo_size_frontend;
1153 unsigned sc_prim_fifo_size_backend;
1154 unsigned sc_hiz_tile_fifo_size;
1155 unsigned sc_earlyz_tile_fifo_size;
1156
1157 unsigned num_tile_pipes;
1158 unsigned backend_enable_mask;
1159 unsigned mem_max_burst_length_bytes;
1160 unsigned mem_row_size_in_kb;
1161 unsigned shader_engine_tile_size;
1162 unsigned num_gpus;
1163 unsigned multi_gpu_tile_size;
1164 unsigned mc_arb_ramcfg;
1165 unsigned gb_addr_config;
1166
1167 uint32_t tile_mode_array[32];
1168 uint32_t macrotile_mode_array[16];
1169 };
1170
1171 struct amdgpu_gfx {
1172 struct mutex gpu_clock_mutex;
1173 struct amdgpu_gca_config config;
1174 struct amdgpu_rlc rlc;
1175 struct amdgpu_mec mec;
1176 struct amdgpu_scratch scratch;
1177 const struct firmware *me_fw; /* ME firmware */
1178 uint32_t me_fw_version;
1179 const struct firmware *pfp_fw; /* PFP firmware */
1180 uint32_t pfp_fw_version;
1181 const struct firmware *ce_fw; /* CE firmware */
1182 uint32_t ce_fw_version;
1183 const struct firmware *rlc_fw; /* RLC firmware */
1184 uint32_t rlc_fw_version;
1185 const struct firmware *mec_fw; /* MEC firmware */
1186 uint32_t mec_fw_version;
1187 const struct firmware *mec2_fw; /* MEC2 firmware */
1188 uint32_t mec2_fw_version;
1189 uint32_t me_feature_version;
1190 uint32_t ce_feature_version;
1191 uint32_t pfp_feature_version;
1192 uint32_t rlc_feature_version;
1193 uint32_t mec_feature_version;
1194 uint32_t mec2_feature_version;
1195 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1196 unsigned num_gfx_rings;
1197 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1198 unsigned num_compute_rings;
1199 struct amdgpu_irq_src eop_irq;
1200 struct amdgpu_irq_src priv_reg_irq;
1201 struct amdgpu_irq_src priv_inst_irq;
1202 /* gfx status */
1203 uint32_t gfx_current_status;
1204 /* ce ram size*/
1205 unsigned ce_ram_size;
1206 };
1207
1208 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1209 unsigned size, struct amdgpu_ib *ib);
1210 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1211 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1212 struct amdgpu_ib *ib, void *owner);
1213 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1214 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1215 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1216 /* Ring access between begin & end cannot sleep */
1217 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1218 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1219 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1220 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1221 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1222 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1223 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1224 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1225 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1226 uint32_t **data);
1227 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1228 unsigned size, uint32_t *data);
1229 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1230 unsigned ring_size, u32 nop, u32 align_mask,
1231 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1232 enum amdgpu_ring_type ring_type);
1233 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1234
1235 /*
1236 * CS.
1237 */
1238 struct amdgpu_cs_chunk {
1239 uint32_t chunk_id;
1240 uint32_t length_dw;
1241 uint32_t *kdata;
1242 void __user *user_ptr;
1243 };
1244
1245 struct amdgpu_cs_parser {
1246 struct amdgpu_device *adev;
1247 struct drm_file *filp;
1248 struct amdgpu_ctx *ctx;
1249 struct amdgpu_bo_list *bo_list;
1250 /* chunks */
1251 unsigned nchunks;
1252 struct amdgpu_cs_chunk *chunks;
1253 /* relocations */
1254 struct amdgpu_bo_list_entry *vm_bos;
1255 struct list_head validated;
1256
1257 struct amdgpu_ib *ibs;
1258 uint32_t num_ibs;
1259
1260 struct ww_acquire_ctx ticket;
1261
1262 /* user fence */
1263 struct amdgpu_user_fence uf;
1264 };
1265
1266 struct amdgpu_job {
1267 struct amd_sched_job base;
1268 struct amdgpu_device *adev;
1269 struct amdgpu_ib *ibs;
1270 uint32_t num_ibs;
1271 struct mutex job_lock;
1272 struct amdgpu_user_fence uf;
1273 int (*free_job)(struct amdgpu_job *job);
1274 };
1275 #define to_amdgpu_job(sched_job) \
1276 container_of((sched_job), struct amdgpu_job, base)
1277
1278 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1279 {
1280 return p->ibs[ib_idx].ptr[idx];
1281 }
1282
1283 /*
1284 * Writeback
1285 */
1286 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1287
1288 struct amdgpu_wb {
1289 struct amdgpu_bo *wb_obj;
1290 volatile uint32_t *wb;
1291 uint64_t gpu_addr;
1292 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1293 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1294 };
1295
1296 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1297 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1298
1299 /**
1300 * struct amdgpu_pm - power management datas
1301 * It keeps track of various data needed to take powermanagement decision.
1302 */
1303
1304 enum amdgpu_pm_state_type {
1305 /* not used for dpm */
1306 POWER_STATE_TYPE_DEFAULT,
1307 POWER_STATE_TYPE_POWERSAVE,
1308 /* user selectable states */
1309 POWER_STATE_TYPE_BATTERY,
1310 POWER_STATE_TYPE_BALANCED,
1311 POWER_STATE_TYPE_PERFORMANCE,
1312 /* internal states */
1313 POWER_STATE_TYPE_INTERNAL_UVD,
1314 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1315 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1316 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1317 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1318 POWER_STATE_TYPE_INTERNAL_BOOT,
1319 POWER_STATE_TYPE_INTERNAL_THERMAL,
1320 POWER_STATE_TYPE_INTERNAL_ACPI,
1321 POWER_STATE_TYPE_INTERNAL_ULV,
1322 POWER_STATE_TYPE_INTERNAL_3DPERF,
1323 };
1324
1325 enum amdgpu_int_thermal_type {
1326 THERMAL_TYPE_NONE,
1327 THERMAL_TYPE_EXTERNAL,
1328 THERMAL_TYPE_EXTERNAL_GPIO,
1329 THERMAL_TYPE_RV6XX,
1330 THERMAL_TYPE_RV770,
1331 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1332 THERMAL_TYPE_EVERGREEN,
1333 THERMAL_TYPE_SUMO,
1334 THERMAL_TYPE_NI,
1335 THERMAL_TYPE_SI,
1336 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1337 THERMAL_TYPE_CI,
1338 THERMAL_TYPE_KV,
1339 };
1340
1341 enum amdgpu_dpm_auto_throttle_src {
1342 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1343 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1344 };
1345
1346 enum amdgpu_dpm_event_src {
1347 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1348 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1349 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1350 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1351 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1352 };
1353
1354 #define AMDGPU_MAX_VCE_LEVELS 6
1355
1356 enum amdgpu_vce_level {
1357 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1358 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1359 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1360 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1361 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1362 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1363 };
1364
1365 struct amdgpu_ps {
1366 u32 caps; /* vbios flags */
1367 u32 class; /* vbios flags */
1368 u32 class2; /* vbios flags */
1369 /* UVD clocks */
1370 u32 vclk;
1371 u32 dclk;
1372 /* VCE clocks */
1373 u32 evclk;
1374 u32 ecclk;
1375 bool vce_active;
1376 enum amdgpu_vce_level vce_level;
1377 /* asic priv */
1378 void *ps_priv;
1379 };
1380
1381 struct amdgpu_dpm_thermal {
1382 /* thermal interrupt work */
1383 struct work_struct work;
1384 /* low temperature threshold */
1385 int min_temp;
1386 /* high temperature threshold */
1387 int max_temp;
1388 /* was last interrupt low to high or high to low */
1389 bool high_to_low;
1390 /* interrupt source */
1391 struct amdgpu_irq_src irq;
1392 };
1393
1394 enum amdgpu_clk_action
1395 {
1396 AMDGPU_SCLK_UP = 1,
1397 AMDGPU_SCLK_DOWN
1398 };
1399
1400 struct amdgpu_blacklist_clocks
1401 {
1402 u32 sclk;
1403 u32 mclk;
1404 enum amdgpu_clk_action action;
1405 };
1406
1407 struct amdgpu_clock_and_voltage_limits {
1408 u32 sclk;
1409 u32 mclk;
1410 u16 vddc;
1411 u16 vddci;
1412 };
1413
1414 struct amdgpu_clock_array {
1415 u32 count;
1416 u32 *values;
1417 };
1418
1419 struct amdgpu_clock_voltage_dependency_entry {
1420 u32 clk;
1421 u16 v;
1422 };
1423
1424 struct amdgpu_clock_voltage_dependency_table {
1425 u32 count;
1426 struct amdgpu_clock_voltage_dependency_entry *entries;
1427 };
1428
1429 union amdgpu_cac_leakage_entry {
1430 struct {
1431 u16 vddc;
1432 u32 leakage;
1433 };
1434 struct {
1435 u16 vddc1;
1436 u16 vddc2;
1437 u16 vddc3;
1438 };
1439 };
1440
1441 struct amdgpu_cac_leakage_table {
1442 u32 count;
1443 union amdgpu_cac_leakage_entry *entries;
1444 };
1445
1446 struct amdgpu_phase_shedding_limits_entry {
1447 u16 voltage;
1448 u32 sclk;
1449 u32 mclk;
1450 };
1451
1452 struct amdgpu_phase_shedding_limits_table {
1453 u32 count;
1454 struct amdgpu_phase_shedding_limits_entry *entries;
1455 };
1456
1457 struct amdgpu_uvd_clock_voltage_dependency_entry {
1458 u32 vclk;
1459 u32 dclk;
1460 u16 v;
1461 };
1462
1463 struct amdgpu_uvd_clock_voltage_dependency_table {
1464 u8 count;
1465 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1466 };
1467
1468 struct amdgpu_vce_clock_voltage_dependency_entry {
1469 u32 ecclk;
1470 u32 evclk;
1471 u16 v;
1472 };
1473
1474 struct amdgpu_vce_clock_voltage_dependency_table {
1475 u8 count;
1476 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1477 };
1478
1479 struct amdgpu_ppm_table {
1480 u8 ppm_design;
1481 u16 cpu_core_number;
1482 u32 platform_tdp;
1483 u32 small_ac_platform_tdp;
1484 u32 platform_tdc;
1485 u32 small_ac_platform_tdc;
1486 u32 apu_tdp;
1487 u32 dgpu_tdp;
1488 u32 dgpu_ulv_power;
1489 u32 tj_max;
1490 };
1491
1492 struct amdgpu_cac_tdp_table {
1493 u16 tdp;
1494 u16 configurable_tdp;
1495 u16 tdc;
1496 u16 battery_power_limit;
1497 u16 small_power_limit;
1498 u16 low_cac_leakage;
1499 u16 high_cac_leakage;
1500 u16 maximum_power_delivery_limit;
1501 };
1502
1503 struct amdgpu_dpm_dynamic_state {
1504 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1505 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1506 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1507 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1508 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1509 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1510 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1511 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1512 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1513 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1514 struct amdgpu_clock_array valid_sclk_values;
1515 struct amdgpu_clock_array valid_mclk_values;
1516 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1517 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1518 u32 mclk_sclk_ratio;
1519 u32 sclk_mclk_delta;
1520 u16 vddc_vddci_delta;
1521 u16 min_vddc_for_pcie_gen2;
1522 struct amdgpu_cac_leakage_table cac_leakage_table;
1523 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1524 struct amdgpu_ppm_table *ppm_table;
1525 struct amdgpu_cac_tdp_table *cac_tdp_table;
1526 };
1527
1528 struct amdgpu_dpm_fan {
1529 u16 t_min;
1530 u16 t_med;
1531 u16 t_high;
1532 u16 pwm_min;
1533 u16 pwm_med;
1534 u16 pwm_high;
1535 u8 t_hyst;
1536 u32 cycle_delay;
1537 u16 t_max;
1538 u8 control_mode;
1539 u16 default_max_fan_pwm;
1540 u16 default_fan_output_sensitivity;
1541 u16 fan_output_sensitivity;
1542 bool ucode_fan_control;
1543 };
1544
1545 enum amdgpu_pcie_gen {
1546 AMDGPU_PCIE_GEN1 = 0,
1547 AMDGPU_PCIE_GEN2 = 1,
1548 AMDGPU_PCIE_GEN3 = 2,
1549 AMDGPU_PCIE_GEN_INVALID = 0xffff
1550 };
1551
1552 enum amdgpu_dpm_forced_level {
1553 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1554 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1555 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1556 };
1557
1558 struct amdgpu_vce_state {
1559 /* vce clocks */
1560 u32 evclk;
1561 u32 ecclk;
1562 /* gpu clocks */
1563 u32 sclk;
1564 u32 mclk;
1565 u8 clk_idx;
1566 u8 pstate;
1567 };
1568
1569 struct amdgpu_dpm_funcs {
1570 int (*get_temperature)(struct amdgpu_device *adev);
1571 int (*pre_set_power_state)(struct amdgpu_device *adev);
1572 int (*set_power_state)(struct amdgpu_device *adev);
1573 void (*post_set_power_state)(struct amdgpu_device *adev);
1574 void (*display_configuration_changed)(struct amdgpu_device *adev);
1575 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1576 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1577 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1578 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1579 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1580 bool (*vblank_too_short)(struct amdgpu_device *adev);
1581 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1582 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1583 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1584 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1585 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1586 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1587 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1588 };
1589
1590 struct amdgpu_dpm {
1591 struct amdgpu_ps *ps;
1592 /* number of valid power states */
1593 int num_ps;
1594 /* current power state that is active */
1595 struct amdgpu_ps *current_ps;
1596 /* requested power state */
1597 struct amdgpu_ps *requested_ps;
1598 /* boot up power state */
1599 struct amdgpu_ps *boot_ps;
1600 /* default uvd power state */
1601 struct amdgpu_ps *uvd_ps;
1602 /* vce requirements */
1603 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1604 enum amdgpu_vce_level vce_level;
1605 enum amdgpu_pm_state_type state;
1606 enum amdgpu_pm_state_type user_state;
1607 u32 platform_caps;
1608 u32 voltage_response_time;
1609 u32 backbias_response_time;
1610 void *priv;
1611 u32 new_active_crtcs;
1612 int new_active_crtc_count;
1613 u32 current_active_crtcs;
1614 int current_active_crtc_count;
1615 struct amdgpu_dpm_dynamic_state dyn_state;
1616 struct amdgpu_dpm_fan fan;
1617 u32 tdp_limit;
1618 u32 near_tdp_limit;
1619 u32 near_tdp_limit_adjusted;
1620 u32 sq_ramping_threshold;
1621 u32 cac_leakage;
1622 u16 tdp_od_limit;
1623 u32 tdp_adjustment;
1624 u16 load_line_slope;
1625 bool power_control;
1626 bool ac_power;
1627 /* special states active */
1628 bool thermal_active;
1629 bool uvd_active;
1630 bool vce_active;
1631 /* thermal handling */
1632 struct amdgpu_dpm_thermal thermal;
1633 /* forced levels */
1634 enum amdgpu_dpm_forced_level forced_level;
1635 };
1636
1637 struct amdgpu_pm {
1638 struct mutex mutex;
1639 u32 current_sclk;
1640 u32 current_mclk;
1641 u32 default_sclk;
1642 u32 default_mclk;
1643 struct amdgpu_i2c_chan *i2c_bus;
1644 /* internal thermal controller on rv6xx+ */
1645 enum amdgpu_int_thermal_type int_thermal_type;
1646 struct device *int_hwmon_dev;
1647 /* fan control parameters */
1648 bool no_fan;
1649 u8 fan_pulses_per_revolution;
1650 u8 fan_min_rpm;
1651 u8 fan_max_rpm;
1652 /* dpm */
1653 bool dpm_enabled;
1654 struct amdgpu_dpm dpm;
1655 const struct firmware *fw; /* SMC firmware */
1656 uint32_t fw_version;
1657 const struct amdgpu_dpm_funcs *funcs;
1658 };
1659
1660 /*
1661 * UVD
1662 */
1663 #define AMDGPU_MAX_UVD_HANDLES 10
1664 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1665 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1666 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1667
1668 struct amdgpu_uvd {
1669 struct amdgpu_bo *vcpu_bo;
1670 void *cpu_addr;
1671 uint64_t gpu_addr;
1672 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1673 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1674 struct delayed_work idle_work;
1675 const struct firmware *fw; /* UVD firmware */
1676 struct amdgpu_ring ring;
1677 struct amdgpu_irq_src irq;
1678 bool address_64_bit;
1679 };
1680
1681 /*
1682 * VCE
1683 */
1684 #define AMDGPU_MAX_VCE_HANDLES 16
1685 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1686
1687 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1688 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1689
1690 struct amdgpu_vce {
1691 struct amdgpu_bo *vcpu_bo;
1692 uint64_t gpu_addr;
1693 unsigned fw_version;
1694 unsigned fb_version;
1695 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1696 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1697 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1698 struct delayed_work idle_work;
1699 const struct firmware *fw; /* VCE firmware */
1700 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1701 struct amdgpu_irq_src irq;
1702 unsigned harvest_config;
1703 };
1704
1705 /*
1706 * SDMA
1707 */
1708 struct amdgpu_sdma_instance {
1709 /* SDMA firmware */
1710 const struct firmware *fw;
1711 uint32_t fw_version;
1712 uint32_t feature_version;
1713
1714 struct amdgpu_ring ring;
1715 bool burst_nop;
1716 };
1717
1718 struct amdgpu_sdma {
1719 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1720 struct amdgpu_irq_src trap_irq;
1721 struct amdgpu_irq_src illegal_inst_irq;
1722 int num_instances;
1723 };
1724
1725 /*
1726 * Firmware
1727 */
1728 struct amdgpu_firmware {
1729 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1730 bool smu_load;
1731 struct amdgpu_bo *fw_buf;
1732 unsigned int fw_size;
1733 };
1734
1735 /*
1736 * Benchmarking
1737 */
1738 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1739
1740
1741 /*
1742 * Testing
1743 */
1744 void amdgpu_test_moves(struct amdgpu_device *adev);
1745 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1746 struct amdgpu_ring *cpA,
1747 struct amdgpu_ring *cpB);
1748 void amdgpu_test_syncing(struct amdgpu_device *adev);
1749
1750 /*
1751 * MMU Notifier
1752 */
1753 #if defined(CONFIG_MMU_NOTIFIER)
1754 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1755 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1756 #else
1757 static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1758 {
1759 return -ENODEV;
1760 }
1761 static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1762 #endif
1763
1764 /*
1765 * Debugfs
1766 */
1767 struct amdgpu_debugfs {
1768 struct drm_info_list *files;
1769 unsigned num_files;
1770 };
1771
1772 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1773 struct drm_info_list *files,
1774 unsigned nfiles);
1775 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1776
1777 #if defined(CONFIG_DEBUG_FS)
1778 int amdgpu_debugfs_init(struct drm_minor *minor);
1779 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1780 #endif
1781
1782 /*
1783 * amdgpu smumgr functions
1784 */
1785 struct amdgpu_smumgr_funcs {
1786 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1787 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1788 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1789 };
1790
1791 /*
1792 * amdgpu smumgr
1793 */
1794 struct amdgpu_smumgr {
1795 struct amdgpu_bo *toc_buf;
1796 struct amdgpu_bo *smu_buf;
1797 /* asic priv smu data */
1798 void *priv;
1799 spinlock_t smu_lock;
1800 /* smumgr functions */
1801 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1802 /* ucode loading complete flag */
1803 uint32_t fw_flags;
1804 };
1805
1806 /*
1807 * ASIC specific register table accessible by UMD
1808 */
1809 struct amdgpu_allowed_register_entry {
1810 uint32_t reg_offset;
1811 bool untouched;
1812 bool grbm_indexed;
1813 };
1814
1815 struct amdgpu_cu_info {
1816 uint32_t number; /* total active CU number */
1817 uint32_t ao_cu_mask;
1818 uint32_t bitmap[4][4];
1819 };
1820
1821
1822 /*
1823 * ASIC specific functions.
1824 */
1825 struct amdgpu_asic_funcs {
1826 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1827 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1828 u32 sh_num, u32 reg_offset, u32 *value);
1829 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1830 int (*reset)(struct amdgpu_device *adev);
1831 /* wait for mc_idle */
1832 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1833 /* get the reference clock */
1834 u32 (*get_xclk)(struct amdgpu_device *adev);
1835 /* get the gpu clock counter */
1836 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1837 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1838 /* MM block clocks */
1839 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1840 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1841 };
1842
1843 /*
1844 * IOCTL.
1845 */
1846 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1847 struct drm_file *filp);
1848 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1849 struct drm_file *filp);
1850
1851 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1852 struct drm_file *filp);
1853 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1854 struct drm_file *filp);
1855 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1856 struct drm_file *filp);
1857 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1858 struct drm_file *filp);
1859 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1860 struct drm_file *filp);
1861 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1862 struct drm_file *filp);
1863 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1864 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1865
1866 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1867 struct drm_file *filp);
1868
1869 /* VRAM scratch page for HDP bug, default vram page */
1870 struct amdgpu_vram_scratch {
1871 struct amdgpu_bo *robj;
1872 volatile uint32_t *ptr;
1873 u64 gpu_addr;
1874 };
1875
1876 /*
1877 * ACPI
1878 */
1879 struct amdgpu_atif_notification_cfg {
1880 bool enabled;
1881 int command_code;
1882 };
1883
1884 struct amdgpu_atif_notifications {
1885 bool display_switch;
1886 bool expansion_mode_change;
1887 bool thermal_state;
1888 bool forced_power_state;
1889 bool system_power_state;
1890 bool display_conf_change;
1891 bool px_gfx_switch;
1892 bool brightness_change;
1893 bool dgpu_display_event;
1894 };
1895
1896 struct amdgpu_atif_functions {
1897 bool system_params;
1898 bool sbios_requests;
1899 bool select_active_disp;
1900 bool lid_state;
1901 bool get_tv_standard;
1902 bool set_tv_standard;
1903 bool get_panel_expansion_mode;
1904 bool set_panel_expansion_mode;
1905 bool temperature_change;
1906 bool graphics_device_types;
1907 };
1908
1909 struct amdgpu_atif {
1910 struct amdgpu_atif_notifications notifications;
1911 struct amdgpu_atif_functions functions;
1912 struct amdgpu_atif_notification_cfg notification_cfg;
1913 struct amdgpu_encoder *encoder_for_bl;
1914 };
1915
1916 struct amdgpu_atcs_functions {
1917 bool get_ext_state;
1918 bool pcie_perf_req;
1919 bool pcie_dev_rdy;
1920 bool pcie_bus_width;
1921 };
1922
1923 struct amdgpu_atcs {
1924 struct amdgpu_atcs_functions functions;
1925 };
1926
1927 /*
1928 * CGS
1929 */
1930 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1931 void amdgpu_cgs_destroy_device(void *cgs_device);
1932
1933
1934 /*
1935 * Core structure, functions and helpers.
1936 */
1937 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1938 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1939
1940 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1941 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1942
1943 struct amdgpu_ip_block_status {
1944 bool valid;
1945 bool sw;
1946 bool hw;
1947 };
1948
1949 struct amdgpu_device {
1950 struct device *dev;
1951 struct drm_device *ddev;
1952 struct pci_dev *pdev;
1953
1954 /* ASIC */
1955 enum amd_asic_type asic_type;
1956 uint32_t family;
1957 uint32_t rev_id;
1958 uint32_t external_rev_id;
1959 unsigned long flags;
1960 int usec_timeout;
1961 const struct amdgpu_asic_funcs *asic_funcs;
1962 bool shutdown;
1963 bool suspend;
1964 bool need_dma32;
1965 bool accel_working;
1966 struct work_struct reset_work;
1967 struct notifier_block acpi_nb;
1968 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1969 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1970 unsigned debugfs_count;
1971 #if defined(CONFIG_DEBUG_FS)
1972 struct dentry *debugfs_regs;
1973 #endif
1974 struct amdgpu_atif atif;
1975 struct amdgpu_atcs atcs;
1976 struct mutex srbm_mutex;
1977 /* GRBM index mutex. Protects concurrent access to GRBM index */
1978 struct mutex grbm_idx_mutex;
1979 struct dev_pm_domain vga_pm_domain;
1980 bool have_disp_power_ref;
1981
1982 /* BIOS */
1983 uint8_t *bios;
1984 bool is_atom_bios;
1985 uint16_t bios_header_start;
1986 struct amdgpu_bo *stollen_vga_memory;
1987 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1988
1989 /* Register/doorbell mmio */
1990 resource_size_t rmmio_base;
1991 resource_size_t rmmio_size;
1992 void __iomem *rmmio;
1993 /* protects concurrent MM_INDEX/DATA based register access */
1994 spinlock_t mmio_idx_lock;
1995 /* protects concurrent SMC based register access */
1996 spinlock_t smc_idx_lock;
1997 amdgpu_rreg_t smc_rreg;
1998 amdgpu_wreg_t smc_wreg;
1999 /* protects concurrent PCIE register access */
2000 spinlock_t pcie_idx_lock;
2001 amdgpu_rreg_t pcie_rreg;
2002 amdgpu_wreg_t pcie_wreg;
2003 /* protects concurrent UVD register access */
2004 spinlock_t uvd_ctx_idx_lock;
2005 amdgpu_rreg_t uvd_ctx_rreg;
2006 amdgpu_wreg_t uvd_ctx_wreg;
2007 /* protects concurrent DIDT register access */
2008 spinlock_t didt_idx_lock;
2009 amdgpu_rreg_t didt_rreg;
2010 amdgpu_wreg_t didt_wreg;
2011 /* protects concurrent ENDPOINT (audio) register access */
2012 spinlock_t audio_endpt_idx_lock;
2013 amdgpu_block_rreg_t audio_endpt_rreg;
2014 amdgpu_block_wreg_t audio_endpt_wreg;
2015 void __iomem *rio_mem;
2016 resource_size_t rio_mem_size;
2017 struct amdgpu_doorbell doorbell;
2018
2019 /* clock/pll info */
2020 struct amdgpu_clock clock;
2021
2022 /* MC */
2023 struct amdgpu_mc mc;
2024 struct amdgpu_gart gart;
2025 struct amdgpu_dummy_page dummy_page;
2026 struct amdgpu_vm_manager vm_manager;
2027
2028 /* memory management */
2029 struct amdgpu_mman mman;
2030 struct amdgpu_gem gem;
2031 struct amdgpu_vram_scratch vram_scratch;
2032 struct amdgpu_wb wb;
2033 atomic64_t vram_usage;
2034 atomic64_t vram_vis_usage;
2035 atomic64_t gtt_usage;
2036 atomic64_t num_bytes_moved;
2037 atomic_t gpu_reset_counter;
2038
2039 /* display */
2040 struct amdgpu_mode_info mode_info;
2041 struct work_struct hotplug_work;
2042 struct amdgpu_irq_src crtc_irq;
2043 struct amdgpu_irq_src pageflip_irq;
2044 struct amdgpu_irq_src hpd_irq;
2045
2046 /* rings */
2047 unsigned fence_context;
2048 struct mutex ring_lock;
2049 unsigned num_rings;
2050 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2051 bool ib_pool_ready;
2052 struct amdgpu_sa_manager ring_tmp_bo;
2053
2054 /* interrupts */
2055 struct amdgpu_irq irq;
2056
2057 /* dpm */
2058 struct amdgpu_pm pm;
2059 u32 cg_flags;
2060 u32 pg_flags;
2061
2062 /* amdgpu smumgr */
2063 struct amdgpu_smumgr smu;
2064
2065 /* gfx */
2066 struct amdgpu_gfx gfx;
2067
2068 /* sdma */
2069 struct amdgpu_sdma sdma;
2070
2071 /* uvd */
2072 bool has_uvd;
2073 struct amdgpu_uvd uvd;
2074
2075 /* vce */
2076 struct amdgpu_vce vce;
2077
2078 /* firmwares */
2079 struct amdgpu_firmware firmware;
2080
2081 /* GDS */
2082 struct amdgpu_gds gds;
2083
2084 const struct amdgpu_ip_block_version *ip_blocks;
2085 int num_ip_blocks;
2086 struct amdgpu_ip_block_status *ip_block_status;
2087 struct mutex mn_lock;
2088 DECLARE_HASHTABLE(mn_hash, 7);
2089
2090 /* tracking pinned memory */
2091 u64 vram_pin_size;
2092 u64 gart_pin_size;
2093
2094 /* amdkfd interface */
2095 struct kfd_dev *kfd;
2096
2097 /* kernel conext for IB submission */
2098 struct amdgpu_ctx kernel_ctx;
2099 };
2100
2101 bool amdgpu_device_is_px(struct drm_device *dev);
2102 int amdgpu_device_init(struct amdgpu_device *adev,
2103 struct drm_device *ddev,
2104 struct pci_dev *pdev,
2105 uint32_t flags);
2106 void amdgpu_device_fini(struct amdgpu_device *adev);
2107 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2108
2109 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2110 bool always_indirect);
2111 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2112 bool always_indirect);
2113 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2114 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2115
2116 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2117 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2118
2119 /*
2120 * Cast helper
2121 */
2122 extern const struct fence_ops amdgpu_fence_ops;
2123 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2124 {
2125 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2126
2127 if (__f->base.ops == &amdgpu_fence_ops)
2128 return __f;
2129
2130 return NULL;
2131 }
2132
2133 /*
2134 * Registers read & write functions.
2135 */
2136 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2137 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2138 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2139 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2140 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2141 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2142 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2143 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2144 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2145 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2146 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2147 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2148 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2149 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2150 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2151 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2152 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2153 #define WREG32_P(reg, val, mask) \
2154 do { \
2155 uint32_t tmp_ = RREG32(reg); \
2156 tmp_ &= (mask); \
2157 tmp_ |= ((val) & ~(mask)); \
2158 WREG32(reg, tmp_); \
2159 } while (0)
2160 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2161 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2162 #define WREG32_PLL_P(reg, val, mask) \
2163 do { \
2164 uint32_t tmp_ = RREG32_PLL(reg); \
2165 tmp_ &= (mask); \
2166 tmp_ |= ((val) & ~(mask)); \
2167 WREG32_PLL(reg, tmp_); \
2168 } while (0)
2169 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2170 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2171 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2172
2173 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2174 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2175
2176 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2177 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2178
2179 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2180 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2181 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2182
2183 #define REG_GET_FIELD(value, reg, field) \
2184 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2185
2186 /*
2187 * BIOS helpers.
2188 */
2189 #define RBIOS8(i) (adev->bios[i])
2190 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2191 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2192
2193 /*
2194 * RING helpers.
2195 */
2196 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2197 {
2198 if (ring->count_dw <= 0)
2199 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2200 ring->ring[ring->wptr++] = v;
2201 ring->wptr &= ring->ptr_mask;
2202 ring->count_dw--;
2203 ring->ring_free_dw--;
2204 }
2205
2206 static inline struct amdgpu_sdma_instance *
2207 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2208 {
2209 struct amdgpu_device *adev = ring->adev;
2210 int i;
2211
2212 for (i = 0; i < adev->sdma.num_instances; i++)
2213 if (&adev->sdma.instance[i].ring == ring)
2214 break;
2215
2216 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2217 return &adev->sdma.instance[i];
2218 else
2219 return NULL;
2220 }
2221
2222 /*
2223 * ASICs macro.
2224 */
2225 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2226 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2227 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2228 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2229 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2230 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2231 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2232 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2233 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2234 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2235 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2236 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2237 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2238 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2239 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2240 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2241 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2242 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2243 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2244 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2245 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2246 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2247 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2248 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2249 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2250 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2251 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2252 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2253 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2254 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2255 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2256 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2257 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2258 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2259 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2260 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2261 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2262 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2263 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2264 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2265 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2266 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2267 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2268 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2269 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2270 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2271 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2272 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2273 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2274 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2275 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2276 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2277 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2278 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2279 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2280 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2281 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2282 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2283 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2284 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2285 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2286 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2287 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2288 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2289 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2290 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2291 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2292
2293 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2294
2295 /* Common functions */
2296 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2297 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2298 bool amdgpu_card_posted(struct amdgpu_device *adev);
2299 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2300 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2301 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
2302 struct drm_file *filp,
2303 struct amdgpu_ctx *ctx,
2304 struct amdgpu_ib *ibs,
2305 uint32_t num_ibs);
2306
2307 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2308 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2309 u32 ip_instance, u32 ring,
2310 struct amdgpu_ring **out_ring);
2311 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2312 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2313 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2314 uint32_t flags);
2315 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2316 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2317 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2318 struct ttm_mem_reg *mem);
2319 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2320 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2321 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2322 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2323 const u32 *registers,
2324 const u32 array_size);
2325
2326 bool amdgpu_device_is_px(struct drm_device *dev);
2327 /* atpx handler */
2328 #if defined(CONFIG_VGA_SWITCHEROO)
2329 void amdgpu_register_atpx_handler(void);
2330 void amdgpu_unregister_atpx_handler(void);
2331 #else
2332 static inline void amdgpu_register_atpx_handler(void) {}
2333 static inline void amdgpu_unregister_atpx_handler(void) {}
2334 #endif
2335
2336 /*
2337 * KMS
2338 */
2339 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2340 extern int amdgpu_max_kms_ioctl;
2341
2342 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2343 int amdgpu_driver_unload_kms(struct drm_device *dev);
2344 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2345 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2346 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2347 struct drm_file *file_priv);
2348 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2349 struct drm_file *file_priv);
2350 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2351 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2352 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2353 int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2354 void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2355 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2356 int *max_error,
2357 struct timeval *vblank_time,
2358 unsigned flags);
2359 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2360 unsigned long arg);
2361
2362 /*
2363 * vm
2364 */
2365 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2366 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2367 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2368 struct amdgpu_vm *vm,
2369 struct list_head *head);
2370 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
2371 struct amdgpu_sync *sync);
2372 void amdgpu_vm_flush(struct amdgpu_ring *ring,
2373 struct amdgpu_vm *vm,
2374 struct fence *updates);
2375 void amdgpu_vm_fence(struct amdgpu_device *adev,
2376 struct amdgpu_vm *vm,
2377 struct amdgpu_fence *fence);
2378 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2379 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2380 struct amdgpu_vm *vm);
2381 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2382 struct amdgpu_vm *vm);
2383 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
2384 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
2385 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2386 struct amdgpu_bo_va *bo_va,
2387 struct ttm_mem_reg *mem);
2388 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2389 struct amdgpu_bo *bo);
2390 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2391 struct amdgpu_bo *bo);
2392 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2393 struct amdgpu_vm *vm,
2394 struct amdgpu_bo *bo);
2395 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2396 struct amdgpu_bo_va *bo_va,
2397 uint64_t addr, uint64_t offset,
2398 uint64_t size, uint32_t flags);
2399 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2400 struct amdgpu_bo_va *bo_va,
2401 uint64_t addr);
2402 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2403 struct amdgpu_bo_va *bo_va);
2404 int amdgpu_vm_free_job(struct amdgpu_job *job);
2405 /*
2406 * functions used by amdgpu_encoder.c
2407 */
2408 struct amdgpu_afmt_acr {
2409 u32 clock;
2410
2411 int n_32khz;
2412 int cts_32khz;
2413
2414 int n_44_1khz;
2415 int cts_44_1khz;
2416
2417 int n_48khz;
2418 int cts_48khz;
2419
2420 };
2421
2422 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2423
2424 /* amdgpu_acpi.c */
2425 #if defined(CONFIG_ACPI)
2426 int amdgpu_acpi_init(struct amdgpu_device *adev);
2427 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2428 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2429 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2430 u8 perf_req, bool advertise);
2431 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2432 #else
2433 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2434 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2435 #endif
2436
2437 struct amdgpu_bo_va_mapping *
2438 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2439 uint64_t addr, struct amdgpu_bo **bo);
2440
2441 #include "amdgpu_object.h"
2442
2443 #endif
Linux kernel - Deliverables
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