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[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_family.h"
51 #include "amdgpu_mode.h"
52 #include "amdgpu_ih.h"
53 #include "amdgpu_irq.h"
54 #include "amdgpu_ucode.h"
55 #include "amdgpu_gds.h"
56
57 /*
58 * Modules parameters.
59 */
60 extern int amdgpu_modeset;
61 extern int amdgpu_vram_limit;
62 extern int amdgpu_gart_size;
63 extern int amdgpu_benchmarking;
64 extern int amdgpu_testing;
65 extern int amdgpu_audio;
66 extern int amdgpu_disp_priority;
67 extern int amdgpu_hw_i2c;
68 extern int amdgpu_pcie_gen2;
69 extern int amdgpu_msi;
70 extern int amdgpu_lockup_timeout;
71 extern int amdgpu_dpm;
72 extern int amdgpu_smc_load_fw;
73 extern int amdgpu_aspm;
74 extern int amdgpu_runtime_pm;
75 extern int amdgpu_hard_reset;
76 extern unsigned amdgpu_ip_block_mask;
77 extern int amdgpu_bapm;
78 extern int amdgpu_deep_color;
79 extern int amdgpu_vm_size;
80 extern int amdgpu_vm_block_size;
81
82 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
83 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
84 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
85 #define AMDGPU_IB_POOL_SIZE 16
86 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
87 #define AMDGPUFB_CONN_LIMIT 4
88 #define AMDGPU_BIOS_NUM_SCRATCH 8
89
90 /* max number of rings */
91 #define AMDGPU_MAX_RINGS 16
92 #define AMDGPU_MAX_GFX_RINGS 1
93 #define AMDGPU_MAX_COMPUTE_RINGS 8
94 #define AMDGPU_MAX_VCE_RINGS 2
95
96 /* number of hw syncs before falling back on blocking */
97 #define AMDGPU_NUM_SYNCS 4
98
99 /* hardcode that limit for now */
100 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
101
102 /* hard reset data */
103 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
104
105 /* reset flags */
106 #define AMDGPU_RESET_GFX (1 << 0)
107 #define AMDGPU_RESET_COMPUTE (1 << 1)
108 #define AMDGPU_RESET_DMA (1 << 2)
109 #define AMDGPU_RESET_CP (1 << 3)
110 #define AMDGPU_RESET_GRBM (1 << 4)
111 #define AMDGPU_RESET_DMA1 (1 << 5)
112 #define AMDGPU_RESET_RLC (1 << 6)
113 #define AMDGPU_RESET_SEM (1 << 7)
114 #define AMDGPU_RESET_IH (1 << 8)
115 #define AMDGPU_RESET_VMC (1 << 9)
116 #define AMDGPU_RESET_MC (1 << 10)
117 #define AMDGPU_RESET_DISPLAY (1 << 11)
118 #define AMDGPU_RESET_UVD (1 << 12)
119 #define AMDGPU_RESET_VCE (1 << 13)
120 #define AMDGPU_RESET_VCE1 (1 << 14)
121
122 /* CG block flags */
123 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
124 #define AMDGPU_CG_BLOCK_MC (1 << 1)
125 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
126 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
127 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
128 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
129 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
130
131 /* CG flags */
132 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
133 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
134 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
135 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
136 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
137 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
138 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
139 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
140 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
141 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
142 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
143 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
144 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
145 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
146 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
147 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
148 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
149
150 /* PG flags */
151 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
152 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
153 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
154 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
155 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
156 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
157 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
158 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
159 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
160 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
161 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
162
163 /* GFX current status */
164 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
165 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
166 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
167 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
168 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
169
170 /* max cursor sizes (in pixels) */
171 #define CIK_CURSOR_WIDTH 128
172 #define CIK_CURSOR_HEIGHT 128
173
174 struct amdgpu_device;
175 struct amdgpu_fence;
176 struct amdgpu_ib;
177 struct amdgpu_vm;
178 struct amdgpu_ring;
179 struct amdgpu_semaphore;
180 struct amdgpu_cs_parser;
181 struct amdgpu_irq_src;
182 struct amdgpu_fpriv;
183
184 enum amdgpu_cp_irq {
185 AMDGPU_CP_IRQ_GFX_EOP = 0,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
193 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
194
195 AMDGPU_CP_IRQ_LAST
196 };
197
198 enum amdgpu_sdma_irq {
199 AMDGPU_SDMA_IRQ_TRAP0 = 0,
200 AMDGPU_SDMA_IRQ_TRAP1,
201
202 AMDGPU_SDMA_IRQ_LAST
203 };
204
205 enum amdgpu_thermal_irq {
206 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
207 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
208
209 AMDGPU_THERMAL_IRQ_LAST
210 };
211
212 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
213 enum amd_ip_block_type block_type,
214 enum amd_clockgating_state state);
215 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
216 enum amd_ip_block_type block_type,
217 enum amd_powergating_state state);
218
219 struct amdgpu_ip_block_version {
220 enum amd_ip_block_type type;
221 u32 major;
222 u32 minor;
223 u32 rev;
224 const struct amd_ip_funcs *funcs;
225 };
226
227 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
228 enum amd_ip_block_type type,
229 u32 major, u32 minor);
230
231 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
232 struct amdgpu_device *adev,
233 enum amd_ip_block_type type);
234
235 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
236 struct amdgpu_buffer_funcs {
237 /* maximum bytes in a single operation */
238 uint32_t copy_max_bytes;
239
240 /* number of dw to reserve per operation */
241 unsigned copy_num_dw;
242
243 /* used for buffer migration */
244 void (*emit_copy_buffer)(struct amdgpu_ring *ring,
245 /* src addr in bytes */
246 uint64_t src_offset,
247 /* dst addr in bytes */
248 uint64_t dst_offset,
249 /* number of byte to transfer */
250 uint32_t byte_count);
251
252 /* maximum bytes in a single operation */
253 uint32_t fill_max_bytes;
254
255 /* number of dw to reserve per operation */
256 unsigned fill_num_dw;
257
258 /* used for buffer clearing */
259 void (*emit_fill_buffer)(struct amdgpu_ring *ring,
260 /* value to write to memory */
261 uint32_t src_data,
262 /* dst addr in bytes */
263 uint64_t dst_offset,
264 /* number of byte to fill */
265 uint32_t byte_count);
266 };
267
268 /* provided by hw blocks that can write ptes, e.g., sdma */
269 struct amdgpu_vm_pte_funcs {
270 /* copy pte entries from GART */
271 void (*copy_pte)(struct amdgpu_ib *ib,
272 uint64_t pe, uint64_t src,
273 unsigned count);
274 /* write pte one entry at a time with addr mapping */
275 void (*write_pte)(struct amdgpu_ib *ib,
276 uint64_t pe,
277 uint64_t addr, unsigned count,
278 uint32_t incr, uint32_t flags);
279 /* for linear pte/pde updates without addr mapping */
280 void (*set_pte_pde)(struct amdgpu_ib *ib,
281 uint64_t pe,
282 uint64_t addr, unsigned count,
283 uint32_t incr, uint32_t flags);
284 /* pad the indirect buffer to the necessary number of dw */
285 void (*pad_ib)(struct amdgpu_ib *ib);
286 };
287
288 /* provided by the gmc block */
289 struct amdgpu_gart_funcs {
290 /* flush the vm tlb via mmio */
291 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
292 uint32_t vmid);
293 /* write pte/pde updates using the cpu */
294 int (*set_pte_pde)(struct amdgpu_device *adev,
295 void *cpu_pt_addr, /* cpu addr of page table */
296 uint32_t gpu_page_idx, /* pte/pde to update */
297 uint64_t addr, /* addr to write into pte/pde */
298 uint32_t flags); /* access flags */
299 };
300
301 /* provided by the ih block */
302 struct amdgpu_ih_funcs {
303 /* ring read/write ptr handling, called from interrupt context */
304 u32 (*get_wptr)(struct amdgpu_device *adev);
305 void (*decode_iv)(struct amdgpu_device *adev,
306 struct amdgpu_iv_entry *entry);
307 void (*set_rptr)(struct amdgpu_device *adev);
308 };
309
310 /* provided by hw blocks that expose a ring buffer for commands */
311 struct amdgpu_ring_funcs {
312 /* ring read/write ptr handling */
313 u32 (*get_rptr)(struct amdgpu_ring *ring);
314 u32 (*get_wptr)(struct amdgpu_ring *ring);
315 void (*set_wptr)(struct amdgpu_ring *ring);
316 /* validating and patching of IBs */
317 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
318 /* command emit functions */
319 void (*emit_ib)(struct amdgpu_ring *ring,
320 struct amdgpu_ib *ib);
321 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
322 uint64_t seq, unsigned flags);
323 bool (*emit_semaphore)(struct amdgpu_ring *ring,
324 struct amdgpu_semaphore *semaphore,
325 bool emit_wait);
326 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
327 uint64_t pd_addr);
328 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
329 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
330 uint32_t gds_base, uint32_t gds_size,
331 uint32_t gws_base, uint32_t gws_size,
332 uint32_t oa_base, uint32_t oa_size);
333 /* testing functions */
334 int (*test_ring)(struct amdgpu_ring *ring);
335 int (*test_ib)(struct amdgpu_ring *ring);
336 bool (*is_lockup)(struct amdgpu_ring *ring);
337 };
338
339 /*
340 * BIOS.
341 */
342 bool amdgpu_get_bios(struct amdgpu_device *adev);
343 bool amdgpu_read_bios(struct amdgpu_device *adev);
344
345 /*
346 * Dummy page
347 */
348 struct amdgpu_dummy_page {
349 struct page *page;
350 dma_addr_t addr;
351 };
352 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
353 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
354
355
356 /*
357 * Clocks
358 */
359
360 #define AMDGPU_MAX_PPLL 3
361
362 struct amdgpu_clock {
363 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
364 struct amdgpu_pll spll;
365 struct amdgpu_pll mpll;
366 /* 10 Khz units */
367 uint32_t default_mclk;
368 uint32_t default_sclk;
369 uint32_t default_dispclk;
370 uint32_t current_dispclk;
371 uint32_t dp_extclk;
372 uint32_t max_pixel_clock;
373 };
374
375 /*
376 * Fences.
377 */
378 struct amdgpu_fence_driver {
379 struct amdgpu_ring *ring;
380 uint64_t gpu_addr;
381 volatile uint32_t *cpu_addr;
382 /* sync_seq is protected by ring emission lock */
383 uint64_t sync_seq[AMDGPU_MAX_RINGS];
384 atomic64_t last_seq;
385 bool initialized;
386 struct amdgpu_irq_src *irq_src;
387 unsigned irq_type;
388 struct delayed_work lockup_work;
389 };
390
391 /* some special values for the owner field */
392 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
393 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
394 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
395
396 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
397 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
398
399 struct amdgpu_fence {
400 struct fence base;
401
402 /* RB, DMA, etc. */
403 struct amdgpu_ring *ring;
404 uint64_t seq;
405
406 /* filp or special value for fence creator */
407 void *owner;
408
409 wait_queue_t fence_wake;
410 };
411
412 struct amdgpu_user_fence {
413 /* write-back bo */
414 struct amdgpu_bo *bo;
415 /* write-back address offset to bo start */
416 uint32_t offset;
417 };
418
419 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
420 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
421 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
422
423 void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
424 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
425 struct amdgpu_irq_src *irq_src,
426 unsigned irq_type);
427 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
428 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
429 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
430 struct amdgpu_fence **fence);
431 void amdgpu_fence_process(struct amdgpu_ring *ring);
432 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
433 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
434 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
435
436 bool amdgpu_fence_signaled(struct amdgpu_fence *fence);
437 int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible);
438 int amdgpu_fence_wait_any(struct amdgpu_device *adev,
439 struct amdgpu_fence **fences,
440 bool intr);
441 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
442 void amdgpu_fence_unref(struct amdgpu_fence **fence);
443
444 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
445 struct amdgpu_ring *ring);
446 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
447 struct amdgpu_ring *ring);
448
449 static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
450 struct amdgpu_fence *b)
451 {
452 if (!a) {
453 return b;
454 }
455
456 if (!b) {
457 return a;
458 }
459
460 BUG_ON(a->ring != b->ring);
461
462 if (a->seq > b->seq) {
463 return a;
464 } else {
465 return b;
466 }
467 }
468
469 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
470 struct amdgpu_fence *b)
471 {
472 if (!a) {
473 return false;
474 }
475
476 if (!b) {
477 return true;
478 }
479
480 BUG_ON(a->ring != b->ring);
481
482 return a->seq < b->seq;
483 }
484
485 int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
486 void *owner, struct amdgpu_fence **fence);
487
488 /*
489 * TTM.
490 */
491 struct amdgpu_mman {
492 struct ttm_bo_global_ref bo_global_ref;
493 struct drm_global_reference mem_global_ref;
494 struct ttm_bo_device bdev;
495 bool mem_global_referenced;
496 bool initialized;
497
498 #if defined(CONFIG_DEBUG_FS)
499 struct dentry *vram;
500 struct dentry *gtt;
501 #endif
502
503 /* buffer handling */
504 const struct amdgpu_buffer_funcs *buffer_funcs;
505 struct amdgpu_ring *buffer_funcs_ring;
506 };
507
508 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
509 uint64_t src_offset,
510 uint64_t dst_offset,
511 uint32_t byte_count,
512 struct reservation_object *resv,
513 struct amdgpu_fence **fence);
514 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
515
516 struct amdgpu_bo_list_entry {
517 struct amdgpu_bo *robj;
518 struct ttm_validate_buffer tv;
519 struct amdgpu_bo_va *bo_va;
520 unsigned prefered_domains;
521 unsigned allowed_domains;
522 uint32_t priority;
523 };
524
525 struct amdgpu_bo_va_mapping {
526 struct list_head list;
527 struct interval_tree_node it;
528 uint64_t offset;
529 uint32_t flags;
530 };
531
532 /* bo virtual addresses in a specific vm */
533 struct amdgpu_bo_va {
534 /* protected by bo being reserved */
535 struct list_head bo_list;
536 uint64_t addr;
537 struct amdgpu_fence *last_pt_update;
538 unsigned ref_count;
539
540 /* protected by vm mutex */
541 struct list_head mappings;
542 struct list_head vm_status;
543
544 /* constant after initialization */
545 struct amdgpu_vm *vm;
546 struct amdgpu_bo *bo;
547 };
548
549 #define AMDGPU_GEM_DOMAIN_MAX 0x3
550
551 struct amdgpu_bo {
552 /* Protected by gem.mutex */
553 struct list_head list;
554 /* Protected by tbo.reserved */
555 u32 initial_domain;
556 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
557 struct ttm_placement placement;
558 struct ttm_buffer_object tbo;
559 struct ttm_bo_kmap_obj kmap;
560 u64 flags;
561 unsigned pin_count;
562 void *kptr;
563 u64 tiling_flags;
564 u64 metadata_flags;
565 void *metadata;
566 u32 metadata_size;
567 /* list of all virtual address to which this bo
568 * is associated to
569 */
570 struct list_head va;
571 /* Constant after initialization */
572 struct amdgpu_device *adev;
573 struct drm_gem_object gem_base;
574
575 struct ttm_bo_kmap_obj dma_buf_vmap;
576 pid_t pid;
577 struct amdgpu_mn *mn;
578 struct list_head mn_list;
579 };
580 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
581
582 void amdgpu_gem_object_free(struct drm_gem_object *obj);
583 int amdgpu_gem_object_open(struct drm_gem_object *obj,
584 struct drm_file *file_priv);
585 void amdgpu_gem_object_close(struct drm_gem_object *obj,
586 struct drm_file *file_priv);
587 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
588 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
589 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
590 struct dma_buf_attachment *attach,
591 struct sg_table *sg);
592 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
593 struct drm_gem_object *gobj,
594 int flags);
595 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
596 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
597 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
598 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
599 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
600 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
601
602 /* sub-allocation manager, it has to be protected by another lock.
603 * By conception this is an helper for other part of the driver
604 * like the indirect buffer or semaphore, which both have their
605 * locking.
606 *
607 * Principe is simple, we keep a list of sub allocation in offset
608 * order (first entry has offset == 0, last entry has the highest
609 * offset).
610 *
611 * When allocating new object we first check if there is room at
612 * the end total_size - (last_object_offset + last_object_size) >=
613 * alloc_size. If so we allocate new object there.
614 *
615 * When there is not enough room at the end, we start waiting for
616 * each sub object until we reach object_offset+object_size >=
617 * alloc_size, this object then become the sub object we return.
618 *
619 * Alignment can't be bigger than page size.
620 *
621 * Hole are not considered for allocation to keep things simple.
622 * Assumption is that there won't be hole (all object on same
623 * alignment).
624 */
625 struct amdgpu_sa_manager {
626 wait_queue_head_t wq;
627 struct amdgpu_bo *bo;
628 struct list_head *hole;
629 struct list_head flist[AMDGPU_MAX_RINGS];
630 struct list_head olist;
631 unsigned size;
632 uint64_t gpu_addr;
633 void *cpu_ptr;
634 uint32_t domain;
635 uint32_t align;
636 };
637
638 struct amdgpu_sa_bo;
639
640 /* sub-allocation buffer */
641 struct amdgpu_sa_bo {
642 struct list_head olist;
643 struct list_head flist;
644 struct amdgpu_sa_manager *manager;
645 unsigned soffset;
646 unsigned eoffset;
647 struct amdgpu_fence *fence;
648 };
649
650 /*
651 * GEM objects.
652 */
653 struct amdgpu_gem {
654 struct mutex mutex;
655 struct list_head objects;
656 };
657
658 int amdgpu_gem_init(struct amdgpu_device *adev);
659 void amdgpu_gem_fini(struct amdgpu_device *adev);
660 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
661 int alignment, u32 initial_domain,
662 u64 flags, bool kernel,
663 struct drm_gem_object **obj);
664
665 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
666 struct drm_device *dev,
667 struct drm_mode_create_dumb *args);
668 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
669 struct drm_device *dev,
670 uint32_t handle, uint64_t *offset_p);
671
672 /*
673 * Semaphores.
674 */
675 struct amdgpu_semaphore {
676 struct amdgpu_sa_bo *sa_bo;
677 signed waiters;
678 uint64_t gpu_addr;
679 };
680
681 int amdgpu_semaphore_create(struct amdgpu_device *adev,
682 struct amdgpu_semaphore **semaphore);
683 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
684 struct amdgpu_semaphore *semaphore);
685 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
686 struct amdgpu_semaphore *semaphore);
687 void amdgpu_semaphore_free(struct amdgpu_device *adev,
688 struct amdgpu_semaphore **semaphore,
689 struct amdgpu_fence *fence);
690
691 /*
692 * Synchronization
693 */
694 struct amdgpu_sync {
695 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
696 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
697 struct amdgpu_fence *last_vm_update;
698 };
699
700 void amdgpu_sync_create(struct amdgpu_sync *sync);
701 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
702 struct fence *f);
703 int amdgpu_sync_resv(struct amdgpu_device *adev,
704 struct amdgpu_sync *sync,
705 struct reservation_object *resv,
706 void *owner);
707 int amdgpu_sync_rings(struct amdgpu_sync *sync,
708 struct amdgpu_ring *ring);
709 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
710 struct amdgpu_fence *fence);
711
712 /*
713 * GART structures, functions & helpers
714 */
715 struct amdgpu_mc;
716
717 #define AMDGPU_GPU_PAGE_SIZE 4096
718 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
719 #define AMDGPU_GPU_PAGE_SHIFT 12
720 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
721
722 struct amdgpu_gart {
723 dma_addr_t table_addr;
724 struct amdgpu_bo *robj;
725 void *ptr;
726 unsigned num_gpu_pages;
727 unsigned num_cpu_pages;
728 unsigned table_size;
729 struct page **pages;
730 dma_addr_t *pages_addr;
731 bool ready;
732 const struct amdgpu_gart_funcs *gart_funcs;
733 };
734
735 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
736 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
737 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
738 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
739 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
740 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
741 int amdgpu_gart_init(struct amdgpu_device *adev);
742 void amdgpu_gart_fini(struct amdgpu_device *adev);
743 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
744 int pages);
745 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
746 int pages, struct page **pagelist,
747 dma_addr_t *dma_addr, uint32_t flags);
748
749 /*
750 * GPU MC structures, functions & helpers
751 */
752 struct amdgpu_mc {
753 resource_size_t aper_size;
754 resource_size_t aper_base;
755 resource_size_t agp_base;
756 /* for some chips with <= 32MB we need to lie
757 * about vram size near mc fb location */
758 u64 mc_vram_size;
759 u64 visible_vram_size;
760 u64 gtt_size;
761 u64 gtt_start;
762 u64 gtt_end;
763 u64 vram_start;
764 u64 vram_end;
765 unsigned vram_width;
766 u64 real_vram_size;
767 int vram_mtrr;
768 u64 gtt_base_align;
769 u64 mc_mask;
770 const struct firmware *fw; /* MC firmware */
771 uint32_t fw_version;
772 struct amdgpu_irq_src vm_fault;
773 uint32_t vram_type;
774 };
775
776 /*
777 * GPU doorbell structures, functions & helpers
778 */
779 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
780 {
781 AMDGPU_DOORBELL_KIQ = 0x000,
782 AMDGPU_DOORBELL_HIQ = 0x001,
783 AMDGPU_DOORBELL_DIQ = 0x002,
784 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
785 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
786 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
787 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
788 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
789 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
790 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
791 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
792 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
793 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
794 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
795 AMDGPU_DOORBELL_IH = 0x1E8,
796 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
797 AMDGPU_DOORBELL_INVALID = 0xFFFF
798 } AMDGPU_DOORBELL_ASSIGNMENT;
799
800 struct amdgpu_doorbell {
801 /* doorbell mmio */
802 resource_size_t base;
803 resource_size_t size;
804 u32 __iomem *ptr;
805 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
806 };
807
808 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
809 phys_addr_t *aperture_base,
810 size_t *aperture_size,
811 size_t *start_offset);
812
813 /*
814 * IRQS.
815 */
816
817 struct amdgpu_flip_work {
818 struct work_struct flip_work;
819 struct work_struct unpin_work;
820 struct amdgpu_device *adev;
821 int crtc_id;
822 uint64_t base;
823 struct drm_pending_vblank_event *event;
824 struct amdgpu_bo *old_rbo;
825 struct fence *fence;
826 };
827
828
829 /*
830 * CP & rings.
831 */
832
833 struct amdgpu_ib {
834 struct amdgpu_sa_bo *sa_bo;
835 uint32_t length_dw;
836 uint64_t gpu_addr;
837 uint32_t *ptr;
838 struct amdgpu_ring *ring;
839 struct amdgpu_fence *fence;
840 struct amdgpu_user_fence *user;
841 struct amdgpu_vm *vm;
842 struct amdgpu_ctx *ctx;
843 struct amdgpu_sync sync;
844 uint32_t gds_base, gds_size;
845 uint32_t gws_base, gws_size;
846 uint32_t oa_base, oa_size;
847 uint32_t flags;
848 /* resulting sequence number */
849 uint64_t sequence;
850 };
851
852 enum amdgpu_ring_type {
853 AMDGPU_RING_TYPE_GFX,
854 AMDGPU_RING_TYPE_COMPUTE,
855 AMDGPU_RING_TYPE_SDMA,
856 AMDGPU_RING_TYPE_UVD,
857 AMDGPU_RING_TYPE_VCE
858 };
859
860 struct amdgpu_ring {
861 struct amdgpu_device *adev;
862 const struct amdgpu_ring_funcs *funcs;
863 struct amdgpu_fence_driver fence_drv;
864
865 struct mutex *ring_lock;
866 struct amdgpu_bo *ring_obj;
867 volatile uint32_t *ring;
868 unsigned rptr_offs;
869 u64 next_rptr_gpu_addr;
870 volatile u32 *next_rptr_cpu_addr;
871 unsigned wptr;
872 unsigned wptr_old;
873 unsigned ring_size;
874 unsigned ring_free_dw;
875 int count_dw;
876 atomic_t last_rptr;
877 atomic64_t last_activity;
878 uint64_t gpu_addr;
879 uint32_t align_mask;
880 uint32_t ptr_mask;
881 bool ready;
882 u32 nop;
883 u32 idx;
884 u64 last_semaphore_signal_addr;
885 u64 last_semaphore_wait_addr;
886 u32 me;
887 u32 pipe;
888 u32 queue;
889 struct amdgpu_bo *mqd_obj;
890 u32 doorbell_index;
891 bool use_doorbell;
892 unsigned wptr_offs;
893 unsigned next_rptr_offs;
894 unsigned fence_offs;
895 struct amdgpu_ctx *current_ctx;
896 enum amdgpu_ring_type type;
897 char name[16];
898 };
899
900 /*
901 * VM
902 */
903
904 /* maximum number of VMIDs */
905 #define AMDGPU_NUM_VM 16
906
907 /* number of entries in page table */
908 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
909
910 /* PTBs (Page Table Blocks) need to be aligned to 32K */
911 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
912 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
913 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
914
915 #define AMDGPU_PTE_VALID (1 << 0)
916 #define AMDGPU_PTE_SYSTEM (1 << 1)
917 #define AMDGPU_PTE_SNOOPED (1 << 2)
918
919 /* VI only */
920 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
921
922 #define AMDGPU_PTE_READABLE (1 << 5)
923 #define AMDGPU_PTE_WRITEABLE (1 << 6)
924
925 /* PTE (Page Table Entry) fragment field for different page sizes */
926 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
927 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
928 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
929
930 struct amdgpu_vm_pt {
931 struct amdgpu_bo *bo;
932 uint64_t addr;
933 };
934
935 struct amdgpu_vm_id {
936 unsigned id;
937 uint64_t pd_gpu_addr;
938 /* last flushed PD/PT update */
939 struct amdgpu_fence *flushed_updates;
940 /* last use of vmid */
941 struct amdgpu_fence *last_id_use;
942 };
943
944 struct amdgpu_vm {
945 struct mutex mutex;
946
947 struct rb_root va;
948
949 /* protecting invalidated and freed */
950 spinlock_t status_lock;
951
952 /* BOs moved, but not yet updated in the PT */
953 struct list_head invalidated;
954
955 /* BOs freed, but not yet updated in the PT */
956 struct list_head freed;
957
958 /* contains the page directory */
959 struct amdgpu_bo *page_directory;
960 unsigned max_pde_used;
961
962 /* array of page tables, one for each page directory entry */
963 struct amdgpu_vm_pt *page_tables;
964
965 /* for id and flush management per ring */
966 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
967 };
968
969 struct amdgpu_vm_manager {
970 struct amdgpu_fence *active[AMDGPU_NUM_VM];
971 uint32_t max_pfn;
972 /* number of VMIDs */
973 unsigned nvm;
974 /* vram base address for page table entry */
975 u64 vram_base_offset;
976 /* is vm enabled? */
977 bool enabled;
978 /* for hw to save the PD addr on suspend/resume */
979 uint32_t saved_table_addr[AMDGPU_NUM_VM];
980 /* vm pte handling */
981 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
982 struct amdgpu_ring *vm_pte_funcs_ring;
983 };
984
985 /*
986 * context related structures
987 */
988
989 #define AMDGPU_CTX_MAX_CS_PENDING 16
990
991 struct amdgpu_ctx_ring {
992 uint64_t sequence;
993 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
994 };
995
996 struct amdgpu_ctx {
997 struct kref refcount;
998 unsigned reset_counter;
999 spinlock_t ring_lock;
1000 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
1001 };
1002
1003 struct amdgpu_ctx_mgr {
1004 struct amdgpu_device *adev;
1005 struct mutex lock;
1006 /* protected by lock */
1007 struct idr ctx_handles;
1008 };
1009
1010 int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1011 uint32_t *id);
1012 int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1013 uint32_t id);
1014
1015 void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
1016
1017 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1018 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1019
1020 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1021 struct fence *fence);
1022 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1023 struct amdgpu_ring *ring, uint64_t seq);
1024
1025 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1026 struct drm_file *filp);
1027
1028
1029 /*
1030 * file private structure
1031 */
1032
1033 struct amdgpu_fpriv {
1034 struct amdgpu_vm vm;
1035 struct mutex bo_list_lock;
1036 struct idr bo_list_handles;
1037 struct amdgpu_ctx_mgr ctx_mgr;
1038 };
1039
1040 /*
1041 * residency list
1042 */
1043
1044 struct amdgpu_bo_list {
1045 struct mutex lock;
1046 struct amdgpu_bo *gds_obj;
1047 struct amdgpu_bo *gws_obj;
1048 struct amdgpu_bo *oa_obj;
1049 bool has_userptr;
1050 unsigned num_entries;
1051 struct amdgpu_bo_list_entry *array;
1052 };
1053
1054 struct amdgpu_bo_list *
1055 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1056 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1057 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1058
1059 /*
1060 * GFX stuff
1061 */
1062 #include "clearstate_defs.h"
1063
1064 struct amdgpu_rlc {
1065 /* for power gating */
1066 struct amdgpu_bo *save_restore_obj;
1067 uint64_t save_restore_gpu_addr;
1068 volatile uint32_t *sr_ptr;
1069 const u32 *reg_list;
1070 u32 reg_list_size;
1071 /* for clear state */
1072 struct amdgpu_bo *clear_state_obj;
1073 uint64_t clear_state_gpu_addr;
1074 volatile uint32_t *cs_ptr;
1075 const struct cs_section_def *cs_data;
1076 u32 clear_state_size;
1077 /* for cp tables */
1078 struct amdgpu_bo *cp_table_obj;
1079 uint64_t cp_table_gpu_addr;
1080 volatile uint32_t *cp_table_ptr;
1081 u32 cp_table_size;
1082 };
1083
1084 struct amdgpu_mec {
1085 struct amdgpu_bo *hpd_eop_obj;
1086 u64 hpd_eop_gpu_addr;
1087 u32 num_pipe;
1088 u32 num_mec;
1089 u32 num_queue;
1090 };
1091
1092 /*
1093 * GPU scratch registers structures, functions & helpers
1094 */
1095 struct amdgpu_scratch {
1096 unsigned num_reg;
1097 uint32_t reg_base;
1098 bool free[32];
1099 uint32_t reg[32];
1100 };
1101
1102 /*
1103 * GFX configurations
1104 */
1105 struct amdgpu_gca_config {
1106 unsigned max_shader_engines;
1107 unsigned max_tile_pipes;
1108 unsigned max_cu_per_sh;
1109 unsigned max_sh_per_se;
1110 unsigned max_backends_per_se;
1111 unsigned max_texture_channel_caches;
1112 unsigned max_gprs;
1113 unsigned max_gs_threads;
1114 unsigned max_hw_contexts;
1115 unsigned sc_prim_fifo_size_frontend;
1116 unsigned sc_prim_fifo_size_backend;
1117 unsigned sc_hiz_tile_fifo_size;
1118 unsigned sc_earlyz_tile_fifo_size;
1119
1120 unsigned num_tile_pipes;
1121 unsigned backend_enable_mask;
1122 unsigned mem_max_burst_length_bytes;
1123 unsigned mem_row_size_in_kb;
1124 unsigned shader_engine_tile_size;
1125 unsigned num_gpus;
1126 unsigned multi_gpu_tile_size;
1127 unsigned mc_arb_ramcfg;
1128 unsigned gb_addr_config;
1129
1130 uint32_t tile_mode_array[32];
1131 uint32_t macrotile_mode_array[16];
1132 };
1133
1134 struct amdgpu_gfx {
1135 struct mutex gpu_clock_mutex;
1136 struct amdgpu_gca_config config;
1137 struct amdgpu_rlc rlc;
1138 struct amdgpu_mec mec;
1139 struct amdgpu_scratch scratch;
1140 const struct firmware *me_fw; /* ME firmware */
1141 uint32_t me_fw_version;
1142 const struct firmware *pfp_fw; /* PFP firmware */
1143 uint32_t pfp_fw_version;
1144 const struct firmware *ce_fw; /* CE firmware */
1145 uint32_t ce_fw_version;
1146 const struct firmware *rlc_fw; /* RLC firmware */
1147 uint32_t rlc_fw_version;
1148 const struct firmware *mec_fw; /* MEC firmware */
1149 uint32_t mec_fw_version;
1150 const struct firmware *mec2_fw; /* MEC2 firmware */
1151 uint32_t mec2_fw_version;
1152 uint32_t me_feature_version;
1153 uint32_t ce_feature_version;
1154 uint32_t pfp_feature_version;
1155 uint32_t rlc_feature_version;
1156 uint32_t mec_feature_version;
1157 uint32_t mec2_feature_version;
1158 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1159 unsigned num_gfx_rings;
1160 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1161 unsigned num_compute_rings;
1162 struct amdgpu_irq_src eop_irq;
1163 struct amdgpu_irq_src priv_reg_irq;
1164 struct amdgpu_irq_src priv_inst_irq;
1165 /* gfx status */
1166 uint32_t gfx_current_status;
1167 /* sync signal for const engine */
1168 unsigned ce_sync_offs;
1169 /* ce ram size*/
1170 unsigned ce_ram_size;
1171 };
1172
1173 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1174 unsigned size, struct amdgpu_ib *ib);
1175 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1176 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1177 struct amdgpu_ib *ib, void *owner);
1178 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1179 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1180 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1181 /* Ring access between begin & end cannot sleep */
1182 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1183 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1184 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1185 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1186 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1187 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1188 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1189 void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1190 bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1191 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1192 uint32_t **data);
1193 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1194 unsigned size, uint32_t *data);
1195 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1196 unsigned ring_size, u32 nop, u32 align_mask,
1197 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1198 enum amdgpu_ring_type ring_type);
1199 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1200
1201 /*
1202 * CS.
1203 */
1204 struct amdgpu_cs_chunk {
1205 uint32_t chunk_id;
1206 uint32_t length_dw;
1207 uint32_t *kdata;
1208 void __user *user_ptr;
1209 };
1210
1211 struct amdgpu_cs_parser {
1212 struct amdgpu_device *adev;
1213 struct drm_file *filp;
1214 struct amdgpu_ctx *ctx;
1215 struct amdgpu_bo_list *bo_list;
1216 /* chunks */
1217 unsigned nchunks;
1218 struct amdgpu_cs_chunk *chunks;
1219 /* relocations */
1220 struct amdgpu_bo_list_entry *vm_bos;
1221 struct list_head validated;
1222
1223 struct amdgpu_ib *ibs;
1224 uint32_t num_ibs;
1225
1226 struct ww_acquire_ctx ticket;
1227
1228 /* user fence */
1229 struct amdgpu_user_fence uf;
1230 };
1231
1232 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1233 {
1234 return p->ibs[ib_idx].ptr[idx];
1235 }
1236
1237 /*
1238 * Writeback
1239 */
1240 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1241
1242 struct amdgpu_wb {
1243 struct amdgpu_bo *wb_obj;
1244 volatile uint32_t *wb;
1245 uint64_t gpu_addr;
1246 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1247 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1248 };
1249
1250 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1251 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1252
1253 /**
1254 * struct amdgpu_pm - power management datas
1255 * It keeps track of various data needed to take powermanagement decision.
1256 */
1257
1258 enum amdgpu_pm_state_type {
1259 /* not used for dpm */
1260 POWER_STATE_TYPE_DEFAULT,
1261 POWER_STATE_TYPE_POWERSAVE,
1262 /* user selectable states */
1263 POWER_STATE_TYPE_BATTERY,
1264 POWER_STATE_TYPE_BALANCED,
1265 POWER_STATE_TYPE_PERFORMANCE,
1266 /* internal states */
1267 POWER_STATE_TYPE_INTERNAL_UVD,
1268 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1269 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1270 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1271 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1272 POWER_STATE_TYPE_INTERNAL_BOOT,
1273 POWER_STATE_TYPE_INTERNAL_THERMAL,
1274 POWER_STATE_TYPE_INTERNAL_ACPI,
1275 POWER_STATE_TYPE_INTERNAL_ULV,
1276 POWER_STATE_TYPE_INTERNAL_3DPERF,
1277 };
1278
1279 enum amdgpu_int_thermal_type {
1280 THERMAL_TYPE_NONE,
1281 THERMAL_TYPE_EXTERNAL,
1282 THERMAL_TYPE_EXTERNAL_GPIO,
1283 THERMAL_TYPE_RV6XX,
1284 THERMAL_TYPE_RV770,
1285 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1286 THERMAL_TYPE_EVERGREEN,
1287 THERMAL_TYPE_SUMO,
1288 THERMAL_TYPE_NI,
1289 THERMAL_TYPE_SI,
1290 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1291 THERMAL_TYPE_CI,
1292 THERMAL_TYPE_KV,
1293 };
1294
1295 enum amdgpu_dpm_auto_throttle_src {
1296 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1297 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1298 };
1299
1300 enum amdgpu_dpm_event_src {
1301 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1302 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1303 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1304 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1305 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1306 };
1307
1308 #define AMDGPU_MAX_VCE_LEVELS 6
1309
1310 enum amdgpu_vce_level {
1311 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1312 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1313 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1314 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1315 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1316 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1317 };
1318
1319 struct amdgpu_ps {
1320 u32 caps; /* vbios flags */
1321 u32 class; /* vbios flags */
1322 u32 class2; /* vbios flags */
1323 /* UVD clocks */
1324 u32 vclk;
1325 u32 dclk;
1326 /* VCE clocks */
1327 u32 evclk;
1328 u32 ecclk;
1329 bool vce_active;
1330 enum amdgpu_vce_level vce_level;
1331 /* asic priv */
1332 void *ps_priv;
1333 };
1334
1335 struct amdgpu_dpm_thermal {
1336 /* thermal interrupt work */
1337 struct work_struct work;
1338 /* low temperature threshold */
1339 int min_temp;
1340 /* high temperature threshold */
1341 int max_temp;
1342 /* was last interrupt low to high or high to low */
1343 bool high_to_low;
1344 /* interrupt source */
1345 struct amdgpu_irq_src irq;
1346 };
1347
1348 enum amdgpu_clk_action
1349 {
1350 AMDGPU_SCLK_UP = 1,
1351 AMDGPU_SCLK_DOWN
1352 };
1353
1354 struct amdgpu_blacklist_clocks
1355 {
1356 u32 sclk;
1357 u32 mclk;
1358 enum amdgpu_clk_action action;
1359 };
1360
1361 struct amdgpu_clock_and_voltage_limits {
1362 u32 sclk;
1363 u32 mclk;
1364 u16 vddc;
1365 u16 vddci;
1366 };
1367
1368 struct amdgpu_clock_array {
1369 u32 count;
1370 u32 *values;
1371 };
1372
1373 struct amdgpu_clock_voltage_dependency_entry {
1374 u32 clk;
1375 u16 v;
1376 };
1377
1378 struct amdgpu_clock_voltage_dependency_table {
1379 u32 count;
1380 struct amdgpu_clock_voltage_dependency_entry *entries;
1381 };
1382
1383 union amdgpu_cac_leakage_entry {
1384 struct {
1385 u16 vddc;
1386 u32 leakage;
1387 };
1388 struct {
1389 u16 vddc1;
1390 u16 vddc2;
1391 u16 vddc3;
1392 };
1393 };
1394
1395 struct amdgpu_cac_leakage_table {
1396 u32 count;
1397 union amdgpu_cac_leakage_entry *entries;
1398 };
1399
1400 struct amdgpu_phase_shedding_limits_entry {
1401 u16 voltage;
1402 u32 sclk;
1403 u32 mclk;
1404 };
1405
1406 struct amdgpu_phase_shedding_limits_table {
1407 u32 count;
1408 struct amdgpu_phase_shedding_limits_entry *entries;
1409 };
1410
1411 struct amdgpu_uvd_clock_voltage_dependency_entry {
1412 u32 vclk;
1413 u32 dclk;
1414 u16 v;
1415 };
1416
1417 struct amdgpu_uvd_clock_voltage_dependency_table {
1418 u8 count;
1419 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1420 };
1421
1422 struct amdgpu_vce_clock_voltage_dependency_entry {
1423 u32 ecclk;
1424 u32 evclk;
1425 u16 v;
1426 };
1427
1428 struct amdgpu_vce_clock_voltage_dependency_table {
1429 u8 count;
1430 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1431 };
1432
1433 struct amdgpu_ppm_table {
1434 u8 ppm_design;
1435 u16 cpu_core_number;
1436 u32 platform_tdp;
1437 u32 small_ac_platform_tdp;
1438 u32 platform_tdc;
1439 u32 small_ac_platform_tdc;
1440 u32 apu_tdp;
1441 u32 dgpu_tdp;
1442 u32 dgpu_ulv_power;
1443 u32 tj_max;
1444 };
1445
1446 struct amdgpu_cac_tdp_table {
1447 u16 tdp;
1448 u16 configurable_tdp;
1449 u16 tdc;
1450 u16 battery_power_limit;
1451 u16 small_power_limit;
1452 u16 low_cac_leakage;
1453 u16 high_cac_leakage;
1454 u16 maximum_power_delivery_limit;
1455 };
1456
1457 struct amdgpu_dpm_dynamic_state {
1458 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1459 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1460 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1461 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1462 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1463 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1464 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1465 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1466 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1467 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1468 struct amdgpu_clock_array valid_sclk_values;
1469 struct amdgpu_clock_array valid_mclk_values;
1470 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1471 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1472 u32 mclk_sclk_ratio;
1473 u32 sclk_mclk_delta;
1474 u16 vddc_vddci_delta;
1475 u16 min_vddc_for_pcie_gen2;
1476 struct amdgpu_cac_leakage_table cac_leakage_table;
1477 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1478 struct amdgpu_ppm_table *ppm_table;
1479 struct amdgpu_cac_tdp_table *cac_tdp_table;
1480 };
1481
1482 struct amdgpu_dpm_fan {
1483 u16 t_min;
1484 u16 t_med;
1485 u16 t_high;
1486 u16 pwm_min;
1487 u16 pwm_med;
1488 u16 pwm_high;
1489 u8 t_hyst;
1490 u32 cycle_delay;
1491 u16 t_max;
1492 u8 control_mode;
1493 u16 default_max_fan_pwm;
1494 u16 default_fan_output_sensitivity;
1495 u16 fan_output_sensitivity;
1496 bool ucode_fan_control;
1497 };
1498
1499 enum amdgpu_pcie_gen {
1500 AMDGPU_PCIE_GEN1 = 0,
1501 AMDGPU_PCIE_GEN2 = 1,
1502 AMDGPU_PCIE_GEN3 = 2,
1503 AMDGPU_PCIE_GEN_INVALID = 0xffff
1504 };
1505
1506 enum amdgpu_dpm_forced_level {
1507 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1508 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1509 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1510 };
1511
1512 struct amdgpu_vce_state {
1513 /* vce clocks */
1514 u32 evclk;
1515 u32 ecclk;
1516 /* gpu clocks */
1517 u32 sclk;
1518 u32 mclk;
1519 u8 clk_idx;
1520 u8 pstate;
1521 };
1522
1523 struct amdgpu_dpm_funcs {
1524 int (*get_temperature)(struct amdgpu_device *adev);
1525 int (*pre_set_power_state)(struct amdgpu_device *adev);
1526 int (*set_power_state)(struct amdgpu_device *adev);
1527 void (*post_set_power_state)(struct amdgpu_device *adev);
1528 void (*display_configuration_changed)(struct amdgpu_device *adev);
1529 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1530 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1531 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1532 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1533 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1534 bool (*vblank_too_short)(struct amdgpu_device *adev);
1535 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1536 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1537 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1538 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1539 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1540 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1541 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1542 };
1543
1544 struct amdgpu_dpm {
1545 struct amdgpu_ps *ps;
1546 /* number of valid power states */
1547 int num_ps;
1548 /* current power state that is active */
1549 struct amdgpu_ps *current_ps;
1550 /* requested power state */
1551 struct amdgpu_ps *requested_ps;
1552 /* boot up power state */
1553 struct amdgpu_ps *boot_ps;
1554 /* default uvd power state */
1555 struct amdgpu_ps *uvd_ps;
1556 /* vce requirements */
1557 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1558 enum amdgpu_vce_level vce_level;
1559 enum amdgpu_pm_state_type state;
1560 enum amdgpu_pm_state_type user_state;
1561 u32 platform_caps;
1562 u32 voltage_response_time;
1563 u32 backbias_response_time;
1564 void *priv;
1565 u32 new_active_crtcs;
1566 int new_active_crtc_count;
1567 u32 current_active_crtcs;
1568 int current_active_crtc_count;
1569 struct amdgpu_dpm_dynamic_state dyn_state;
1570 struct amdgpu_dpm_fan fan;
1571 u32 tdp_limit;
1572 u32 near_tdp_limit;
1573 u32 near_tdp_limit_adjusted;
1574 u32 sq_ramping_threshold;
1575 u32 cac_leakage;
1576 u16 tdp_od_limit;
1577 u32 tdp_adjustment;
1578 u16 load_line_slope;
1579 bool power_control;
1580 bool ac_power;
1581 /* special states active */
1582 bool thermal_active;
1583 bool uvd_active;
1584 bool vce_active;
1585 /* thermal handling */
1586 struct amdgpu_dpm_thermal thermal;
1587 /* forced levels */
1588 enum amdgpu_dpm_forced_level forced_level;
1589 };
1590
1591 struct amdgpu_pm {
1592 struct mutex mutex;
1593 u32 current_sclk;
1594 u32 current_mclk;
1595 u32 default_sclk;
1596 u32 default_mclk;
1597 struct amdgpu_i2c_chan *i2c_bus;
1598 /* internal thermal controller on rv6xx+ */
1599 enum amdgpu_int_thermal_type int_thermal_type;
1600 struct device *int_hwmon_dev;
1601 /* fan control parameters */
1602 bool no_fan;
1603 u8 fan_pulses_per_revolution;
1604 u8 fan_min_rpm;
1605 u8 fan_max_rpm;
1606 /* dpm */
1607 bool dpm_enabled;
1608 struct amdgpu_dpm dpm;
1609 const struct firmware *fw; /* SMC firmware */
1610 uint32_t fw_version;
1611 const struct amdgpu_dpm_funcs *funcs;
1612 };
1613
1614 /*
1615 * UVD
1616 */
1617 #define AMDGPU_MAX_UVD_HANDLES 10
1618 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1619 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1620 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1621
1622 struct amdgpu_uvd {
1623 struct amdgpu_bo *vcpu_bo;
1624 void *cpu_addr;
1625 uint64_t gpu_addr;
1626 void *saved_bo;
1627 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1628 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1629 struct delayed_work idle_work;
1630 const struct firmware *fw; /* UVD firmware */
1631 struct amdgpu_ring ring;
1632 struct amdgpu_irq_src irq;
1633 bool address_64_bit;
1634 };
1635
1636 /*
1637 * VCE
1638 */
1639 #define AMDGPU_MAX_VCE_HANDLES 16
1640 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1641
1642 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1643 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1644
1645 struct amdgpu_vce {
1646 struct amdgpu_bo *vcpu_bo;
1647 uint64_t gpu_addr;
1648 unsigned fw_version;
1649 unsigned fb_version;
1650 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1651 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1652 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1653 struct delayed_work idle_work;
1654 const struct firmware *fw; /* VCE firmware */
1655 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1656 struct amdgpu_irq_src irq;
1657 unsigned harvest_config;
1658 };
1659
1660 /*
1661 * SDMA
1662 */
1663 struct amdgpu_sdma {
1664 /* SDMA firmware */
1665 const struct firmware *fw;
1666 uint32_t fw_version;
1667 uint32_t feature_version;
1668
1669 struct amdgpu_ring ring;
1670 };
1671
1672 /*
1673 * Firmware
1674 */
1675 struct amdgpu_firmware {
1676 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1677 bool smu_load;
1678 struct amdgpu_bo *fw_buf;
1679 unsigned int fw_size;
1680 };
1681
1682 /*
1683 * Benchmarking
1684 */
1685 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1686
1687
1688 /*
1689 * Testing
1690 */
1691 void amdgpu_test_moves(struct amdgpu_device *adev);
1692 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1693 struct amdgpu_ring *cpA,
1694 struct amdgpu_ring *cpB);
1695 void amdgpu_test_syncing(struct amdgpu_device *adev);
1696
1697 /*
1698 * MMU Notifier
1699 */
1700 #if defined(CONFIG_MMU_NOTIFIER)
1701 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1702 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1703 #else
1704 static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1705 {
1706 return -ENODEV;
1707 }
1708 static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1709 #endif
1710
1711 /*
1712 * Debugfs
1713 */
1714 struct amdgpu_debugfs {
1715 struct drm_info_list *files;
1716 unsigned num_files;
1717 };
1718
1719 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1720 struct drm_info_list *files,
1721 unsigned nfiles);
1722 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1723
1724 #if defined(CONFIG_DEBUG_FS)
1725 int amdgpu_debugfs_init(struct drm_minor *minor);
1726 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1727 #endif
1728
1729 /*
1730 * amdgpu smumgr functions
1731 */
1732 struct amdgpu_smumgr_funcs {
1733 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1734 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1735 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1736 };
1737
1738 /*
1739 * amdgpu smumgr
1740 */
1741 struct amdgpu_smumgr {
1742 struct amdgpu_bo *toc_buf;
1743 struct amdgpu_bo *smu_buf;
1744 /* asic priv smu data */
1745 void *priv;
1746 spinlock_t smu_lock;
1747 /* smumgr functions */
1748 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1749 /* ucode loading complete flag */
1750 uint32_t fw_flags;
1751 };
1752
1753 /*
1754 * ASIC specific register table accessible by UMD
1755 */
1756 struct amdgpu_allowed_register_entry {
1757 uint32_t reg_offset;
1758 bool untouched;
1759 bool grbm_indexed;
1760 };
1761
1762 struct amdgpu_cu_info {
1763 uint32_t number; /* total active CU number */
1764 uint32_t ao_cu_mask;
1765 uint32_t bitmap[4][4];
1766 };
1767
1768
1769 /*
1770 * ASIC specific functions.
1771 */
1772 struct amdgpu_asic_funcs {
1773 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1774 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1775 u32 sh_num, u32 reg_offset, u32 *value);
1776 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1777 int (*reset)(struct amdgpu_device *adev);
1778 /* wait for mc_idle */
1779 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1780 /* get the reference clock */
1781 u32 (*get_xclk)(struct amdgpu_device *adev);
1782 /* get the gpu clock counter */
1783 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1784 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1785 /* MM block clocks */
1786 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1787 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1788 };
1789
1790 /*
1791 * IOCTL.
1792 */
1793 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1794 struct drm_file *filp);
1795 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1796 struct drm_file *filp);
1797
1798 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1799 struct drm_file *filp);
1800 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1801 struct drm_file *filp);
1802 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1803 struct drm_file *filp);
1804 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1805 struct drm_file *filp);
1806 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1807 struct drm_file *filp);
1808 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1809 struct drm_file *filp);
1810 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1811 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1812
1813 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1814 struct drm_file *filp);
1815
1816 /* VRAM scratch page for HDP bug, default vram page */
1817 struct amdgpu_vram_scratch {
1818 struct amdgpu_bo *robj;
1819 volatile uint32_t *ptr;
1820 u64 gpu_addr;
1821 };
1822
1823 /*
1824 * ACPI
1825 */
1826 struct amdgpu_atif_notification_cfg {
1827 bool enabled;
1828 int command_code;
1829 };
1830
1831 struct amdgpu_atif_notifications {
1832 bool display_switch;
1833 bool expansion_mode_change;
1834 bool thermal_state;
1835 bool forced_power_state;
1836 bool system_power_state;
1837 bool display_conf_change;
1838 bool px_gfx_switch;
1839 bool brightness_change;
1840 bool dgpu_display_event;
1841 };
1842
1843 struct amdgpu_atif_functions {
1844 bool system_params;
1845 bool sbios_requests;
1846 bool select_active_disp;
1847 bool lid_state;
1848 bool get_tv_standard;
1849 bool set_tv_standard;
1850 bool get_panel_expansion_mode;
1851 bool set_panel_expansion_mode;
1852 bool temperature_change;
1853 bool graphics_device_types;
1854 };
1855
1856 struct amdgpu_atif {
1857 struct amdgpu_atif_notifications notifications;
1858 struct amdgpu_atif_functions functions;
1859 struct amdgpu_atif_notification_cfg notification_cfg;
1860 struct amdgpu_encoder *encoder_for_bl;
1861 };
1862
1863 struct amdgpu_atcs_functions {
1864 bool get_ext_state;
1865 bool pcie_perf_req;
1866 bool pcie_dev_rdy;
1867 bool pcie_bus_width;
1868 };
1869
1870 struct amdgpu_atcs {
1871 struct amdgpu_atcs_functions functions;
1872 };
1873
1874 /*
1875 * CGS
1876 */
1877 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1878 void amdgpu_cgs_destroy_device(void *cgs_device);
1879
1880
1881 /*
1882 * Core structure, functions and helpers.
1883 */
1884 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1885 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1886
1887 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1888 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1889
1890 struct amdgpu_ip_block_status {
1891 bool valid;
1892 bool sw;
1893 bool hw;
1894 };
1895
1896 struct amdgpu_device {
1897 struct device *dev;
1898 struct drm_device *ddev;
1899 struct pci_dev *pdev;
1900 struct rw_semaphore exclusive_lock;
1901
1902 /* ASIC */
1903 enum amdgpu_asic_type asic_type;
1904 uint32_t family;
1905 uint32_t rev_id;
1906 uint32_t external_rev_id;
1907 unsigned long flags;
1908 int usec_timeout;
1909 const struct amdgpu_asic_funcs *asic_funcs;
1910 bool shutdown;
1911 bool suspend;
1912 bool need_dma32;
1913 bool accel_working;
1914 bool needs_reset;
1915 struct work_struct reset_work;
1916 struct notifier_block acpi_nb;
1917 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1918 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1919 unsigned debugfs_count;
1920 #if defined(CONFIG_DEBUG_FS)
1921 struct dentry *debugfs_regs;
1922 #endif
1923 struct amdgpu_atif atif;
1924 struct amdgpu_atcs atcs;
1925 struct mutex srbm_mutex;
1926 /* GRBM index mutex. Protects concurrent access to GRBM index */
1927 struct mutex grbm_idx_mutex;
1928 struct dev_pm_domain vga_pm_domain;
1929 bool have_disp_power_ref;
1930
1931 /* BIOS */
1932 uint8_t *bios;
1933 bool is_atom_bios;
1934 uint16_t bios_header_start;
1935 struct amdgpu_bo *stollen_vga_memory;
1936 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1937
1938 /* Register/doorbell mmio */
1939 resource_size_t rmmio_base;
1940 resource_size_t rmmio_size;
1941 void __iomem *rmmio;
1942 /* protects concurrent MM_INDEX/DATA based register access */
1943 spinlock_t mmio_idx_lock;
1944 /* protects concurrent SMC based register access */
1945 spinlock_t smc_idx_lock;
1946 amdgpu_rreg_t smc_rreg;
1947 amdgpu_wreg_t smc_wreg;
1948 /* protects concurrent PCIE register access */
1949 spinlock_t pcie_idx_lock;
1950 amdgpu_rreg_t pcie_rreg;
1951 amdgpu_wreg_t pcie_wreg;
1952 /* protects concurrent UVD register access */
1953 spinlock_t uvd_ctx_idx_lock;
1954 amdgpu_rreg_t uvd_ctx_rreg;
1955 amdgpu_wreg_t uvd_ctx_wreg;
1956 /* protects concurrent DIDT register access */
1957 spinlock_t didt_idx_lock;
1958 amdgpu_rreg_t didt_rreg;
1959 amdgpu_wreg_t didt_wreg;
1960 /* protects concurrent ENDPOINT (audio) register access */
1961 spinlock_t audio_endpt_idx_lock;
1962 amdgpu_block_rreg_t audio_endpt_rreg;
1963 amdgpu_block_wreg_t audio_endpt_wreg;
1964 void __iomem *rio_mem;
1965 resource_size_t rio_mem_size;
1966 struct amdgpu_doorbell doorbell;
1967
1968 /* clock/pll info */
1969 struct amdgpu_clock clock;
1970
1971 /* MC */
1972 struct amdgpu_mc mc;
1973 struct amdgpu_gart gart;
1974 struct amdgpu_dummy_page dummy_page;
1975 struct amdgpu_vm_manager vm_manager;
1976
1977 /* memory management */
1978 struct amdgpu_mman mman;
1979 struct amdgpu_gem gem;
1980 struct amdgpu_vram_scratch vram_scratch;
1981 struct amdgpu_wb wb;
1982 atomic64_t vram_usage;
1983 atomic64_t vram_vis_usage;
1984 atomic64_t gtt_usage;
1985 atomic64_t num_bytes_moved;
1986 atomic_t gpu_reset_counter;
1987
1988 /* display */
1989 struct amdgpu_mode_info mode_info;
1990 struct work_struct hotplug_work;
1991 struct amdgpu_irq_src crtc_irq;
1992 struct amdgpu_irq_src pageflip_irq;
1993 struct amdgpu_irq_src hpd_irq;
1994
1995 /* rings */
1996 wait_queue_head_t fence_queue;
1997 unsigned fence_context;
1998 struct mutex ring_lock;
1999 unsigned num_rings;
2000 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2001 bool ib_pool_ready;
2002 struct amdgpu_sa_manager ring_tmp_bo;
2003
2004 /* interrupts */
2005 struct amdgpu_irq irq;
2006
2007 /* dpm */
2008 struct amdgpu_pm pm;
2009 u32 cg_flags;
2010 u32 pg_flags;
2011
2012 /* amdgpu smumgr */
2013 struct amdgpu_smumgr smu;
2014
2015 /* gfx */
2016 struct amdgpu_gfx gfx;
2017
2018 /* sdma */
2019 struct amdgpu_sdma sdma[2];
2020 struct amdgpu_irq_src sdma_trap_irq;
2021 struct amdgpu_irq_src sdma_illegal_inst_irq;
2022
2023 /* uvd */
2024 bool has_uvd;
2025 struct amdgpu_uvd uvd;
2026
2027 /* vce */
2028 struct amdgpu_vce vce;
2029
2030 /* firmwares */
2031 struct amdgpu_firmware firmware;
2032
2033 /* GDS */
2034 struct amdgpu_gds gds;
2035
2036 const struct amdgpu_ip_block_version *ip_blocks;
2037 int num_ip_blocks;
2038 struct amdgpu_ip_block_status *ip_block_status;
2039 struct mutex mn_lock;
2040 DECLARE_HASHTABLE(mn_hash, 7);
2041
2042 /* tracking pinned memory */
2043 u64 vram_pin_size;
2044 u64 gart_pin_size;
2045
2046 /* amdkfd interface */
2047 struct kfd_dev *kfd;
2048 };
2049
2050 bool amdgpu_device_is_px(struct drm_device *dev);
2051 int amdgpu_device_init(struct amdgpu_device *adev,
2052 struct drm_device *ddev,
2053 struct pci_dev *pdev,
2054 uint32_t flags);
2055 void amdgpu_device_fini(struct amdgpu_device *adev);
2056 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2057
2058 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2059 bool always_indirect);
2060 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2061 bool always_indirect);
2062 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2063 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2064
2065 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2066 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2067
2068 /*
2069 * Cast helper
2070 */
2071 extern const struct fence_ops amdgpu_fence_ops;
2072 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2073 {
2074 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2075
2076 if (__f->base.ops == &amdgpu_fence_ops)
2077 return __f;
2078
2079 return NULL;
2080 }
2081
2082 /*
2083 * Registers read & write functions.
2084 */
2085 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2086 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2087 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2088 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2089 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2090 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2091 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2092 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2093 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2094 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2095 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2096 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2097 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2098 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2099 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2100 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2101 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2102 #define WREG32_P(reg, val, mask) \
2103 do { \
2104 uint32_t tmp_ = RREG32(reg); \
2105 tmp_ &= (mask); \
2106 tmp_ |= ((val) & ~(mask)); \
2107 WREG32(reg, tmp_); \
2108 } while (0)
2109 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2110 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2111 #define WREG32_PLL_P(reg, val, mask) \
2112 do { \
2113 uint32_t tmp_ = RREG32_PLL(reg); \
2114 tmp_ &= (mask); \
2115 tmp_ |= ((val) & ~(mask)); \
2116 WREG32_PLL(reg, tmp_); \
2117 } while (0)
2118 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2119 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2120 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2121
2122 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2123 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2124
2125 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2126 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2127
2128 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2129 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2130 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2131
2132 #define REG_GET_FIELD(value, reg, field) \
2133 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2134
2135 /*
2136 * BIOS helpers.
2137 */
2138 #define RBIOS8(i) (adev->bios[i])
2139 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2140 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2141
2142 /*
2143 * RING helpers.
2144 */
2145 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2146 {
2147 if (ring->count_dw <= 0)
2148 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2149 ring->ring[ring->wptr++] = v;
2150 ring->wptr &= ring->ptr_mask;
2151 ring->count_dw--;
2152 ring->ring_free_dw--;
2153 }
2154
2155 /*
2156 * ASICs macro.
2157 */
2158 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2159 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2160 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2161 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2162 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2163 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2164 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2165 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2166 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2167 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2168 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2169 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2170 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2171 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2172 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2173 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2174 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2175 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2176 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2177 #define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2178 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2179 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2180 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2181 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2182 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2183 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2184 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2185 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2186 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2187 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2188 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2189 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2190 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2191 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2192 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2193 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2194 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2195 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2196 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2197 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2198 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2199 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2200 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2201 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2202 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2203 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2204 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2205 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2206 #define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2207 #define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2208 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2209 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2210 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2211 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2212 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2213 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2214 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2215 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2216 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2217 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2218 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2219 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2220 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2221 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2222 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2223 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2224 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2225 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2226
2227 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2228
2229 /* Common functions */
2230 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2231 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2232 bool amdgpu_card_posted(struct amdgpu_device *adev);
2233 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2234 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2235 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2236 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2237 u32 ip_instance, u32 ring,
2238 struct amdgpu_ring **out_ring);
2239 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2240 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2241 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2242 uint32_t flags);
2243 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2244 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2245 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2246 struct ttm_mem_reg *mem);
2247 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2248 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2249 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2250 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2251 const u32 *registers,
2252 const u32 array_size);
2253
2254 bool amdgpu_device_is_px(struct drm_device *dev);
2255 /* atpx handler */
2256 #if defined(CONFIG_VGA_SWITCHEROO)
2257 void amdgpu_register_atpx_handler(void);
2258 void amdgpu_unregister_atpx_handler(void);
2259 #else
2260 static inline void amdgpu_register_atpx_handler(void) {}
2261 static inline void amdgpu_unregister_atpx_handler(void) {}
2262 #endif
2263
2264 /*
2265 * KMS
2266 */
2267 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2268 extern int amdgpu_max_kms_ioctl;
2269
2270 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2271 int amdgpu_driver_unload_kms(struct drm_device *dev);
2272 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2273 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2274 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2275 struct drm_file *file_priv);
2276 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2277 struct drm_file *file_priv);
2278 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2279 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2280 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2281 int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2282 void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2283 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2284 int *max_error,
2285 struct timeval *vblank_time,
2286 unsigned flags);
2287 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2288 unsigned long arg);
2289
2290 /*
2291 * vm
2292 */
2293 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2294 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2295 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2296 struct amdgpu_vm *vm,
2297 struct list_head *head);
2298 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
2299 struct amdgpu_sync *sync);
2300 void amdgpu_vm_flush(struct amdgpu_ring *ring,
2301 struct amdgpu_vm *vm,
2302 struct amdgpu_fence *updates);
2303 void amdgpu_vm_fence(struct amdgpu_device *adev,
2304 struct amdgpu_vm *vm,
2305 struct amdgpu_fence *fence);
2306 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2307 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2308 struct amdgpu_vm *vm);
2309 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2310 struct amdgpu_vm *vm);
2311 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
2312 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
2313 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2314 struct amdgpu_bo_va *bo_va,
2315 struct ttm_mem_reg *mem);
2316 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2317 struct amdgpu_bo *bo);
2318 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2319 struct amdgpu_bo *bo);
2320 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2321 struct amdgpu_vm *vm,
2322 struct amdgpu_bo *bo);
2323 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2324 struct amdgpu_bo_va *bo_va,
2325 uint64_t addr, uint64_t offset,
2326 uint64_t size, uint32_t flags);
2327 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2328 struct amdgpu_bo_va *bo_va,
2329 uint64_t addr);
2330 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2331 struct amdgpu_bo_va *bo_va);
2332
2333 /*
2334 * functions used by amdgpu_encoder.c
2335 */
2336 struct amdgpu_afmt_acr {
2337 u32 clock;
2338
2339 int n_32khz;
2340 int cts_32khz;
2341
2342 int n_44_1khz;
2343 int cts_44_1khz;
2344
2345 int n_48khz;
2346 int cts_48khz;
2347
2348 };
2349
2350 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2351
2352 /* amdgpu_acpi.c */
2353 #if defined(CONFIG_ACPI)
2354 int amdgpu_acpi_init(struct amdgpu_device *adev);
2355 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2356 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2357 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2358 u8 perf_req, bool advertise);
2359 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2360 #else
2361 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2362 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2363 #endif
2364
2365 struct amdgpu_bo_va_mapping *
2366 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2367 uint64_t addr, struct amdgpu_bo **bo);
2368
2369 #include "amdgpu_object.h"
2370
2371 #endif
Linux kernel - Deliverables
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