projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/amdgpu: fix incorrect mutex usage v3
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55
56 #include "gpu_scheduler.h"
57
58 /*
59 * Modules parameters.
60 */
61 extern int amdgpu_modeset;
62 extern int amdgpu_vram_limit;
63 extern int amdgpu_gart_size;
64 extern int amdgpu_benchmarking;
65 extern int amdgpu_testing;
66 extern int amdgpu_audio;
67 extern int amdgpu_disp_priority;
68 extern int amdgpu_hw_i2c;
69 extern int amdgpu_pcie_gen2;
70 extern int amdgpu_msi;
71 extern int amdgpu_lockup_timeout;
72 extern int amdgpu_dpm;
73 extern int amdgpu_smc_load_fw;
74 extern int amdgpu_aspm;
75 extern int amdgpu_runtime_pm;
76 extern int amdgpu_hard_reset;
77 extern unsigned amdgpu_ip_block_mask;
78 extern int amdgpu_bapm;
79 extern int amdgpu_deep_color;
80 extern int amdgpu_vm_size;
81 extern int amdgpu_vm_block_size;
82 extern int amdgpu_vm_fault_stop;
83 extern int amdgpu_vm_debug;
84 extern int amdgpu_enable_scheduler;
85 extern int amdgpu_sched_jobs;
86 extern int amdgpu_sched_hw_submission;
87 extern int amdgpu_enable_semaphores;
88
89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93 #define AMDGPU_IB_POOL_SIZE 16
94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95 #define AMDGPUFB_CONN_LIMIT 4
96 #define AMDGPU_BIOS_NUM_SCRATCH 8
97
98 /* max number of rings */
99 #define AMDGPU_MAX_RINGS 16
100 #define AMDGPU_MAX_GFX_RINGS 1
101 #define AMDGPU_MAX_COMPUTE_RINGS 8
102 #define AMDGPU_MAX_VCE_RINGS 2
103
104 /* max number of IP instances */
105 #define AMDGPU_MAX_SDMA_INSTANCES 2
106
107 /* number of hw syncs before falling back on blocking */
108 #define AMDGPU_NUM_SYNCS 4
109
110 /* hardcode that limit for now */
111 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
112
113 /* hard reset data */
114 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
115
116 /* reset flags */
117 #define AMDGPU_RESET_GFX (1 << 0)
118 #define AMDGPU_RESET_COMPUTE (1 << 1)
119 #define AMDGPU_RESET_DMA (1 << 2)
120 #define AMDGPU_RESET_CP (1 << 3)
121 #define AMDGPU_RESET_GRBM (1 << 4)
122 #define AMDGPU_RESET_DMA1 (1 << 5)
123 #define AMDGPU_RESET_RLC (1 << 6)
124 #define AMDGPU_RESET_SEM (1 << 7)
125 #define AMDGPU_RESET_IH (1 << 8)
126 #define AMDGPU_RESET_VMC (1 << 9)
127 #define AMDGPU_RESET_MC (1 << 10)
128 #define AMDGPU_RESET_DISPLAY (1 << 11)
129 #define AMDGPU_RESET_UVD (1 << 12)
130 #define AMDGPU_RESET_VCE (1 << 13)
131 #define AMDGPU_RESET_VCE1 (1 << 14)
132
133 /* CG block flags */
134 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
135 #define AMDGPU_CG_BLOCK_MC (1 << 1)
136 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
137 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
138 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
139 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
140 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
141
142 /* CG flags */
143 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
144 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
145 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
146 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
147 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
148 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
149 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
150 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
151 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
152 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
153 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
154 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
155 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
156 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
157 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
158 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
159 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
160
161 /* PG flags */
162 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
163 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
164 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
165 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
166 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
167 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
168 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
169 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
170 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
171 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
172 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
173
174 /* GFX current status */
175 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
176 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
177 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
178 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
179 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
180
181 /* max cursor sizes (in pixels) */
182 #define CIK_CURSOR_WIDTH 128
183 #define CIK_CURSOR_HEIGHT 128
184
185 struct amdgpu_device;
186 struct amdgpu_fence;
187 struct amdgpu_ib;
188 struct amdgpu_vm;
189 struct amdgpu_ring;
190 struct amdgpu_semaphore;
191 struct amdgpu_cs_parser;
192 struct amdgpu_job;
193 struct amdgpu_irq_src;
194 struct amdgpu_fpriv;
195
196 enum amdgpu_cp_irq {
197 AMDGPU_CP_IRQ_GFX_EOP = 0,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
206
207 AMDGPU_CP_IRQ_LAST
208 };
209
210 enum amdgpu_sdma_irq {
211 AMDGPU_SDMA_IRQ_TRAP0 = 0,
212 AMDGPU_SDMA_IRQ_TRAP1,
213
214 AMDGPU_SDMA_IRQ_LAST
215 };
216
217 enum amdgpu_thermal_irq {
218 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
219 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
220
221 AMDGPU_THERMAL_IRQ_LAST
222 };
223
224 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
225 enum amd_ip_block_type block_type,
226 enum amd_clockgating_state state);
227 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
228 enum amd_ip_block_type block_type,
229 enum amd_powergating_state state);
230
231 struct amdgpu_ip_block_version {
232 enum amd_ip_block_type type;
233 u32 major;
234 u32 minor;
235 u32 rev;
236 const struct amd_ip_funcs *funcs;
237 };
238
239 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
240 enum amd_ip_block_type type,
241 u32 major, u32 minor);
242
243 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
244 struct amdgpu_device *adev,
245 enum amd_ip_block_type type);
246
247 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
248 struct amdgpu_buffer_funcs {
249 /* maximum bytes in a single operation */
250 uint32_t copy_max_bytes;
251
252 /* number of dw to reserve per operation */
253 unsigned copy_num_dw;
254
255 /* used for buffer migration */
256 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
257 /* src addr in bytes */
258 uint64_t src_offset,
259 /* dst addr in bytes */
260 uint64_t dst_offset,
261 /* number of byte to transfer */
262 uint32_t byte_count);
263
264 /* maximum bytes in a single operation */
265 uint32_t fill_max_bytes;
266
267 /* number of dw to reserve per operation */
268 unsigned fill_num_dw;
269
270 /* used for buffer clearing */
271 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
272 /* value to write to memory */
273 uint32_t src_data,
274 /* dst addr in bytes */
275 uint64_t dst_offset,
276 /* number of byte to fill */
277 uint32_t byte_count);
278 };
279
280 /* provided by hw blocks that can write ptes, e.g., sdma */
281 struct amdgpu_vm_pte_funcs {
282 /* copy pte entries from GART */
283 void (*copy_pte)(struct amdgpu_ib *ib,
284 uint64_t pe, uint64_t src,
285 unsigned count);
286 /* write pte one entry at a time with addr mapping */
287 void (*write_pte)(struct amdgpu_ib *ib,
288 uint64_t pe,
289 uint64_t addr, unsigned count,
290 uint32_t incr, uint32_t flags);
291 /* for linear pte/pde updates without addr mapping */
292 void (*set_pte_pde)(struct amdgpu_ib *ib,
293 uint64_t pe,
294 uint64_t addr, unsigned count,
295 uint32_t incr, uint32_t flags);
296 /* pad the indirect buffer to the necessary number of dw */
297 void (*pad_ib)(struct amdgpu_ib *ib);
298 };
299
300 /* provided by the gmc block */
301 struct amdgpu_gart_funcs {
302 /* flush the vm tlb via mmio */
303 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
304 uint32_t vmid);
305 /* write pte/pde updates using the cpu */
306 int (*set_pte_pde)(struct amdgpu_device *adev,
307 void *cpu_pt_addr, /* cpu addr of page table */
308 uint32_t gpu_page_idx, /* pte/pde to update */
309 uint64_t addr, /* addr to write into pte/pde */
310 uint32_t flags); /* access flags */
311 };
312
313 /* provided by the ih block */
314 struct amdgpu_ih_funcs {
315 /* ring read/write ptr handling, called from interrupt context */
316 u32 (*get_wptr)(struct amdgpu_device *adev);
317 void (*decode_iv)(struct amdgpu_device *adev,
318 struct amdgpu_iv_entry *entry);
319 void (*set_rptr)(struct amdgpu_device *adev);
320 };
321
322 /* provided by hw blocks that expose a ring buffer for commands */
323 struct amdgpu_ring_funcs {
324 /* ring read/write ptr handling */
325 u32 (*get_rptr)(struct amdgpu_ring *ring);
326 u32 (*get_wptr)(struct amdgpu_ring *ring);
327 void (*set_wptr)(struct amdgpu_ring *ring);
328 /* validating and patching of IBs */
329 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
330 /* command emit functions */
331 void (*emit_ib)(struct amdgpu_ring *ring,
332 struct amdgpu_ib *ib);
333 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
334 uint64_t seq, unsigned flags);
335 bool (*emit_semaphore)(struct amdgpu_ring *ring,
336 struct amdgpu_semaphore *semaphore,
337 bool emit_wait);
338 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
339 uint64_t pd_addr);
340 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
341 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
342 uint32_t gds_base, uint32_t gds_size,
343 uint32_t gws_base, uint32_t gws_size,
344 uint32_t oa_base, uint32_t oa_size);
345 /* testing functions */
346 int (*test_ring)(struct amdgpu_ring *ring);
347 int (*test_ib)(struct amdgpu_ring *ring);
348 /* insert NOP packets */
349 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
350 };
351
352 /*
353 * BIOS.
354 */
355 bool amdgpu_get_bios(struct amdgpu_device *adev);
356 bool amdgpu_read_bios(struct amdgpu_device *adev);
357
358 /*
359 * Dummy page
360 */
361 struct amdgpu_dummy_page {
362 struct page *page;
363 dma_addr_t addr;
364 };
365 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
366 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
367
368
369 /*
370 * Clocks
371 */
372
373 #define AMDGPU_MAX_PPLL 3
374
375 struct amdgpu_clock {
376 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
377 struct amdgpu_pll spll;
378 struct amdgpu_pll mpll;
379 /* 10 Khz units */
380 uint32_t default_mclk;
381 uint32_t default_sclk;
382 uint32_t default_dispclk;
383 uint32_t current_dispclk;
384 uint32_t dp_extclk;
385 uint32_t max_pixel_clock;
386 };
387
388 /*
389 * Fences.
390 */
391 struct amdgpu_fence_driver {
392 uint64_t gpu_addr;
393 volatile uint32_t *cpu_addr;
394 /* sync_seq is protected by ring emission lock */
395 uint64_t sync_seq[AMDGPU_MAX_RINGS];
396 atomic64_t last_seq;
397 bool initialized;
398 struct amdgpu_irq_src *irq_src;
399 unsigned irq_type;
400 struct timer_list fallback_timer;
401 wait_queue_head_t fence_queue;
402 };
403
404 /* some special values for the owner field */
405 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
406 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
407
408 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
409 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
410
411 struct amdgpu_fence {
412 struct fence base;
413
414 /* RB, DMA, etc. */
415 struct amdgpu_ring *ring;
416 uint64_t seq;
417
418 /* filp or special value for fence creator */
419 void *owner;
420
421 wait_queue_t fence_wake;
422 };
423
424 struct amdgpu_user_fence {
425 /* write-back bo */
426 struct amdgpu_bo *bo;
427 /* write-back address offset to bo start */
428 uint32_t offset;
429 };
430
431 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
432 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
433 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
434
435 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
436 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
437 struct amdgpu_irq_src *irq_src,
438 unsigned irq_type);
439 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
440 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
441 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
442 struct amdgpu_fence **fence);
443 void amdgpu_fence_process(struct amdgpu_ring *ring);
444 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
445 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
446 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
447
448 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
449 struct amdgpu_ring *ring);
450 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
451 struct amdgpu_ring *ring);
452
453 /*
454 * TTM.
455 */
456 struct amdgpu_mman {
457 struct ttm_bo_global_ref bo_global_ref;
458 struct drm_global_reference mem_global_ref;
459 struct ttm_bo_device bdev;
460 bool mem_global_referenced;
461 bool initialized;
462
463 #if defined(CONFIG_DEBUG_FS)
464 struct dentry *vram;
465 struct dentry *gtt;
466 #endif
467
468 /* buffer handling */
469 const struct amdgpu_buffer_funcs *buffer_funcs;
470 struct amdgpu_ring *buffer_funcs_ring;
471 };
472
473 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
474 uint64_t src_offset,
475 uint64_t dst_offset,
476 uint32_t byte_count,
477 struct reservation_object *resv,
478 struct fence **fence);
479 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
480
481 struct amdgpu_bo_list_entry {
482 struct amdgpu_bo *robj;
483 struct ttm_validate_buffer tv;
484 struct amdgpu_bo_va *bo_va;
485 unsigned prefered_domains;
486 unsigned allowed_domains;
487 uint32_t priority;
488 };
489
490 struct amdgpu_bo_va_mapping {
491 struct list_head list;
492 struct interval_tree_node it;
493 uint64_t offset;
494 uint32_t flags;
495 };
496
497 /* bo virtual addresses in a specific vm */
498 struct amdgpu_bo_va {
499 /* protected by bo being reserved */
500 struct list_head bo_list;
501 struct fence *last_pt_update;
502 unsigned ref_count;
503
504 /* protected by vm mutex and spinlock */
505 struct list_head vm_status;
506
507 /* mappings for this bo_va */
508 struct list_head invalids;
509 struct list_head valids;
510
511 /* constant after initialization */
512 struct amdgpu_vm *vm;
513 struct amdgpu_bo *bo;
514 };
515
516 #define AMDGPU_GEM_DOMAIN_MAX 0x3
517
518 struct amdgpu_bo {
519 /* Protected by gem.mutex */
520 struct list_head list;
521 /* Protected by tbo.reserved */
522 u32 initial_domain;
523 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
524 struct ttm_placement placement;
525 struct ttm_buffer_object tbo;
526 struct ttm_bo_kmap_obj kmap;
527 u64 flags;
528 unsigned pin_count;
529 void *kptr;
530 u64 tiling_flags;
531 u64 metadata_flags;
532 void *metadata;
533 u32 metadata_size;
534 /* list of all virtual address to which this bo
535 * is associated to
536 */
537 struct list_head va;
538 /* Constant after initialization */
539 struct amdgpu_device *adev;
540 struct drm_gem_object gem_base;
541
542 struct ttm_bo_kmap_obj dma_buf_vmap;
543 pid_t pid;
544 struct amdgpu_mn *mn;
545 struct list_head mn_list;
546 };
547 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
548
549 void amdgpu_gem_object_free(struct drm_gem_object *obj);
550 int amdgpu_gem_object_open(struct drm_gem_object *obj,
551 struct drm_file *file_priv);
552 void amdgpu_gem_object_close(struct drm_gem_object *obj,
553 struct drm_file *file_priv);
554 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
555 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
556 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
557 struct dma_buf_attachment *attach,
558 struct sg_table *sg);
559 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
560 struct drm_gem_object *gobj,
561 int flags);
562 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
563 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
564 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
565 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
566 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
567 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
568
569 /* sub-allocation manager, it has to be protected by another lock.
570 * By conception this is an helper for other part of the driver
571 * like the indirect buffer or semaphore, which both have their
572 * locking.
573 *
574 * Principe is simple, we keep a list of sub allocation in offset
575 * order (first entry has offset == 0, last entry has the highest
576 * offset).
577 *
578 * When allocating new object we first check if there is room at
579 * the end total_size - (last_object_offset + last_object_size) >=
580 * alloc_size. If so we allocate new object there.
581 *
582 * When there is not enough room at the end, we start waiting for
583 * each sub object until we reach object_offset+object_size >=
584 * alloc_size, this object then become the sub object we return.
585 *
586 * Alignment can't be bigger than page size.
587 *
588 * Hole are not considered for allocation to keep things simple.
589 * Assumption is that there won't be hole (all object on same
590 * alignment).
591 */
592 struct amdgpu_sa_manager {
593 wait_queue_head_t wq;
594 struct amdgpu_bo *bo;
595 struct list_head *hole;
596 struct list_head flist[AMDGPU_MAX_RINGS];
597 struct list_head olist;
598 unsigned size;
599 uint64_t gpu_addr;
600 void *cpu_ptr;
601 uint32_t domain;
602 uint32_t align;
603 };
604
605 struct amdgpu_sa_bo;
606
607 /* sub-allocation buffer */
608 struct amdgpu_sa_bo {
609 struct list_head olist;
610 struct list_head flist;
611 struct amdgpu_sa_manager *manager;
612 unsigned soffset;
613 unsigned eoffset;
614 struct fence *fence;
615 };
616
617 /*
618 * GEM objects.
619 */
620 struct amdgpu_gem {
621 struct mutex mutex;
622 struct list_head objects;
623 };
624
625 int amdgpu_gem_init(struct amdgpu_device *adev);
626 void amdgpu_gem_fini(struct amdgpu_device *adev);
627 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
628 int alignment, u32 initial_domain,
629 u64 flags, bool kernel,
630 struct drm_gem_object **obj);
631
632 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
633 struct drm_device *dev,
634 struct drm_mode_create_dumb *args);
635 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
636 struct drm_device *dev,
637 uint32_t handle, uint64_t *offset_p);
638
639 /*
640 * Semaphores.
641 */
642 struct amdgpu_semaphore {
643 struct amdgpu_sa_bo *sa_bo;
644 signed waiters;
645 uint64_t gpu_addr;
646 };
647
648 int amdgpu_semaphore_create(struct amdgpu_device *adev,
649 struct amdgpu_semaphore **semaphore);
650 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
651 struct amdgpu_semaphore *semaphore);
652 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
653 struct amdgpu_semaphore *semaphore);
654 void amdgpu_semaphore_free(struct amdgpu_device *adev,
655 struct amdgpu_semaphore **semaphore,
656 struct fence *fence);
657
658 /*
659 * Synchronization
660 */
661 struct amdgpu_sync {
662 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
663 struct fence *sync_to[AMDGPU_MAX_RINGS];
664 DECLARE_HASHTABLE(fences, 4);
665 struct fence *last_vm_update;
666 };
667
668 void amdgpu_sync_create(struct amdgpu_sync *sync);
669 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
670 struct fence *f);
671 int amdgpu_sync_resv(struct amdgpu_device *adev,
672 struct amdgpu_sync *sync,
673 struct reservation_object *resv,
674 void *owner);
675 int amdgpu_sync_rings(struct amdgpu_sync *sync,
676 struct amdgpu_ring *ring);
677 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
678 int amdgpu_sync_wait(struct amdgpu_sync *sync);
679 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
680 struct fence *fence);
681
682 /*
683 * GART structures, functions & helpers
684 */
685 struct amdgpu_mc;
686
687 #define AMDGPU_GPU_PAGE_SIZE 4096
688 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
689 #define AMDGPU_GPU_PAGE_SHIFT 12
690 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
691
692 struct amdgpu_gart {
693 dma_addr_t table_addr;
694 struct amdgpu_bo *robj;
695 void *ptr;
696 unsigned num_gpu_pages;
697 unsigned num_cpu_pages;
698 unsigned table_size;
699 struct page **pages;
700 dma_addr_t *pages_addr;
701 bool ready;
702 const struct amdgpu_gart_funcs *gart_funcs;
703 };
704
705 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
706 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
707 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
708 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
709 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
710 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
711 int amdgpu_gart_init(struct amdgpu_device *adev);
712 void amdgpu_gart_fini(struct amdgpu_device *adev);
713 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
714 int pages);
715 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
716 int pages, struct page **pagelist,
717 dma_addr_t *dma_addr, uint32_t flags);
718
719 /*
720 * GPU MC structures, functions & helpers
721 */
722 struct amdgpu_mc {
723 resource_size_t aper_size;
724 resource_size_t aper_base;
725 resource_size_t agp_base;
726 /* for some chips with <= 32MB we need to lie
727 * about vram size near mc fb location */
728 u64 mc_vram_size;
729 u64 visible_vram_size;
730 u64 gtt_size;
731 u64 gtt_start;
732 u64 gtt_end;
733 u64 vram_start;
734 u64 vram_end;
735 unsigned vram_width;
736 u64 real_vram_size;
737 int vram_mtrr;
738 u64 gtt_base_align;
739 u64 mc_mask;
740 const struct firmware *fw; /* MC firmware */
741 uint32_t fw_version;
742 struct amdgpu_irq_src vm_fault;
743 uint32_t vram_type;
744 };
745
746 /*
747 * GPU doorbell structures, functions & helpers
748 */
749 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
750 {
751 AMDGPU_DOORBELL_KIQ = 0x000,
752 AMDGPU_DOORBELL_HIQ = 0x001,
753 AMDGPU_DOORBELL_DIQ = 0x002,
754 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
755 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
756 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
757 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
758 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
759 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
760 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
761 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
762 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
763 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
764 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
765 AMDGPU_DOORBELL_IH = 0x1E8,
766 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
767 AMDGPU_DOORBELL_INVALID = 0xFFFF
768 } AMDGPU_DOORBELL_ASSIGNMENT;
769
770 struct amdgpu_doorbell {
771 /* doorbell mmio */
772 resource_size_t base;
773 resource_size_t size;
774 u32 __iomem *ptr;
775 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
776 };
777
778 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
779 phys_addr_t *aperture_base,
780 size_t *aperture_size,
781 size_t *start_offset);
782
783 /*
784 * IRQS.
785 */
786
787 struct amdgpu_flip_work {
788 struct work_struct flip_work;
789 struct work_struct unpin_work;
790 struct amdgpu_device *adev;
791 int crtc_id;
792 uint64_t base;
793 struct drm_pending_vblank_event *event;
794 struct amdgpu_bo *old_rbo;
795 struct fence *excl;
796 unsigned shared_count;
797 struct fence **shared;
798 };
799
800
801 /*
802 * CP & rings.
803 */
804
805 struct amdgpu_ib {
806 struct amdgpu_sa_bo *sa_bo;
807 uint32_t length_dw;
808 uint64_t gpu_addr;
809 uint32_t *ptr;
810 struct amdgpu_ring *ring;
811 struct amdgpu_fence *fence;
812 struct amdgpu_user_fence *user;
813 struct amdgpu_vm *vm;
814 struct amdgpu_ctx *ctx;
815 struct amdgpu_sync sync;
816 uint32_t gds_base, gds_size;
817 uint32_t gws_base, gws_size;
818 uint32_t oa_base, oa_size;
819 uint32_t flags;
820 /* resulting sequence number */
821 uint64_t sequence;
822 };
823
824 enum amdgpu_ring_type {
825 AMDGPU_RING_TYPE_GFX,
826 AMDGPU_RING_TYPE_COMPUTE,
827 AMDGPU_RING_TYPE_SDMA,
828 AMDGPU_RING_TYPE_UVD,
829 AMDGPU_RING_TYPE_VCE
830 };
831
832 extern struct amd_sched_backend_ops amdgpu_sched_ops;
833
834 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
835 struct amdgpu_ring *ring,
836 struct amdgpu_ib *ibs,
837 unsigned num_ibs,
838 int (*free_job)(struct amdgpu_job *),
839 void *owner,
840 struct fence **fence);
841
842 struct amdgpu_ring {
843 struct amdgpu_device *adev;
844 const struct amdgpu_ring_funcs *funcs;
845 struct amdgpu_fence_driver fence_drv;
846 struct amd_gpu_scheduler sched;
847
848 spinlock_t fence_lock;
849 struct mutex *ring_lock;
850 struct amdgpu_bo *ring_obj;
851 volatile uint32_t *ring;
852 unsigned rptr_offs;
853 u64 next_rptr_gpu_addr;
854 volatile u32 *next_rptr_cpu_addr;
855 unsigned wptr;
856 unsigned wptr_old;
857 unsigned ring_size;
858 unsigned ring_free_dw;
859 int count_dw;
860 uint64_t gpu_addr;
861 uint32_t align_mask;
862 uint32_t ptr_mask;
863 bool ready;
864 u32 nop;
865 u32 idx;
866 u64 last_semaphore_signal_addr;
867 u64 last_semaphore_wait_addr;
868 u32 me;
869 u32 pipe;
870 u32 queue;
871 struct amdgpu_bo *mqd_obj;
872 u32 doorbell_index;
873 bool use_doorbell;
874 unsigned wptr_offs;
875 unsigned next_rptr_offs;
876 unsigned fence_offs;
877 struct amdgpu_ctx *current_ctx;
878 enum amdgpu_ring_type type;
879 char name[16];
880 bool is_pte_ring;
881 };
882
883 /*
884 * VM
885 */
886
887 /* maximum number of VMIDs */
888 #define AMDGPU_NUM_VM 16
889
890 /* number of entries in page table */
891 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
892
893 /* PTBs (Page Table Blocks) need to be aligned to 32K */
894 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
895 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
896 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
897
898 #define AMDGPU_PTE_VALID (1 << 0)
899 #define AMDGPU_PTE_SYSTEM (1 << 1)
900 #define AMDGPU_PTE_SNOOPED (1 << 2)
901
902 /* VI only */
903 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
904
905 #define AMDGPU_PTE_READABLE (1 << 5)
906 #define AMDGPU_PTE_WRITEABLE (1 << 6)
907
908 /* PTE (Page Table Entry) fragment field for different page sizes */
909 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
910 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
911 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
912
913 /* How to programm VM fault handling */
914 #define AMDGPU_VM_FAULT_STOP_NEVER 0
915 #define AMDGPU_VM_FAULT_STOP_FIRST 1
916 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
917
918 struct amdgpu_vm_pt {
919 struct amdgpu_bo *bo;
920 uint64_t addr;
921 };
922
923 struct amdgpu_vm_id {
924 unsigned id;
925 uint64_t pd_gpu_addr;
926 /* last flushed PD/PT update */
927 struct fence *flushed_updates;
928 /* last use of vmid */
929 struct fence *last_id_use;
930 };
931
932 struct amdgpu_vm {
933 struct mutex mutex;
934
935 struct rb_root va;
936
937 /* protecting invalidated */
938 spinlock_t status_lock;
939
940 /* BOs moved, but not yet updated in the PT */
941 struct list_head invalidated;
942
943 /* BOs cleared in the PT because of a move */
944 struct list_head cleared;
945
946 /* BO mappings freed, but not yet updated in the PT */
947 struct list_head freed;
948
949 /* contains the page directory */
950 struct amdgpu_bo *page_directory;
951 unsigned max_pde_used;
952 struct fence *page_directory_fence;
953
954 /* array of page tables, one for each page directory entry */
955 struct amdgpu_vm_pt *page_tables;
956
957 /* for id and flush management per ring */
958 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
959 };
960
961 struct amdgpu_vm_manager {
962 struct fence *active[AMDGPU_NUM_VM];
963 uint32_t max_pfn;
964 /* number of VMIDs */
965 unsigned nvm;
966 /* vram base address for page table entry */
967 u64 vram_base_offset;
968 /* is vm enabled? */
969 bool enabled;
970 /* for hw to save the PD addr on suspend/resume */
971 uint32_t saved_table_addr[AMDGPU_NUM_VM];
972 /* vm pte handling */
973 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
974 struct amdgpu_ring *vm_pte_funcs_ring;
975 };
976
977 /*
978 * context related structures
979 */
980
981 #define AMDGPU_CTX_MAX_CS_PENDING 16
982
983 struct amdgpu_ctx_ring {
984 uint64_t sequence;
985 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
986 struct amd_sched_entity entity;
987 };
988
989 struct amdgpu_ctx {
990 struct kref refcount;
991 struct amdgpu_device *adev;
992 unsigned reset_counter;
993 spinlock_t ring_lock;
994 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
995 };
996
997 struct amdgpu_ctx_mgr {
998 struct amdgpu_device *adev;
999 struct mutex lock;
1000 /* protected by lock */
1001 struct idr ctx_handles;
1002 };
1003
1004 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
1005 struct amdgpu_ctx *ctx);
1006 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
1007
1008 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1009 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1010
1011 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1012 struct fence *fence);
1013 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1014 struct amdgpu_ring *ring, uint64_t seq);
1015
1016 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1017 struct drm_file *filp);
1018
1019 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1020 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1021
1022 /*
1023 * file private structure
1024 */
1025
1026 struct amdgpu_fpriv {
1027 struct amdgpu_vm vm;
1028 struct mutex bo_list_lock;
1029 struct idr bo_list_handles;
1030 struct amdgpu_ctx_mgr ctx_mgr;
1031 };
1032
1033 /*
1034 * residency list
1035 */
1036
1037 struct amdgpu_bo_list {
1038 struct mutex lock;
1039 struct amdgpu_bo *gds_obj;
1040 struct amdgpu_bo *gws_obj;
1041 struct amdgpu_bo *oa_obj;
1042 bool has_userptr;
1043 unsigned num_entries;
1044 struct amdgpu_bo_list_entry *array;
1045 };
1046
1047 struct amdgpu_bo_list *
1048 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1049 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1050 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1051
1052 /*
1053 * GFX stuff
1054 */
1055 #include "clearstate_defs.h"
1056
1057 struct amdgpu_rlc {
1058 /* for power gating */
1059 struct amdgpu_bo *save_restore_obj;
1060 uint64_t save_restore_gpu_addr;
1061 volatile uint32_t *sr_ptr;
1062 const u32 *reg_list;
1063 u32 reg_list_size;
1064 /* for clear state */
1065 struct amdgpu_bo *clear_state_obj;
1066 uint64_t clear_state_gpu_addr;
1067 volatile uint32_t *cs_ptr;
1068 const struct cs_section_def *cs_data;
1069 u32 clear_state_size;
1070 /* for cp tables */
1071 struct amdgpu_bo *cp_table_obj;
1072 uint64_t cp_table_gpu_addr;
1073 volatile uint32_t *cp_table_ptr;
1074 u32 cp_table_size;
1075 };
1076
1077 struct amdgpu_mec {
1078 struct amdgpu_bo *hpd_eop_obj;
1079 u64 hpd_eop_gpu_addr;
1080 u32 num_pipe;
1081 u32 num_mec;
1082 u32 num_queue;
1083 };
1084
1085 /*
1086 * GPU scratch registers structures, functions & helpers
1087 */
1088 struct amdgpu_scratch {
1089 unsigned num_reg;
1090 uint32_t reg_base;
1091 bool free[32];
1092 uint32_t reg[32];
1093 };
1094
1095 /*
1096 * GFX configurations
1097 */
1098 struct amdgpu_gca_config {
1099 unsigned max_shader_engines;
1100 unsigned max_tile_pipes;
1101 unsigned max_cu_per_sh;
1102 unsigned max_sh_per_se;
1103 unsigned max_backends_per_se;
1104 unsigned max_texture_channel_caches;
1105 unsigned max_gprs;
1106 unsigned max_gs_threads;
1107 unsigned max_hw_contexts;
1108 unsigned sc_prim_fifo_size_frontend;
1109 unsigned sc_prim_fifo_size_backend;
1110 unsigned sc_hiz_tile_fifo_size;
1111 unsigned sc_earlyz_tile_fifo_size;
1112
1113 unsigned num_tile_pipes;
1114 unsigned backend_enable_mask;
1115 unsigned mem_max_burst_length_bytes;
1116 unsigned mem_row_size_in_kb;
1117 unsigned shader_engine_tile_size;
1118 unsigned num_gpus;
1119 unsigned multi_gpu_tile_size;
1120 unsigned mc_arb_ramcfg;
1121 unsigned gb_addr_config;
1122
1123 uint32_t tile_mode_array[32];
1124 uint32_t macrotile_mode_array[16];
1125 };
1126
1127 struct amdgpu_gfx {
1128 struct mutex gpu_clock_mutex;
1129 struct amdgpu_gca_config config;
1130 struct amdgpu_rlc rlc;
1131 struct amdgpu_mec mec;
1132 struct amdgpu_scratch scratch;
1133 const struct firmware *me_fw; /* ME firmware */
1134 uint32_t me_fw_version;
1135 const struct firmware *pfp_fw; /* PFP firmware */
1136 uint32_t pfp_fw_version;
1137 const struct firmware *ce_fw; /* CE firmware */
1138 uint32_t ce_fw_version;
1139 const struct firmware *rlc_fw; /* RLC firmware */
1140 uint32_t rlc_fw_version;
1141 const struct firmware *mec_fw; /* MEC firmware */
1142 uint32_t mec_fw_version;
1143 const struct firmware *mec2_fw; /* MEC2 firmware */
1144 uint32_t mec2_fw_version;
1145 uint32_t me_feature_version;
1146 uint32_t ce_feature_version;
1147 uint32_t pfp_feature_version;
1148 uint32_t rlc_feature_version;
1149 uint32_t mec_feature_version;
1150 uint32_t mec2_feature_version;
1151 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1152 unsigned num_gfx_rings;
1153 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1154 unsigned num_compute_rings;
1155 struct amdgpu_irq_src eop_irq;
1156 struct amdgpu_irq_src priv_reg_irq;
1157 struct amdgpu_irq_src priv_inst_irq;
1158 /* gfx status */
1159 uint32_t gfx_current_status;
1160 /* ce ram size*/
1161 unsigned ce_ram_size;
1162 };
1163
1164 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1165 unsigned size, struct amdgpu_ib *ib);
1166 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1167 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1168 struct amdgpu_ib *ib, void *owner);
1169 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1170 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1171 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1172 /* Ring access between begin & end cannot sleep */
1173 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1174 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1175 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1176 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1177 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1178 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1179 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1180 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1181 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1182 uint32_t **data);
1183 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1184 unsigned size, uint32_t *data);
1185 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1186 unsigned ring_size, u32 nop, u32 align_mask,
1187 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1188 enum amdgpu_ring_type ring_type);
1189 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1190 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
1191
1192 /*
1193 * CS.
1194 */
1195 struct amdgpu_cs_chunk {
1196 uint32_t chunk_id;
1197 uint32_t length_dw;
1198 uint32_t *kdata;
1199 void __user *user_ptr;
1200 };
1201
1202 struct amdgpu_cs_parser {
1203 struct amdgpu_device *adev;
1204 struct drm_file *filp;
1205 struct amdgpu_ctx *ctx;
1206 struct amdgpu_bo_list *bo_list;
1207 /* chunks */
1208 unsigned nchunks;
1209 struct amdgpu_cs_chunk *chunks;
1210 /* relocations */
1211 struct amdgpu_bo_list_entry *vm_bos;
1212 struct list_head validated;
1213
1214 struct amdgpu_ib *ibs;
1215 uint32_t num_ibs;
1216
1217 struct ww_acquire_ctx ticket;
1218
1219 /* user fence */
1220 struct amdgpu_user_fence uf;
1221 };
1222
1223 struct amdgpu_job {
1224 struct amd_sched_job base;
1225 struct amdgpu_device *adev;
1226 struct amdgpu_ib *ibs;
1227 uint32_t num_ibs;
1228 void *owner;
1229 struct amdgpu_user_fence uf;
1230 int (*free_job)(struct amdgpu_job *job);
1231 };
1232 #define to_amdgpu_job(sched_job) \
1233 container_of((sched_job), struct amdgpu_job, base)
1234
1235 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1236 {
1237 return p->ibs[ib_idx].ptr[idx];
1238 }
1239
1240 /*
1241 * Writeback
1242 */
1243 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1244
1245 struct amdgpu_wb {
1246 struct amdgpu_bo *wb_obj;
1247 volatile uint32_t *wb;
1248 uint64_t gpu_addr;
1249 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1250 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1251 };
1252
1253 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1254 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1255
1256 /**
1257 * struct amdgpu_pm - power management datas
1258 * It keeps track of various data needed to take powermanagement decision.
1259 */
1260
1261 enum amdgpu_pm_state_type {
1262 /* not used for dpm */
1263 POWER_STATE_TYPE_DEFAULT,
1264 POWER_STATE_TYPE_POWERSAVE,
1265 /* user selectable states */
1266 POWER_STATE_TYPE_BATTERY,
1267 POWER_STATE_TYPE_BALANCED,
1268 POWER_STATE_TYPE_PERFORMANCE,
1269 /* internal states */
1270 POWER_STATE_TYPE_INTERNAL_UVD,
1271 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1272 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1273 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1274 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1275 POWER_STATE_TYPE_INTERNAL_BOOT,
1276 POWER_STATE_TYPE_INTERNAL_THERMAL,
1277 POWER_STATE_TYPE_INTERNAL_ACPI,
1278 POWER_STATE_TYPE_INTERNAL_ULV,
1279 POWER_STATE_TYPE_INTERNAL_3DPERF,
1280 };
1281
1282 enum amdgpu_int_thermal_type {
1283 THERMAL_TYPE_NONE,
1284 THERMAL_TYPE_EXTERNAL,
1285 THERMAL_TYPE_EXTERNAL_GPIO,
1286 THERMAL_TYPE_RV6XX,
1287 THERMAL_TYPE_RV770,
1288 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1289 THERMAL_TYPE_EVERGREEN,
1290 THERMAL_TYPE_SUMO,
1291 THERMAL_TYPE_NI,
1292 THERMAL_TYPE_SI,
1293 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1294 THERMAL_TYPE_CI,
1295 THERMAL_TYPE_KV,
1296 };
1297
1298 enum amdgpu_dpm_auto_throttle_src {
1299 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1300 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1301 };
1302
1303 enum amdgpu_dpm_event_src {
1304 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1305 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1306 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1307 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1308 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1309 };
1310
1311 #define AMDGPU_MAX_VCE_LEVELS 6
1312
1313 enum amdgpu_vce_level {
1314 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1315 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1316 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1317 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1318 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1319 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1320 };
1321
1322 struct amdgpu_ps {
1323 u32 caps; /* vbios flags */
1324 u32 class; /* vbios flags */
1325 u32 class2; /* vbios flags */
1326 /* UVD clocks */
1327 u32 vclk;
1328 u32 dclk;
1329 /* VCE clocks */
1330 u32 evclk;
1331 u32 ecclk;
1332 bool vce_active;
1333 enum amdgpu_vce_level vce_level;
1334 /* asic priv */
1335 void *ps_priv;
1336 };
1337
1338 struct amdgpu_dpm_thermal {
1339 /* thermal interrupt work */
1340 struct work_struct work;
1341 /* low temperature threshold */
1342 int min_temp;
1343 /* high temperature threshold */
1344 int max_temp;
1345 /* was last interrupt low to high or high to low */
1346 bool high_to_low;
1347 /* interrupt source */
1348 struct amdgpu_irq_src irq;
1349 };
1350
1351 enum amdgpu_clk_action
1352 {
1353 AMDGPU_SCLK_UP = 1,
1354 AMDGPU_SCLK_DOWN
1355 };
1356
1357 struct amdgpu_blacklist_clocks
1358 {
1359 u32 sclk;
1360 u32 mclk;
1361 enum amdgpu_clk_action action;
1362 };
1363
1364 struct amdgpu_clock_and_voltage_limits {
1365 u32 sclk;
1366 u32 mclk;
1367 u16 vddc;
1368 u16 vddci;
1369 };
1370
1371 struct amdgpu_clock_array {
1372 u32 count;
1373 u32 *values;
1374 };
1375
1376 struct amdgpu_clock_voltage_dependency_entry {
1377 u32 clk;
1378 u16 v;
1379 };
1380
1381 struct amdgpu_clock_voltage_dependency_table {
1382 u32 count;
1383 struct amdgpu_clock_voltage_dependency_entry *entries;
1384 };
1385
1386 union amdgpu_cac_leakage_entry {
1387 struct {
1388 u16 vddc;
1389 u32 leakage;
1390 };
1391 struct {
1392 u16 vddc1;
1393 u16 vddc2;
1394 u16 vddc3;
1395 };
1396 };
1397
1398 struct amdgpu_cac_leakage_table {
1399 u32 count;
1400 union amdgpu_cac_leakage_entry *entries;
1401 };
1402
1403 struct amdgpu_phase_shedding_limits_entry {
1404 u16 voltage;
1405 u32 sclk;
1406 u32 mclk;
1407 };
1408
1409 struct amdgpu_phase_shedding_limits_table {
1410 u32 count;
1411 struct amdgpu_phase_shedding_limits_entry *entries;
1412 };
1413
1414 struct amdgpu_uvd_clock_voltage_dependency_entry {
1415 u32 vclk;
1416 u32 dclk;
1417 u16 v;
1418 };
1419
1420 struct amdgpu_uvd_clock_voltage_dependency_table {
1421 u8 count;
1422 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1423 };
1424
1425 struct amdgpu_vce_clock_voltage_dependency_entry {
1426 u32 ecclk;
1427 u32 evclk;
1428 u16 v;
1429 };
1430
1431 struct amdgpu_vce_clock_voltage_dependency_table {
1432 u8 count;
1433 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1434 };
1435
1436 struct amdgpu_ppm_table {
1437 u8 ppm_design;
1438 u16 cpu_core_number;
1439 u32 platform_tdp;
1440 u32 small_ac_platform_tdp;
1441 u32 platform_tdc;
1442 u32 small_ac_platform_tdc;
1443 u32 apu_tdp;
1444 u32 dgpu_tdp;
1445 u32 dgpu_ulv_power;
1446 u32 tj_max;
1447 };
1448
1449 struct amdgpu_cac_tdp_table {
1450 u16 tdp;
1451 u16 configurable_tdp;
1452 u16 tdc;
1453 u16 battery_power_limit;
1454 u16 small_power_limit;
1455 u16 low_cac_leakage;
1456 u16 high_cac_leakage;
1457 u16 maximum_power_delivery_limit;
1458 };
1459
1460 struct amdgpu_dpm_dynamic_state {
1461 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1462 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1463 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1464 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1465 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1466 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1467 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1468 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1469 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1470 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1471 struct amdgpu_clock_array valid_sclk_values;
1472 struct amdgpu_clock_array valid_mclk_values;
1473 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1474 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1475 u32 mclk_sclk_ratio;
1476 u32 sclk_mclk_delta;
1477 u16 vddc_vddci_delta;
1478 u16 min_vddc_for_pcie_gen2;
1479 struct amdgpu_cac_leakage_table cac_leakage_table;
1480 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1481 struct amdgpu_ppm_table *ppm_table;
1482 struct amdgpu_cac_tdp_table *cac_tdp_table;
1483 };
1484
1485 struct amdgpu_dpm_fan {
1486 u16 t_min;
1487 u16 t_med;
1488 u16 t_high;
1489 u16 pwm_min;
1490 u16 pwm_med;
1491 u16 pwm_high;
1492 u8 t_hyst;
1493 u32 cycle_delay;
1494 u16 t_max;
1495 u8 control_mode;
1496 u16 default_max_fan_pwm;
1497 u16 default_fan_output_sensitivity;
1498 u16 fan_output_sensitivity;
1499 bool ucode_fan_control;
1500 };
1501
1502 enum amdgpu_pcie_gen {
1503 AMDGPU_PCIE_GEN1 = 0,
1504 AMDGPU_PCIE_GEN2 = 1,
1505 AMDGPU_PCIE_GEN3 = 2,
1506 AMDGPU_PCIE_GEN_INVALID = 0xffff
1507 };
1508
1509 enum amdgpu_dpm_forced_level {
1510 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1511 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1512 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1513 };
1514
1515 struct amdgpu_vce_state {
1516 /* vce clocks */
1517 u32 evclk;
1518 u32 ecclk;
1519 /* gpu clocks */
1520 u32 sclk;
1521 u32 mclk;
1522 u8 clk_idx;
1523 u8 pstate;
1524 };
1525
1526 struct amdgpu_dpm_funcs {
1527 int (*get_temperature)(struct amdgpu_device *adev);
1528 int (*pre_set_power_state)(struct amdgpu_device *adev);
1529 int (*set_power_state)(struct amdgpu_device *adev);
1530 void (*post_set_power_state)(struct amdgpu_device *adev);
1531 void (*display_configuration_changed)(struct amdgpu_device *adev);
1532 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1533 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1534 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1535 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1536 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1537 bool (*vblank_too_short)(struct amdgpu_device *adev);
1538 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1539 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1540 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1541 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1542 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1543 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1544 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1545 };
1546
1547 struct amdgpu_dpm {
1548 struct amdgpu_ps *ps;
1549 /* number of valid power states */
1550 int num_ps;
1551 /* current power state that is active */
1552 struct amdgpu_ps *current_ps;
1553 /* requested power state */
1554 struct amdgpu_ps *requested_ps;
1555 /* boot up power state */
1556 struct amdgpu_ps *boot_ps;
1557 /* default uvd power state */
1558 struct amdgpu_ps *uvd_ps;
1559 /* vce requirements */
1560 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1561 enum amdgpu_vce_level vce_level;
1562 enum amdgpu_pm_state_type state;
1563 enum amdgpu_pm_state_type user_state;
1564 u32 platform_caps;
1565 u32 voltage_response_time;
1566 u32 backbias_response_time;
1567 void *priv;
1568 u32 new_active_crtcs;
1569 int new_active_crtc_count;
1570 u32 current_active_crtcs;
1571 int current_active_crtc_count;
1572 struct amdgpu_dpm_dynamic_state dyn_state;
1573 struct amdgpu_dpm_fan fan;
1574 u32 tdp_limit;
1575 u32 near_tdp_limit;
1576 u32 near_tdp_limit_adjusted;
1577 u32 sq_ramping_threshold;
1578 u32 cac_leakage;
1579 u16 tdp_od_limit;
1580 u32 tdp_adjustment;
1581 u16 load_line_slope;
1582 bool power_control;
1583 bool ac_power;
1584 /* special states active */
1585 bool thermal_active;
1586 bool uvd_active;
1587 bool vce_active;
1588 /* thermal handling */
1589 struct amdgpu_dpm_thermal thermal;
1590 /* forced levels */
1591 enum amdgpu_dpm_forced_level forced_level;
1592 };
1593
1594 struct amdgpu_pm {
1595 struct mutex mutex;
1596 u32 current_sclk;
1597 u32 current_mclk;
1598 u32 default_sclk;
1599 u32 default_mclk;
1600 struct amdgpu_i2c_chan *i2c_bus;
1601 /* internal thermal controller on rv6xx+ */
1602 enum amdgpu_int_thermal_type int_thermal_type;
1603 struct device *int_hwmon_dev;
1604 /* fan control parameters */
1605 bool no_fan;
1606 u8 fan_pulses_per_revolution;
1607 u8 fan_min_rpm;
1608 u8 fan_max_rpm;
1609 /* dpm */
1610 bool dpm_enabled;
1611 bool sysfs_initialized;
1612 struct amdgpu_dpm dpm;
1613 const struct firmware *fw; /* SMC firmware */
1614 uint32_t fw_version;
1615 const struct amdgpu_dpm_funcs *funcs;
1616 };
1617
1618 /*
1619 * UVD
1620 */
1621 #define AMDGPU_MAX_UVD_HANDLES 10
1622 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1623 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1624 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1625
1626 struct amdgpu_uvd {
1627 struct amdgpu_bo *vcpu_bo;
1628 void *cpu_addr;
1629 uint64_t gpu_addr;
1630 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1631 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1632 struct delayed_work idle_work;
1633 const struct firmware *fw; /* UVD firmware */
1634 struct amdgpu_ring ring;
1635 struct amdgpu_irq_src irq;
1636 bool address_64_bit;
1637 };
1638
1639 /*
1640 * VCE
1641 */
1642 #define AMDGPU_MAX_VCE_HANDLES 16
1643 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1644
1645 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1646 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1647
1648 struct amdgpu_vce {
1649 struct amdgpu_bo *vcpu_bo;
1650 uint64_t gpu_addr;
1651 unsigned fw_version;
1652 unsigned fb_version;
1653 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1654 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1655 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1656 struct delayed_work idle_work;
1657 const struct firmware *fw; /* VCE firmware */
1658 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1659 struct amdgpu_irq_src irq;
1660 unsigned harvest_config;
1661 };
1662
1663 /*
1664 * SDMA
1665 */
1666 struct amdgpu_sdma_instance {
1667 /* SDMA firmware */
1668 const struct firmware *fw;
1669 uint32_t fw_version;
1670 uint32_t feature_version;
1671
1672 struct amdgpu_ring ring;
1673 bool burst_nop;
1674 };
1675
1676 struct amdgpu_sdma {
1677 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1678 struct amdgpu_irq_src trap_irq;
1679 struct amdgpu_irq_src illegal_inst_irq;
1680 int num_instances;
1681 };
1682
1683 /*
1684 * Firmware
1685 */
1686 struct amdgpu_firmware {
1687 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1688 bool smu_load;
1689 struct amdgpu_bo *fw_buf;
1690 unsigned int fw_size;
1691 };
1692
1693 /*
1694 * Benchmarking
1695 */
1696 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1697
1698
1699 /*
1700 * Testing
1701 */
1702 void amdgpu_test_moves(struct amdgpu_device *adev);
1703 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1704 struct amdgpu_ring *cpA,
1705 struct amdgpu_ring *cpB);
1706 void amdgpu_test_syncing(struct amdgpu_device *adev);
1707
1708 /*
1709 * MMU Notifier
1710 */
1711 #if defined(CONFIG_MMU_NOTIFIER)
1712 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1713 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1714 #else
1715 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1716 {
1717 return -ENODEV;
1718 }
1719 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1720 #endif
1721
1722 /*
1723 * Debugfs
1724 */
1725 struct amdgpu_debugfs {
1726 struct drm_info_list *files;
1727 unsigned num_files;
1728 };
1729
1730 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1731 struct drm_info_list *files,
1732 unsigned nfiles);
1733 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1734
1735 #if defined(CONFIG_DEBUG_FS)
1736 int amdgpu_debugfs_init(struct drm_minor *minor);
1737 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1738 #endif
1739
1740 /*
1741 * amdgpu smumgr functions
1742 */
1743 struct amdgpu_smumgr_funcs {
1744 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1745 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1746 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1747 };
1748
1749 /*
1750 * amdgpu smumgr
1751 */
1752 struct amdgpu_smumgr {
1753 struct amdgpu_bo *toc_buf;
1754 struct amdgpu_bo *smu_buf;
1755 /* asic priv smu data */
1756 void *priv;
1757 spinlock_t smu_lock;
1758 /* smumgr functions */
1759 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1760 /* ucode loading complete flag */
1761 uint32_t fw_flags;
1762 };
1763
1764 /*
1765 * ASIC specific register table accessible by UMD
1766 */
1767 struct amdgpu_allowed_register_entry {
1768 uint32_t reg_offset;
1769 bool untouched;
1770 bool grbm_indexed;
1771 };
1772
1773 struct amdgpu_cu_info {
1774 uint32_t number; /* total active CU number */
1775 uint32_t ao_cu_mask;
1776 uint32_t bitmap[4][4];
1777 };
1778
1779
1780 /*
1781 * ASIC specific functions.
1782 */
1783 struct amdgpu_asic_funcs {
1784 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1785 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1786 u32 sh_num, u32 reg_offset, u32 *value);
1787 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1788 int (*reset)(struct amdgpu_device *adev);
1789 /* wait for mc_idle */
1790 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1791 /* get the reference clock */
1792 u32 (*get_xclk)(struct amdgpu_device *adev);
1793 /* get the gpu clock counter */
1794 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1795 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1796 /* MM block clocks */
1797 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1798 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1799 };
1800
1801 /*
1802 * IOCTL.
1803 */
1804 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1805 struct drm_file *filp);
1806 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1807 struct drm_file *filp);
1808
1809 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1810 struct drm_file *filp);
1811 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1812 struct drm_file *filp);
1813 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1814 struct drm_file *filp);
1815 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1816 struct drm_file *filp);
1817 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1818 struct drm_file *filp);
1819 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1820 struct drm_file *filp);
1821 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1822 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1823
1824 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1825 struct drm_file *filp);
1826
1827 /* VRAM scratch page for HDP bug, default vram page */
1828 struct amdgpu_vram_scratch {
1829 struct amdgpu_bo *robj;
1830 volatile uint32_t *ptr;
1831 u64 gpu_addr;
1832 };
1833
1834 /*
1835 * ACPI
1836 */
1837 struct amdgpu_atif_notification_cfg {
1838 bool enabled;
1839 int command_code;
1840 };
1841
1842 struct amdgpu_atif_notifications {
1843 bool display_switch;
1844 bool expansion_mode_change;
1845 bool thermal_state;
1846 bool forced_power_state;
1847 bool system_power_state;
1848 bool display_conf_change;
1849 bool px_gfx_switch;
1850 bool brightness_change;
1851 bool dgpu_display_event;
1852 };
1853
1854 struct amdgpu_atif_functions {
1855 bool system_params;
1856 bool sbios_requests;
1857 bool select_active_disp;
1858 bool lid_state;
1859 bool get_tv_standard;
1860 bool set_tv_standard;
1861 bool get_panel_expansion_mode;
1862 bool set_panel_expansion_mode;
1863 bool temperature_change;
1864 bool graphics_device_types;
1865 };
1866
1867 struct amdgpu_atif {
1868 struct amdgpu_atif_notifications notifications;
1869 struct amdgpu_atif_functions functions;
1870 struct amdgpu_atif_notification_cfg notification_cfg;
1871 struct amdgpu_encoder *encoder_for_bl;
1872 };
1873
1874 struct amdgpu_atcs_functions {
1875 bool get_ext_state;
1876 bool pcie_perf_req;
1877 bool pcie_dev_rdy;
1878 bool pcie_bus_width;
1879 };
1880
1881 struct amdgpu_atcs {
1882 struct amdgpu_atcs_functions functions;
1883 };
1884
1885 /*
1886 * CGS
1887 */
1888 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1889 void amdgpu_cgs_destroy_device(void *cgs_device);
1890
1891
1892 /*
1893 * Core structure, functions and helpers.
1894 */
1895 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1896 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1897
1898 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1899 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1900
1901 struct amdgpu_ip_block_status {
1902 bool valid;
1903 bool sw;
1904 bool hw;
1905 };
1906
1907 struct amdgpu_device {
1908 struct device *dev;
1909 struct drm_device *ddev;
1910 struct pci_dev *pdev;
1911
1912 /* ASIC */
1913 enum amd_asic_type asic_type;
1914 uint32_t family;
1915 uint32_t rev_id;
1916 uint32_t external_rev_id;
1917 unsigned long flags;
1918 int usec_timeout;
1919 const struct amdgpu_asic_funcs *asic_funcs;
1920 bool shutdown;
1921 bool suspend;
1922 bool need_dma32;
1923 bool accel_working;
1924 struct work_struct reset_work;
1925 struct notifier_block acpi_nb;
1926 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1927 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1928 unsigned debugfs_count;
1929 #if defined(CONFIG_DEBUG_FS)
1930 struct dentry *debugfs_regs;
1931 #endif
1932 struct amdgpu_atif atif;
1933 struct amdgpu_atcs atcs;
1934 struct mutex srbm_mutex;
1935 /* GRBM index mutex. Protects concurrent access to GRBM index */
1936 struct mutex grbm_idx_mutex;
1937 struct dev_pm_domain vga_pm_domain;
1938 bool have_disp_power_ref;
1939
1940 /* BIOS */
1941 uint8_t *bios;
1942 bool is_atom_bios;
1943 uint16_t bios_header_start;
1944 struct amdgpu_bo *stollen_vga_memory;
1945 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1946
1947 /* Register/doorbell mmio */
1948 resource_size_t rmmio_base;
1949 resource_size_t rmmio_size;
1950 void __iomem *rmmio;
1951 /* protects concurrent MM_INDEX/DATA based register access */
1952 spinlock_t mmio_idx_lock;
1953 /* protects concurrent SMC based register access */
1954 spinlock_t smc_idx_lock;
1955 amdgpu_rreg_t smc_rreg;
1956 amdgpu_wreg_t smc_wreg;
1957 /* protects concurrent PCIE register access */
1958 spinlock_t pcie_idx_lock;
1959 amdgpu_rreg_t pcie_rreg;
1960 amdgpu_wreg_t pcie_wreg;
1961 /* protects concurrent UVD register access */
1962 spinlock_t uvd_ctx_idx_lock;
1963 amdgpu_rreg_t uvd_ctx_rreg;
1964 amdgpu_wreg_t uvd_ctx_wreg;
1965 /* protects concurrent DIDT register access */
1966 spinlock_t didt_idx_lock;
1967 amdgpu_rreg_t didt_rreg;
1968 amdgpu_wreg_t didt_wreg;
1969 /* protects concurrent ENDPOINT (audio) register access */
1970 spinlock_t audio_endpt_idx_lock;
1971 amdgpu_block_rreg_t audio_endpt_rreg;
1972 amdgpu_block_wreg_t audio_endpt_wreg;
1973 void __iomem *rio_mem;
1974 resource_size_t rio_mem_size;
1975 struct amdgpu_doorbell doorbell;
1976
1977 /* clock/pll info */
1978 struct amdgpu_clock clock;
1979
1980 /* MC */
1981 struct amdgpu_mc mc;
1982 struct amdgpu_gart gart;
1983 struct amdgpu_dummy_page dummy_page;
1984 struct amdgpu_vm_manager vm_manager;
1985
1986 /* memory management */
1987 struct amdgpu_mman mman;
1988 struct amdgpu_gem gem;
1989 struct amdgpu_vram_scratch vram_scratch;
1990 struct amdgpu_wb wb;
1991 atomic64_t vram_usage;
1992 atomic64_t vram_vis_usage;
1993 atomic64_t gtt_usage;
1994 atomic64_t num_bytes_moved;
1995 atomic_t gpu_reset_counter;
1996
1997 /* display */
1998 struct amdgpu_mode_info mode_info;
1999 struct work_struct hotplug_work;
2000 struct amdgpu_irq_src crtc_irq;
2001 struct amdgpu_irq_src pageflip_irq;
2002 struct amdgpu_irq_src hpd_irq;
2003
2004 /* rings */
2005 unsigned fence_context;
2006 struct mutex ring_lock;
2007 unsigned num_rings;
2008 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2009 bool ib_pool_ready;
2010 struct amdgpu_sa_manager ring_tmp_bo;
2011
2012 /* interrupts */
2013 struct amdgpu_irq irq;
2014
2015 /* dpm */
2016 struct amdgpu_pm pm;
2017 u32 cg_flags;
2018 u32 pg_flags;
2019
2020 /* amdgpu smumgr */
2021 struct amdgpu_smumgr smu;
2022
2023 /* gfx */
2024 struct amdgpu_gfx gfx;
2025
2026 /* sdma */
2027 struct amdgpu_sdma sdma;
2028
2029 /* uvd */
2030 bool has_uvd;
2031 struct amdgpu_uvd uvd;
2032
2033 /* vce */
2034 struct amdgpu_vce vce;
2035
2036 /* firmwares */
2037 struct amdgpu_firmware firmware;
2038
2039 /* GDS */
2040 struct amdgpu_gds gds;
2041
2042 const struct amdgpu_ip_block_version *ip_blocks;
2043 int num_ip_blocks;
2044 struct amdgpu_ip_block_status *ip_block_status;
2045 struct mutex mn_lock;
2046 DECLARE_HASHTABLE(mn_hash, 7);
2047
2048 /* tracking pinned memory */
2049 u64 vram_pin_size;
2050 u64 gart_pin_size;
2051
2052 /* amdkfd interface */
2053 struct kfd_dev *kfd;
2054
2055 /* kernel conext for IB submission */
2056 struct amdgpu_ctx kernel_ctx;
2057 };
2058
2059 bool amdgpu_device_is_px(struct drm_device *dev);
2060 int amdgpu_device_init(struct amdgpu_device *adev,
2061 struct drm_device *ddev,
2062 struct pci_dev *pdev,
2063 uint32_t flags);
2064 void amdgpu_device_fini(struct amdgpu_device *adev);
2065 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2066
2067 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2068 bool always_indirect);
2069 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2070 bool always_indirect);
2071 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2072 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2073
2074 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2075 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2076
2077 /*
2078 * Cast helper
2079 */
2080 extern const struct fence_ops amdgpu_fence_ops;
2081 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2082 {
2083 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2084
2085 if (__f->base.ops == &amdgpu_fence_ops)
2086 return __f;
2087
2088 return NULL;
2089 }
2090
2091 /*
2092 * Registers read & write functions.
2093 */
2094 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2095 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2096 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2097 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2098 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2099 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2100 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2101 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2102 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2103 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2104 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2105 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2106 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2107 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2108 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2109 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2110 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2111 #define WREG32_P(reg, val, mask) \
2112 do { \
2113 uint32_t tmp_ = RREG32(reg); \
2114 tmp_ &= (mask); \
2115 tmp_ |= ((val) & ~(mask)); \
2116 WREG32(reg, tmp_); \
2117 } while (0)
2118 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2119 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2120 #define WREG32_PLL_P(reg, val, mask) \
2121 do { \
2122 uint32_t tmp_ = RREG32_PLL(reg); \
2123 tmp_ &= (mask); \
2124 tmp_ |= ((val) & ~(mask)); \
2125 WREG32_PLL(reg, tmp_); \
2126 } while (0)
2127 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2128 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2129 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2130
2131 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2132 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2133
2134 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2135 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2136
2137 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2138 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2139 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2140
2141 #define REG_GET_FIELD(value, reg, field) \
2142 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2143
2144 /*
2145 * BIOS helpers.
2146 */
2147 #define RBIOS8(i) (adev->bios[i])
2148 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2149 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2150
2151 /*
2152 * RING helpers.
2153 */
2154 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2155 {
2156 if (ring->count_dw <= 0)
2157 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2158 ring->ring[ring->wptr++] = v;
2159 ring->wptr &= ring->ptr_mask;
2160 ring->count_dw--;
2161 ring->ring_free_dw--;
2162 }
2163
2164 static inline struct amdgpu_sdma_instance *
2165 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2166 {
2167 struct amdgpu_device *adev = ring->adev;
2168 int i;
2169
2170 for (i = 0; i < adev->sdma.num_instances; i++)
2171 if (&adev->sdma.instance[i].ring == ring)
2172 break;
2173
2174 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2175 return &adev->sdma.instance[i];
2176 else
2177 return NULL;
2178 }
2179
2180 /*
2181 * ASICs macro.
2182 */
2183 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2184 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2185 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2186 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2187 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2188 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2189 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2190 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2191 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2192 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2193 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2194 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2195 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2196 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2197 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2198 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2199 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2200 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2201 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2202 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2203 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2204 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2205 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2206 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2207 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2208 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2209 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2210 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2211 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2212 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2213 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2214 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2215 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2216 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2217 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2218 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2219 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2220 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2221 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2222 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2223 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2224 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2225 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2226 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2227 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2228 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2229 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2230 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2231 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2232 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2233 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2234 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2235 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2236 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2237 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2238 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2239 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2240 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2241 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2242 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2243 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2244 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2245 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2246 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2247 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2248 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2249 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2250
2251 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2252
2253 /* Common functions */
2254 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2255 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2256 bool amdgpu_card_posted(struct amdgpu_device *adev);
2257 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2258 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2259
2260 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2261 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2262 u32 ip_instance, u32 ring,
2263 struct amdgpu_ring **out_ring);
2264 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2265 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2266 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2267 uint32_t flags);
2268 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2269 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2270 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2271 struct ttm_mem_reg *mem);
2272 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2273 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2274 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2275 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2276 const u32 *registers,
2277 const u32 array_size);
2278
2279 bool amdgpu_device_is_px(struct drm_device *dev);
2280 /* atpx handler */
2281 #if defined(CONFIG_VGA_SWITCHEROO)
2282 void amdgpu_register_atpx_handler(void);
2283 void amdgpu_unregister_atpx_handler(void);
2284 #else
2285 static inline void amdgpu_register_atpx_handler(void) {}
2286 static inline void amdgpu_unregister_atpx_handler(void) {}
2287 #endif
2288
2289 /*
2290 * KMS
2291 */
2292 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2293 extern int amdgpu_max_kms_ioctl;
2294
2295 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2296 int amdgpu_driver_unload_kms(struct drm_device *dev);
2297 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2298 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2299 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2300 struct drm_file *file_priv);
2301 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2302 struct drm_file *file_priv);
2303 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2304 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2305 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2306 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2307 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2308 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2309 int *max_error,
2310 struct timeval *vblank_time,
2311 unsigned flags);
2312 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2313 unsigned long arg);
2314
2315 /*
2316 * vm
2317 */
2318 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2319 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2320 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2321 struct amdgpu_vm *vm,
2322 struct list_head *head);
2323 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
2324 struct amdgpu_sync *sync);
2325 void amdgpu_vm_flush(struct amdgpu_ring *ring,
2326 struct amdgpu_vm *vm,
2327 struct fence *updates);
2328 void amdgpu_vm_fence(struct amdgpu_device *adev,
2329 struct amdgpu_vm *vm,
2330 struct fence *fence);
2331 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2332 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2333 struct amdgpu_vm *vm);
2334 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2335 struct amdgpu_vm *vm);
2336 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
2337 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
2338 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2339 struct amdgpu_bo_va *bo_va,
2340 struct ttm_mem_reg *mem);
2341 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2342 struct amdgpu_bo *bo);
2343 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2344 struct amdgpu_bo *bo);
2345 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2346 struct amdgpu_vm *vm,
2347 struct amdgpu_bo *bo);
2348 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2349 struct amdgpu_bo_va *bo_va,
2350 uint64_t addr, uint64_t offset,
2351 uint64_t size, uint32_t flags);
2352 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2353 struct amdgpu_bo_va *bo_va,
2354 uint64_t addr);
2355 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2356 struct amdgpu_bo_va *bo_va);
2357 int amdgpu_vm_free_job(struct amdgpu_job *job);
2358 /*
2359 * functions used by amdgpu_encoder.c
2360 */
2361 struct amdgpu_afmt_acr {
2362 u32 clock;
2363
2364 int n_32khz;
2365 int cts_32khz;
2366
2367 int n_44_1khz;
2368 int cts_44_1khz;
2369
2370 int n_48khz;
2371 int cts_48khz;
2372
2373 };
2374
2375 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2376
2377 /* amdgpu_acpi.c */
2378 #if defined(CONFIG_ACPI)
2379 int amdgpu_acpi_init(struct amdgpu_device *adev);
2380 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2381 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2382 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2383 u8 perf_req, bool advertise);
2384 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2385 #else
2386 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2387 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2388 #endif
2389
2390 struct amdgpu_bo_va_mapping *
2391 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2392 uint64_t addr, struct amdgpu_bo **bo);
2393
2394 #include "amdgpu_object.h"
2395
2396 #endif
Linux kernel - Deliverables
This page took 0.125914 seconds and 6 git commands to generate.