drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/pci.h>
  25 #include "amdgpu.h"
  26 #include "cgs_linux.h"
  27 #include "atom.h"
  28
  29 struct amdgpu_cgs_device {
  30         struct cgs_device base;
  31         struct amdgpu_device *adev;
  32 };
  33
  34 #define CGS_FUNC_ADEV                                                   \
  35         struct amdgpu_device *adev =                                    \
  36                 ((struct amdgpu_cgs_device *)cgs_device)->adev
  37
  38 static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
  39                                    uint64_t *mc_start, uint64_t *mc_size,
  40                                    uint64_t *mem_size)
  41 {
  42         return 0;
  43 }
  44
  45 static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem,
  46                                 uint64_t size,
  47                                 uint64_t min_offset, uint64_t max_offset,
  48                                 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
  49 {
  50         return 0;
  51 }
  52
  53 static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
  54 {
  55         return 0;
  56 }
  57
  58 static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
  59                                     enum cgs_gpu_mem_type type,
  60                                     uint64_t size, uint64_t align,
  61                                     uint64_t min_offset, uint64_t max_offset,
  62                                     cgs_handle_t *handle)
  63 {
  64         return 0;
  65 }
  66
  67 static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd,
  68                                      cgs_handle_t *handle)
  69 {
  70         /* TODO */
  71         return 0;
  72 }
  73
  74 static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
  75 {
  76         /* TODO */
  77         return 0;
  78 }
  79
  80 static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
  81                                    uint64_t *mcaddr)
  82 {
  83         /* TODO */
  84         return 0;
  85 }
  86
  87 static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
  88 {
  89         /* TODO */
  90         return 0;
  91 }
  92
  93 static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
  94                                    void **map)
  95 {
  96         /* TODO */
  97         return 0;
  98 }
  99
 100 static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
 101 {
 102         /* TODO */
 103         return 0;
 104 }
 105
 106 static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
 107 {
 108         CGS_FUNC_ADEV;
 109         return RREG32(offset);
 110 }
 111
 112 static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset,
 113                                       uint32_t value)
 114 {
 115         CGS_FUNC_ADEV;
 116         WREG32(offset, value);
 117 }
 118
 119 static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
 120                                              enum cgs_ind_reg space,
 121                                              unsigned index)
 122 {
 123         CGS_FUNC_ADEV;
 124         switch (space) {
 125         case CGS_IND_REG__MMIO:
 126                 return RREG32_IDX(index);
 127         case CGS_IND_REG__PCIE:
 128                 return RREG32_PCIE(index);
 129         case CGS_IND_REG__SMC:
 130                 return RREG32_SMC(index);
 131         case CGS_IND_REG__UVD_CTX:
 132                 return RREG32_UVD_CTX(index);
 133         case CGS_IND_REG__DIDT:
 134                 return RREG32_DIDT(index);
 135         case CGS_IND_REG__AUDIO_ENDPT:
 136                 DRM_ERROR("audio endpt register access not implemented.\n");
 137                 return 0;
 138         }
 139         WARN(1, "Invalid indirect register space");
 140         return 0;
 141 }
 142
 143 static void amdgpu_cgs_write_ind_register(void *cgs_device,
 144                                           enum cgs_ind_reg space,
 145                                           unsigned index, uint32_t value)
 146 {
 147         CGS_FUNC_ADEV;
 148         switch (space) {
 149         case CGS_IND_REG__MMIO:
 150                 return WREG32_IDX(index, value);
 151         case CGS_IND_REG__PCIE:
 152                 return WREG32_PCIE(index, value);
 153         case CGS_IND_REG__SMC:
 154                 return WREG32_SMC(index, value);
 155         case CGS_IND_REG__UVD_CTX:
 156                 return WREG32_UVD_CTX(index, value);
 157         case CGS_IND_REG__DIDT:
 158                 return WREG32_DIDT(index, value);
 159         case CGS_IND_REG__AUDIO_ENDPT:
 160                 DRM_ERROR("audio endpt register access not implemented.\n");
 161                 return;
 162         }
 163         WARN(1, "Invalid indirect register space");
 164 }
 165
 166 static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
 167 {
 168         CGS_FUNC_ADEV;
 169         uint8_t val;
 170         int ret = pci_read_config_byte(adev->pdev, addr, &val);
 171         if (WARN(ret, "pci_read_config_byte error"))
 172                 return 0;
 173         return val;
 174 }
 175
 176 static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
 177 {
 178         CGS_FUNC_ADEV;
 179         uint16_t val;
 180         int ret = pci_read_config_word(adev->pdev, addr, &val);
 181         if (WARN(ret, "pci_read_config_word error"))
 182                 return 0;
 183         return val;
 184 }
 185
 186 static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
 187                                                  unsigned addr)
 188 {
 189         CGS_FUNC_ADEV;
 190         uint32_t val;
 191         int ret = pci_read_config_dword(adev->pdev, addr, &val);
 192         if (WARN(ret, "pci_read_config_dword error"))
 193                 return 0;
 194         return val;
 195 }
 196
 197 static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
 198                                              uint8_t value)
 199 {
 200         CGS_FUNC_ADEV;
 201         int ret = pci_write_config_byte(adev->pdev, addr, value);
 202         WARN(ret, "pci_write_config_byte error");
 203 }
 204
 205 static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
 206                                              uint16_t value)
 207 {
 208         CGS_FUNC_ADEV;
 209         int ret = pci_write_config_word(adev->pdev, addr, value);
 210         WARN(ret, "pci_write_config_word error");
 211 }
 212
 213 static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
 214                                               uint32_t value)
 215 {
 216         CGS_FUNC_ADEV;
 217         int ret = pci_write_config_dword(adev->pdev, addr, value);
 218         WARN(ret, "pci_write_config_dword error");
 219 }
 220
 221 static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device,
 222                                                   unsigned table, uint16_t *size,
 223                                                   uint8_t *frev, uint8_t *crev)
 224 {
 225         CGS_FUNC_ADEV;
 226         uint16_t data_start;
 227
 228         if (amdgpu_atom_parse_data_header(
 229                     adev->mode_info.atom_context, table, size,
 230                     frev, crev, &data_start))
 231                 return (uint8_t*)adev->mode_info.atom_context->bios +
 232                         data_start;
 233
 234         return NULL;
 235 }
 236
 237 static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
 238                                               uint8_t *frev, uint8_t *crev)
 239 {
 240         CGS_FUNC_ADEV;
 241
 242         if (amdgpu_atom_parse_cmd_header(
 243                     adev->mode_info.atom_context, table,
 244                     frev, crev))
 245                 return 0;
 246
 247         return -EINVAL;
 248 }
 249
 250 static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
 251                                           void *args)
 252 {
 253         CGS_FUNC_ADEV;
 254
 255         return amdgpu_atom_execute_table(
 256                 adev->mode_info.atom_context, table, args);
 257 }
 258
 259 static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request)
 260 {
 261         /* TODO */
 262         return 0;
 263 }
 264
 265 static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request)
 266 {
 267         /* TODO */
 268         return 0;
 269 }
 270
 271 static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request,
 272                                      int active)
 273 {
 274         /* TODO */
 275         return 0;
 276 }
 277
 278 static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request,
 279                                        enum cgs_clock clock, unsigned freq)
 280 {
 281         /* TODO */
 282         return 0;
 283 }
 284
 285 static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
 286                                         enum cgs_engine engine, int powered)
 287 {
 288         /* TODO */
 289         return 0;
 290 }
 291
 292
 293
 294 static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
 295                                             enum cgs_clock clock,
 296                                             struct cgs_clock_limits *limits)
 297 {
 298         /* TODO */
 299         return 0;
 300 }
 301
 302 static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
 303                                           const uint32_t *voltages)
 304 {
 305         DRM_ERROR("not implemented");
 306         return -EPERM;
 307 }
 308
 309 struct cgs_irq_params {
 310         unsigned src_id;
 311         cgs_irq_source_set_func_t set;
 312         cgs_irq_handler_func_t handler;
 313         void *private_data;
 314 };
 315
 316 static int cgs_set_irq_state(struct amdgpu_device *adev,
 317                              struct amdgpu_irq_src *src,
 318                              unsigned type,
 319                              enum amdgpu_interrupt_state state)
 320 {
 321         struct cgs_irq_params *irq_params =
 322                 (struct cgs_irq_params *)src->data;
 323         if (!irq_params)
 324                 return -EINVAL;
 325         if (!irq_params->set)
 326                 return -EINVAL;
 327         return irq_params->set(irq_params->private_data,
 328                                irq_params->src_id,
 329                                type,
 330                                (int)state);
 331 }
 332
 333 static int cgs_process_irq(struct amdgpu_device *adev,
 334                            struct amdgpu_irq_src *source,
 335                            struct amdgpu_iv_entry *entry)
 336 {
 337         struct cgs_irq_params *irq_params =
 338                 (struct cgs_irq_params *)source->data;
 339         if (!irq_params)
 340                 return -EINVAL;
 341         if (!irq_params->handler)
 342                 return -EINVAL;
 343         return irq_params->handler(irq_params->private_data,
 344                                    irq_params->src_id,
 345                                    entry->iv_entry);
 346 }
 347
 348 static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
 349         .set = cgs_set_irq_state,
 350         .process = cgs_process_irq,
 351 };
 352
 353 static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
 354                                      unsigned num_types,
 355                                      cgs_irq_source_set_func_t set,
 356                                      cgs_irq_handler_func_t handler,
 357                                      void *private_data)
 358 {
 359         CGS_FUNC_ADEV;
 360         int ret = 0;
 361         struct cgs_irq_params *irq_params;
 362         struct amdgpu_irq_src *source =
 363                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
 364         if (!source)
 365                 return -ENOMEM;
 366         irq_params =
 367                 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
 368         if (!irq_params) {
 369                 kfree(source);
 370                 return -ENOMEM;
 371         }
 372         source->num_types = num_types;
 373         source->funcs = &cgs_irq_funcs;
 374         irq_params->src_id = src_id;
 375         irq_params->set = set;
 376         irq_params->handler = handler;
 377         irq_params->private_data = private_data;
 378         source->data = (void *)irq_params;
 379         ret = amdgpu_irq_add_id(adev, src_id, source);
 380         if (ret) {
 381                 kfree(irq_params);
 382                 kfree(source);
 383         }
 384
 385         return ret;
 386 }
 387
 388 static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
 389 {
 390         CGS_FUNC_ADEV;
 391         return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
 392 }
 393
 394 static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
 395 {
 396         CGS_FUNC_ADEV;
 397         return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
 398 }
 399
 400 static const struct cgs_ops amdgpu_cgs_ops = {
 401         amdgpu_cgs_gpu_mem_info,
 402         amdgpu_cgs_gmap_kmem,
 403         amdgpu_cgs_gunmap_kmem,
 404         amdgpu_cgs_alloc_gpu_mem,
 405         amdgpu_cgs_free_gpu_mem,
 406         amdgpu_cgs_gmap_gpu_mem,
 407         amdgpu_cgs_gunmap_gpu_mem,
 408         amdgpu_cgs_kmap_gpu_mem,
 409         amdgpu_cgs_kunmap_gpu_mem,
 410         amdgpu_cgs_read_register,
 411         amdgpu_cgs_write_register,
 412         amdgpu_cgs_read_ind_register,
 413         amdgpu_cgs_write_ind_register,
 414         amdgpu_cgs_read_pci_config_byte,
 415         amdgpu_cgs_read_pci_config_word,
 416         amdgpu_cgs_read_pci_config_dword,
 417         amdgpu_cgs_write_pci_config_byte,
 418         amdgpu_cgs_write_pci_config_word,
 419         amdgpu_cgs_write_pci_config_dword,
 420         amdgpu_cgs_atom_get_data_table,
 421         amdgpu_cgs_atom_get_cmd_table_revs,
 422         amdgpu_cgs_atom_exec_cmd_table,
 423         amdgpu_cgs_create_pm_request,
 424         amdgpu_cgs_destroy_pm_request,
 425         amdgpu_cgs_set_pm_request,
 426         amdgpu_cgs_pm_request_clock,
 427         amdgpu_cgs_pm_request_engine,
 428         amdgpu_cgs_pm_query_clock_limits,
 429         amdgpu_cgs_set_camera_voltages
 430 };
 431
 432 static const struct cgs_os_ops amdgpu_cgs_os_ops = {
 433         amdgpu_cgs_import_gpu_mem,
 434         amdgpu_cgs_add_irq_source,
 435         amdgpu_cgs_irq_get,
 436         amdgpu_cgs_irq_put
 437 };
 438
 439 void *amdgpu_cgs_create_device(struct amdgpu_device *adev)
 440 {
 441         struct amdgpu_cgs_device *cgs_device =
 442                 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
 443
 444         if (!cgs_device) {
 445                 DRM_ERROR("Couldn't allocate CGS device structure\n");
 446                 return NULL;
 447         }
 448
 449         cgs_device->base.ops = &amdgpu_cgs_ops;
 450         cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
 451         cgs_device->adev = adev;
 452
 453         return cgs_device;
 454 }
 455
 456 void amdgpu_cgs_destroy_device(void *cgs_device)
 457 {
 458         kfree(cgs_device);
 459 }