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233ac9c64eb3abaa28f8a1fde51e1fb78de81e2f
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cs.c
1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27 #include <linux/list_sort.h>
28 #include <drm/drmP.h>
29 #include <drm/amdgpu_drm.h>
30 #include "amdgpu.h"
31 #include "amdgpu_trace.h"
32
33 #define AMDGPU_CS_MAX_PRIORITY 32u
34 #define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1)
35
36 /* This is based on the bucket sort with O(n) time complexity.
37 * An item with priority "i" is added to bucket[i]. The lists are then
38 * concatenated in descending order.
39 */
40 struct amdgpu_cs_buckets {
41 struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
42 };
43
44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
45 {
46 unsigned i;
47
48 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
49 INIT_LIST_HEAD(&b->bucket[i]);
50 }
51
52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
53 struct list_head *item, unsigned priority)
54 {
55 /* Since buffers which appear sooner in the relocation list are
56 * likely to be used more often than buffers which appear later
57 * in the list, the sort mustn't change the ordering of buffers
58 * with the same priority, i.e. it must be stable.
59 */
60 list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
61 }
62
63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
64 struct list_head *out_list)
65 {
66 unsigned i;
67
68 /* Connect the sorted buckets in the output list. */
69 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
70 list_splice(&b->bucket[i], out_list);
71 }
72 }
73
74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
75 u32 ip_instance, u32 ring,
76 struct amdgpu_ring **out_ring)
77 {
78 /* Right now all IPs have only one instance - multiple rings. */
79 if (ip_instance != 0) {
80 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
81 return -EINVAL;
82 }
83
84 switch (ip_type) {
85 default:
86 DRM_ERROR("unknown ip type: %d\n", ip_type);
87 return -EINVAL;
88 case AMDGPU_HW_IP_GFX:
89 if (ring < adev->gfx.num_gfx_rings) {
90 *out_ring = &adev->gfx.gfx_ring[ring];
91 } else {
92 DRM_ERROR("only %d gfx rings are supported now\n",
93 adev->gfx.num_gfx_rings);
94 return -EINVAL;
95 }
96 break;
97 case AMDGPU_HW_IP_COMPUTE:
98 if (ring < adev->gfx.num_compute_rings) {
99 *out_ring = &adev->gfx.compute_ring[ring];
100 } else {
101 DRM_ERROR("only %d compute rings are supported now\n",
102 adev->gfx.num_compute_rings);
103 return -EINVAL;
104 }
105 break;
106 case AMDGPU_HW_IP_DMA:
107 if (ring < adev->sdma.num_instances) {
108 *out_ring = &adev->sdma.instance[ring].ring;
109 } else {
110 DRM_ERROR("only %d SDMA rings are supported\n",
111 adev->sdma.num_instances);
112 return -EINVAL;
113 }
114 break;
115 case AMDGPU_HW_IP_UVD:
116 *out_ring = &adev->uvd.ring;
117 break;
118 case AMDGPU_HW_IP_VCE:
119 if (ring < 2){
120 *out_ring = &adev->vce.ring[ring];
121 } else {
122 DRM_ERROR("only two VCE rings are supported\n");
123 return -EINVAL;
124 }
125 break;
126 }
127 return 0;
128 }
129
130 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
131 struct drm_file *filp,
132 struct amdgpu_ctx *ctx,
133 struct amdgpu_ib *ibs,
134 uint32_t num_ibs)
135 {
136 struct amdgpu_cs_parser *parser;
137 int i;
138
139 parser = kzalloc(sizeof(struct amdgpu_cs_parser), GFP_KERNEL);
140 if (!parser)
141 return NULL;
142
143 parser->adev = adev;
144 parser->filp = filp;
145 parser->ctx = ctx;
146 parser->ibs = ibs;
147 parser->num_ibs = num_ibs;
148 for (i = 0; i < num_ibs; i++)
149 ibs[i].ctx = ctx;
150
151 return parser;
152 }
153
154 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
155 {
156 union drm_amdgpu_cs *cs = data;
157 uint64_t *chunk_array_user;
158 uint64_t *chunk_array;
159 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
160 unsigned size, i;
161 int ret;
162
163 if (cs->in.num_chunks == 0)
164 return 0;
165
166 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
167 if (!chunk_array)
168 return -ENOMEM;
169
170 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
171 if (!p->ctx) {
172 ret = -EINVAL;
173 goto free_chunk;
174 }
175
176 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
177
178 /* get chunks */
179 INIT_LIST_HEAD(&p->validated);
180 chunk_array_user = (uint64_t __user *)(cs->in.chunks);
181 if (copy_from_user(chunk_array, chunk_array_user,
182 sizeof(uint64_t)*cs->in.num_chunks)) {
183 ret = -EFAULT;
184 goto put_bo_list;
185 }
186
187 p->nchunks = cs->in.num_chunks;
188 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
189 GFP_KERNEL);
190 if (!p->chunks) {
191 ret = -ENOMEM;
192 goto put_bo_list;
193 }
194
195 for (i = 0; i < p->nchunks; i++) {
196 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
197 struct drm_amdgpu_cs_chunk user_chunk;
198 uint32_t __user *cdata;
199
200 chunk_ptr = (void __user *)chunk_array[i];
201 if (copy_from_user(&user_chunk, chunk_ptr,
202 sizeof(struct drm_amdgpu_cs_chunk))) {
203 ret = -EFAULT;
204 i--;
205 goto free_partial_kdata;
206 }
207 p->chunks[i].chunk_id = user_chunk.chunk_id;
208 p->chunks[i].length_dw = user_chunk.length_dw;
209
210 size = p->chunks[i].length_dw;
211 cdata = (void __user *)user_chunk.chunk_data;
212 p->chunks[i].user_ptr = cdata;
213
214 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
215 if (p->chunks[i].kdata == NULL) {
216 ret = -ENOMEM;
217 i--;
218 goto free_partial_kdata;
219 }
220 size *= sizeof(uint32_t);
221 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
222 ret = -EFAULT;
223 goto free_partial_kdata;
224 }
225
226 switch (p->chunks[i].chunk_id) {
227 case AMDGPU_CHUNK_ID_IB:
228 p->num_ibs++;
229 break;
230
231 case AMDGPU_CHUNK_ID_FENCE:
232 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
233 if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
234 uint32_t handle;
235 struct drm_gem_object *gobj;
236 struct drm_amdgpu_cs_chunk_fence *fence_data;
237
238 fence_data = (void *)p->chunks[i].kdata;
239 handle = fence_data->handle;
240 gobj = drm_gem_object_lookup(p->adev->ddev,
241 p->filp, handle);
242 if (gobj == NULL) {
243 ret = -EINVAL;
244 goto free_partial_kdata;
245 }
246
247 p->uf.bo = gem_to_amdgpu_bo(gobj);
248 p->uf.offset = fence_data->offset;
249 } else {
250 ret = -EINVAL;
251 goto free_partial_kdata;
252 }
253 break;
254
255 case AMDGPU_CHUNK_ID_DEPENDENCIES:
256 break;
257
258 default:
259 ret = -EINVAL;
260 goto free_partial_kdata;
261 }
262 }
263
264
265 p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
266 if (!p->ibs) {
267 ret = -ENOMEM;
268 goto free_all_kdata;
269 }
270
271 kfree(chunk_array);
272 return 0;
273
274 free_all_kdata:
275 i = p->nchunks - 1;
276 free_partial_kdata:
277 for (; i >= 0; i--)
278 drm_free_large(p->chunks[i].kdata);
279 kfree(p->chunks);
280 put_bo_list:
281 if (p->bo_list)
282 amdgpu_bo_list_put(p->bo_list);
283 amdgpu_ctx_put(p->ctx);
284 free_chunk:
285 kfree(chunk_array);
286
287 return ret;
288 }
289
290 /* Returns how many bytes TTM can move per IB.
291 */
292 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
293 {
294 u64 real_vram_size = adev->mc.real_vram_size;
295 u64 vram_usage = atomic64_read(&adev->vram_usage);
296
297 /* This function is based on the current VRAM usage.
298 *
299 * - If all of VRAM is free, allow relocating the number of bytes that
300 * is equal to 1/4 of the size of VRAM for this IB.
301
302 * - If more than one half of VRAM is occupied, only allow relocating
303 * 1 MB of data for this IB.
304 *
305 * - From 0 to one half of used VRAM, the threshold decreases
306 * linearly.
307 * __________________
308 * 1/4 of -|\ |
309 * VRAM | \ |
310 * | \ |
311 * | \ |
312 * | \ |
313 * | \ |
314 * | \ |
315 * | \________|1 MB
316 * |----------------|
317 * VRAM 0 % 100 %
318 * used used
319 *
320 * Note: It's a threshold, not a limit. The threshold must be crossed
321 * for buffer relocations to stop, so any buffer of an arbitrary size
322 * can be moved as long as the threshold isn't crossed before
323 * the relocation takes place. We don't want to disable buffer
324 * relocations completely.
325 *
326 * The idea is that buffers should be placed in VRAM at creation time
327 * and TTM should only do a minimum number of relocations during
328 * command submission. In practice, you need to submit at least
329 * a dozen IBs to move all buffers to VRAM if they are in GTT.
330 *
331 * Also, things can get pretty crazy under memory pressure and actual
332 * VRAM usage can change a lot, so playing safe even at 50% does
333 * consistently increase performance.
334 */
335
336 u64 half_vram = real_vram_size >> 1;
337 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
338 u64 bytes_moved_threshold = half_free_vram >> 1;
339 return max(bytes_moved_threshold, 1024*1024ull);
340 }
341
342 int amdgpu_cs_list_validate(struct amdgpu_device *adev,
343 struct amdgpu_vm *vm,
344 struct list_head *validated)
345 {
346 struct amdgpu_bo_list_entry *lobj;
347 struct amdgpu_bo *bo;
348 u64 bytes_moved = 0, initial_bytes_moved;
349 u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
350 int r;
351
352 list_for_each_entry(lobj, validated, tv.head) {
353 bo = lobj->robj;
354 if (!bo->pin_count) {
355 u32 domain = lobj->prefered_domains;
356 u32 current_domain =
357 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
358
359 /* Check if this buffer will be moved and don't move it
360 * if we have moved too many buffers for this IB already.
361 *
362 * Note that this allows moving at least one buffer of
363 * any size, because it doesn't take the current "bo"
364 * into account. We don't want to disallow buffer moves
365 * completely.
366 */
367 if ((lobj->allowed_domains & current_domain) != 0 &&
368 (domain & current_domain) == 0 && /* will be moved */
369 bytes_moved > bytes_moved_threshold) {
370 /* don't move it */
371 domain = current_domain;
372 }
373
374 retry:
375 amdgpu_ttm_placement_from_domain(bo, domain);
376 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
377 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
378 bytes_moved += atomic64_read(&adev->num_bytes_moved) -
379 initial_bytes_moved;
380
381 if (unlikely(r)) {
382 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
383 domain = lobj->allowed_domains;
384 goto retry;
385 }
386 return r;
387 }
388 }
389 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
390 }
391 return 0;
392 }
393
394 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
395 {
396 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
397 struct amdgpu_cs_buckets buckets;
398 struct list_head duplicates;
399 bool need_mmap_lock = false;
400 int i, r;
401
402 if (p->bo_list) {
403 need_mmap_lock = p->bo_list->has_userptr;
404 amdgpu_cs_buckets_init(&buckets);
405 for (i = 0; i < p->bo_list->num_entries; i++)
406 amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
407 p->bo_list->array[i].priority);
408
409 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
410 }
411
412 p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
413 &p->validated);
414
415 if (need_mmap_lock)
416 down_read(&current->mm->mmap_sem);
417
418 INIT_LIST_HEAD(&duplicates);
419 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
420 if (unlikely(r != 0))
421 goto error_reserve;
422
423 r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
424 if (r)
425 goto error_validate;
426
427 r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates);
428
429 error_validate:
430 if (r)
431 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
432
433 error_reserve:
434 if (need_mmap_lock)
435 up_read(&current->mm->mmap_sem);
436
437 return r;
438 }
439
440 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
441 {
442 struct amdgpu_bo_list_entry *e;
443 int r;
444
445 list_for_each_entry(e, &p->validated, tv.head) {
446 struct reservation_object *resv = e->robj->tbo.resv;
447 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
448
449 if (r)
450 return r;
451 }
452 return 0;
453 }
454
455 static int cmp_size_smaller_first(void *priv, struct list_head *a,
456 struct list_head *b)
457 {
458 struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
459 struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
460
461 /* Sort A before B if A is smaller. */
462 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
463 }
464
465 static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff)
466 {
467 if (!error) {
468 /* Sort the buffer list from the smallest to largest buffer,
469 * which affects the order of buffers in the LRU list.
470 * This assures that the smallest buffers are added first
471 * to the LRU list, so they are likely to be later evicted
472 * first, instead of large buffers whose eviction is more
473 * expensive.
474 *
475 * This slightly lowers the number of bytes moved by TTM
476 * per frame under memory pressure.
477 */
478 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
479
480 ttm_eu_fence_buffer_objects(&parser->ticket,
481 &parser->validated,
482 &parser->ibs[parser->num_ibs-1].fence->base);
483 } else if (backoff) {
484 ttm_eu_backoff_reservation(&parser->ticket,
485 &parser->validated);
486 }
487 }
488
489 static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser)
490 {
491 unsigned i;
492 if (parser->ctx)
493 amdgpu_ctx_put(parser->ctx);
494 if (parser->bo_list)
495 amdgpu_bo_list_put(parser->bo_list);
496
497 drm_free_large(parser->vm_bos);
498 for (i = 0; i < parser->nchunks; i++)
499 drm_free_large(parser->chunks[i].kdata);
500 kfree(parser->chunks);
501 if (!amdgpu_enable_scheduler)
502 {
503 if (parser->ibs)
504 for (i = 0; i < parser->num_ibs; i++)
505 amdgpu_ib_free(parser->adev, &parser->ibs[i]);
506 kfree(parser->ibs);
507 if (parser->uf.bo)
508 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
509 }
510
511 kfree(parser);
512 }
513
514 /**
515 * cs_parser_fini() - clean parser states
516 * @parser: parser structure holding parsing context.
517 * @error: error number
518 *
519 * If error is set than unvalidate buffer, otherwise just free memory
520 * used by parsing context.
521 **/
522 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
523 {
524 amdgpu_cs_parser_fini_early(parser, error, backoff);
525 amdgpu_cs_parser_fini_late(parser);
526 }
527
528 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
529 struct amdgpu_vm *vm)
530 {
531 struct amdgpu_device *adev = p->adev;
532 struct amdgpu_bo_va *bo_va;
533 struct amdgpu_bo *bo;
534 int i, r;
535
536 r = amdgpu_vm_update_page_directory(adev, vm);
537 if (r)
538 return r;
539
540 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence);
541 if (r)
542 return r;
543
544 r = amdgpu_vm_clear_freed(adev, vm);
545 if (r)
546 return r;
547
548 if (p->bo_list) {
549 for (i = 0; i < p->bo_list->num_entries; i++) {
550 struct fence *f;
551
552 /* ignore duplicates */
553 bo = p->bo_list->array[i].robj;
554 if (!bo)
555 continue;
556
557 bo_va = p->bo_list->array[i].bo_va;
558 if (bo_va == NULL)
559 continue;
560
561 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
562 if (r)
563 return r;
564
565 f = bo_va->last_pt_update;
566 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
567 if (r)
568 return r;
569 }
570
571 }
572
573 r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
574
575 if (amdgpu_vm_debug && p->bo_list) {
576 /* Invalidate all BOs to test for userspace bugs */
577 for (i = 0; i < p->bo_list->num_entries; i++) {
578 /* ignore duplicates */
579 bo = p->bo_list->array[i].robj;
580 if (!bo)
581 continue;
582
583 amdgpu_vm_bo_invalidate(adev, bo);
584 }
585 }
586
587 return r;
588 }
589
590 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
591 struct amdgpu_cs_parser *parser)
592 {
593 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
594 struct amdgpu_vm *vm = &fpriv->vm;
595 struct amdgpu_ring *ring;
596 int i, r;
597
598 if (parser->num_ibs == 0)
599 return 0;
600
601 /* Only for UVD/VCE VM emulation */
602 for (i = 0; i < parser->num_ibs; i++) {
603 ring = parser->ibs[i].ring;
604 if (ring->funcs->parse_cs) {
605 r = amdgpu_ring_parse_cs(ring, parser, i);
606 if (r)
607 return r;
608 }
609 }
610
611 r = amdgpu_bo_vm_update_pte(parser, vm);
612 if (r) {
613 goto out;
614 }
615 amdgpu_cs_sync_rings(parser);
616 if (!amdgpu_enable_scheduler)
617 r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
618 parser->filp);
619
620 out:
621 return r;
622 }
623
624 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
625 {
626 if (r == -EDEADLK) {
627 r = amdgpu_gpu_reset(adev);
628 if (!r)
629 r = -EAGAIN;
630 }
631 return r;
632 }
633
634 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
635 struct amdgpu_cs_parser *parser)
636 {
637 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
638 struct amdgpu_vm *vm = &fpriv->vm;
639 int i, j;
640 int r;
641
642 for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
643 struct amdgpu_cs_chunk *chunk;
644 struct amdgpu_ib *ib;
645 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
646 struct amdgpu_ring *ring;
647
648 chunk = &parser->chunks[i];
649 ib = &parser->ibs[j];
650 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
651
652 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
653 continue;
654
655 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
656 chunk_ib->ip_instance, chunk_ib->ring,
657 &ring);
658 if (r)
659 return r;
660
661 if (ring->funcs->parse_cs) {
662 struct amdgpu_bo_va_mapping *m;
663 struct amdgpu_bo *aobj = NULL;
664 uint64_t offset;
665 uint8_t *kptr;
666
667 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
668 &aobj);
669 if (!aobj) {
670 DRM_ERROR("IB va_start is invalid\n");
671 return -EINVAL;
672 }
673
674 if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
675 (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
676 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
677 return -EINVAL;
678 }
679
680 /* the IB should be reserved at this point */
681 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
682 if (r) {
683 return r;
684 }
685
686 offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
687 kptr += chunk_ib->va_start - offset;
688
689 r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
690 if (r) {
691 DRM_ERROR("Failed to get ib !\n");
692 return r;
693 }
694
695 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
696 amdgpu_bo_kunmap(aobj);
697 } else {
698 r = amdgpu_ib_get(ring, vm, 0, ib);
699 if (r) {
700 DRM_ERROR("Failed to get ib !\n");
701 return r;
702 }
703
704 ib->gpu_addr = chunk_ib->va_start;
705 }
706
707 ib->length_dw = chunk_ib->ib_bytes / 4;
708 ib->flags = chunk_ib->flags;
709 ib->ctx = parser->ctx;
710 j++;
711 }
712
713 if (!parser->num_ibs)
714 return 0;
715
716 /* add GDS resources to first IB */
717 if (parser->bo_list) {
718 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
719 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
720 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
721 struct amdgpu_ib *ib = &parser->ibs[0];
722
723 if (gds) {
724 ib->gds_base = amdgpu_bo_gpu_offset(gds);
725 ib->gds_size = amdgpu_bo_size(gds);
726 }
727 if (gws) {
728 ib->gws_base = amdgpu_bo_gpu_offset(gws);
729 ib->gws_size = amdgpu_bo_size(gws);
730 }
731 if (oa) {
732 ib->oa_base = amdgpu_bo_gpu_offset(oa);
733 ib->oa_size = amdgpu_bo_size(oa);
734 }
735 }
736 /* wrap the last IB with user fence */
737 if (parser->uf.bo) {
738 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
739
740 /* UVD & VCE fw doesn't support user fences */
741 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
742 ib->ring->type == AMDGPU_RING_TYPE_VCE)
743 return -EINVAL;
744
745 ib->user = &parser->uf;
746 }
747
748 return 0;
749 }
750
751 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
752 struct amdgpu_cs_parser *p)
753 {
754 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
755 struct amdgpu_ib *ib;
756 int i, j, r;
757
758 if (!p->num_ibs)
759 return 0;
760
761 /* Add dependencies to first IB */
762 ib = &p->ibs[0];
763 for (i = 0; i < p->nchunks; ++i) {
764 struct drm_amdgpu_cs_chunk_dep *deps;
765 struct amdgpu_cs_chunk *chunk;
766 unsigned num_deps;
767
768 chunk = &p->chunks[i];
769
770 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
771 continue;
772
773 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
774 num_deps = chunk->length_dw * 4 /
775 sizeof(struct drm_amdgpu_cs_chunk_dep);
776
777 for (j = 0; j < num_deps; ++j) {
778 struct amdgpu_ring *ring;
779 struct amdgpu_ctx *ctx;
780 struct fence *fence;
781
782 r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
783 deps[j].ip_instance,
784 deps[j].ring, &ring);
785 if (r)
786 return r;
787
788 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
789 if (ctx == NULL)
790 return -EINVAL;
791
792 fence = amdgpu_ctx_get_fence(ctx, ring,
793 deps[j].handle);
794 if (IS_ERR(fence)) {
795 r = PTR_ERR(fence);
796 amdgpu_ctx_put(ctx);
797 return r;
798
799 } else if (fence) {
800 r = amdgpu_sync_fence(adev, &ib->sync, fence);
801 fence_put(fence);
802 amdgpu_ctx_put(ctx);
803 if (r)
804 return r;
805 }
806 }
807 }
808
809 return 0;
810 }
811
812 static int amdgpu_cs_free_job(struct amdgpu_job *job)
813 {
814 int i;
815 if (job->ibs)
816 for (i = 0; i < job->num_ibs; i++)
817 amdgpu_ib_free(job->adev, &job->ibs[i]);
818 kfree(job->ibs);
819 if (job->uf.bo)
820 drm_gem_object_unreference_unlocked(&job->uf.bo->gem_base);
821 return 0;
822 }
823
824 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
825 {
826 struct amdgpu_device *adev = dev->dev_private;
827 union drm_amdgpu_cs *cs = data;
828 struct amdgpu_fpriv *fpriv = filp->driver_priv;
829 struct amdgpu_vm *vm = &fpriv->vm;
830 struct amdgpu_cs_parser *parser;
831 bool reserved_buffers = false;
832 int i, r;
833
834 if (!adev->accel_working)
835 return -EBUSY;
836
837 parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0);
838 if (!parser)
839 return -ENOMEM;
840 r = amdgpu_cs_parser_init(parser, data);
841 if (r) {
842 DRM_ERROR("Failed to initialize parser !\n");
843 amdgpu_cs_parser_fini(parser, r, false);
844 r = amdgpu_cs_handle_lockup(adev, r);
845 return r;
846 }
847 mutex_lock(&vm->mutex);
848 r = amdgpu_cs_parser_relocs(parser);
849 if (r == -ENOMEM)
850 DRM_ERROR("Not enough memory for command submission!\n");
851 else if (r && r != -ERESTARTSYS)
852 DRM_ERROR("Failed to process the buffer list %d!\n", r);
853 else if (!r) {
854 reserved_buffers = true;
855 r = amdgpu_cs_ib_fill(adev, parser);
856 }
857
858 if (!r) {
859 r = amdgpu_cs_dependencies(adev, parser);
860 if (r)
861 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
862 }
863
864 if (r)
865 goto out;
866
867 for (i = 0; i < parser->num_ibs; i++)
868 trace_amdgpu_cs(parser, i);
869
870 r = amdgpu_cs_ib_vm_chunk(adev, parser);
871 if (r)
872 goto out;
873
874 if (amdgpu_enable_scheduler && parser->num_ibs) {
875 struct amdgpu_job *job;
876 struct amdgpu_ring * ring = parser->ibs->ring;
877 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
878 if (!job) {
879 r = -ENOMEM;
880 goto out;
881 }
882 job->base.sched = &ring->sched;
883 job->base.s_entity = &parser->ctx->rings[ring->idx].entity;
884 job->adev = parser->adev;
885 job->ibs = parser->ibs;
886 job->num_ibs = parser->num_ibs;
887 job->base.owner = parser->filp;
888 mutex_init(&job->job_lock);
889 if (job->ibs[job->num_ibs - 1].user) {
890 memcpy(&job->uf, &parser->uf,
891 sizeof(struct amdgpu_user_fence));
892 job->ibs[job->num_ibs - 1].user = &job->uf;
893 }
894
895 job->free_job = amdgpu_cs_free_job;
896 mutex_lock(&job->job_lock);
897 r = amd_sched_entity_push_job(&job->base);
898 if (r) {
899 mutex_unlock(&job->job_lock);
900 amdgpu_cs_free_job(job);
901 kfree(job);
902 goto out;
903 }
904 cs->out.handle =
905 amdgpu_ctx_add_fence(parser->ctx, ring,
906 &job->base.s_fence->base);
907 parser->ibs[parser->num_ibs - 1].sequence = cs->out.handle;
908
909 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
910 ttm_eu_fence_buffer_objects(&parser->ticket,
911 &parser->validated,
912 &job->base.s_fence->base);
913
914 mutex_unlock(&job->job_lock);
915 amdgpu_cs_parser_fini_late(parser);
916 mutex_unlock(&vm->mutex);
917 return 0;
918 }
919
920 cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
921 out:
922 amdgpu_cs_parser_fini(parser, r, reserved_buffers);
923 mutex_unlock(&vm->mutex);
924 r = amdgpu_cs_handle_lockup(adev, r);
925 return r;
926 }
927
928 /**
929 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
930 *
931 * @dev: drm device
932 * @data: data from userspace
933 * @filp: file private
934 *
935 * Wait for the command submission identified by handle to finish.
936 */
937 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
938 struct drm_file *filp)
939 {
940 union drm_amdgpu_wait_cs *wait = data;
941 struct amdgpu_device *adev = dev->dev_private;
942 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
943 struct amdgpu_ring *ring = NULL;
944 struct amdgpu_ctx *ctx;
945 struct fence *fence;
946 long r;
947
948 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
949 wait->in.ring, &ring);
950 if (r)
951 return r;
952
953 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
954 if (ctx == NULL)
955 return -EINVAL;
956
957 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
958 if (IS_ERR(fence))
959 r = PTR_ERR(fence);
960 else if (fence) {
961 r = fence_wait_timeout(fence, true, timeout);
962 fence_put(fence);
963 } else
964 r = 1;
965
966 amdgpu_ctx_put(ctx);
967 if (r < 0)
968 return r;
969
970 memset(wait, 0, sizeof(*wait));
971 wait->out.status = (r == 0);
972
973 return 0;
974 }
975
976 /**
977 * amdgpu_cs_find_bo_va - find bo_va for VM address
978 *
979 * @parser: command submission parser context
980 * @addr: VM address
981 * @bo: resulting BO of the mapping found
982 *
983 * Search the buffer objects in the command submission context for a certain
984 * virtual memory address. Returns allocation structure when found, NULL
985 * otherwise.
986 */
987 struct amdgpu_bo_va_mapping *
988 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
989 uint64_t addr, struct amdgpu_bo **bo)
990 {
991 struct amdgpu_bo_list_entry *reloc;
992 struct amdgpu_bo_va_mapping *mapping;
993
994 addr /= AMDGPU_GPU_PAGE_SIZE;
995
996 list_for_each_entry(reloc, &parser->validated, tv.head) {
997 if (!reloc->bo_va)
998 continue;
999
1000 list_for_each_entry(mapping, &reloc->bo_va->valids, list) {
1001 if (mapping->it.start > addr ||
1002 addr > mapping->it.last)
1003 continue;
1004
1005 *bo = reloc->bo_va->bo;
1006 return mapping;
1007 }
1008
1009 list_for_each_entry(mapping, &reloc->bo_va->invalids, list) {
1010 if (mapping->it.start > addr ||
1011 addr > mapping->it.last)
1012 continue;
1013
1014 *bo = reloc->bo_va->bo;
1015 return mapping;
1016 }
1017 }
1018
1019 return NULL;
1020 }
Linux kernel - Deliverables
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