drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: monk liu <monk.liu@amd.com>
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27
  28 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
  29                     struct amdgpu_ctx *ctx)
  30 {
  31         unsigned i, j;
  32         int r;
  33
  34         memset(ctx, 0, sizeof(*ctx));
  35         ctx->adev = adev;
  36         kref_init(&ctx->refcount);
  37         spin_lock_init(&ctx->ring_lock);
  38         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
  39                 ctx->rings[i].sequence = 1;
  40
  41         if (amdgpu_enable_scheduler) {
  42                 /* create context entity for each ring */
  43                 for (i = 0; i < adev->num_rings; i++) {
  44                         struct amd_sched_rq *rq;
  45                         if (kernel)
  46                                 rq = &adev->rings[i]->sched.kernel_rq;
  47                         else
  48                                 rq = &adev->rings[i]->sched.sched_rq;
  49                         r = amd_sched_entity_init(&adev->rings[i]->sched,
  50                                                   &ctx->rings[i].entity,
  51                                                   rq, amdgpu_sched_jobs);
  52                         if (r)
  53                                 break;
  54                 }
  55
  56                 if (i < adev->num_rings) {
  57                         for (j = 0; j < i; j++)
  58                                 amd_sched_entity_fini(&adev->rings[j]->sched,
  59                                                       &ctx->rings[j].entity);
  60                         kfree(ctx);
  61                         return r;
  62                 }
  63         }
  64         return 0;
  65 }
  66
  67 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
  68 {
  69         struct amdgpu_device *adev = ctx->adev;
  70         unsigned i, j;
  71
  72         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
  73                 for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
  74                         fence_put(ctx->rings[i].fences[j]);
  75
  76         if (amdgpu_enable_scheduler) {
  77                 for (i = 0; i < adev->num_rings; i++)
  78                         amd_sched_entity_fini(&adev->rings[i]->sched,
  79                                               &ctx->rings[i].entity);
  80         }
  81 }
  82
  83 static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
  84                             struct amdgpu_fpriv *fpriv,
  85                             uint32_t *id)
  86 {
  87         struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  88         struct amdgpu_ctx *ctx;
  89         int r;
  90
  91         ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
  92         if (!ctx)
  93                 return -ENOMEM;
  94
  95         mutex_lock(&mgr->lock);
  96         r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
  97         if (r < 0) {
  98                 mutex_unlock(&mgr->lock);
  99                 kfree(ctx);
 100                 return r;
 101         }
 102         *id = (uint32_t)r;
 103         r = amdgpu_ctx_init(adev, false, ctx);
 104         mutex_unlock(&mgr->lock);
 105
 106         return r;
 107 }
 108
 109 static void amdgpu_ctx_do_release(struct kref *ref)
 110 {
 111         struct amdgpu_ctx *ctx;
 112
 113         ctx = container_of(ref, struct amdgpu_ctx, refcount);
 114
 115         amdgpu_ctx_fini(ctx);
 116
 117         kfree(ctx);
 118 }
 119
 120 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
 121 {
 122         struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
 123         struct amdgpu_ctx *ctx;
 124
 125         mutex_lock(&mgr->lock);
 126         ctx = idr_find(&mgr->ctx_handles, id);
 127         if (ctx) {
 128                 idr_remove(&mgr->ctx_handles, id);
 129                 kref_put(&ctx->refcount, amdgpu_ctx_do_release);
 130                 mutex_unlock(&mgr->lock);
 131                 return 0;
 132         }
 133         mutex_unlock(&mgr->lock);
 134         return -EINVAL;
 135 }
 136
 137 static int amdgpu_ctx_query(struct amdgpu_device *adev,
 138                             struct amdgpu_fpriv *fpriv, uint32_t id,
 139                             union drm_amdgpu_ctx_out *out)
 140 {
 141         struct amdgpu_ctx *ctx;
 142         struct amdgpu_ctx_mgr *mgr;
 143         unsigned reset_counter;
 144
 145         if (!fpriv)
 146                 return -EINVAL;
 147
 148         mgr = &fpriv->ctx_mgr;
 149         mutex_lock(&mgr->lock);
 150         ctx = idr_find(&mgr->ctx_handles, id);
 151         if (!ctx) {
 152                 mutex_unlock(&mgr->lock);
 153                 return -EINVAL;
 154         }
 155
 156         /* TODO: these two are always zero */
 157         out->state.flags = 0x0;
 158         out->state.hangs = 0x0;
 159
 160         /* determine if a GPU reset has occured since the last call */
 161         reset_counter = atomic_read(&adev->gpu_reset_counter);
 162         /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
 163         if (ctx->reset_counter == reset_counter)
 164                 out->state.reset_status = AMDGPU_CTX_NO_RESET;
 165         else
 166                 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
 167         ctx->reset_counter = reset_counter;
 168
 169         mutex_unlock(&mgr->lock);
 170         return 0;
 171 }
 172
 173 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
 174                      struct drm_file *filp)
 175 {
 176         int r;
 177         uint32_t id;
 178
 179         union drm_amdgpu_ctx *args = data;
 180         struct amdgpu_device *adev = dev->dev_private;
 181         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 182
 183         r = 0;
 184         id = args->in.ctx_id;
 185
 186         switch (args->in.op) {
 187                 case AMDGPU_CTX_OP_ALLOC_CTX:
 188                         r = amdgpu_ctx_alloc(adev, fpriv, &id);
 189                         args->out.alloc.ctx_id = id;
 190                         break;
 191                 case AMDGPU_CTX_OP_FREE_CTX:
 192                         r = amdgpu_ctx_free(fpriv, id);
 193                         break;
 194                 case AMDGPU_CTX_OP_QUERY_STATE:
 195                         r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
 196                         break;
 197                 default:
 198                         return -EINVAL;
 199         }
 200
 201         return r;
 202 }
 203
 204 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
 205 {
 206         struct amdgpu_ctx *ctx;
 207         struct amdgpu_ctx_mgr *mgr;
 208
 209         if (!fpriv)
 210                 return NULL;
 211
 212         mgr = &fpriv->ctx_mgr;
 213
 214         mutex_lock(&mgr->lock);
 215         ctx = idr_find(&mgr->ctx_handles, id);
 216         if (ctx)
 217                 kref_get(&ctx->refcount);
 218         mutex_unlock(&mgr->lock);
 219         return ctx;
 220 }
 221
 222 int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
 223 {
 224         if (ctx == NULL)
 225                 return -EINVAL;
 226
 227         kref_put(&ctx->refcount, amdgpu_ctx_do_release);
 228         return 0;
 229 }
 230
 231 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
 232                               struct fence *fence)
 233 {
 234         struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
 235         uint64_t seq = cring->sequence;
 236         unsigned idx = 0;
 237         struct fence *other = NULL;
 238
 239         idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
 240         other = cring->fences[idx];
 241         if (other) {
 242                 signed long r;
 243                 r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
 244                 if (r < 0)
 245                         DRM_ERROR("Error (%ld) waiting for fence!\n", r);
 246         }
 247
 248         fence_get(fence);
 249
 250         spin_lock(&ctx->ring_lock);
 251         cring->fences[idx] = fence;
 252         cring->sequence++;
 253         spin_unlock(&ctx->ring_lock);
 254
 255         fence_put(other);
 256
 257         return seq;
 258 }
 259
 260 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
 261                                    struct amdgpu_ring *ring, uint64_t seq)
 262 {
 263         struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
 264         struct fence *fence;
 265
 266         spin_lock(&ctx->ring_lock);
 267
 268         if (seq >= cring->sequence) {
 269                 spin_unlock(&ctx->ring_lock);
 270                 return ERR_PTR(-EINVAL);
 271         }
 272
 273
 274         if (seq + AMDGPU_CTX_MAX_CS_PENDING < cring->sequence) {
 275                 spin_unlock(&ctx->ring_lock);
 276                 return NULL;
 277         }
 278
 279         fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
 280         spin_unlock(&ctx->ring_lock);
 281
 282         return fence;
 283 }
 284
 285 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
 286 {
 287         mutex_init(&mgr->lock);
 288         idr_init(&mgr->ctx_handles);
 289 }
 290
 291 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
 292 {
 293         struct amdgpu_ctx *ctx;
 294         struct idr *idp;
 295         uint32_t id;
 296
 297         idp = &mgr->ctx_handles;
 298
 299         idr_for_each_entry(idp, ctx, id) {
 300                 if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
 301                         DRM_ERROR("ctx %p is still alive\n", ctx);
 302         }
 303
 304         idr_destroy(&mgr->ctx_handles);
 305         mutex_destroy(&mgr->lock);
 306 }