2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: monk liu <monk.liu@amd.com>
28 int amdgpu_ctx_init(struct amdgpu_device
*adev
, bool kernel
,
29 struct amdgpu_ctx
*ctx
)
34 memset(ctx
, 0, sizeof(*ctx
));
36 kref_init(&ctx
->refcount
);
37 spin_lock_init(&ctx
->ring_lock
);
38 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
39 ctx
->rings
[i
].sequence
= 1;
41 if (amdgpu_enable_scheduler
) {
42 /* create context entity for each ring */
43 for (i
= 0; i
< adev
->num_rings
; i
++) {
44 struct amd_sched_rq
*rq
;
46 rq
= &adev
->rings
[i
]->sched
.kernel_rq
;
48 rq
= &adev
->rings
[i
]->sched
.sched_rq
;
49 r
= amd_sched_entity_init(&adev
->rings
[i
]->sched
,
50 &ctx
->rings
[i
].entity
,
51 rq
, amdgpu_sched_jobs
);
56 if (i
< adev
->num_rings
) {
57 for (j
= 0; j
< i
; j
++)
58 amd_sched_entity_fini(&adev
->rings
[j
]->sched
,
59 &ctx
->rings
[j
].entity
);
67 void amdgpu_ctx_fini(struct amdgpu_ctx
*ctx
)
69 struct amdgpu_device
*adev
= ctx
->adev
;
72 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
73 for (j
= 0; j
< AMDGPU_CTX_MAX_CS_PENDING
; ++j
)
74 fence_put(ctx
->rings
[i
].fences
[j
]);
76 if (amdgpu_enable_scheduler
) {
77 for (i
= 0; i
< adev
->num_rings
; i
++)
78 amd_sched_entity_fini(&adev
->rings
[i
]->sched
,
79 &ctx
->rings
[i
].entity
);
83 static int amdgpu_ctx_alloc(struct amdgpu_device
*adev
,
84 struct amdgpu_fpriv
*fpriv
,
87 struct amdgpu_ctx_mgr
*mgr
= &fpriv
->ctx_mgr
;
88 struct amdgpu_ctx
*ctx
;
91 ctx
= kmalloc(sizeof(*ctx
), GFP_KERNEL
);
95 mutex_lock(&mgr
->lock
);
96 r
= idr_alloc(&mgr
->ctx_handles
, ctx
, 1, 0, GFP_KERNEL
);
98 mutex_unlock(&mgr
->lock
);
103 r
= amdgpu_ctx_init(adev
, false, ctx
);
104 mutex_unlock(&mgr
->lock
);
109 static void amdgpu_ctx_do_release(struct kref
*ref
)
111 struct amdgpu_ctx
*ctx
;
113 ctx
= container_of(ref
, struct amdgpu_ctx
, refcount
);
115 amdgpu_ctx_fini(ctx
);
120 static int amdgpu_ctx_free(struct amdgpu_fpriv
*fpriv
, uint32_t id
)
122 struct amdgpu_ctx_mgr
*mgr
= &fpriv
->ctx_mgr
;
123 struct amdgpu_ctx
*ctx
;
125 mutex_lock(&mgr
->lock
);
126 ctx
= idr_find(&mgr
->ctx_handles
, id
);
128 idr_remove(&mgr
->ctx_handles
, id
);
129 kref_put(&ctx
->refcount
, amdgpu_ctx_do_release
);
130 mutex_unlock(&mgr
->lock
);
133 mutex_unlock(&mgr
->lock
);
137 static int amdgpu_ctx_query(struct amdgpu_device
*adev
,
138 struct amdgpu_fpriv
*fpriv
, uint32_t id
,
139 union drm_amdgpu_ctx_out
*out
)
141 struct amdgpu_ctx
*ctx
;
142 struct amdgpu_ctx_mgr
*mgr
;
143 unsigned reset_counter
;
148 mgr
= &fpriv
->ctx_mgr
;
149 mutex_lock(&mgr
->lock
);
150 ctx
= idr_find(&mgr
->ctx_handles
, id
);
152 mutex_unlock(&mgr
->lock
);
156 /* TODO: these two are always zero */
157 out
->state
.flags
= 0x0;
158 out
->state
.hangs
= 0x0;
160 /* determine if a GPU reset has occured since the last call */
161 reset_counter
= atomic_read(&adev
->gpu_reset_counter
);
162 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
163 if (ctx
->reset_counter
== reset_counter
)
164 out
->state
.reset_status
= AMDGPU_CTX_NO_RESET
;
166 out
->state
.reset_status
= AMDGPU_CTX_UNKNOWN_RESET
;
167 ctx
->reset_counter
= reset_counter
;
169 mutex_unlock(&mgr
->lock
);
173 int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
174 struct drm_file
*filp
)
179 union drm_amdgpu_ctx
*args
= data
;
180 struct amdgpu_device
*adev
= dev
->dev_private
;
181 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
184 id
= args
->in
.ctx_id
;
186 switch (args
->in
.op
) {
187 case AMDGPU_CTX_OP_ALLOC_CTX
:
188 r
= amdgpu_ctx_alloc(adev
, fpriv
, &id
);
189 args
->out
.alloc
.ctx_id
= id
;
191 case AMDGPU_CTX_OP_FREE_CTX
:
192 r
= amdgpu_ctx_free(fpriv
, id
);
194 case AMDGPU_CTX_OP_QUERY_STATE
:
195 r
= amdgpu_ctx_query(adev
, fpriv
, id
, &args
->out
);
204 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
)
206 struct amdgpu_ctx
*ctx
;
207 struct amdgpu_ctx_mgr
*mgr
;
212 mgr
= &fpriv
->ctx_mgr
;
214 mutex_lock(&mgr
->lock
);
215 ctx
= idr_find(&mgr
->ctx_handles
, id
);
217 kref_get(&ctx
->refcount
);
218 mutex_unlock(&mgr
->lock
);
222 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
)
227 kref_put(&ctx
->refcount
, amdgpu_ctx_do_release
);
231 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx
*ctx
, struct amdgpu_ring
*ring
,
234 struct amdgpu_ctx_ring
*cring
= & ctx
->rings
[ring
->idx
];
235 uint64_t seq
= cring
->sequence
;
237 struct fence
*other
= NULL
;
239 idx
= seq
% AMDGPU_CTX_MAX_CS_PENDING
;
240 other
= cring
->fences
[idx
];
243 r
= fence_wait_timeout(other
, false, MAX_SCHEDULE_TIMEOUT
);
245 DRM_ERROR("Error (%ld) waiting for fence!\n", r
);
250 spin_lock(&ctx
->ring_lock
);
251 cring
->fences
[idx
] = fence
;
253 spin_unlock(&ctx
->ring_lock
);
260 struct fence
*amdgpu_ctx_get_fence(struct amdgpu_ctx
*ctx
,
261 struct amdgpu_ring
*ring
, uint64_t seq
)
263 struct amdgpu_ctx_ring
*cring
= & ctx
->rings
[ring
->idx
];
266 spin_lock(&ctx
->ring_lock
);
268 if (seq
>= cring
->sequence
) {
269 spin_unlock(&ctx
->ring_lock
);
270 return ERR_PTR(-EINVAL
);
274 if (seq
+ AMDGPU_CTX_MAX_CS_PENDING
< cring
->sequence
) {
275 spin_unlock(&ctx
->ring_lock
);
279 fence
= fence_get(cring
->fences
[seq
% AMDGPU_CTX_MAX_CS_PENDING
]);
280 spin_unlock(&ctx
->ring_lock
);
285 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr
*mgr
)
287 mutex_init(&mgr
->lock
);
288 idr_init(&mgr
->ctx_handles
);
291 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
*mgr
)
293 struct amdgpu_ctx
*ctx
;
297 idp
= &mgr
->ctx_handles
;
299 idr_for_each_entry(idp
, ctx
, id
) {
300 if (kref_put(&ctx
->refcount
, amdgpu_ctx_do_release
) != 1)
301 DRM_ERROR("ctx %p is still alive\n", ctx
);
304 idr_destroy(&mgr
->ctx_handles
);
305 mutex_destroy(&mgr
->lock
);