2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/amdgpu_drm.h>
29 #include "amdgpu_i2c.h"
31 #include "amdgpu_connectors.h"
32 #include <asm/div64.h>
34 #include <linux/pm_runtime.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
38 static void amdgpu_flip_wait_fence(struct amdgpu_device
*adev
,
41 struct amdgpu_fence
*fence
;
47 fence
= to_amdgpu_fence(*f
);
49 r
= fence_wait(&fence
->base
, false);
51 r
= amdgpu_gpu_reset(adev
);
53 r
= fence_wait(*f
, false);
56 DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r
);
58 /* We continue with the page flip even if we failed to wait on
59 * the fence, otherwise the DRM core and userspace will be
60 * confused about which BO the CRTC is scanning out
66 static void amdgpu_flip_work_func(struct work_struct
*__work
)
68 struct amdgpu_flip_work
*work
=
69 container_of(__work
, struct amdgpu_flip_work
, flip_work
);
70 struct amdgpu_device
*adev
= work
->adev
;
71 struct amdgpu_crtc
*amdgpuCrtc
= adev
->mode_info
.crtcs
[work
->crtc_id
];
73 struct drm_crtc
*crtc
= &amdgpuCrtc
->base
;
77 amdgpu_flip_wait_fence(adev
, &work
->excl
);
78 for (i
= 0; i
< work
->shared_count
; ++i
)
79 amdgpu_flip_wait_fence(adev
, &work
->shared
[i
]);
81 /* We borrow the event spin lock for protecting flip_status */
82 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
84 /* set the proper interrupt */
85 amdgpu_irq_get(adev
, &adev
->pageflip_irq
, work
->crtc_id
);
86 /* do the flip (mmio) */
87 adev
->mode_info
.funcs
->page_flip(adev
, work
->crtc_id
, work
->base
);
88 /* set the flip status */
89 amdgpuCrtc
->pflip_status
= AMDGPU_FLIP_SUBMITTED
;
91 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
95 * Handle unpin events outside the interrupt handler proper.
97 static void amdgpu_unpin_work_func(struct work_struct
*__work
)
99 struct amdgpu_flip_work
*work
=
100 container_of(__work
, struct amdgpu_flip_work
, unpin_work
);
103 /* unpin of the old buffer */
104 r
= amdgpu_bo_reserve(work
->old_rbo
, false);
105 if (likely(r
== 0)) {
106 r
= amdgpu_bo_unpin(work
->old_rbo
);
107 if (unlikely(r
!= 0)) {
108 DRM_ERROR("failed to unpin buffer after flip\n");
110 amdgpu_bo_unreserve(work
->old_rbo
);
112 DRM_ERROR("failed to reserve buffer after flip\n");
114 drm_gem_object_unreference_unlocked(&work
->old_rbo
->gem_base
);
119 int amdgpu_crtc_page_flip(struct drm_crtc
*crtc
,
120 struct drm_framebuffer
*fb
,
121 struct drm_pending_vblank_event
*event
,
122 uint32_t page_flip_flags
)
124 struct drm_device
*dev
= crtc
->dev
;
125 struct amdgpu_device
*adev
= dev
->dev_private
;
126 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
127 struct amdgpu_framebuffer
*old_amdgpu_fb
;
128 struct amdgpu_framebuffer
*new_amdgpu_fb
;
129 struct drm_gem_object
*obj
;
130 struct amdgpu_flip_work
*work
;
131 struct amdgpu_bo
*new_rbo
;
137 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
141 INIT_WORK(&work
->flip_work
, amdgpu_flip_work_func
);
142 INIT_WORK(&work
->unpin_work
, amdgpu_unpin_work_func
);
146 work
->crtc_id
= amdgpu_crtc
->crtc_id
;
148 /* schedule unpin of the old buffer */
149 old_amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
150 obj
= old_amdgpu_fb
->obj
;
152 /* take a reference to the old object */
153 drm_gem_object_reference(obj
);
154 work
->old_rbo
= gem_to_amdgpu_bo(obj
);
156 new_amdgpu_fb
= to_amdgpu_framebuffer(fb
);
157 obj
= new_amdgpu_fb
->obj
;
158 new_rbo
= gem_to_amdgpu_bo(obj
);
160 /* pin the new buffer */
161 r
= amdgpu_bo_reserve(new_rbo
, false);
162 if (unlikely(r
!= 0)) {
163 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
167 r
= amdgpu_bo_pin_restricted(new_rbo
, AMDGPU_GEM_DOMAIN_VRAM
, 0, 0, &base
);
168 if (unlikely(r
!= 0)) {
169 amdgpu_bo_unreserve(new_rbo
);
171 DRM_ERROR("failed to pin new rbo buffer before flip\n");
175 r
= reservation_object_get_fences_rcu(new_rbo
->tbo
.resv
, &work
->excl
,
178 if (unlikely(r
!= 0)) {
179 amdgpu_bo_unreserve(new_rbo
);
180 DRM_ERROR("failed to get fences for buffer\n");
184 fence_get(work
->excl
);
185 for (i
= 0; i
< work
->shared_count
; ++i
)
186 fence_get(work
->shared
[i
]);
188 amdgpu_bo_get_tiling_flags(new_rbo
, &tiling_flags
);
189 amdgpu_bo_unreserve(new_rbo
);
193 r
= drm_vblank_get(crtc
->dev
, amdgpu_crtc
->crtc_id
);
195 DRM_ERROR("failed to get vblank before flip\n");
199 /* we borrow the event spin lock for protecting flip_wrok */
200 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
201 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_NONE
) {
202 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
203 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
208 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_PENDING
;
209 amdgpu_crtc
->pflip_works
= work
;
212 crtc
->primary
->fb
= fb
;
213 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
214 queue_work(amdgpu_crtc
->pflip_queue
, &work
->flip_work
);
218 drm_vblank_put(crtc
->dev
, amdgpu_crtc
->crtc_id
);
221 if (unlikely(amdgpu_bo_reserve(new_rbo
, false) != 0)) {
222 DRM_ERROR("failed to reserve new rbo in error path\n");
225 if (unlikely(amdgpu_bo_unpin(new_rbo
) != 0)) {
226 DRM_ERROR("failed to unpin new rbo in error path\n");
228 amdgpu_bo_unreserve(new_rbo
);
231 drm_gem_object_unreference_unlocked(&work
->old_rbo
->gem_base
);
232 fence_put(work
->excl
);
233 for (i
= 0; i
< work
->shared_count
; ++i
)
234 fence_put(work
->shared
[i
]);
241 int amdgpu_crtc_set_config(struct drm_mode_set
*set
)
243 struct drm_device
*dev
;
244 struct amdgpu_device
*adev
;
245 struct drm_crtc
*crtc
;
249 if (!set
|| !set
->crtc
)
252 dev
= set
->crtc
->dev
;
254 ret
= pm_runtime_get_sync(dev
->dev
);
258 ret
= drm_crtc_helper_set_config(set
);
260 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
264 pm_runtime_mark_last_busy(dev
->dev
);
266 adev
= dev
->dev_private
;
267 /* if we have active crtcs and we don't have a power ref,
268 take the current one */
269 if (active
&& !adev
->have_disp_power_ref
) {
270 adev
->have_disp_power_ref
= true;
273 /* if we have no active crtcs, then drop the power ref
275 if (!active
&& adev
->have_disp_power_ref
) {
276 pm_runtime_put_autosuspend(dev
->dev
);
277 adev
->have_disp_power_ref
= false;
280 /* drop the power reference we got coming in here */
281 pm_runtime_put_autosuspend(dev
->dev
);
285 static const char *encoder_names
[38] = {
305 "INTERNAL_KLDSCP_TMDS1",
306 "INTERNAL_KLDSCP_DVO1",
307 "INTERNAL_KLDSCP_DAC1",
308 "INTERNAL_KLDSCP_DAC2",
317 "INTERNAL_KLDSCP_LVTMA",
326 static const char *hpd_names
[6] = {
335 void amdgpu_print_display_setup(struct drm_device
*dev
)
337 struct drm_connector
*connector
;
338 struct amdgpu_connector
*amdgpu_connector
;
339 struct drm_encoder
*encoder
;
340 struct amdgpu_encoder
*amdgpu_encoder
;
344 DRM_INFO("AMDGPU Display Connectors\n");
345 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
346 amdgpu_connector
= to_amdgpu_connector(connector
);
347 DRM_INFO("Connector %d:\n", i
);
348 DRM_INFO(" %s\n", connector
->name
);
349 if (amdgpu_connector
->hpd
.hpd
!= AMDGPU_HPD_NONE
)
350 DRM_INFO(" %s\n", hpd_names
[amdgpu_connector
->hpd
.hpd
]);
351 if (amdgpu_connector
->ddc_bus
) {
352 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
353 amdgpu_connector
->ddc_bus
->rec
.mask_clk_reg
,
354 amdgpu_connector
->ddc_bus
->rec
.mask_data_reg
,
355 amdgpu_connector
->ddc_bus
->rec
.a_clk_reg
,
356 amdgpu_connector
->ddc_bus
->rec
.a_data_reg
,
357 amdgpu_connector
->ddc_bus
->rec
.en_clk_reg
,
358 amdgpu_connector
->ddc_bus
->rec
.en_data_reg
,
359 amdgpu_connector
->ddc_bus
->rec
.y_clk_reg
,
360 amdgpu_connector
->ddc_bus
->rec
.y_data_reg
);
361 if (amdgpu_connector
->router
.ddc_valid
)
362 DRM_INFO(" DDC Router 0x%x/0x%x\n",
363 amdgpu_connector
->router
.ddc_mux_control_pin
,
364 amdgpu_connector
->router
.ddc_mux_state
);
365 if (amdgpu_connector
->router
.cd_valid
)
366 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
367 amdgpu_connector
->router
.cd_mux_control_pin
,
368 amdgpu_connector
->router
.cd_mux_state
);
370 if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
||
371 connector
->connector_type
== DRM_MODE_CONNECTOR_DVII
||
372 connector
->connector_type
== DRM_MODE_CONNECTOR_DVID
||
373 connector
->connector_type
== DRM_MODE_CONNECTOR_DVIA
||
374 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIA
||
375 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIB
)
376 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
378 DRM_INFO(" Encoders:\n");
379 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
380 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
381 devices
= amdgpu_encoder
->devices
& amdgpu_connector
->devices
;
383 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
384 DRM_INFO(" CRT1: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
385 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
386 DRM_INFO(" CRT2: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
387 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
388 DRM_INFO(" LCD1: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
389 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
390 DRM_INFO(" DFP1: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
391 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
392 DRM_INFO(" DFP2: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
393 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
394 DRM_INFO(" DFP3: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
395 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
396 DRM_INFO(" DFP4: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
397 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
398 DRM_INFO(" DFP5: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
399 if (devices
& ATOM_DEVICE_DFP6_SUPPORT
)
400 DRM_INFO(" DFP6: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
401 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
402 DRM_INFO(" TV1: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
403 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
404 DRM_INFO(" CV: %s\n", encoder_names
[amdgpu_encoder
->encoder_id
]);
415 bool amdgpu_ddc_probe(struct amdgpu_connector
*amdgpu_connector
,
421 struct i2c_msg msgs
[] = {
436 /* on hw with routers, select right port */
437 if (amdgpu_connector
->router
.ddc_valid
)
438 amdgpu_i2c_router_select_ddc_port(amdgpu_connector
);
441 ret
= i2c_transfer(&amdgpu_connector
->ddc_bus
->aux
.ddc
, msgs
, 2);
443 ret
= i2c_transfer(&amdgpu_connector
->ddc_bus
->adapter
, msgs
, 2);
447 /* Couldn't find an accessible DDC on this connector */
449 /* Probe also for valid EDID header
450 * EDID header starts with:
451 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
452 * Only the first 6 bytes must be valid as
453 * drm_edid_block_valid() can fix the last 2 bytes */
454 if (drm_edid_header_is_valid(buf
) < 6) {
455 /* Couldn't find an accessible EDID on this
462 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
464 struct amdgpu_framebuffer
*amdgpu_fb
= to_amdgpu_framebuffer(fb
);
466 if (amdgpu_fb
->obj
) {
467 drm_gem_object_unreference_unlocked(amdgpu_fb
->obj
);
469 drm_framebuffer_cleanup(fb
);
473 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
474 struct drm_file
*file_priv
,
475 unsigned int *handle
)
477 struct amdgpu_framebuffer
*amdgpu_fb
= to_amdgpu_framebuffer(fb
);
479 return drm_gem_handle_create(file_priv
, amdgpu_fb
->obj
, handle
);
482 static const struct drm_framebuffer_funcs amdgpu_fb_funcs
= {
483 .destroy
= amdgpu_user_framebuffer_destroy
,
484 .create_handle
= amdgpu_user_framebuffer_create_handle
,
488 amdgpu_framebuffer_init(struct drm_device
*dev
,
489 struct amdgpu_framebuffer
*rfb
,
490 struct drm_mode_fb_cmd2
*mode_cmd
,
491 struct drm_gem_object
*obj
)
495 drm_helper_mode_fill_fb_struct(&rfb
->base
, mode_cmd
);
496 ret
= drm_framebuffer_init(dev
, &rfb
->base
, &amdgpu_fb_funcs
);
504 static struct drm_framebuffer
*
505 amdgpu_user_framebuffer_create(struct drm_device
*dev
,
506 struct drm_file
*file_priv
,
507 struct drm_mode_fb_cmd2
*mode_cmd
)
509 struct drm_gem_object
*obj
;
510 struct amdgpu_framebuffer
*amdgpu_fb
;
513 obj
= drm_gem_object_lookup(dev
, file_priv
, mode_cmd
->handles
[0]);
515 dev_err(&dev
->pdev
->dev
, "No GEM object associated to handle 0x%08X, "
516 "can't create framebuffer\n", mode_cmd
->handles
[0]);
517 return ERR_PTR(-ENOENT
);
520 amdgpu_fb
= kzalloc(sizeof(*amdgpu_fb
), GFP_KERNEL
);
521 if (amdgpu_fb
== NULL
) {
522 drm_gem_object_unreference_unlocked(obj
);
523 return ERR_PTR(-ENOMEM
);
526 ret
= amdgpu_framebuffer_init(dev
, amdgpu_fb
, mode_cmd
, obj
);
529 drm_gem_object_unreference_unlocked(obj
);
533 return &amdgpu_fb
->base
;
536 static void amdgpu_output_poll_changed(struct drm_device
*dev
)
538 struct amdgpu_device
*adev
= dev
->dev_private
;
539 amdgpu_fb_output_poll_changed(adev
);
542 const struct drm_mode_config_funcs amdgpu_mode_funcs
= {
543 .fb_create
= amdgpu_user_framebuffer_create
,
544 .output_poll_changed
= amdgpu_output_poll_changed
547 static struct drm_prop_enum_list amdgpu_underscan_enum_list
[] =
548 { { UNDERSCAN_OFF
, "off" },
549 { UNDERSCAN_ON
, "on" },
550 { UNDERSCAN_AUTO
, "auto" },
553 static struct drm_prop_enum_list amdgpu_audio_enum_list
[] =
554 { { AMDGPU_AUDIO_DISABLE
, "off" },
555 { AMDGPU_AUDIO_ENABLE
, "on" },
556 { AMDGPU_AUDIO_AUTO
, "auto" },
559 /* XXX support different dither options? spatial, temporal, both, etc. */
560 static struct drm_prop_enum_list amdgpu_dither_enum_list
[] =
561 { { AMDGPU_FMT_DITHER_DISABLE
, "off" },
562 { AMDGPU_FMT_DITHER_ENABLE
, "on" },
565 int amdgpu_modeset_create_props(struct amdgpu_device
*adev
)
569 if (adev
->is_atom_bios
) {
570 adev
->mode_info
.coherent_mode_property
=
571 drm_property_create_range(adev
->ddev
, 0 , "coherent", 0, 1);
572 if (!adev
->mode_info
.coherent_mode_property
)
576 adev
->mode_info
.load_detect_property
=
577 drm_property_create_range(adev
->ddev
, 0, "load detection", 0, 1);
578 if (!adev
->mode_info
.load_detect_property
)
581 drm_mode_create_scaling_mode_property(adev
->ddev
);
583 sz
= ARRAY_SIZE(amdgpu_underscan_enum_list
);
584 adev
->mode_info
.underscan_property
=
585 drm_property_create_enum(adev
->ddev
, 0,
587 amdgpu_underscan_enum_list
, sz
);
589 adev
->mode_info
.underscan_hborder_property
=
590 drm_property_create_range(adev
->ddev
, 0,
591 "underscan hborder", 0, 128);
592 if (!adev
->mode_info
.underscan_hborder_property
)
595 adev
->mode_info
.underscan_vborder_property
=
596 drm_property_create_range(adev
->ddev
, 0,
597 "underscan vborder", 0, 128);
598 if (!adev
->mode_info
.underscan_vborder_property
)
601 sz
= ARRAY_SIZE(amdgpu_audio_enum_list
);
602 adev
->mode_info
.audio_property
=
603 drm_property_create_enum(adev
->ddev
, 0,
605 amdgpu_audio_enum_list
, sz
);
607 sz
= ARRAY_SIZE(amdgpu_dither_enum_list
);
608 adev
->mode_info
.dither_property
=
609 drm_property_create_enum(adev
->ddev
, 0,
611 amdgpu_dither_enum_list
, sz
);
616 void amdgpu_update_display_priority(struct amdgpu_device
*adev
)
618 /* adjustment options for the display watermarks */
619 if ((amdgpu_disp_priority
== 0) || (amdgpu_disp_priority
> 2))
620 adev
->mode_info
.disp_priority
= 0;
622 adev
->mode_info
.disp_priority
= amdgpu_disp_priority
;
626 static bool is_hdtv_mode(const struct drm_display_mode
*mode
)
628 /* try and guess if this is a tv or a monitor */
629 if ((mode
->vdisplay
== 480 && mode
->hdisplay
== 720) || /* 480p */
630 (mode
->vdisplay
== 576) || /* 576p */
631 (mode
->vdisplay
== 720) || /* 720p */
632 (mode
->vdisplay
== 1080)) /* 1080p */
638 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
639 const struct drm_display_mode
*mode
,
640 struct drm_display_mode
*adjusted_mode
)
642 struct drm_device
*dev
= crtc
->dev
;
643 struct drm_encoder
*encoder
;
644 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
645 struct amdgpu_encoder
*amdgpu_encoder
;
646 struct drm_connector
*connector
;
647 struct amdgpu_connector
*amdgpu_connector
;
648 u32 src_v
= 1, dst_v
= 1;
649 u32 src_h
= 1, dst_h
= 1;
651 amdgpu_crtc
->h_border
= 0;
652 amdgpu_crtc
->v_border
= 0;
654 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
655 if (encoder
->crtc
!= crtc
)
657 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
658 connector
= amdgpu_get_connector_for_encoder(encoder
);
659 amdgpu_connector
= to_amdgpu_connector(connector
);
662 if (amdgpu_encoder
->rmx_type
== RMX_OFF
)
663 amdgpu_crtc
->rmx_type
= RMX_OFF
;
664 else if (mode
->hdisplay
< amdgpu_encoder
->native_mode
.hdisplay
||
665 mode
->vdisplay
< amdgpu_encoder
->native_mode
.vdisplay
)
666 amdgpu_crtc
->rmx_type
= amdgpu_encoder
->rmx_type
;
668 amdgpu_crtc
->rmx_type
= RMX_OFF
;
669 /* copy native mode */
670 memcpy(&amdgpu_crtc
->native_mode
,
671 &amdgpu_encoder
->native_mode
,
672 sizeof(struct drm_display_mode
));
673 src_v
= crtc
->mode
.vdisplay
;
674 dst_v
= amdgpu_crtc
->native_mode
.vdisplay
;
675 src_h
= crtc
->mode
.hdisplay
;
676 dst_h
= amdgpu_crtc
->native_mode
.hdisplay
;
678 /* fix up for overscan on hdmi */
679 if ((!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
)) &&
680 ((amdgpu_encoder
->underscan_type
== UNDERSCAN_ON
) ||
681 ((amdgpu_encoder
->underscan_type
== UNDERSCAN_AUTO
) &&
682 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
683 is_hdtv_mode(mode
)))) {
684 if (amdgpu_encoder
->underscan_hborder
!= 0)
685 amdgpu_crtc
->h_border
= amdgpu_encoder
->underscan_hborder
;
687 amdgpu_crtc
->h_border
= (mode
->hdisplay
>> 5) + 16;
688 if (amdgpu_encoder
->underscan_vborder
!= 0)
689 amdgpu_crtc
->v_border
= amdgpu_encoder
->underscan_vborder
;
691 amdgpu_crtc
->v_border
= (mode
->vdisplay
>> 5) + 16;
692 amdgpu_crtc
->rmx_type
= RMX_FULL
;
693 src_v
= crtc
->mode
.vdisplay
;
694 dst_v
= crtc
->mode
.vdisplay
- (amdgpu_crtc
->v_border
* 2);
695 src_h
= crtc
->mode
.hdisplay
;
696 dst_h
= crtc
->mode
.hdisplay
- (amdgpu_crtc
->h_border
* 2);
699 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
) {
701 a
.full
= dfixed_const(src_v
);
702 b
.full
= dfixed_const(dst_v
);
703 amdgpu_crtc
->vsc
.full
= dfixed_div(a
, b
);
704 a
.full
= dfixed_const(src_h
);
705 b
.full
= dfixed_const(dst_h
);
706 amdgpu_crtc
->hsc
.full
= dfixed_div(a
, b
);
708 amdgpu_crtc
->vsc
.full
= dfixed_const(1);
709 amdgpu_crtc
->hsc
.full
= dfixed_const(1);
715 * Retrieve current video scanout position of crtc on a given gpu, and
716 * an optional accurate timestamp of when query happened.
718 * \param dev Device to query.
719 * \param crtc Crtc to query.
720 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
721 * \param *vpos Location where vertical scanout position should be stored.
722 * \param *hpos Location where horizontal scanout position should go.
723 * \param *stime Target location for timestamp taken immediately before
724 * scanout position query. Can be NULL to skip timestamp.
725 * \param *etime Target location for timestamp taken immediately after
726 * scanout position query. Can be NULL to skip timestamp.
728 * Returns vpos as a positive number while in active scanout area.
729 * Returns vpos as a negative number inside vblank, counting the number
730 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
731 * until start of active scanout / end of vblank."
733 * \return Flags, or'ed together as follows:
735 * DRM_SCANOUTPOS_VALID = Query successful.
736 * DRM_SCANOUTPOS_INVBL = Inside vblank.
737 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
738 * this flag means that returned position may be offset by a constant but
739 * unknown small number of scanlines wrt. real scanout position.
742 int amdgpu_get_crtc_scanoutpos(struct drm_device
*dev
, int crtc
, unsigned int flags
,
743 int *vpos
, int *hpos
, ktime_t
*stime
, ktime_t
*etime
,
744 const struct drm_display_mode
*mode
)
746 u32 vbl
= 0, position
= 0;
747 int vbl_start
, vbl_end
, vtotal
, ret
= 0;
750 struct amdgpu_device
*adev
= dev
->dev_private
;
752 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
754 /* Get optional system timestamp before query. */
756 *stime
= ktime_get();
758 if (amdgpu_display_page_flip_get_scanoutpos(adev
, crtc
, &vbl
, &position
) == 0)
759 ret
|= DRM_SCANOUTPOS_VALID
;
761 /* Get optional system timestamp after query. */
763 *etime
= ktime_get();
765 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
767 /* Decode into vertical and horizontal scanout position. */
768 *vpos
= position
& 0x1fff;
769 *hpos
= (position
>> 16) & 0x1fff;
771 /* Valid vblank area boundaries from gpu retrieved? */
774 ret
|= DRM_SCANOUTPOS_ACCURATE
;
775 vbl_start
= vbl
& 0x1fff;
776 vbl_end
= (vbl
>> 16) & 0x1fff;
779 /* No: Fake something reasonable which gives at least ok results. */
780 vbl_start
= mode
->crtc_vdisplay
;
784 /* Test scanout position against vblank region. */
785 if ((*vpos
< vbl_start
) && (*vpos
>= vbl_end
))
788 /* Check if inside vblank area and apply corrective offsets:
789 * vpos will then be >=0 in video scanout area, but negative
790 * within vblank area, counting down the number of lines until
794 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
795 if (in_vbl
&& (*vpos
>= vbl_start
)) {
796 vtotal
= mode
->crtc_vtotal
;
797 *vpos
= *vpos
- vtotal
;
800 /* Correct for shifted end of vbl at vbl_end. */
801 *vpos
= *vpos
- vbl_end
;
805 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
807 /* Is vpos outside nominal vblank area, but less than
808 * 1/100 of a frame height away from start of vblank?
809 * If so, assume this isn't a massively delayed vblank
810 * interrupt, but a vblank interrupt that fired a few
811 * microseconds before true start of vblank. Compensate
812 * by adding a full frame duration to the final timestamp.
813 * Happens, e.g., on ATI R500, R600.
815 * We only do this if DRM_CALLED_FROM_VBLIRQ.
817 if ((flags
& DRM_CALLED_FROM_VBLIRQ
) && !in_vbl
) {
818 vbl_start
= mode
->crtc_vdisplay
;
819 vtotal
= mode
->crtc_vtotal
;
821 if (vbl_start
- *vpos
< vtotal
/ 100) {
824 /* Signal this correction as "applied". */
832 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device
*adev
, int crtc
)
834 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
)
835 return AMDGPU_CRTC_IRQ_NONE
;
839 return AMDGPU_CRTC_IRQ_VBLANK1
;
841 return AMDGPU_CRTC_IRQ_VBLANK2
;
843 return AMDGPU_CRTC_IRQ_VBLANK3
;
845 return AMDGPU_CRTC_IRQ_VBLANK4
;
847 return AMDGPU_CRTC_IRQ_VBLANK5
;
849 return AMDGPU_CRTC_IRQ_VBLANK6
;
851 return AMDGPU_CRTC_IRQ_NONE
;