drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __AMDGPU_DPM_H__
  24 #define __AMDGPU_DPM_H__
  25
  26 #define R600_SSTU_DFLT                               0
  27 #define R600_SST_DFLT                                0x00C8
  28
  29 /* XXX are these ok? */
  30 #define R600_TEMP_RANGE_MIN (90 * 1000)
  31 #define R600_TEMP_RANGE_MAX (120 * 1000)
  32
  33 #define FDO_PWM_MODE_STATIC  1
  34 #define FDO_PWM_MODE_STATIC_RPM 5
  35
  36 enum amdgpu_td {
  37         AMDGPU_TD_AUTO,
  38         AMDGPU_TD_UP,
  39         AMDGPU_TD_DOWN,
  40 };
  41
  42 enum amdgpu_display_watermark {
  43         AMDGPU_DISPLAY_WATERMARK_LOW = 0,
  44         AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
  45 };
  46
  47 enum amdgpu_display_gap
  48 {
  49     AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
  50     AMDGPU_PM_DISPLAY_GAP_VBLANK       = 1,
  51     AMDGPU_PM_DISPLAY_GAP_WATERMARK    = 2,
  52     AMDGPU_PM_DISPLAY_GAP_IGNORE       = 3,
  53 };
  54
  55 void amdgpu_dpm_print_class_info(u32 class, u32 class2);
  56 void amdgpu_dpm_print_cap_info(u32 caps);
  57 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
  58                                 struct amdgpu_ps *rps);
  59 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
  60 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
  61 bool amdgpu_is_uvd_state(u32 class, u32 class2);
  62 void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
  63                               u32 *p, u32 *u);
  64 int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
  65
  66 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
  67
  68 int amdgpu_get_platform_caps(struct amdgpu_device *adev);
  69
  70 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
  71 void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
  72
  73 void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
  74
  75 enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
  76                                                  u32 sys_mask,
  77                                                  enum amdgpu_pcie_gen asic_gen,
  78                                                  enum amdgpu_pcie_gen default_gen);
  79
  80 u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
  81                                  u16 asic_lanes,
  82                                  u16 default_lanes);
  83 u8 amdgpu_encode_pci_lane_width(u32 lanes);
  84
  85 #endif