drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "cik_dpm.h"
  34 #include "vi_dpm.h"
  35
  36 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
  37 {
  38         int ret = 0;
  39         struct amd_powerplay *amd_pp;
  40
  41         amd_pp = &(adev->powerplay);
  42
  43         if (adev->pp_enabled) {
  44 #ifdef CONFIG_DRM_AMD_POWERPLAY
  45                 struct amd_pp_init *pp_init;
  46
  47                 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
  48
  49                 if (pp_init == NULL)
  50                         return -ENOMEM;
  51
  52                 pp_init->chip_family = adev->family;
  53                 pp_init->chip_id = adev->asic_type;
  54                 pp_init->device = amdgpu_cgs_create_device(adev);
  55
  56                 ret = amd_powerplay_init(pp_init, amd_pp);
  57                 kfree(pp_init);
  58 #endif
  59         } else {
  60                 amd_pp->pp_handle = (void *)adev;
  61
  62                 switch (adev->asic_type) {
  63 #ifdef CONFIG_DRM_AMDGPU_CIK
  64                 case CHIP_BONAIRE:
  65                 case CHIP_HAWAII:
  66                         amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  67                         break;
  68                 case CHIP_KABINI:
  69                 case CHIP_MULLINS:
  70                 case CHIP_KAVERI:
  71                         amd_pp->ip_funcs = &kv_dpm_ip_funcs;
  72                         break;
  73 #endif
  74                 case CHIP_TOPAZ:
  75                         amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
  76                         break;
  77                 case CHIP_TONGA:
  78                         amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
  79                         break;
  80                 case CHIP_FIJI:
  81                         amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
  82                         break;
  83                 case CHIP_CARRIZO:
  84                 case CHIP_STONEY:
  85                         amd_pp->ip_funcs = &cz_dpm_ip_funcs;
  86                         break;
  87                 default:
  88                         ret = -EINVAL;
  89                         break;
  90                 }
  91         }
  92         return ret;
  93 }
  94
  95 static int amdgpu_pp_early_init(void *handle)
  96 {
  97         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  98         int ret = 0;
  99
 100 #ifdef CONFIG_DRM_AMD_POWERPLAY
 101         switch (adev->asic_type) {
 102         case CHIP_TONGA:
 103         case CHIP_FIJI:
 104                 adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
 105                 break;
 106         case CHIP_CARRIZO:
 107         case CHIP_STONEY:
 108                 adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
 109                 break;
 110         /* These chips don't have powerplay implemenations */
 111         case CHIP_BONAIRE:
 112         case CHIP_HAWAII:
 113         case CHIP_KABINI:
 114         case CHIP_MULLINS:
 115         case CHIP_KAVERI:
 116         case CHIP_TOPAZ:
 117         default:
 118                 adev->pp_enabled = false;
 119                 break;
 120         }
 121 #else
 122         adev->pp_enabled = false;
 123 #endif
 124
 125         ret = amdgpu_powerplay_init(adev);
 126         if (ret)
 127                 return ret;
 128
 129         if (adev->powerplay.ip_funcs->early_init)
 130                 ret = adev->powerplay.ip_funcs->early_init(
 131                                         adev->powerplay.pp_handle);
 132         return ret;
 133 }
 134
 135
 136 static int amdgpu_pp_late_init(void *handle)
 137 {
 138         int ret = 0;
 139         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 140
 141         if (adev->powerplay.ip_funcs->late_init)
 142                 ret = adev->powerplay.ip_funcs->late_init(
 143                                         adev->powerplay.pp_handle);
 144
 145 #ifdef CONFIG_DRM_AMD_POWERPLAY
 146         if (adev->pp_enabled)
 147                 amdgpu_pm_sysfs_init(adev);
 148 #endif
 149         return ret;
 150 }
 151
 152 static int amdgpu_pp_sw_init(void *handle)
 153 {
 154         int ret = 0;
 155         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 156
 157         if (adev->powerplay.ip_funcs->sw_init)
 158                 ret = adev->powerplay.ip_funcs->sw_init(
 159                                         adev->powerplay.pp_handle);
 160
 161 #ifdef CONFIG_DRM_AMD_POWERPLAY
 162         if (adev->pp_enabled) {
 163                 if (amdgpu_dpm == 0)
 164                         adev->pm.dpm_enabled = false;
 165                 else
 166                         adev->pm.dpm_enabled = true;
 167         }
 168 #endif
 169
 170         return ret;
 171 }
 172
 173 static int amdgpu_pp_sw_fini(void *handle)
 174 {
 175         int ret = 0;
 176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 177
 178         if (adev->powerplay.ip_funcs->sw_fini)
 179                 ret = adev->powerplay.ip_funcs->sw_fini(
 180                                         adev->powerplay.pp_handle);
 181         if (ret)
 182                 return ret;
 183
 184 #ifdef CONFIG_DRM_AMD_POWERPLAY
 185         if (adev->pp_enabled) {
 186                 amdgpu_pm_sysfs_fini(adev);
 187                 amd_powerplay_fini(adev->powerplay.pp_handle);
 188         }
 189 #endif
 190
 191         return ret;
 192 }
 193
 194 static int amdgpu_pp_hw_init(void *handle)
 195 {
 196         int ret = 0;
 197         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 198
 199         if (adev->pp_enabled && adev->firmware.smu_load)
 200                 amdgpu_ucode_init_bo(adev);
 201
 202         if (adev->powerplay.ip_funcs->hw_init)
 203                 ret = adev->powerplay.ip_funcs->hw_init(
 204                                         adev->powerplay.pp_handle);
 205
 206         return ret;
 207 }
 208
 209 static int amdgpu_pp_hw_fini(void *handle)
 210 {
 211         int ret = 0;
 212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 213
 214         if (adev->powerplay.ip_funcs->hw_fini)
 215                 ret = adev->powerplay.ip_funcs->hw_fini(
 216                                         adev->powerplay.pp_handle);
 217
 218         if (adev->pp_enabled && adev->firmware.smu_load)
 219                 amdgpu_ucode_fini_bo(adev);
 220
 221         return ret;
 222 }
 223
 224 static int amdgpu_pp_suspend(void *handle)
 225 {
 226         int ret = 0;
 227         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 228
 229         if (adev->powerplay.ip_funcs->suspend)
 230                 ret = adev->powerplay.ip_funcs->suspend(
 231                                          adev->powerplay.pp_handle);
 232         return ret;
 233 }
 234
 235 static int amdgpu_pp_resume(void *handle)
 236 {
 237         int ret = 0;
 238         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 239
 240         if (adev->powerplay.ip_funcs->resume)
 241                 ret = adev->powerplay.ip_funcs->resume(
 242                                         adev->powerplay.pp_handle);
 243         return ret;
 244 }
 245
 246 static int amdgpu_pp_set_clockgating_state(void *handle,
 247                                         enum amd_clockgating_state state)
 248 {
 249         int ret = 0;
 250         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 251
 252         if (adev->powerplay.ip_funcs->set_clockgating_state)
 253                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 254                                 adev->powerplay.pp_handle, state);
 255         return ret;
 256 }
 257
 258 static int amdgpu_pp_set_powergating_state(void *handle,
 259                                         enum amd_powergating_state state)
 260 {
 261         int ret = 0;
 262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 263
 264         if (adev->powerplay.ip_funcs->set_powergating_state)
 265                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 266                                  adev->powerplay.pp_handle, state);
 267         return ret;
 268 }
 269
 270
 271 static bool amdgpu_pp_is_idle(void *handle)
 272 {
 273         bool ret = true;
 274         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 275
 276         if (adev->powerplay.ip_funcs->is_idle)
 277                 ret = adev->powerplay.ip_funcs->is_idle(
 278                                         adev->powerplay.pp_handle);
 279         return ret;
 280 }
 281
 282 static int amdgpu_pp_wait_for_idle(void *handle)
 283 {
 284         int ret = 0;
 285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 286
 287         if (adev->powerplay.ip_funcs->wait_for_idle)
 288                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 289                                         adev->powerplay.pp_handle);
 290         return ret;
 291 }
 292
 293 static int amdgpu_pp_soft_reset(void *handle)
 294 {
 295         int ret = 0;
 296         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 297
 298         if (adev->powerplay.ip_funcs->soft_reset)
 299                 ret = adev->powerplay.ip_funcs->soft_reset(
 300                                         adev->powerplay.pp_handle);
 301         return ret;
 302 }
 303
 304 static void amdgpu_pp_print_status(void *handle)
 305 {
 306         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 307
 308         if (adev->powerplay.ip_funcs->print_status)
 309                 adev->powerplay.ip_funcs->print_status(
 310                                         adev->powerplay.pp_handle);
 311 }
 312
 313 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 314         .early_init = amdgpu_pp_early_init,
 315         .late_init = amdgpu_pp_late_init,
 316         .sw_init = amdgpu_pp_sw_init,
 317         .sw_fini = amdgpu_pp_sw_fini,
 318         .hw_init = amdgpu_pp_hw_init,
 319         .hw_fini = amdgpu_pp_hw_fini,
 320         .suspend = amdgpu_pp_suspend,
 321         .resume = amdgpu_pp_resume,
 322         .is_idle = amdgpu_pp_is_idle,
 323         .wait_for_idle = amdgpu_pp_wait_for_idle,
 324         .soft_reset = amdgpu_pp_soft_reset,
 325         .print_status = amdgpu_pp_print_status,
 326         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 327         .set_powergating_state = amdgpu_pp_set_powergating_state,
 328 };