2 * Copyright 2009 VMware, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Michel Dänzer
25 #include <drm/amdgpu_drm.h>
27 #include "amdgpu_uvd.h"
28 #include "amdgpu_vce.h"
30 /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
31 static void amdgpu_do_test_moves(struct amdgpu_device
*adev
)
33 struct amdgpu_ring
*ring
= adev
->mman
.buffer_funcs_ring
;
34 struct amdgpu_bo
*vram_obj
= NULL
;
35 struct amdgpu_bo
**gtt_obj
= NULL
;
36 uint64_t gtt_addr
, vram_addr
;
43 * (Total GTT - IB pool - writeback page - ring buffers) / test size
45 n
= adev
->mc
.gtt_size
- AMDGPU_IB_POOL_SIZE
*64*1024;
46 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
48 n
-= adev
->rings
[i
]->ring_size
;
50 n
-= AMDGPU_GPU_PAGE_SIZE
;
51 if (adev
->irq
.ih
.ring_obj
)
52 n
-= adev
->irq
.ih
.ring_size
;
55 gtt_obj
= kzalloc(n
* sizeof(*gtt_obj
), GFP_KERNEL
);
57 DRM_ERROR("Failed to allocate %d pointers\n", n
);
62 r
= amdgpu_bo_create(adev
, size
, PAGE_SIZE
, true,
63 AMDGPU_GEM_DOMAIN_VRAM
, 0,
64 NULL
, NULL
, &vram_obj
);
66 DRM_ERROR("Failed to create VRAM object\n");
69 r
= amdgpu_bo_reserve(vram_obj
, false);
72 r
= amdgpu_bo_pin(vram_obj
, AMDGPU_GEM_DOMAIN_VRAM
, &vram_addr
);
74 DRM_ERROR("Failed to pin VRAM object\n");
77 for (i
= 0; i
< n
; i
++) {
78 void *gtt_map
, *vram_map
;
79 void **gtt_start
, **gtt_end
;
80 void **vram_start
, **vram_end
;
81 struct fence
*fence
= NULL
;
83 r
= amdgpu_bo_create(adev
, size
, PAGE_SIZE
, true,
84 AMDGPU_GEM_DOMAIN_GTT
, 0, NULL
,
87 DRM_ERROR("Failed to create GTT object %d\n", i
);
91 r
= amdgpu_bo_reserve(gtt_obj
[i
], false);
93 goto out_lclean_unref
;
94 r
= amdgpu_bo_pin(gtt_obj
[i
], AMDGPU_GEM_DOMAIN_GTT
, >t_addr
);
96 DRM_ERROR("Failed to pin GTT object %d\n", i
);
97 goto out_lclean_unres
;
100 r
= amdgpu_bo_kmap(gtt_obj
[i
], >t_map
);
102 DRM_ERROR("Failed to map GTT object %d\n", i
);
103 goto out_lclean_unpin
;
106 for (gtt_start
= gtt_map
, gtt_end
= gtt_map
+ size
;
109 *gtt_start
= gtt_start
;
111 amdgpu_bo_kunmap(gtt_obj
[i
]);
113 r
= amdgpu_copy_buffer(ring
, gtt_addr
, vram_addr
,
117 DRM_ERROR("Failed GTT->VRAM copy %d\n", i
);
118 goto out_lclean_unpin
;
121 r
= fence_wait(fence
, false);
123 DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i
);
124 goto out_lclean_unpin
;
129 r
= amdgpu_bo_kmap(vram_obj
, &vram_map
);
131 DRM_ERROR("Failed to map VRAM object after copy %d\n", i
);
132 goto out_lclean_unpin
;
135 for (gtt_start
= gtt_map
, gtt_end
= gtt_map
+ size
,
136 vram_start
= vram_map
, vram_end
= vram_map
+ size
;
137 vram_start
< vram_end
;
138 gtt_start
++, vram_start
++) {
139 if (*vram_start
!= gtt_start
) {
140 DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
141 "expected 0x%p (GTT/VRAM offset "
142 "0x%16llx/0x%16llx)\n",
143 i
, *vram_start
, gtt_start
,
145 (gtt_addr
- adev
->mc
.gtt_start
+
146 (void*)gtt_start
- gtt_map
),
148 (vram_addr
- adev
->mc
.vram_start
+
149 (void*)gtt_start
- gtt_map
));
150 amdgpu_bo_kunmap(vram_obj
);
151 goto out_lclean_unpin
;
153 *vram_start
= vram_start
;
156 amdgpu_bo_kunmap(vram_obj
);
158 r
= amdgpu_copy_buffer(ring
, vram_addr
, gtt_addr
,
162 DRM_ERROR("Failed VRAM->GTT copy %d\n", i
);
163 goto out_lclean_unpin
;
166 r
= fence_wait(fence
, false);
168 DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i
);
169 goto out_lclean_unpin
;
174 r
= amdgpu_bo_kmap(gtt_obj
[i
], >t_map
);
176 DRM_ERROR("Failed to map GTT object after copy %d\n", i
);
177 goto out_lclean_unpin
;
180 for (gtt_start
= gtt_map
, gtt_end
= gtt_map
+ size
,
181 vram_start
= vram_map
, vram_end
= vram_map
+ size
;
183 gtt_start
++, vram_start
++) {
184 if (*gtt_start
!= vram_start
) {
185 DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
186 "expected 0x%p (VRAM/GTT offset "
187 "0x%16llx/0x%16llx)\n",
188 i
, *gtt_start
, vram_start
,
190 (vram_addr
- adev
->mc
.vram_start
+
191 (void*)vram_start
- vram_map
),
193 (gtt_addr
- adev
->mc
.gtt_start
+
194 (void*)vram_start
- vram_map
));
195 amdgpu_bo_kunmap(gtt_obj
[i
]);
196 goto out_lclean_unpin
;
200 amdgpu_bo_kunmap(gtt_obj
[i
]);
202 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
203 gtt_addr
- adev
->mc
.gtt_start
);
207 amdgpu_bo_unpin(gtt_obj
[i
]);
209 amdgpu_bo_unreserve(gtt_obj
[i
]);
211 amdgpu_bo_unref(>t_obj
[i
]);
213 for (--i
; i
>= 0; --i
) {
214 amdgpu_bo_unpin(gtt_obj
[i
]);
215 amdgpu_bo_unreserve(gtt_obj
[i
]);
216 amdgpu_bo_unref(>t_obj
[i
]);
223 amdgpu_bo_unpin(vram_obj
);
225 amdgpu_bo_unreserve(vram_obj
);
227 amdgpu_bo_unref(&vram_obj
);
231 printk(KERN_WARNING
"Error while testing BO move.\n");
235 void amdgpu_test_moves(struct amdgpu_device
*adev
)
237 if (adev
->mman
.buffer_funcs
)
238 amdgpu_do_test_moves(adev
);
241 static int amdgpu_test_create_and_emit_fence(struct amdgpu_device
*adev
,
242 struct amdgpu_ring
*ring
,
243 struct fence
**fence
)
245 uint32_t handle
= ring
->idx
^ 0xdeafbeef;
248 if (ring
== &adev
->uvd
.ring
) {
249 r
= amdgpu_uvd_get_create_msg(ring
, handle
, NULL
);
251 DRM_ERROR("Failed to get dummy create msg\n");
255 r
= amdgpu_uvd_get_destroy_msg(ring
, handle
, fence
);
257 DRM_ERROR("Failed to get dummy destroy msg\n");
261 } else if (ring
== &adev
->vce
.ring
[0] ||
262 ring
== &adev
->vce
.ring
[1]) {
263 r
= amdgpu_vce_get_create_msg(ring
, handle
, NULL
);
265 DRM_ERROR("Failed to get dummy create msg\n");
269 r
= amdgpu_vce_get_destroy_msg(ring
, handle
, fence
);
271 DRM_ERROR("Failed to get dummy destroy msg\n");
275 struct amdgpu_fence
*a_fence
= NULL
;
276 r
= amdgpu_ring_lock(ring
, 64);
278 DRM_ERROR("Failed to lock ring A %d\n", ring
->idx
);
281 amdgpu_fence_emit(ring
, AMDGPU_FENCE_OWNER_UNDEFINED
, &a_fence
);
282 amdgpu_ring_unlock_commit(ring
);
283 *fence
= &a_fence
->base
;
288 void amdgpu_test_ring_sync(struct amdgpu_device
*adev
,
289 struct amdgpu_ring
*ringA
,
290 struct amdgpu_ring
*ringB
)
292 struct fence
*fence1
= NULL
, *fence2
= NULL
;
293 struct amdgpu_semaphore
*semaphore
= NULL
;
296 r
= amdgpu_semaphore_create(adev
, &semaphore
);
298 DRM_ERROR("Failed to create semaphore\n");
302 r
= amdgpu_ring_lock(ringA
, 64);
304 DRM_ERROR("Failed to lock ring A %d\n", ringA
->idx
);
307 amdgpu_semaphore_emit_wait(ringA
, semaphore
);
308 amdgpu_ring_unlock_commit(ringA
);
310 r
= amdgpu_test_create_and_emit_fence(adev
, ringA
, &fence1
);
314 r
= amdgpu_ring_lock(ringA
, 64);
316 DRM_ERROR("Failed to lock ring A %d\n", ringA
->idx
);
319 amdgpu_semaphore_emit_wait(ringA
, semaphore
);
320 amdgpu_ring_unlock_commit(ringA
);
322 r
= amdgpu_test_create_and_emit_fence(adev
, ringA
, &fence2
);
328 if (fence_is_signaled(fence1
)) {
329 DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
333 r
= amdgpu_ring_lock(ringB
, 64);
335 DRM_ERROR("Failed to lock ring B %p\n", ringB
);
338 amdgpu_semaphore_emit_signal(ringB
, semaphore
);
339 amdgpu_ring_unlock_commit(ringB
);
341 r
= fence_wait(fence1
, false);
343 DRM_ERROR("Failed to wait for sync fence 1\n");
349 if (fence_is_signaled(fence2
)) {
350 DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
354 r
= amdgpu_ring_lock(ringB
, 64);
356 DRM_ERROR("Failed to lock ring B %p\n", ringB
);
359 amdgpu_semaphore_emit_signal(ringB
, semaphore
);
360 amdgpu_ring_unlock_commit(ringB
);
362 r
= fence_wait(fence2
, false);
364 DRM_ERROR("Failed to wait for sync fence 1\n");
369 amdgpu_semaphore_free(adev
, &semaphore
, NULL
);
378 printk(KERN_WARNING
"Error while testing ring sync (%d).\n", r
);
381 static void amdgpu_test_ring_sync2(struct amdgpu_device
*adev
,
382 struct amdgpu_ring
*ringA
,
383 struct amdgpu_ring
*ringB
,
384 struct amdgpu_ring
*ringC
)
386 struct fence
*fenceA
= NULL
, *fenceB
= NULL
;
387 struct amdgpu_semaphore
*semaphore
= NULL
;
391 r
= amdgpu_semaphore_create(adev
, &semaphore
);
393 DRM_ERROR("Failed to create semaphore\n");
397 r
= amdgpu_ring_lock(ringA
, 64);
399 DRM_ERROR("Failed to lock ring A %d\n", ringA
->idx
);
402 amdgpu_semaphore_emit_wait(ringA
, semaphore
);
403 amdgpu_ring_unlock_commit(ringA
);
405 r
= amdgpu_test_create_and_emit_fence(adev
, ringA
, &fenceA
);
409 r
= amdgpu_ring_lock(ringB
, 64);
411 DRM_ERROR("Failed to lock ring B %d\n", ringB
->idx
);
414 amdgpu_semaphore_emit_wait(ringB
, semaphore
);
415 amdgpu_ring_unlock_commit(ringB
);
416 r
= amdgpu_test_create_and_emit_fence(adev
, ringB
, &fenceB
);
422 if (fence_is_signaled(fenceA
)) {
423 DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
426 if (fence_is_signaled(fenceB
)) {
427 DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
431 r
= amdgpu_ring_lock(ringC
, 64);
433 DRM_ERROR("Failed to lock ring B %p\n", ringC
);
436 amdgpu_semaphore_emit_signal(ringC
, semaphore
);
437 amdgpu_ring_unlock_commit(ringC
);
439 for (i
= 0; i
< 30; ++i
) {
441 sigA
= fence_is_signaled(fenceA
);
442 sigB
= fence_is_signaled(fenceB
);
447 if (!sigA
&& !sigB
) {
448 DRM_ERROR("Neither fence A nor B has been signaled\n");
450 } else if (sigA
&& sigB
) {
451 DRM_ERROR("Both fence A and B has been signaled\n");
455 DRM_INFO("Fence %c was first signaled\n", sigA
? 'A' : 'B');
457 r
= amdgpu_ring_lock(ringC
, 64);
459 DRM_ERROR("Failed to lock ring B %p\n", ringC
);
462 amdgpu_semaphore_emit_signal(ringC
, semaphore
);
463 amdgpu_ring_unlock_commit(ringC
);
467 r
= fence_wait(fenceA
, false);
469 DRM_ERROR("Failed to wait for sync fence A\n");
472 r
= fence_wait(fenceB
, false);
474 DRM_ERROR("Failed to wait for sync fence B\n");
479 amdgpu_semaphore_free(adev
, &semaphore
, NULL
);
488 printk(KERN_WARNING
"Error while testing ring sync (%d).\n", r
);
491 static bool amdgpu_test_sync_possible(struct amdgpu_ring
*ringA
,
492 struct amdgpu_ring
*ringB
)
494 if (ringA
== &ringA
->adev
->vce
.ring
[0] &&
495 ringB
== &ringB
->adev
->vce
.ring
[1])
501 void amdgpu_test_syncing(struct amdgpu_device
*adev
)
505 for (i
= 1; i
< AMDGPU_MAX_RINGS
; ++i
) {
506 struct amdgpu_ring
*ringA
= adev
->rings
[i
];
507 if (!ringA
|| !ringA
->ready
)
510 for (j
= 0; j
< i
; ++j
) {
511 struct amdgpu_ring
*ringB
= adev
->rings
[j
];
512 if (!ringB
|| !ringB
->ready
)
515 if (!amdgpu_test_sync_possible(ringA
, ringB
))
518 DRM_INFO("Testing syncing between rings %d and %d...\n", i
, j
);
519 amdgpu_test_ring_sync(adev
, ringA
, ringB
);
521 DRM_INFO("Testing syncing between rings %d and %d...\n", j
, i
);
522 amdgpu_test_ring_sync(adev
, ringB
, ringA
);
524 for (k
= 0; k
< j
; ++k
) {
525 struct amdgpu_ring
*ringC
= adev
->rings
[k
];
526 if (!ringC
|| !ringC
->ready
)
529 if (!amdgpu_test_sync_possible(ringA
, ringC
))
532 if (!amdgpu_test_sync_possible(ringB
, ringC
))
535 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i
, j
, k
);
536 amdgpu_test_ring_sync2(adev
, ringA
, ringB
, ringC
);
538 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i
, k
, j
);
539 amdgpu_test_ring_sync2(adev
, ringA
, ringC
, ringB
);
541 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j
, i
, k
);
542 amdgpu_test_ring_sync2(adev
, ringB
, ringA
, ringC
);
544 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j
, k
, i
);
545 amdgpu_test_ring_sync2(adev
, ringB
, ringC
, ringA
);
547 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k
, i
, j
);
548 amdgpu_test_ring_sync2(adev
, ringC
, ringA
, ringB
);
550 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k
, j
, i
);
551 amdgpu_test_ring_sync2(adev
, ringC
, ringB
, ringA
);