2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <ttm/ttm_bo_api.h>
33 #include <ttm/ttm_bo_driver.h>
34 #include <ttm/ttm_placement.h>
35 #include <ttm/ttm_module.h>
36 #include <ttm/ttm_page_alloc.h>
38 #include <drm/amdgpu_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swiotlb.h>
42 #include <linux/swap.h>
43 #include <linux/pagemap.h>
44 #include <linux/debugfs.h>
46 #include "bif/bif_4_1_d.h"
48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device
*adev
);
51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device
*adev
);
53 static struct amdgpu_device
*amdgpu_get_adev(struct ttm_bo_device
*bdev
)
55 struct amdgpu_mman
*mman
;
56 struct amdgpu_device
*adev
;
58 mman
= container_of(bdev
, struct amdgpu_mman
, bdev
);
59 adev
= container_of(mman
, struct amdgpu_device
, mman
);
67 static int amdgpu_ttm_mem_global_init(struct drm_global_reference
*ref
)
69 return ttm_mem_global_init(ref
->object
);
72 static void amdgpu_ttm_mem_global_release(struct drm_global_reference
*ref
)
74 ttm_mem_global_release(ref
->object
);
77 static int amdgpu_ttm_global_init(struct amdgpu_device
*adev
)
79 struct drm_global_reference
*global_ref
;
80 struct amdgpu_ring
*ring
;
81 struct amd_sched_rq
*rq
;
84 adev
->mman
.mem_global_referenced
= false;
85 global_ref
= &adev
->mman
.mem_global_ref
;
86 global_ref
->global_type
= DRM_GLOBAL_TTM_MEM
;
87 global_ref
->size
= sizeof(struct ttm_mem_global
);
88 global_ref
->init
= &amdgpu_ttm_mem_global_init
;
89 global_ref
->release
= &amdgpu_ttm_mem_global_release
;
90 r
= drm_global_item_ref(global_ref
);
92 DRM_ERROR("Failed setting up TTM memory accounting "
97 adev
->mman
.bo_global_ref
.mem_glob
=
98 adev
->mman
.mem_global_ref
.object
;
99 global_ref
= &adev
->mman
.bo_global_ref
.ref
;
100 global_ref
->global_type
= DRM_GLOBAL_TTM_BO
;
101 global_ref
->size
= sizeof(struct ttm_bo_global
);
102 global_ref
->init
= &ttm_bo_global_init
;
103 global_ref
->release
= &ttm_bo_global_release
;
104 r
= drm_global_item_ref(global_ref
);
106 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
107 drm_global_item_unref(&adev
->mman
.mem_global_ref
);
111 ring
= adev
->mman
.buffer_funcs_ring
;
112 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_KERNEL
];
113 r
= amd_sched_entity_init(&ring
->sched
, &adev
->mman
.entity
,
114 rq
, amdgpu_sched_jobs
);
116 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
117 drm_global_item_unref(&adev
->mman
.mem_global_ref
);
118 drm_global_item_unref(&adev
->mman
.bo_global_ref
.ref
);
122 adev
->mman
.mem_global_referenced
= true;
127 static void amdgpu_ttm_global_fini(struct amdgpu_device
*adev
)
129 if (adev
->mman
.mem_global_referenced
) {
130 amd_sched_entity_fini(adev
->mman
.entity
.sched
,
132 drm_global_item_unref(&adev
->mman
.bo_global_ref
.ref
);
133 drm_global_item_unref(&adev
->mman
.mem_global_ref
);
134 adev
->mman
.mem_global_referenced
= false;
138 static int amdgpu_invalidate_caches(struct ttm_bo_device
*bdev
, uint32_t flags
)
143 static int amdgpu_init_mem_type(struct ttm_bo_device
*bdev
, uint32_t type
,
144 struct ttm_mem_type_manager
*man
)
146 struct amdgpu_device
*adev
;
148 adev
= amdgpu_get_adev(bdev
);
153 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
154 man
->available_caching
= TTM_PL_MASK_CACHING
;
155 man
->default_caching
= TTM_PL_FLAG_CACHED
;
158 man
->func
= &ttm_bo_manager_func
;
159 man
->gpu_offset
= adev
->mc
.gtt_start
;
160 man
->available_caching
= TTM_PL_MASK_CACHING
;
161 man
->default_caching
= TTM_PL_FLAG_CACHED
;
162 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
| TTM_MEMTYPE_FLAG_CMA
;
165 /* "On-card" video ram */
166 man
->func
= &ttm_bo_manager_func
;
167 man
->gpu_offset
= adev
->mc
.vram_start
;
168 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
|
169 TTM_MEMTYPE_FLAG_MAPPABLE
;
170 man
->available_caching
= TTM_PL_FLAG_UNCACHED
| TTM_PL_FLAG_WC
;
171 man
->default_caching
= TTM_PL_FLAG_WC
;
176 /* On-chip GDS memory*/
177 man
->func
= &ttm_bo_manager_func
;
179 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
| TTM_MEMTYPE_FLAG_CMA
;
180 man
->available_caching
= TTM_PL_FLAG_UNCACHED
;
181 man
->default_caching
= TTM_PL_FLAG_UNCACHED
;
184 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type
);
190 static void amdgpu_evict_flags(struct ttm_buffer_object
*bo
,
191 struct ttm_placement
*placement
)
193 struct amdgpu_bo
*rbo
;
194 static struct ttm_place placements
= {
197 .flags
= TTM_PL_MASK_CACHING
| TTM_PL_FLAG_SYSTEM
200 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo
)) {
201 placement
->placement
= &placements
;
202 placement
->busy_placement
= &placements
;
203 placement
->num_placement
= 1;
204 placement
->num_busy_placement
= 1;
207 rbo
= container_of(bo
, struct amdgpu_bo
, tbo
);
208 switch (bo
->mem
.mem_type
) {
210 if (rbo
->adev
->mman
.buffer_funcs_ring
->ready
== false)
211 amdgpu_ttm_placement_from_domain(rbo
, AMDGPU_GEM_DOMAIN_CPU
);
213 amdgpu_ttm_placement_from_domain(rbo
, AMDGPU_GEM_DOMAIN_GTT
);
217 amdgpu_ttm_placement_from_domain(rbo
, AMDGPU_GEM_DOMAIN_CPU
);
219 *placement
= rbo
->placement
;
222 static int amdgpu_verify_access(struct ttm_buffer_object
*bo
, struct file
*filp
)
224 struct amdgpu_bo
*rbo
= container_of(bo
, struct amdgpu_bo
, tbo
);
226 if (amdgpu_ttm_tt_get_usermm(bo
->ttm
))
228 return drm_vma_node_verify_access(&rbo
->gem_base
.vma_node
, filp
);
231 static void amdgpu_move_null(struct ttm_buffer_object
*bo
,
232 struct ttm_mem_reg
*new_mem
)
234 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
236 BUG_ON(old_mem
->mm_node
!= NULL
);
238 new_mem
->mm_node
= NULL
;
241 static int amdgpu_move_blit(struct ttm_buffer_object
*bo
,
242 bool evict
, bool no_wait_gpu
,
243 struct ttm_mem_reg
*new_mem
,
244 struct ttm_mem_reg
*old_mem
)
246 struct amdgpu_device
*adev
;
247 struct amdgpu_ring
*ring
;
248 uint64_t old_start
, new_start
;
252 adev
= amdgpu_get_adev(bo
->bdev
);
253 ring
= adev
->mman
.buffer_funcs_ring
;
254 old_start
= (u64
)old_mem
->start
<< PAGE_SHIFT
;
255 new_start
= (u64
)new_mem
->start
<< PAGE_SHIFT
;
257 switch (old_mem
->mem_type
) {
259 old_start
+= adev
->mc
.vram_start
;
262 old_start
+= adev
->mc
.gtt_start
;
265 DRM_ERROR("Unknown placement %d\n", old_mem
->mem_type
);
268 switch (new_mem
->mem_type
) {
270 new_start
+= adev
->mc
.vram_start
;
273 new_start
+= adev
->mc
.gtt_start
;
276 DRM_ERROR("Unknown placement %d\n", old_mem
->mem_type
);
280 DRM_ERROR("Trying to move memory with ring turned off.\n");
284 BUILD_BUG_ON((PAGE_SIZE
% AMDGPU_GPU_PAGE_SIZE
) != 0);
286 r
= amdgpu_copy_buffer(ring
, old_start
, new_start
,
287 new_mem
->num_pages
* PAGE_SIZE
, /* bytes */
292 r
= ttm_bo_pipeline_move(bo
, fence
, evict
, new_mem
);
297 static int amdgpu_move_vram_ram(struct ttm_buffer_object
*bo
,
298 bool evict
, bool interruptible
,
300 struct ttm_mem_reg
*new_mem
)
302 struct amdgpu_device
*adev
;
303 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
304 struct ttm_mem_reg tmp_mem
;
305 struct ttm_place placements
;
306 struct ttm_placement placement
;
309 adev
= amdgpu_get_adev(bo
->bdev
);
311 tmp_mem
.mm_node
= NULL
;
312 placement
.num_placement
= 1;
313 placement
.placement
= &placements
;
314 placement
.num_busy_placement
= 1;
315 placement
.busy_placement
= &placements
;
318 placements
.flags
= TTM_PL_MASK_CACHING
| TTM_PL_FLAG_TT
;
319 r
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
,
320 interruptible
, no_wait_gpu
);
325 r
= ttm_tt_set_placement_caching(bo
->ttm
, tmp_mem
.placement
);
330 r
= ttm_tt_bind(bo
->ttm
, &tmp_mem
);
334 r
= amdgpu_move_blit(bo
, true, no_wait_gpu
, &tmp_mem
, old_mem
);
338 r
= ttm_bo_move_ttm(bo
, true, interruptible
, no_wait_gpu
, new_mem
);
340 ttm_bo_mem_put(bo
, &tmp_mem
);
344 static int amdgpu_move_ram_vram(struct ttm_buffer_object
*bo
,
345 bool evict
, bool interruptible
,
347 struct ttm_mem_reg
*new_mem
)
349 struct amdgpu_device
*adev
;
350 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
351 struct ttm_mem_reg tmp_mem
;
352 struct ttm_placement placement
;
353 struct ttm_place placements
;
356 adev
= amdgpu_get_adev(bo
->bdev
);
358 tmp_mem
.mm_node
= NULL
;
359 placement
.num_placement
= 1;
360 placement
.placement
= &placements
;
361 placement
.num_busy_placement
= 1;
362 placement
.busy_placement
= &placements
;
365 placements
.flags
= TTM_PL_MASK_CACHING
| TTM_PL_FLAG_TT
;
366 r
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
,
367 interruptible
, no_wait_gpu
);
371 r
= ttm_bo_move_ttm(bo
, true, interruptible
, no_wait_gpu
, &tmp_mem
);
375 r
= amdgpu_move_blit(bo
, true, no_wait_gpu
, new_mem
, old_mem
);
380 ttm_bo_mem_put(bo
, &tmp_mem
);
384 static int amdgpu_bo_move(struct ttm_buffer_object
*bo
,
385 bool evict
, bool interruptible
,
387 struct ttm_mem_reg
*new_mem
)
389 struct amdgpu_device
*adev
;
390 struct amdgpu_bo
*abo
;
391 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
394 /* Can't move a pinned BO */
395 abo
= container_of(bo
, struct amdgpu_bo
, tbo
);
396 if (WARN_ON_ONCE(abo
->pin_count
> 0))
399 adev
= amdgpu_get_adev(bo
->bdev
);
401 /* remember the eviction */
403 atomic64_inc(&adev
->num_evictions
);
405 if (old_mem
->mem_type
== TTM_PL_SYSTEM
&& bo
->ttm
== NULL
) {
406 amdgpu_move_null(bo
, new_mem
);
409 if ((old_mem
->mem_type
== TTM_PL_TT
&&
410 new_mem
->mem_type
== TTM_PL_SYSTEM
) ||
411 (old_mem
->mem_type
== TTM_PL_SYSTEM
&&
412 new_mem
->mem_type
== TTM_PL_TT
)) {
414 amdgpu_move_null(bo
, new_mem
);
417 if (adev
->mman
.buffer_funcs
== NULL
||
418 adev
->mman
.buffer_funcs_ring
== NULL
||
419 !adev
->mman
.buffer_funcs_ring
->ready
) {
424 if (old_mem
->mem_type
== TTM_PL_VRAM
&&
425 new_mem
->mem_type
== TTM_PL_SYSTEM
) {
426 r
= amdgpu_move_vram_ram(bo
, evict
, interruptible
,
427 no_wait_gpu
, new_mem
);
428 } else if (old_mem
->mem_type
== TTM_PL_SYSTEM
&&
429 new_mem
->mem_type
== TTM_PL_VRAM
) {
430 r
= amdgpu_move_ram_vram(bo
, evict
, interruptible
,
431 no_wait_gpu
, new_mem
);
433 r
= amdgpu_move_blit(bo
, evict
, no_wait_gpu
, new_mem
, old_mem
);
438 r
= ttm_bo_move_memcpy(bo
, evict
, interruptible
,
439 no_wait_gpu
, new_mem
);
445 /* update statistics */
446 atomic64_add((u64
)bo
->num_pages
<< PAGE_SHIFT
, &adev
->num_bytes_moved
);
450 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
452 struct ttm_mem_type_manager
*man
= &bdev
->man
[mem
->mem_type
];
453 struct amdgpu_device
*adev
= amdgpu_get_adev(bdev
);
455 mem
->bus
.addr
= NULL
;
457 mem
->bus
.size
= mem
->num_pages
<< PAGE_SHIFT
;
459 mem
->bus
.is_iomem
= false;
460 if (!(man
->flags
& TTM_MEMTYPE_FLAG_MAPPABLE
))
462 switch (mem
->mem_type
) {
469 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
470 /* check if it's visible */
471 if ((mem
->bus
.offset
+ mem
->bus
.size
) > adev
->mc
.visible_vram_size
)
473 mem
->bus
.base
= adev
->mc
.aper_base
;
474 mem
->bus
.is_iomem
= true;
477 * Alpha: use bus.addr to hold the ioremap() return,
478 * so we can modify bus.base below.
480 if (mem
->placement
& TTM_PL_FLAG_WC
)
482 ioremap_wc(mem
->bus
.base
+ mem
->bus
.offset
,
486 ioremap_nocache(mem
->bus
.base
+ mem
->bus
.offset
,
490 * Alpha: Use just the bus offset plus
491 * the hose/domain memory base for bus.base.
492 * It then can be used to build PTEs for VRAM
493 * access, as done in ttm_bo_vm_fault().
495 mem
->bus
.base
= (mem
->bus
.base
& 0x0ffffffffUL
) +
496 adev
->ddev
->hose
->dense_mem_base
;
505 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
510 * TTM backend functions.
512 struct amdgpu_ttm_gup_task_list
{
513 struct list_head list
;
514 struct task_struct
*task
;
517 struct amdgpu_ttm_tt
{
518 struct ttm_dma_tt ttm
;
519 struct amdgpu_device
*adev
;
522 struct mm_struct
*usermm
;
524 spinlock_t guptasklock
;
525 struct list_head guptasks
;
526 atomic_t mmu_invalidations
;
529 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt
*ttm
, struct page
**pages
)
531 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
532 int write
= !(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
536 if (gtt
->userflags
& AMDGPU_GEM_USERPTR_ANONONLY
) {
537 /* check that we only use anonymous memory
538 to prevent problems with writeback */
539 unsigned long end
= gtt
->userptr
+ ttm
->num_pages
* PAGE_SIZE
;
540 struct vm_area_struct
*vma
;
542 vma
= find_vma(gtt
->usermm
, gtt
->userptr
);
543 if (!vma
|| vma
->vm_file
|| vma
->vm_end
< end
)
548 unsigned num_pages
= ttm
->num_pages
- pinned
;
549 uint64_t userptr
= gtt
->userptr
+ pinned
* PAGE_SIZE
;
550 struct page
**p
= pages
+ pinned
;
551 struct amdgpu_ttm_gup_task_list guptask
;
553 guptask
.task
= current
;
554 spin_lock(>t
->guptasklock
);
555 list_add(&guptask
.list
, >t
->guptasks
);
556 spin_unlock(>t
->guptasklock
);
558 r
= get_user_pages(userptr
, num_pages
, write
, 0, p
, NULL
);
560 spin_lock(>t
->guptasklock
);
561 list_del(&guptask
.list
);
562 spin_unlock(>t
->guptasklock
);
569 } while (pinned
< ttm
->num_pages
);
574 release_pages(pages
, pinned
, 0);
578 /* prepare the sg table with the user pages */
579 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt
*ttm
)
581 struct amdgpu_device
*adev
= amdgpu_get_adev(ttm
->bdev
);
582 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
586 int write
= !(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
587 enum dma_data_direction direction
= write
?
588 DMA_BIDIRECTIONAL
: DMA_TO_DEVICE
;
590 r
= sg_alloc_table_from_pages(ttm
->sg
, ttm
->pages
, ttm
->num_pages
, 0,
591 ttm
->num_pages
<< PAGE_SHIFT
,
597 nents
= dma_map_sg(adev
->dev
, ttm
->sg
->sgl
, ttm
->sg
->nents
, direction
);
598 if (nents
!= ttm
->sg
->nents
)
601 drm_prime_sg_to_page_addr_arrays(ttm
->sg
, ttm
->pages
,
602 gtt
->ttm
.dma_address
, ttm
->num_pages
);
611 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt
*ttm
)
613 struct amdgpu_device
*adev
= amdgpu_get_adev(ttm
->bdev
);
614 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
615 struct sg_page_iter sg_iter
;
617 int write
= !(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
618 enum dma_data_direction direction
= write
?
619 DMA_BIDIRECTIONAL
: DMA_TO_DEVICE
;
621 /* double check that we don't free the table twice */
625 /* free the sg table and pages again */
626 dma_unmap_sg(adev
->dev
, ttm
->sg
->sgl
, ttm
->sg
->nents
, direction
);
628 for_each_sg_page(ttm
->sg
->sgl
, &sg_iter
, ttm
->sg
->nents
, 0) {
629 struct page
*page
= sg_page_iter_page(&sg_iter
);
630 if (!(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
))
631 set_page_dirty(page
);
633 mark_page_accessed(page
);
637 sg_free_table(ttm
->sg
);
640 static int amdgpu_ttm_backend_bind(struct ttm_tt
*ttm
,
641 struct ttm_mem_reg
*bo_mem
)
643 struct amdgpu_ttm_tt
*gtt
= (void*)ttm
;
644 uint32_t flags
= amdgpu_ttm_tt_pte_flags(gtt
->adev
, ttm
, bo_mem
);
648 r
= amdgpu_ttm_tt_pin_userptr(ttm
);
650 DRM_ERROR("failed to pin userptr\n");
654 gtt
->offset
= (unsigned long)(bo_mem
->start
<< PAGE_SHIFT
);
655 if (!ttm
->num_pages
) {
656 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
657 ttm
->num_pages
, bo_mem
, ttm
);
660 if (bo_mem
->mem_type
== AMDGPU_PL_GDS
||
661 bo_mem
->mem_type
== AMDGPU_PL_GWS
||
662 bo_mem
->mem_type
== AMDGPU_PL_OA
)
665 r
= amdgpu_gart_bind(gtt
->adev
, gtt
->offset
, ttm
->num_pages
,
666 ttm
->pages
, gtt
->ttm
.dma_address
, flags
);
669 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
670 ttm
->num_pages
, (unsigned)gtt
->offset
);
676 static int amdgpu_ttm_backend_unbind(struct ttm_tt
*ttm
)
678 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
680 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
681 if (gtt
->adev
->gart
.ready
)
682 amdgpu_gart_unbind(gtt
->adev
, gtt
->offset
, ttm
->num_pages
);
685 amdgpu_ttm_tt_unpin_userptr(ttm
);
690 static void amdgpu_ttm_backend_destroy(struct ttm_tt
*ttm
)
692 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
694 ttm_dma_tt_fini(>t
->ttm
);
698 static struct ttm_backend_func amdgpu_backend_func
= {
699 .bind
= &amdgpu_ttm_backend_bind
,
700 .unbind
= &amdgpu_ttm_backend_unbind
,
701 .destroy
= &amdgpu_ttm_backend_destroy
,
704 static struct ttm_tt
*amdgpu_ttm_tt_create(struct ttm_bo_device
*bdev
,
705 unsigned long size
, uint32_t page_flags
,
706 struct page
*dummy_read_page
)
708 struct amdgpu_device
*adev
;
709 struct amdgpu_ttm_tt
*gtt
;
711 adev
= amdgpu_get_adev(bdev
);
713 gtt
= kzalloc(sizeof(struct amdgpu_ttm_tt
), GFP_KERNEL
);
717 gtt
->ttm
.ttm
.func
= &amdgpu_backend_func
;
719 if (ttm_dma_tt_init(>t
->ttm
, bdev
, size
, page_flags
, dummy_read_page
)) {
723 return >t
->ttm
.ttm
;
726 static int amdgpu_ttm_tt_populate(struct ttm_tt
*ttm
)
728 struct amdgpu_device
*adev
;
729 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
732 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
734 if (ttm
->state
!= tt_unpopulated
)
737 if (gtt
&& gtt
->userptr
) {
738 ttm
->sg
= kzalloc(sizeof(struct sg_table
), GFP_KERNEL
);
742 ttm
->page_flags
|= TTM_PAGE_FLAG_SG
;
743 ttm
->state
= tt_unbound
;
747 if (slave
&& ttm
->sg
) {
748 drm_prime_sg_to_page_addr_arrays(ttm
->sg
, ttm
->pages
,
749 gtt
->ttm
.dma_address
, ttm
->num_pages
);
750 ttm
->state
= tt_unbound
;
754 adev
= amdgpu_get_adev(ttm
->bdev
);
756 #ifdef CONFIG_SWIOTLB
757 if (swiotlb_nr_tbl()) {
758 return ttm_dma_populate(>t
->ttm
, adev
->dev
);
762 r
= ttm_pool_populate(ttm
);
767 for (i
= 0; i
< ttm
->num_pages
; i
++) {
768 gtt
->ttm
.dma_address
[i
] = pci_map_page(adev
->pdev
, ttm
->pages
[i
],
770 PCI_DMA_BIDIRECTIONAL
);
771 if (pci_dma_mapping_error(adev
->pdev
, gtt
->ttm
.dma_address
[i
])) {
773 pci_unmap_page(adev
->pdev
, gtt
->ttm
.dma_address
[i
],
774 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
775 gtt
->ttm
.dma_address
[i
] = 0;
777 ttm_pool_unpopulate(ttm
);
784 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt
*ttm
)
786 struct amdgpu_device
*adev
;
787 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
789 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
791 if (gtt
&& gtt
->userptr
) {
793 ttm
->page_flags
&= ~TTM_PAGE_FLAG_SG
;
800 adev
= amdgpu_get_adev(ttm
->bdev
);
802 #ifdef CONFIG_SWIOTLB
803 if (swiotlb_nr_tbl()) {
804 ttm_dma_unpopulate(>t
->ttm
, adev
->dev
);
809 for (i
= 0; i
< ttm
->num_pages
; i
++) {
810 if (gtt
->ttm
.dma_address
[i
]) {
811 pci_unmap_page(adev
->pdev
, gtt
->ttm
.dma_address
[i
],
812 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
816 ttm_pool_unpopulate(ttm
);
819 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
822 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
828 gtt
->usermm
= current
->mm
;
829 gtt
->userflags
= flags
;
830 spin_lock_init(>t
->guptasklock
);
831 INIT_LIST_HEAD(>t
->guptasks
);
832 atomic_set(>t
->mmu_invalidations
, 0);
837 struct mm_struct
*amdgpu_ttm_tt_get_usermm(struct ttm_tt
*ttm
)
839 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
847 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt
*ttm
, unsigned long start
,
850 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
851 struct amdgpu_ttm_gup_task_list
*entry
;
854 if (gtt
== NULL
|| !gtt
->userptr
)
857 size
= (unsigned long)gtt
->ttm
.ttm
.num_pages
* PAGE_SIZE
;
858 if (gtt
->userptr
> end
|| gtt
->userptr
+ size
<= start
)
861 spin_lock(>t
->guptasklock
);
862 list_for_each_entry(entry
, >t
->guptasks
, list
) {
863 if (entry
->task
== current
) {
864 spin_unlock(>t
->guptasklock
);
868 spin_unlock(>t
->guptasklock
);
870 atomic_inc(>t
->mmu_invalidations
);
875 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt
*ttm
,
876 int *last_invalidated
)
878 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
879 int prev_invalidated
= *last_invalidated
;
881 *last_invalidated
= atomic_read(>t
->mmu_invalidations
);
882 return prev_invalidated
!= *last_invalidated
;
885 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
)
887 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
892 return !!(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
895 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
896 struct ttm_mem_reg
*mem
)
900 if (mem
&& mem
->mem_type
!= TTM_PL_SYSTEM
)
901 flags
|= AMDGPU_PTE_VALID
;
903 if (mem
&& mem
->mem_type
== TTM_PL_TT
) {
904 flags
|= AMDGPU_PTE_SYSTEM
;
906 if (ttm
->caching_state
== tt_cached
)
907 flags
|= AMDGPU_PTE_SNOOPED
;
910 if (adev
->asic_type
>= CHIP_TONGA
)
911 flags
|= AMDGPU_PTE_EXECUTABLE
;
913 flags
|= AMDGPU_PTE_READABLE
;
915 if (!amdgpu_ttm_tt_is_readonly(ttm
))
916 flags
|= AMDGPU_PTE_WRITEABLE
;
921 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object
*tbo
)
923 struct amdgpu_device
*adev
= amdgpu_get_adev(tbo
->bdev
);
926 for (i
= 0; i
< AMDGPU_TTM_LRU_SIZE
; ++i
) {
927 struct amdgpu_mman_lru
*lru
= &adev
->mman
.log2_size
[i
];
929 for (j
= 0; j
< TTM_NUM_MEM_TYPES
; ++j
)
930 if (&tbo
->lru
== lru
->lru
[j
])
931 lru
->lru
[j
] = tbo
->lru
.prev
;
933 if (&tbo
->swap
== lru
->swap_lru
)
934 lru
->swap_lru
= tbo
->swap
.prev
;
938 static struct amdgpu_mman_lru
*amdgpu_ttm_lru(struct ttm_buffer_object
*tbo
)
940 struct amdgpu_device
*adev
= amdgpu_get_adev(tbo
->bdev
);
941 unsigned log2_size
= min(ilog2(tbo
->num_pages
),
942 AMDGPU_TTM_LRU_SIZE
- 1);
944 return &adev
->mman
.log2_size
[log2_size
];
947 static struct list_head
*amdgpu_ttm_lru_tail(struct ttm_buffer_object
*tbo
)
949 struct amdgpu_mman_lru
*lru
= amdgpu_ttm_lru(tbo
);
950 struct list_head
*res
= lru
->lru
[tbo
->mem
.mem_type
];
952 lru
->lru
[tbo
->mem
.mem_type
] = &tbo
->lru
;
953 while ((++lru
)->lru
[tbo
->mem
.mem_type
] == res
)
954 lru
->lru
[tbo
->mem
.mem_type
] = &tbo
->lru
;
959 static struct list_head
*amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object
*tbo
)
961 struct amdgpu_mman_lru
*lru
= amdgpu_ttm_lru(tbo
);
962 struct list_head
*res
= lru
->swap_lru
;
964 lru
->swap_lru
= &tbo
->swap
;
965 while ((++lru
)->swap_lru
== res
)
966 lru
->swap_lru
= &tbo
->swap
;
971 static struct ttm_bo_driver amdgpu_bo_driver
= {
972 .ttm_tt_create
= &amdgpu_ttm_tt_create
,
973 .ttm_tt_populate
= &amdgpu_ttm_tt_populate
,
974 .ttm_tt_unpopulate
= &amdgpu_ttm_tt_unpopulate
,
975 .invalidate_caches
= &amdgpu_invalidate_caches
,
976 .init_mem_type
= &amdgpu_init_mem_type
,
977 .evict_flags
= &amdgpu_evict_flags
,
978 .move
= &amdgpu_bo_move
,
979 .verify_access
= &amdgpu_verify_access
,
980 .move_notify
= &amdgpu_bo_move_notify
,
981 .fault_reserve_notify
= &amdgpu_bo_fault_reserve_notify
,
982 .io_mem_reserve
= &amdgpu_ttm_io_mem_reserve
,
983 .io_mem_free
= &amdgpu_ttm_io_mem_free
,
984 .lru_removal
= &amdgpu_ttm_lru_removal
,
985 .lru_tail
= &amdgpu_ttm_lru_tail
,
986 .swap_lru_tail
= &amdgpu_ttm_swap_lru_tail
,
989 int amdgpu_ttm_init(struct amdgpu_device
*adev
)
994 r
= amdgpu_ttm_global_init(adev
);
998 /* No others user of address space so set it to 0 */
999 r
= ttm_bo_device_init(&adev
->mman
.bdev
,
1000 adev
->mman
.bo_global_ref
.ref
.object
,
1002 adev
->ddev
->anon_inode
->i_mapping
,
1003 DRM_FILE_PAGE_OFFSET
,
1006 DRM_ERROR("failed initializing buffer object driver(%d).\n", r
);
1010 for (i
= 0; i
< AMDGPU_TTM_LRU_SIZE
; ++i
) {
1011 struct amdgpu_mman_lru
*lru
= &adev
->mman
.log2_size
[i
];
1013 for (j
= 0; j
< TTM_NUM_MEM_TYPES
; ++j
)
1014 lru
->lru
[j
] = &adev
->mman
.bdev
.man
[j
].lru
;
1015 lru
->swap_lru
= &adev
->mman
.bdev
.glob
->swap_lru
;
1018 for (j
= 0; j
< TTM_NUM_MEM_TYPES
; ++j
)
1019 adev
->mman
.guard
.lru
[j
] = NULL
;
1020 adev
->mman
.guard
.swap_lru
= NULL
;
1022 adev
->mman
.initialized
= true;
1023 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, TTM_PL_VRAM
,
1024 adev
->mc
.real_vram_size
>> PAGE_SHIFT
);
1026 DRM_ERROR("Failed initializing VRAM heap.\n");
1029 /* Change the size here instead of the init above so only lpfn is affected */
1030 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
1032 r
= amdgpu_bo_create(adev
, 256 * 1024, PAGE_SIZE
, true,
1033 AMDGPU_GEM_DOMAIN_VRAM
,
1034 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
1035 NULL
, NULL
, &adev
->stollen_vga_memory
);
1039 r
= amdgpu_bo_reserve(adev
->stollen_vga_memory
, false);
1042 r
= amdgpu_bo_pin(adev
->stollen_vga_memory
, AMDGPU_GEM_DOMAIN_VRAM
, NULL
);
1043 amdgpu_bo_unreserve(adev
->stollen_vga_memory
);
1045 amdgpu_bo_unref(&adev
->stollen_vga_memory
);
1048 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1049 (unsigned) (adev
->mc
.real_vram_size
/ (1024 * 1024)));
1050 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, TTM_PL_TT
,
1051 adev
->mc
.gtt_size
>> PAGE_SHIFT
);
1053 DRM_ERROR("Failed initializing GTT heap.\n");
1056 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1057 (unsigned)(adev
->mc
.gtt_size
/ (1024 * 1024)));
1059 adev
->gds
.mem
.total_size
= adev
->gds
.mem
.total_size
<< AMDGPU_GDS_SHIFT
;
1060 adev
->gds
.mem
.gfx_partition_size
= adev
->gds
.mem
.gfx_partition_size
<< AMDGPU_GDS_SHIFT
;
1061 adev
->gds
.mem
.cs_partition_size
= adev
->gds
.mem
.cs_partition_size
<< AMDGPU_GDS_SHIFT
;
1062 adev
->gds
.gws
.total_size
= adev
->gds
.gws
.total_size
<< AMDGPU_GWS_SHIFT
;
1063 adev
->gds
.gws
.gfx_partition_size
= adev
->gds
.gws
.gfx_partition_size
<< AMDGPU_GWS_SHIFT
;
1064 adev
->gds
.gws
.cs_partition_size
= adev
->gds
.gws
.cs_partition_size
<< AMDGPU_GWS_SHIFT
;
1065 adev
->gds
.oa
.total_size
= adev
->gds
.oa
.total_size
<< AMDGPU_OA_SHIFT
;
1066 adev
->gds
.oa
.gfx_partition_size
= adev
->gds
.oa
.gfx_partition_size
<< AMDGPU_OA_SHIFT
;
1067 adev
->gds
.oa
.cs_partition_size
= adev
->gds
.oa
.cs_partition_size
<< AMDGPU_OA_SHIFT
;
1069 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, AMDGPU_PL_GDS
,
1070 adev
->gds
.mem
.total_size
>> PAGE_SHIFT
);
1072 DRM_ERROR("Failed initializing GDS heap.\n");
1077 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, AMDGPU_PL_GWS
,
1078 adev
->gds
.gws
.total_size
>> PAGE_SHIFT
);
1080 DRM_ERROR("Failed initializing gws heap.\n");
1085 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, AMDGPU_PL_OA
,
1086 adev
->gds
.oa
.total_size
>> PAGE_SHIFT
);
1088 DRM_ERROR("Failed initializing oa heap.\n");
1092 r
= amdgpu_ttm_debugfs_init(adev
);
1094 DRM_ERROR("Failed to init debugfs\n");
1100 void amdgpu_ttm_fini(struct amdgpu_device
*adev
)
1104 if (!adev
->mman
.initialized
)
1106 amdgpu_ttm_debugfs_fini(adev
);
1107 if (adev
->stollen_vga_memory
) {
1108 r
= amdgpu_bo_reserve(adev
->stollen_vga_memory
, false);
1110 amdgpu_bo_unpin(adev
->stollen_vga_memory
);
1111 amdgpu_bo_unreserve(adev
->stollen_vga_memory
);
1113 amdgpu_bo_unref(&adev
->stollen_vga_memory
);
1115 ttm_bo_clean_mm(&adev
->mman
.bdev
, TTM_PL_VRAM
);
1116 ttm_bo_clean_mm(&adev
->mman
.bdev
, TTM_PL_TT
);
1117 ttm_bo_clean_mm(&adev
->mman
.bdev
, AMDGPU_PL_GDS
);
1118 ttm_bo_clean_mm(&adev
->mman
.bdev
, AMDGPU_PL_GWS
);
1119 ttm_bo_clean_mm(&adev
->mman
.bdev
, AMDGPU_PL_OA
);
1120 ttm_bo_device_release(&adev
->mman
.bdev
);
1121 amdgpu_gart_fini(adev
);
1122 amdgpu_ttm_global_fini(adev
);
1123 adev
->mman
.initialized
= false;
1124 DRM_INFO("amdgpu: ttm finalized\n");
1127 /* this should only be called at bootup or when userspace
1129 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
)
1131 struct ttm_mem_type_manager
*man
;
1133 if (!adev
->mman
.initialized
)
1136 man
= &adev
->mman
.bdev
.man
[TTM_PL_VRAM
];
1137 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1138 man
->size
= size
>> PAGE_SHIFT
;
1141 int amdgpu_mmap(struct file
*filp
, struct vm_area_struct
*vma
)
1143 struct drm_file
*file_priv
;
1144 struct amdgpu_device
*adev
;
1146 if (unlikely(vma
->vm_pgoff
< DRM_FILE_PAGE_OFFSET
))
1149 file_priv
= filp
->private_data
;
1150 adev
= file_priv
->minor
->dev
->dev_private
;
1154 return ttm_bo_mmap(filp
, vma
, &adev
->mman
.bdev
);
1157 int amdgpu_copy_buffer(struct amdgpu_ring
*ring
,
1158 uint64_t src_offset
,
1159 uint64_t dst_offset
,
1160 uint32_t byte_count
,
1161 struct reservation_object
*resv
,
1162 struct fence
**fence
)
1164 struct amdgpu_device
*adev
= ring
->adev
;
1165 struct amdgpu_job
*job
;
1168 unsigned num_loops
, num_dw
;
1172 max_bytes
= adev
->mman
.buffer_funcs
->copy_max_bytes
;
1173 num_loops
= DIV_ROUND_UP(byte_count
, max_bytes
);
1174 num_dw
= num_loops
* adev
->mman
.buffer_funcs
->copy_num_dw
;
1176 /* for IB padding */
1177 while (num_dw
& 0x7)
1180 r
= amdgpu_job_alloc_with_ib(adev
, num_dw
* 4, &job
);
1185 r
= amdgpu_sync_resv(adev
, &job
->sync
, resv
,
1186 AMDGPU_FENCE_OWNER_UNDEFINED
);
1188 DRM_ERROR("sync failed (%d).\n", r
);
1193 for (i
= 0; i
< num_loops
; i
++) {
1194 uint32_t cur_size_in_bytes
= min(byte_count
, max_bytes
);
1196 amdgpu_emit_copy_buffer(adev
, &job
->ibs
[0], src_offset
,
1197 dst_offset
, cur_size_in_bytes
);
1199 src_offset
+= cur_size_in_bytes
;
1200 dst_offset
+= cur_size_in_bytes
;
1201 byte_count
-= cur_size_in_bytes
;
1204 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
1205 WARN_ON(job
->ibs
[0].length_dw
> num_dw
);
1206 r
= amdgpu_job_submit(job
, ring
, &adev
->mman
.entity
,
1207 AMDGPU_FENCE_OWNER_UNDEFINED
, fence
);
1214 amdgpu_job_free(job
);
1218 #if defined(CONFIG_DEBUG_FS)
1220 static int amdgpu_mm_dump_table(struct seq_file
*m
, void *data
)
1222 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1223 unsigned ttm_pl
= *(int *)node
->info_ent
->data
;
1224 struct drm_device
*dev
= node
->minor
->dev
;
1225 struct amdgpu_device
*adev
= dev
->dev_private
;
1226 struct drm_mm
*mm
= (struct drm_mm
*)adev
->mman
.bdev
.man
[ttm_pl
].priv
;
1228 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
1230 spin_lock(&glob
->lru_lock
);
1231 ret
= drm_mm_dump_table(m
, mm
);
1232 spin_unlock(&glob
->lru_lock
);
1233 if (ttm_pl
== TTM_PL_VRAM
)
1234 seq_printf(m
, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1235 adev
->mman
.bdev
.man
[ttm_pl
].size
,
1236 (u64
)atomic64_read(&adev
->vram_usage
) >> 20,
1237 (u64
)atomic64_read(&adev
->vram_vis_usage
) >> 20);
1241 static int ttm_pl_vram
= TTM_PL_VRAM
;
1242 static int ttm_pl_tt
= TTM_PL_TT
;
1244 static const struct drm_info_list amdgpu_ttm_debugfs_list
[] = {
1245 {"amdgpu_vram_mm", amdgpu_mm_dump_table
, 0, &ttm_pl_vram
},
1246 {"amdgpu_gtt_mm", amdgpu_mm_dump_table
, 0, &ttm_pl_tt
},
1247 {"ttm_page_pool", ttm_page_alloc_debugfs
, 0, NULL
},
1248 #ifdef CONFIG_SWIOTLB
1249 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs
, 0, NULL
}
1253 static ssize_t
amdgpu_ttm_vram_read(struct file
*f
, char __user
*buf
,
1254 size_t size
, loff_t
*pos
)
1256 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
1260 if (size
& 0x3 || *pos
& 0x3)
1264 unsigned long flags
;
1267 if (*pos
>= adev
->mc
.mc_vram_size
)
1270 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
1271 WREG32(mmMM_INDEX
, ((uint32_t)*pos
) | 0x80000000);
1272 WREG32(mmMM_INDEX_HI
, *pos
>> 31);
1273 value
= RREG32(mmMM_DATA
);
1274 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
1276 r
= put_user(value
, (uint32_t *)buf
);
1289 static const struct file_operations amdgpu_ttm_vram_fops
= {
1290 .owner
= THIS_MODULE
,
1291 .read
= amdgpu_ttm_vram_read
,
1292 .llseek
= default_llseek
1295 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1297 static ssize_t
amdgpu_ttm_gtt_read(struct file
*f
, char __user
*buf
,
1298 size_t size
, loff_t
*pos
)
1300 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
1305 loff_t p
= *pos
/ PAGE_SIZE
;
1306 unsigned off
= *pos
& ~PAGE_MASK
;
1307 size_t cur_size
= min_t(size_t, size
, PAGE_SIZE
- off
);
1311 if (p
>= adev
->gart
.num_cpu_pages
)
1314 page
= adev
->gart
.pages
[p
];
1319 r
= copy_to_user(buf
, ptr
, cur_size
);
1320 kunmap(adev
->gart
.pages
[p
]);
1322 r
= clear_user(buf
, cur_size
);
1336 static const struct file_operations amdgpu_ttm_gtt_fops
= {
1337 .owner
= THIS_MODULE
,
1338 .read
= amdgpu_ttm_gtt_read
,
1339 .llseek
= default_llseek
1346 static int amdgpu_ttm_debugfs_init(struct amdgpu_device
*adev
)
1348 #if defined(CONFIG_DEBUG_FS)
1351 struct drm_minor
*minor
= adev
->ddev
->primary
;
1352 struct dentry
*ent
, *root
= minor
->debugfs_root
;
1354 ent
= debugfs_create_file("amdgpu_vram", S_IFREG
| S_IRUGO
, root
,
1355 adev
, &amdgpu_ttm_vram_fops
);
1357 return PTR_ERR(ent
);
1358 i_size_write(ent
->d_inode
, adev
->mc
.mc_vram_size
);
1359 adev
->mman
.vram
= ent
;
1361 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1362 ent
= debugfs_create_file("amdgpu_gtt", S_IFREG
| S_IRUGO
, root
,
1363 adev
, &amdgpu_ttm_gtt_fops
);
1365 return PTR_ERR(ent
);
1366 i_size_write(ent
->d_inode
, adev
->mc
.gtt_size
);
1367 adev
->mman
.gtt
= ent
;
1370 count
= ARRAY_SIZE(amdgpu_ttm_debugfs_list
);
1372 #ifdef CONFIG_SWIOTLB
1373 if (!swiotlb_nr_tbl())
1377 return amdgpu_debugfs_add_files(adev
, amdgpu_ttm_debugfs_list
, count
);
1384 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device
*adev
)
1386 #if defined(CONFIG_DEBUG_FS)
1388 debugfs_remove(adev
->mman
.vram
);
1389 adev
->mman
.vram
= NULL
;
1391 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1392 debugfs_remove(adev
->mman
.gtt
);
1393 adev
->mman
.gtt
= NULL
;